Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of achieving reduction in recovery loss.SOLUTION: A vertical semiconductor device comprising a wide gap semiconductor includes an n-type first layer. The semiconductor device includes an n-type second layer that is in contact with an upper surface of the first layer, the second layer having an n-type impurity concentration lower than that of the first layer. The semiconductor device includes a p-type body layer in contact with an upper surface of the second layer. The semiconductor device includes an n-type source region disposed on an upper part of the body layer. The semiconductor device includes a gate electrode structure disposed in contact with the body layer. A p-type first specific region is disposed in the first layer. The first specific region is disposed in a part of the first layer as viewed in a direction vertical to the upper surface of the first layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Vertical semiconductor devices made of wide-gap semiconductors are being developed, one example of which is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-140242 Summary of the Invention [Problem to be solved by the invention]

[0004] In vertical semiconductor devices, a diode exists between the drain and source. When a large recovery current flows during the recovery operation of the diode to turn off after a large current operation, recovery loss occurs and the turn-off response slows down. [Means for solving the problem]

[0005] One embodiment of the semiconductor device disclosed in this specification is a vertical semiconductor device made of a wide-gap semiconductor. The semiconductor device includes an n-type first layer. The semiconductor device includes an n-type second layer in contact with an upper surface of the first layer, the second layer having a lower n-type impurity concentration than the first layer. The semiconductor device includes a p-type body layer in contact with an upper surface of the second layer. The semiconductor device includes an n-type source region disposed above the body layer. The semiconductor device includes a gate electrode structure disposed in contact with the body layer. A p-type first specific region is disposed within the first layer. The first specific region is disposed in a part of the first layer when viewed from a direction perpendicular to the upper surface of the first layer.

[0006] In the above configuration, a p-type first specific region is disposed within the first layer. This allows holes, which are minority carriers, to disappear in the first specific region when the diode inside the vertical semiconductor device operates in the forward direction. This reduces the hole density inside the semiconductor device, thereby reducing recovery loss when transitioning to reverse recovery operation and improving turn-off responsiveness.

[0007] One embodiment of a method for manufacturing a semiconductor device disclosed in this specification is a method for manufacturing a vertical semiconductor device made of a wide-gap semiconductor. The method includes an ion implantation step of forming a p-type first specific region by ion implanting p-type impurities into a portion of the surface of an n-type first layer. The method also includes a step of forming an n-type second layer, the n-type second layer having a lower n-type impurity concentration than the first layer, on an upper surface of the first layer by epitaxial growth. The method also includes a step of forming a p-type body layer on an upper surface of the second layer by epitaxial growth. The method also includes a step of forming an n-type source region on an upper portion of the body layer. The method also includes a step of forming a gate electrode structure in contact with the body layer. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a semiconductor device 1. FIG. [Figure 2] FIG. 10 is a diagram showing a simulation result of a hole density distribution. [Figure 3] FIG. 10 is a cross-sectional view of a main part of a semiconductor device 201 according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a main part of a semiconductor device 301 according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0009] (Structure of semiconductor device 1) FIG. 1 shows a cross-sectional side view of a semiconductor device 1. FIG. 1 shows only a partial cross section of the semiconductor device 1. The unit structure shown in FIG. 1 is repeatedly formed in the semiconductor device 1. The semiconductor device 1 is a power semiconductor element known as a MOSFET. The semiconductor device 1 is a trench gate type.

[0010] In FIG. 1, reference numeral 2 denotes a semiconductor layer made of a wide-gap semiconductor. Various materials such as SiC, GaN, Ga2O3, and diamond can be used for the wide-gap semiconductor. In this example, the material of the semiconductor layer 2 is SiC. The direction parallel to the surface 2s of the semiconductor layer 2 and extending to the left and right of the paper surface is the x-direction, and the direction perpendicular to the paper surface is the y-direction. The direction perpendicular to the surface 2s is the z-direction. A source electrode 30 is formed on the surface 2s of the semiconductor layer 2, and a drain electrode 31 is formed on the back surface.

[0011] The semiconductor layer 2 is n + Mold support substrate 10, n + a buffer layer 11, an n-type drift layer 12, a p-type body layer 13, and an n + type source region 14 and p + The semiconductor device has a body contact region 15. A buffer layer 11 is in contact with the upper surface of the support substrate 10. A second interface IF2 is formed between the support substrate 10 and the buffer layer 11. A drift layer 12 is in contact with the upper surface of the buffer layer 11. A first interface IF1 is formed between the buffer layer 11 and the drift layer 12. The first interface IF1 is a boundary region where the n-type impurity concentration changes significantly. This boundary region may have a width in the depth direction. In other words, the first interface IF1 is not limited to a surface, but may be a layer having a width in the depth direction.

[0012] The n-type impurity concentration in the drift layer 12 is sufficiently lower than that in the support substrate 10 and the buffer layer 11. For example, the n-type impurity concentration in the drift layer 12 is 1 / 10 or less of the n-type impurity concentration in the support substrate 10 and the buffer layer 11. In this example, the impurity concentration in the support substrate 10 is 2×10 19 (cm -3), and the buffer layer 11 is 1×10 19 (cm -3 ), and the drift layer 12 is 1×10 16 (cm -3 ) Here, the support substrate 10 and the buffer layer 11 correspond to an example of the first layer, and the drift layer 12 corresponds to an example of the second layer.

[0013] A trench 20 is formed in the semiconductor layer 2. The trench 20 extends deep from the surface 2s through the source region 14 and the body layer 13 to reach the drift layer 12. A conductive gate electrode 23 is filled inside the trench 20 with a gate insulating film 22 interposed therebetween. An interlayer insulating film 24 is formed on the upper surface of the gate electrode 23. The interlayer insulating film 24 insulates the gate electrode 23 from the source electrode 30.

[0014] A p-type first specific region 51, a second specific region 52a, and a second specific region 52b are arranged in the buffer layer 11. The first specific region 51 is arranged in the vicinity of the first interface IF1 so as to include the region in the vicinity of the first interface IF1. Here, the phrase "the first specific region 51 includes the region in the vicinity of the first interface IF1" encompasses a state in which the first specific region 51 is arranged at a position several nanometers to several tens of nanometers away from the first interface IF1.

[0015] The second specific regions 52a and 52b are disposed below (in the -z direction) the first specific region 51 in the depth direction. The first specific region 51, the second specific region 52a, and the second specific region 52b are isolated from each other by the buffer layer 11.

[0016] When viewed from the direction perpendicular to the top surface of the buffer layer 11 (the +z direction), the first specific region 51, the second specific region 52a, and the second specific region 52b are disposed in a part of the buffer layer 11. That is, when viewed from the +z direction, the first specific region 51, the second specific region 52a, and the second specific region 52b overlap with the trench 20. When viewed from the +z direction, the second specific regions 52a and 52b are included within the first specific region 51. This allows a current path CP to be formed on the side of the first specific region 51, the second specific region 52a, and the second specific region 52b.

[0017] The first specific region 51 has a width W1 in a direction parallel to the first interface IF1 (x-direction). The second specific regions 52a and 52b have widths W2 and W3 in the x-direction. The widths W2 and W3 are smaller than the width W1. This prevents the current path CP from spreading laterally (x-direction) on the sides of the second specific regions 52a and 52b. This reduces the on-resistance of the semiconductor device 1.

[0018] The first specific region 51, the second specific region 52a, and the second specific region 52b are regions formed by ion implantation of p-type impurities. Therefore, the first specific region 51, the second specific region 52a, and the second specific region 52b contain defects formed by ion implantation. The defect density of the first specific region 51, the second specific region 52a, and the second specific region 52b is higher than the defect density of the buffer layer 11. In this example, aluminum is used as the p-type impurity. The concentration of the p-type impurity in the first specific region 51, the second specific region 52a, and the second specific region 52b is 0.5 to 5×10 18 (cm -3 ) was decided.

[0019] The hole trapping energy level of defects formed in the first specific region 51 is preferably greater than the valence band edge and less than the mid-gap energy. The mid-gap energy varies depending on the type of semiconductor material. More preferably, the hole trapping energy level is greater than the valence band edge by 0.2 eV or more. This level can be achieved by using aluminum as a p-type impurity for forming the first specific region 51 and appropriately adjusting the concentration of the p-type impurity. Providing this level can enhance the recombination of trapped holes during diode conduction. This enhances the effect of reducing the hole density within the semiconductor device 1. It is more preferable that the hole trapping energy levels of the second specific regions 52a and 52b are also greater than the valence band edge and less than the mid-gap energy.

[0020] (effect) A vertical semiconductor device such as the semiconductor device 1 (FIG. 1) has a diode between the drain and source. When the semiconductor device is turned off from high-current operation, this diode performs a recovery operation. If a large recovery current flows during this recovery operation, recovery loss and reduced turn-off response may occur. To address this issue, the technology of this embodiment provides a p-type first specific region 51, a second specific region 52a, and a second specific region 52b in the buffer layer 11. This allows minority carriers, i.e., holes, to be eliminated in the first specific region 51, the second specific region 52a, and the second specific region 52b when the diode within the semiconductor device 1 operates in the forward direction. This reduces the hole density within the semiconductor device 1. This reduces the recovery current and recovery time when the device transitions to reverse recovery operation, thereby reducing recovery loss and improving turn-off response.

[0021] Furthermore, the technology of this embodiment allows holes in the recovery current to remain in the first specific region 51, the second specific region 52a, and the second specific region 52b. Since the rapid discharge of holes can be suppressed, the time change in the recovery current is reduced, and the surge voltage can be reduced. This makes it possible to suppress noise.

[0022] When a forward voltage is applied to the diode in the semiconductor device 1, bipolar operation occurs, generating energy through the recombination of electrons and holes. This recombination energy may expand basal plane dislocations present in the SiC support substrate 10, resulting in Shockley stacking faults. Stacking faults hinder carrier conduction, increasing the on-resistance of the semiconductor device 1. This phenomenon is known as bipolar degradation. Therefore, in the technology of this embodiment, p-type first specific region 51, second specific region 52a, and second specific region 52b are disposed within the buffer layer 11. This reduces the hole density during forward current flow, thereby suppressing bipolar degradation.

[0023] The defect density in the first specific region 51, the second specific region 52a, and the second specific region 52b is set higher than the defect density in the buffer layer 11. This increases the recombination rate of holes due to defects in the first specific region 51, the second specific region 52a, and the second specific region 52b, thereby further enhancing the effect of reducing the hole density inside the semiconductor device 1.

[0024] The effect of reducing the hole density can be enhanced by increasing the total volume of the p-type specific regions formed in the n-type buffer layer 11. However, simply increasing the thickness of the specific regions would result in a deterioration in the breakdown voltage of the semiconductor device 1. Therefore, in the technology of this embodiment, the first specific region 51, the second specific region 52a, and the second specific region 52b are stacked and spaced apart from each other. This allows for a structure in which pn junctions are stacked. By ensuring the extent of the depletion layer, it is possible to reduce the hole density while maintaining the breakdown voltage.

[0025] (Simulation results) Various simulations were performed using a semiconductor device of a comparative example and the semiconductor device 1 of this example. The semiconductor device of the comparative example differs from the semiconductor device 1 of this example (FIG. 1) only in that it does not include the first specific region 51, the second specific region 52a, and the second specific region 52b. FIG. 2 shows the simulation results of the hole density distribution in the comparative example and this example. FIG. 2 shows the simulation results for the cross section taken along line AA in FIG. 1. That is, it shows the hole density distribution in the cross section passing through the gate electrode 23, the first specific region 51, the second specific region 52a, and the second specific region 52b. FIG. 2 also shows the hole density distribution in the cross section taken along line AA in FIG. 1, when the forward current is applied for a time of 2 ns and the current is 3 kA / cm. 2 2 shows the simulation results for the semiconductor device. In FIG. 2, the horizontal axis represents the depth direction of the semiconductor device, and the vertical axis represents the hole density. Graph G0 shows the results of the comparative example. Graph G1 shows the results of the present example.

[0026] Here, attention is focused on the hole density at the second interface IF2. The bipolar degradation described above occurs due to the expansion of stacking faults present in the support substrate 10. Therefore, reducing the hole concentration at the second interface IF2 of the support substrate 10 is important for suppressing bipolar degradation. The hole density at the second interface IF2 in the comparative example was 4.5×10 15 cm -3 (See point P0). On the other hand, in this example, 12 cm -3 (See point P1). That is, it can be seen that the semiconductor device 1 of this embodiment, by including the first specific region 51, the second specific region 52a, and the second specific region 52b, can reduce the hole density to 1 / 1000 or less compared to the comparative example (See arrow A1). Therefore, it is possible to effectively suppress bipolar degradation.

[0027] Furthermore, the recovery loss according to the simulation results was 0.68 mJ in the comparative example, but 0.22 mJ in this example. Furthermore, the recovery surge voltage according to the simulation results was 1710 V in the comparative example, but 1160 V in this example. That is, it can be seen that the semiconductor device 1 of this example, by including the first specific region 51, the second specific region 52a, and the second specific region 52b, can reduce the recovery loss by approximately 68% and the recovery surge voltage by approximately 36%.

[0028] Furthermore, the breakdown voltage according to the simulation results was 1370 V in the comparative example, but 1310 V in this example. Furthermore, the on-resistance according to the simulation results was 4.9 mΩ in the comparative example, but 5.0 mΩ in this example. In other words, it can be seen that the semiconductor device 1 of this example has the same breakdown voltage and on-resistance as the semiconductor of the comparative example.

[0029] (Method of manufacturing semiconductor device 1) First, an n-type buffer layer 11 is formed on the upper surface of the support substrate 10 by epitaxial growth. Next, an ion implantation process is performed in which p-type impurities are ion-implanted into a portion of the surface of the buffer layer 11. More specifically, a first mask having an opening corresponding to the first specific region 51 is formed on the surface of the buffer layer 11. The p-type impurities are ion-implanted through the first mask at a first implantation energy. The first implantation energy is appropriately adjusted so that the first specific region 51 includes a region near the surface of the buffer layer 11. A second mask having an opening corresponding to the second specific region 52a is formed on the surface of the buffer layer 11. The p-type impurities are ion-implanted through the second mask at a second implantation energy. The second implantation energy is greater than the first implantation energy. A third mask having an opening corresponding to the second specific region 52b is formed on the surface of the buffer layer 11. The p-type impurities are ion-implanted through the third mask at a third implantation energy. The third implantation energy is greater than the second implantation energy. The order in which the first specific region 51, the second specific region 52a, and the second specific region 52b are formed is not particularly limited.

[0030] An n-type drift layer 12 is formed on the upper surface of the buffer layer 11 by epitaxial growth. The n-type impurity concentration of the drift layer 12 is lower than the n-type impurity concentration of the buffer layer 11. A p-type body layer 13 is formed on the upper surface of the drift layer 12 by epitaxial growth. Annealing is then performed for crystal recovery and activation at some point after the ion implantation step. This completes the semiconductor layer 2.

[0031] Ion implantation is performed from the surface 2s of the semiconductor layer 2, + type source region 14 and p + A mold body contact region 15 is formed on the surface 2s. Then, a mask having openings corresponding to the trenches 20 is formed on the surface 2s. The trenches 20 are formed by dry etching through the mask. Thereafter, a gate insulating film 22, a gate electrode 23, an interlayer insulating film 24, a source electrode 30, and a drain electrode 31 are formed, completing the semiconductor device 1 shown in FIG. [Example]

[0032] (Structure of semiconductor device 201) FIG. 3 shows a cross-sectional view of a main part of a semiconductor device 201 according to a second embodiment. The same reference numerals are used to designate common parts between the semiconductor device 201 of the second embodiment and the semiconductor device 1 of the first embodiment, and a description thereof will be omitted. The semiconductor device 201 of the second embodiment differs from the semiconductor device 1 of the first embodiment (FIG. 1) only in that it does not include the second specific regions 52a and 52b. The first specific region 51 is disposed in the vicinity of the first interface IF1 so as to include the region in the vicinity of the first interface IF1. In this embodiment, the concentration of p-type impurities (aluminum) in the first specific region 51 is 1.5×10 18 (cm -3 ) was decided.

[0033] (Simulation results) The semiconductor device 201 of Example 2 was subjected to a simulation similar to that of Example 1. As a result, the hole density at the second interface IF2 was 4.5×10 15 cm -3) in Example 2, 2.1 × 10 13 cm -3 That is, by providing the first specific region 51, the semiconductor device 201 of Example 2 can reduce the hole density to 1 / 100 or less compared to the comparative example.

[0034] The recovery loss was the same in Example 1 (0.22 mJ) and Example 2 (0.22 mJ). The recovery surge voltage was lower in Example 2 (1090 V) than in Example 1 (1160 V). The breakdown voltage was the same in Example 1 (1310 V) and Example 2 (1280 V). The on-resistance was the same in Example 1 (5.0 mΩ) and Example 2 (5.0 mΩ). That is, it can be seen that the semiconductor device 201 of Example 2 can maintain characteristics equivalent to those of the semiconductor device 1 of Example 1.

[0035] (effect) The first interface IF1 is a boundary region where the n-type impurity concentration changes significantly, and therefore is a region where electron-hole recombination frequently occurs. In the technology of Example 2, only one first specific region 51 is disposed so as to include the region near the first interface IF1. This makes it possible to effectively reduce the hole density inside the semiconductor device 1 using one of the first specific regions 51. This makes it possible to reduce recovery loss and improve turn-off responsiveness. [Example]

[0036] (Structure of semiconductor device 301) 4 shows a cross-sectional view of a main part of a semiconductor device 301 according to Example 3. The same reference numerals are used to designate common parts between the semiconductor device 301 of Example 3 and the semiconductor device 1 of Example 1, and descriptions thereof will be omitted. The semiconductor device 301 of Example 3 differs from the semiconductor device 1 of Example 1 (FIG. 1) in that it does not include second specific regions 52a and 52b, and it includes third specific regions 53a and 53b.

[0037] The third specific regions 53a and 53b are disposed above the first specific region 51 in the depth direction (on the +z direction side). The first specific region 51, the third specific region 53a, and the third specific region 53b are isolated from each other by the buffer layer 11. When viewed from the +z direction, the third specific regions 53a and 53b are included within the range of the first specific region 51. The widths W2m and W3m of the third specific regions 53a and 53b are smaller than the width W1. In Example 3, the concentration of the p-type impurity (aluminum) in the first specific region 51 is 4.0×10 17 (cm -3 ), third specific area 53a=7.9×10 17 (cm -3 ), third specific area 53b=5.3×10 17 (cm -3 ), and

[0038] An example of a method for manufacturing the third specific regions 53a and 53b will be described. The epitaxial growth of the drift layer 12 on the upper surface of the buffer layer 11 is interrupted midway. Then, a mask having an opening corresponding to the third specific region 53a is formed on the surface of the drift layer 12, and p-type impurities are ion-implanted with a fourth implantation energy. Furthermore, a mask having an opening corresponding to the third specific region 53b is formed on the surface of the drift layer 12, and p-type impurities are ion-implanted with a fifth implantation energy. The fifth implantation energy is smaller than the fourth implantation energy. The epitaxial growth of the drift layer 12 is then resumed, and the drift layer 12 is completed.

[0039] (Simulation results) The semiconductor device 301 of Example 3 was subjected to a simulation similar to that of Example 1. As a result, the hole density at the second interface IF2 was 4.5×10 15 cm -3 ) in Example 3, 3.7 × 10 13 cm -3 That is, in the semiconductor device 301 of Example 3, by including the first specific region 51, the third specific region 53a, and the third specific region 53b, the hole density can be reduced to 1 / 100 or less compared to the comparative example.

[0040] The recovery loss was the same in Example 1 (0.22 mJ) and Example 3 (0.22 mJ). The recovery surge voltage was lower in Example 3 (1090 V) than in Example 1 (1160 V). The breakdown voltage was the same in Example 1 (1310 V) and Example 3 (1270 V). The on-resistance was slightly higher in Example 2 (7.3 mΩ) than in Example 1 (5.0 mΩ). That is, it can be seen that the semiconductor device 301 of Example 3 can maintain characteristics equivalent to those of the semiconductor device 1 of Example 1.

[0041] Although specific examples of the present technology have been described in detail above, these are merely examples and do not limit the scope of the claims. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility.

[0042] (Variation) Although the wide-gap semiconductor material is SiC in the above description, it is not limited to this. Various wide-gap semiconductor materials such as GaN, Ga2O3, and diamond can also be used. Si can also be used as the semiconductor material.

[0043] The technology of this specification is applicable to vertical semiconductor devices in general. Therefore, the gate electrode structure is not limited to a trench type. It may also be a planar type gate electrode structure in which a gate electrode is disposed on the surface 2s of the semiconductor layer 2 via a gate insulating film. Furthermore, the type of semiconductor device is not limited to a MOSFET. It may be various types such as a diode or an IGBT.

[0044] The number of second specific regions in Example 2 and the number of third specific regions in Example 3 are not limited to two. They may be one, three, or more. The widths of the second specific regions and the third specific regions can be set in various ways. For example, the width of at least one of the second specific regions 52a and 52b may be equal to or greater than the width of the first specific region 51. Furthermore, for example, the width of at least one of the third specific regions 53a and 53b may be equal to or greater than the width of the first specific region 51.

[0045] Aspects of the present technology are listed below. [Aspect 1] A vertical semiconductor device made of a wide-gap semiconductor, an n-type first layer; an n-type second layer in contact with an upper surface of the first layer, the second layer having a lower n-type impurity concentration than the first layer; a p-type body layer in contact with an upper surface of the second layer; an n-type source region disposed on the body layer; a gate electrode structure disposed in contact with the body layer; Equipped with a p-type first specific region is disposed in the first layer; the first specific region is disposed in a part of the first layer when viewed from a direction perpendicular to the top surface of the first layer; Semiconductor device. [Aspect 2] 2. The semiconductor device according to aspect 1, wherein the first specific region includes a region near the interface between the first layer and the second layer. [Aspect 3] a p-type second specific region disposed in the first layer and below the first specific region in a depth direction, 3. The semiconductor device according to aspect 2, wherein the first specific region and the second specific region are isolated by the first layer. [Aspect 4] the second specific region is included within the first specific region when viewed from a direction perpendicular to the first layer, 4. The semiconductor device according to aspect 3, wherein the second specific region has a smaller width in a direction parallel to the interface than the first specific region. [Aspect 5] a p-type third specific region disposed inside the second layer and above the first specific region in a depth direction, 5. The semiconductor device according to any one of aspects 1 to 4, wherein the first specific region and the third specific region are isolated by the second layer. [Aspect 6] the first specific region includes defects formed by ion implantation, 6. The semiconductor device according to any one of aspects 1 to 5, wherein the defect density of the first specific region is higher than the defect density of the first layer. [Aspect 7] 7. The semiconductor device according to any one of aspects 1 to 6, wherein the hole trap energy level of the first specific region is higher than the valence band edge and lower than the mid-gap energy. [Aspect 8] the source region is separated from the second layer by the body layer; the gate electrode structure is a trench electrode extending from an upper surface of the source region through the source region and the body layer toward a depth thereof so as to reach the second layer; 8. The semiconductor device according to any one of aspects 1 to 7, wherein the gate electrode structure faces the body layer at a position separating the second layer and the source region via a gate insulating film. [Aspect 9] A method for manufacturing a vertical semiconductor device made of a wide-gap semiconductor, comprising: an ion implantation step of ion-implanting p-type impurities into a portion of a surface of the n-type first layer to form a p-type first specific region; forming an n-type second layer having an n-type impurity concentration lower than that of the first layer by epitaxial growth on an upper surface of the first layer; forming a p-type body layer on an upper surface of the second layer by epitaxial growth; forming an n-type source region on the body layer; forming a gate electrode structure in contact with the body layer; A method for manufacturing a semiconductor device, comprising: [Aspect 10] In the ion implantation step, ions are implanted so that the first specific region includes a region near the interface between the first layer and the second layer; In the ion implantation step, a p-type second specific region is further formed in the first layer and disposed below the first specific region in a depth direction, 10. The method for manufacturing a semiconductor device according to claim 9, wherein the first specific region and the second specific region are isolated by the first layer. [Explanation of symbols]

[0046] 1: semiconductor device 10: supporting substrate 11: buffer layer 12: drift layer 13: body layer 14: source region 20: trench 22: gate insulating film 23: gate electrode 51: first specific region 52a, 52b: second specific region IF1: first interface

Claims

1. A vertical semiconductor device made of a wide-gap semiconductor, an n-type first layer; an n-type second layer in contact with an upper surface of the first layer, the second layer having a lower n-type impurity concentration than the first layer; a p-type body layer in contact with an upper surface of the second layer; an n-type source region disposed on the body layer; a gate electrode structure disposed in contact with the body layer; Equipped with a p-type first specific region is disposed in the first layer; the first specific region is disposed in a part of the first layer when viewed from a direction perpendicular to an upper surface of the first layer; Semiconductor device.

2. The semiconductor device according to claim 1 , wherein the first specific region includes a region in the vicinity of an interface between the first layer and the second layer.

3. a p-type second specific region disposed inside the first layer and below the first specific region in a depth direction, The semiconductor device according to claim 2 , wherein the first specific region and the second specific region are isolated by the first layer.

4. the second specific region is included within the first specific region when viewed from a direction perpendicular to the first layer, The semiconductor device according to claim 3 , wherein the width of the second specific region in a direction parallel to the interface is smaller than that of the first specific region.

5. a p-type third specific region disposed inside the second layer and above the first specific region in a depth direction, The semiconductor device according to claim 4 , wherein the first specific region and the third specific region are isolated by the second layer.

6. the first specific region includes defects formed by ion implantation, The semiconductor device according to claim 2 , wherein the defect density of said first specific region is higher than the defect density of said first layer.

7. 3. The semiconductor device according to claim 2, wherein the hole trap energy level of said first specific region is higher than the valence band edge and lower than the mid-gap energy.

8. the source region is separated from the second layer by the body layer; the gate electrode structure is a trench electrode extending from an upper surface of the source region through the source region and the body layer toward a depth thereof so as to reach the second layer, 8. The semiconductor device according to claim 1, wherein the gate electrode structure faces the body layer at a position separating the second layer and the source region via a gate insulating film.

9. A method for manufacturing a vertical semiconductor device made of a wide-gap semiconductor, comprising: an ion implantation step of ion-implanting p-type impurities into a portion of a surface of the n-type first layer to form a p-type first specific region; forming an n-type second layer having an n-type impurity concentration lower than that of the first layer by epitaxial growth on an upper surface of the first layer; forming a p-type body layer on an upper surface of the second layer by epitaxial growth; forming an n-type source region on the body layer; forming a gate electrode structure in contact with the body layer; A method for manufacturing a semiconductor device, comprising:

10. In the ion implantation step, ions are implanted so that the first specific region includes a region near the interface between the first layer and the second layer; In the ion implantation step, a p-type second specific region is further formed in the first layer and disposed below the first specific region in a depth direction, The method for manufacturing a semiconductor device according to claim 9 , wherein the first specific region and the second specific region are isolated by the first layer.

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