Semiconductor device

Abstract

To provide a semiconductor device capable of improving resistance.SOLUTION: A semiconductor device comprises a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate 1, a resistor R embedded within the insulating layer 2, a first conductive ring 1R provided around the resistor R, and a second ring TIV provided within the insulating layer 2, and connecting the semiconductor substrate 1 and the first ring 1R in the thickness direction of the insulating layer 2.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a plurality of resistance elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 085026

[0004] [overview] The present disclosure provides a semiconductor device capable of improving durability.

[0005] The semiconductor device of the present disclosure comprises a semiconductor substrate, an insulating layer provided on the semiconductor substrate, a resistor embedded in the insulating layer, a conductive first ring provided around the resistor, and a second ring provided in the insulating layer and connecting the semiconductor substrate and the first ring in the thickness direction of the insulating layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor package. [Figure 2] FIG. 2 is a circuit diagram of the resistor chip and the amplifier chip. [Figure 3] FIG. 3 is a graph showing the relationship between the input voltage HV (kV) and the output voltage Vout (V). [Figure 4] FIG. 4 is a diagram showing the planar configuration of the resistor chip and the amplifier chip. [Figure 5] FIG. 5 is a diagram showing a vertical cross-sectional configuration of the resistor chip. [Figure 6] FIG. 6 is a diagram showing a vertical cross-sectional configuration of the resistor chip. [Figure 7]FIG. 7 is a diagram showing a planar configuration of the combined resistor chip. [Figure 8] FIG. 8 is a diagram showing the vertical end face configuration of the combined resistor chip. [Figure 9] FIG. 9 is a diagram showing the vertical end face configuration of the combined resistor chip. [Figure 10] FIG. 10 is a diagram showing the vertical end face configuration of the combined resistor chip. [Figure 11] FIG. 11 is a diagram showing the vertical end face configuration of the combined resistor chip. [Figure 12] FIG. 12 is a diagram showing a planar configuration for explaining the electrical connection relationship of the voltage dividing circuit formed on the resistor chip. [Figure 13] FIG. 13 is a diagram showing an example of a detailed structure of a resistor portion in a voltage dividing circuit formed on a resistor chip. [Figure 14] FIG. 14 is a diagram showing a longitudinal cross-sectional configuration of a portion taken along line AA in FIG. [Figure 15] FIG. 15 is a diagram showing a vertical cross-sectional configuration of a portion taken along line BB in FIG. [Figure 16] FIG. 16 is a diagram showing a vertical cross-sectional configuration of a portion taken along line CC in FIG. [Figure 17] FIG. 17 is a diagram showing a longitudinal cross-sectional configuration of a portion taken along line DD in FIG. [Figure 18] 18A and 18B are a plan view of the vicinity of the first electrode of a capacitively coupled dummy wiring (FIG. 18A) and a plan view of the vicinity of the first electrode of an electrically connected dummy wiring (FIG. 18B). [Figure 19] FIG. 19 is a plan view of a resistor chip equipped with capacitively coupled dummy wiring. [Figure 20] FIG. 20 is a plan view of a resistor chip provided with electrically connected dummy wiring. [Figure 21] 21A and 21B are a longitudinal sectional view of the second ring TIV having the first structure (FIG. 21A) and a longitudinal sectional view of the second ring TIV having the second structure (FIG. 21B).

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] 1 is a plan view of a semiconductor package, with the top cover removed.

[0009] The semiconductor package 100 includes a case 101 having a recess D1. The case 101 is made of an insulating material such as resin or ceramic. An XYZ three-dimensional Cartesian coordinate system is set. The thickness direction of the semiconductor package 100 is defined as the Z-axis direction, the direction perpendicular to the Z-axis direction is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The positive direction of the Z-axis is defined as the depth direction (downward direction) of the recess D1.

[0010] The semiconductor package 100 includes a resistor chip 10 (semiconductor device) disposed on a first die pad 110 in the recess D1, and an amplifier chip 20 (semiconductor device) disposed on a second die pad 120 in the recess D1. The open end of the recess D1 of the semiconductor package 100 is sealed with a lid (not shown), creating an airtight space inside the recess D1. The lid may be made of an insulating material such as resin, and the recess D1 may be filled with a gas or an insulating material. A ground potential (GND) is applied to the first die pad 110 and the second die pad 120 via the lead frame.

[0011] The lower surface of the resistor chip 10 is fixed to the first die pad 110. The upper surface of the resistor chip 10 is electrically connected to the first inner lead 10a and the second inner lead 10b of the lead frame via bonding wires. The first inner lead 10a and the second inner lead 10b are continuous with the outer leads exposed to the outside of the package.

[0012] The first inner lead 10a is electrically connected to the first input terminal HV(+), which is electrically connected to the positive electrode of the battery 200. The second inner lead 10b is electrically connected to the second input terminal HV(-), which is electrically connected to the negative electrode of the battery 200.

[0013] The bottom surface of the amplifier chip 20 is fixed to the second die pad 120. The top surface of the amplifier chip 20 is electrically connected to the third inner lead 10c, the fourth inner lead 10d, the fifth inner lead 10e, the sixth inner lead 10f, the seventh inner lead 10g, the eighth inner lead 10h, the ninth inner lead 10i, and the tenth inner lead 10j of the lead frame via bonding wires. Note that connection in an electric circuit means an electrical connection, and when it is clear that an electrical connection is made by a physical connection, the term "connection" may be used simply to avoid redundancy in expression.

[0014] The third inner lead 10c is supplied with a power supply potential VCC. The sixth inner lead 10f outputs a positive monitor signal P-MONI. The seventh inner lead 10g is connected to an output terminal as an outer lead, and outputs an output voltage Vout. The eighth inner lead 10h outputs a negative monitor signal N-MONI. The ninth inner lead 10i outputs a voltage monitor signal V-MONI. Note that the symbols for these signals also refer to the symbols indicating the terminals as outer leads corresponding to the signals. The fourth inner lead 10d, fifth inner lead 10e, and tenth inner lead 10j can be used for spare functions.

[0015] FIG. 2 is a circuit diagram of the resistor chip 10 and the amplifier chip 20.

[0016] The resistor chip 10 configures a voltage divider circuit including a resistor R (resistor pattern). The resistor R includes a first resistor RP electrically connected to a first electrode E1 and a second resistor RN electrically connected to a second electrode E2. The resistor R electrically connects the first resistor RP and the second resistor RN and includes voltage detection resistors (RPS, RNS) having a lower resistance value than both the first resistor RP and the second resistor RN. The resistor chip 10 includes a first output electrode EP, a second output electrode EN, and a reference electrode EG electrically connected to different locations of the voltage detection resistors (RPS, RNS). The voltage detection resistors (RPS, RNS) include a first voltage detection resistor RPS and a second voltage detection resistor RNS.

[0017] The first resistor RP is connected between the first electrode E1 and the first output electrode EP. The second resistor RN is connected between the second electrode E2 and the second output electrode EN. The first voltage detection resistor RPS is connected between the first output electrode EP and the reference electrode EG. The second voltage detection resistor RNS is connected between the second output electrode EN and the reference electrode EG. The resistance value R of the first voltage detection resistor RPS is RPS is the resistance R of the first resistor RP RP is smaller than (R RPS <R RP ) The resistance value R of the second voltage detection resistor RNS RNS is the resistance R of the second resistor RN RN is smaller than (R RNS <R RN ) In detail, 0Ω <R RPS <K×R RP , 0 Ω <R RNS <K×R RN is.

[0018] The coefficient K, which indicates the relative resistance value of the detection resistor, is smaller than 1, and illustratively, the values ​​of the coefficient K are 5%, 3%, 1%, 0.5%, 0.3%, 0.25%, 0.2%, 0.1%, and 0.01%. By setting the value of the coefficient K, the resistance value of the detection resistor can be set to, for example, 0.01 MΩ to 10 MΩ. As a preferred example, the resistance value of the detection resistor can be set to, for example, 1 / 100 or less of the resistance value of the corresponding resistor (R RPS ≦1%×R RP , R RNS ≦1%×R RN ). This ratio is, for example, R RPS ≦0.5%×R RP , R RNS ≦0.5%×R RN , or R RPS ≦0.2%×R RP , R RNS ≦0.2%×R RN When an input voltage is applied between the first electrode E1 and the second electrode E2, the input voltage is divided according to the ratio of the resistance values ​​of the resistors.

[0019] For example, let's assume that the input voltage is 1000 V, the resistance of resistor R (the combined series resistance of each resistor) is k × 1000 MΩ, where k is a positive value, for example, k = 0.5. Let's also assume that the resistance of the first resistor RP is k × 499.5 MΩ, the resistance of the first voltage detection resistor RPS is k × 0.5 MΩ, the resistance of the second resistor RN is k × 499.5 MΩ, and the resistance of the second voltage detection resistor RNS is k × 0.5 MΩ.

[0020] In this example, a voltage of 499.5V is applied across the first resistor RP, a voltage of 0.5V is applied across the first voltage detection resistor RPS, a voltage of 499.5V is applied across the second resistor RN, and a voltage of 0.5V is applied across the second voltage detection resistor RNS. A voltage of 0.5V is applied between the reference electrode EG and the first output electrode EP, and a voltage of 0.5V is applied between the reference electrode EG and the second output electrode EN. A voltage of 1V is applied between the first output electrode EP and the second output electrode EN. In other words, the resistor chip 10 constituting the voltage divider circuit can output an output voltage of 1V when the input voltage is 1000V. Of course, it can also output an output voltage of 0.5V when the input voltage is 500V. The resistance value of the resistor R between the first electrode E1 and the second electrode E2 can be between 1MΩ and 1000MΩ. The resistance value of resistor R can be set to 100 MΩ or more and 800 MΩ or less. The resistance value of resistor R can also be set to 300 MΩ or more and 600 MΩ or less. This resistance value should be high enough to withstand high voltages and allow voltage detection.

[0021] The amplifier chip 20 is a differential amplifier circuit and includes a differential amplifier 20D. The differential amplifier 20D receives a positive signal output from the first output electrode EP and a negative signal output from the second output electrode EN, and outputs the difference between these signals as an output voltage Vout.

[0022] The first output electrode EP is connected to the first voltage follower 21P via a bonding wire. The second output electrode EN is connected to the second voltage follower 21N via a bonding wire. A power supply potential VCC is supplied to the amplifier chip 20.

[0023] The output signal of the first voltage follower 21P is output to the outside of the amplifier chip 20 as a positive monitor signal P-MONI. The output signal of the second voltage follower 21N is output to the outside of the amplifier chip 20 as a negative monitor signal N-MONI. The reference electrode EG has a reference potential V-REG and is connected to a second voltage adjustment circuit 29 via a bonding wire. The second voltage adjustment circuit 29 generates a reference potential V-REG that is half the power supply potential VCC. The reference potential V-REG is output to the outside of the amplifier chip 20 as a voltage monitor signal V-MONI.

[0024] A first dummy wiring region DM1 can be arranged around the first resistor RP in this example as needed. The first dummy wiring region DM1 includes a plurality of dummy wirings (dummy electrodes, dummy wiring patterns, dummy metals, and dummy conductors). A second dummy wiring region DM2 can be arranged around the second resistor RN in this example as needed. The second dummy wiring region DM2 includes a plurality of dummy wirings (dummy electrodes, dummy wiring patterns, dummy metals, and dummy conductors). The dummy wirings do not contribute to the transmission of the input signal (input voltage), but contribute to increasing the withstand voltage of the resistor chip 10. Note that resistors that do not include dummy wirings are also possible.

[0025] FIG. 3 is a graph showing the relationship between the input voltage HV (kV) and the output voltage Vout (V).

[0026] The input voltage HV (kV) is the difference between the positive first voltage V1 applied to the first input terminal HV(+) and the negative second voltage V2 applied to the second input terminal HV(-) in FIG. 2 (= V1 - V2 ≈ 2 × V1). For example, if the positive first voltage V1 = 600 V and the negative second voltage V2 = -600 V, the input voltage HV (kV) = 1.2 (kV). In this case, the detection voltage (voltage between the first output electrode EP and the second output electrode EN) of the resistor chip 10 shown in FIG. 2 is, for example, 1.2 V (= 1 / 1000 of the input voltage). The amplifier chip 20 amplifies the detection voltage and outputs it as the output voltage Vout (V). The input voltage HV (kV) and the output voltage Vout (V) have a linear relationship with a slope a (Vout (V) = a × HV (kV)). For example, if the amplification factor of the amplifier chip 20 is 3.75, the output voltage Vout is 3.75×1.2V=4.5V.

[0027] FIG. 4 is a diagram showing the planar configuration of the resistor chip and the amplifier chip.

[0028] The resistor chip 10 includes, in a plan view (XY plane), a resistor R, a first ring 1R surrounding the resistor R, and a second ring TIV provided below the first ring 1R (on the semiconductor substrate side). The planar shapes of the first ring 1R and the second ring TIV are substantially the same, each having a rectangular annular shape, and overlapping in plan view. This figure is a schematic diagram, and for clarity, the first ring 1R is indicated by a dotted line. The resistor R, the first ring 1R, and the second ring TIV are embedded in an insulating layer provided on the semiconductor substrate, but the insulating layer is not shown. The first ring 1R has a rectangular ring shape surrounding the Z axis in plan view. The second ring TIV also has a rectangular ring shape surrounding the Z axis in plan view.

[0029] The amplifier chip 20 includes a processing circuit 20P inside a semiconductor substrate. The processing circuit 20P includes an amplifier that amplifies the voltage output from the resistor chip 10, and an exemplary circuit configuration is as shown in FIG.

[0030] FIG. 5 is a diagram showing a vertical cross-sectional configuration of the resistor chip 10. As shown in FIG.

[0031] The resistor chip 10 as a semiconductor device includes a semiconductor substrate 1, an insulating layer 2, a resistor R, a first ring 1R, and a second ring TIV. The insulating layer 2 is provided on the semiconductor substrate 1. The resistor R is embedded in the insulating layer 2. The first ring 1R is made of a conductive material, is located at approximately the same height as the resistor R, and is provided around the resistor R. The second ring TIV is provided in the insulating layer 2, and connects the semiconductor substrate 1 and the first ring 1R in the thickness direction of the insulating layer 2.

[0032] The insulating layer 2 is made of a dielectric material such as an oxide or a nitride. The insulating layer 2 is made of a substrate-side dielectric layer 2AB and an upper dielectric layer 2A located on the substrate-side dielectric layer 2AB. H The substrate-side dielectric layer 2AB is located closer to the semiconductor substrate 1 than the lower surface of the resistor R including the embedded electrode. The first ring 1R is provided with the upper dielectric layer 2A. H The second ring TIV is embedded in the substrate-side dielectric layer 2AB. The second ring TIV is formed by laminating a plurality of rings along the thickness direction of the insulating layer 2.

[0033] The resistor R includes the first electrode E1, the second electrode E2, the first output electrode EP, the second output electrode EN, and the reference electrode EG. These electrodes are arranged inside the first ring 1R in a plan view. The upper dielectric layer 2A H A protective film 4 is provided on the top. The protective film 4 has the function of protecting the resistor R, but the surfaces of the various electrodes can be exposed so that wire bonding or the like can be performed.

[0034] The material of the second ring TIV may be a conductive material. This conductive material may include at least one conductive material selected from the group consisting of Cu (copper), W (tungsten), Al (aluminum), Si (silicon), and TiN (titanium nitride). When Si is used as the material of the second ring TIV, polysilicon doped with impurities may be used. Exemplary materials for the second ring TIV are copper (Cu) and W (tungsten).

[0035] The conductive first ring 1R is arranged around the resistor R and is located near the edge of the resistor chip 10, stabilizing the potential around the resistor R. The second ring TIV, if made of a conductive material, similarly fixes the potential relative to the surrounding environment, contributing to stabilizing the potential around the resistor R. The second ring TIV electrically connects the first ring 1R to the semiconductor substrate 1. It is also possible to set the potential of a portion of the semiconductor substrate 1 to ground potential and fix the second ring TIV to the ground potential of the semiconductor substrate 1. The second ring TIV is annular and formed by stacking multiple rings in the thickness direction of the insulating layer 2, functioning as a thick wall against the external environment. Therefore, the second ring TIV can prevent moisture from penetrating into the insulating layer 2 and protect the resistor chip 10 from the surrounding environment. The second ring TIV can be conductive and waterproof.

[0036] When only waterproofing is required, the second ring TIV does not need to be electrically conductive. In this case, the second ring TIV may contain at least one waterproof material selected from the group consisting of SiN, SiCON, and SiC. This waterproof material has higher waterproofing performance than SiO2.

[0037] When only the conductivity is considered, the second ring TIV does not need to be ring-shaped, but may be made of a conductive material. In this case, the resistor chip 10 includes a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate, a resistor R embedded in the insulating layer 2, a conductive first ring 1R provided around the resistor R, and a conductive material (second ring TIV) provided in the insulating layer 2 and connecting the semiconductor substrate 1 and the first ring 1R in the thickness direction of the insulating layer 2.

[0038] FIG. 6 is a diagram showing a vertical cross-sectional configuration of the resistor chip.

[0039] This figure shows a more detailed configuration of the structure shown in Fig. 5. Note that this figure also shows a vertical cross-sectional structure taken along the F1-F1 arrow line or the F2-F2 arrow line in Fig. 13.

[0040] The insulating layer 2 is provided on the semiconductor substrate 1. The insulating layer 2 includes a plurality of stacked dielectric layers (first dielectric layer 2A, second dielectric layer 2B). At least one of the plurality of dielectric layers (first dielectric layer 2A) is made of a material containing silicon oxide. At least one of the plurality of dielectric layers (second dielectric layer 2B) is made of a material containing silicon nitride. In this example, the first dielectric layer 2A and the second dielectric layer 2B are alternately stacked. The silicon oxide in this example is SiO2, but the elemental composition ratio may be changed or other elements may be included as necessary. The silicon nitride in this example is Si3N4, but the elemental composition ratio may be changed or other elements may be included as necessary. The thickness of the insulating layer 2 may be, for example, 5 μm or more and 50 μm or less.

[0041] The insulating layer 2 is a lower dielectric layer 2A formed on a second dielectric layer 2B located at the top. L and the lower dielectric layer 2A L Upper dielectric layer 2A formed on H The lower dielectric layer 2A L and upper dielectric layer 2A H The exemplary material of the upper dielectric layer 2A is the same as that of the first dielectric layer 2A. HA first protective film 4A is formed on the first protective film 4A. The material of the first protective film 4A can be an inorganic insulator such as silicon oxide or silicon nitride. A second protective film 4B is formed on the first protective film 4A. The material of the second protective film 4B can be a resin (insulator) such as polyimide.

[0042] In the region directly above the first electrode E1, the upper dielectric layer 2A H The first protective film 4A and the second protective film 4B have been removed, exposing the upper surface of the first electrode E1. Wiring (bonding wire, wiring pattern) is connected to the upper surface of the first electrode E1 (electrode pad). The structure of the second electrode side is the same as the structure of the first electrode E1 side, and the upper surface of the second electrode E2 (FIG. 2) is exposed.

[0043] The resistor R (see FIG. 4) has a plurality of linear resistors 3 extending along the Y-axis aligned along the X-axis direction. The resistor includes a first via electrode VE5 provided at one end of the linear resistor 3 in the Y-axis direction and a second via electrode VE7 provided at the other end. The first via electrode VE5 connects one end of the linear resistor 3 to the buried electrode BE directly below it, and this buried electrode BE is electrically connected via a via electrode to one end of the linear resistor 3 adjacent to it in the positive direction of the X-axis. The second via electrode VE7 connects the other end of the linear resistor 3 to the buried electrode BE directly below it, and this buried electrode BE is electrically connected via a via electrode to the other end of the linear resistor 3 adjacent to it in the negative direction of the X-axis. An example of a material for the first via electrode VE5 and the second via electrode VE7 is W (tungsten), and an example of a material for the buried electrode BE is Cu (copper).

[0044] The resistor chip 10 includes a first ring 1R (annular conductor) embedded in the upper region of the insulating layer 2. The first ring 1R includes a peripheral electrode 1R1, a peripheral via electrode 1R2, and a peripheral resistor 1R3. The peripheral via electrode 1R2 connects the upper surface of the peripheral electrode 1R1 to the lower surface of the peripheral resistor 1R3. The material of the peripheral electrode 1R1 may be the same as the material of the buried electrode BE. The material of the peripheral via electrode 1R2 may be the same as the material of the first via electrode VE5. The material of the resistive layer constituting the peripheral resistor 1R3 may be the same as the material of the linear resistor 3. The planar shape of the peripheral resistor 1R3 may be a continuous annular shape or an intermittent annular shape. When the peripheral resistor 1R3 has an annular shape formed by intermittently arranging multiple linear resistors, the peripheral electrode 1R1 may connect the ends of adjacent linear resistors via the peripheral via electrode 1R2.

[0045] The buried electrode BE and the peripheral electrode 1R1 are formed on the lower dielectric layer 2A. L The insulating layer 2 is formed on the semiconductor substrate 1 and is embedded in the insulating layer 2.

[0046] The first ring 1R may be configured to include only the annular peripheral electrode 1R1.

[0047] The second ring TIV comprises a plurality of rings stacked along the thickness direction of the insulating layer 2. The upper ring T2 is an annular body having a rectangular shape in a plan view, and the upper surface of the upper ring T2 is connected to the lower surface of the peripheral electrode 1R1 through the via electrode T1. The lower ring T3 is an annular body having a rectangular shape in a plan view, and the upper surface of the lower ring T3 is connected to the lower surface of the upper ring T2. An example of the material of the upper ring T2 and the lower ring T3 is Cu (copper), but other conductive materials can also be used.

[0048] The lower surface of the lower ring T3 is connected to the surface of the semiconductor substrate 1 through a via electrode T4. The semiconductor substrate 1 may have a contact region 1C1 to which a P-type or N-type impurity is added to reduce resistance. The via electrode T4 in the lowest layer may be connected to the contact region 1C1.

[0049] The via electrodes T1 and T4 may each be a ring-shaped body having a rectangular shape in a plan view. Each via electrode may also be a double ring-shaped conductor in the same horizontal plane. One example of the material for these via electrodes is tungsten (W), but other conductive materials may also be used.

[0050] When forming a second ring TIV that penetrates the insulating layer 2, a method can be used in which one dielectric layer (insulating layer) is formed, a ring-shaped opening is formed in this layer, and a metal is filled in the opening. The opening can be formed by patterning a resist using photolithography and etching. The opening can be filled with metal by sputtering or plating, etc. Since forming an opening for each layer does not provide high production efficiency, a method can be used in which multiple dielectric layers are formed, a ring-shaped opening is formed in these dielectric layers, and a metal is filled in the opening.

[0051] For example, after sequentially forming the second dielectric layer 2B, the first dielectric layer 2A, the second dielectric layer 2B, and the first dielectric layer 2A on the lowest first dielectric layer 2A in which the via electrode T4 is embedded, a ring-shaped opening is formed from the surface toward the depth until the lowest first dielectric layer 2A is reached, and a metal is filled in the opening to form the lower ring T3.

[0052] Next, a second dielectric layer 2B, a first dielectric layer 2A, a second dielectric layer 2B, and a first dielectric layer 2A are sequentially formed on the upper first dielectric layer 2A in which the lower ring T3 is embedded, and then a ring-shaped opening is formed from the surface toward the depth until it reaches the first dielectric layer 2A in which the lower ring T3 is embedded, and a metal is filled in the opening to form the upper ring T2.

[0053] Of course, after all the dielectric layers have been formed, a ring-shaped opening may be formed and metal may be filled in the opening to form the second ring TIV.

[0054] FIG. 7 is a diagram showing a planar configuration of the combined resistor chip.

[0055] The resistor chip 10 includes, in a plan view (XY plane), a first ring 1R that surrounds the entire area where the resistor R and the processing circuit 20P are formed, and a second ring TIV that is provided below the first ring 1R (on the semiconductor substrate side). The planar shapes of the first ring 1R and the second ring TIV are approximately the same, both having rectangular annular shapes, and overlapping in a planar view. This figure is a schematic diagram, and for clarity of explanation, the first ring 1R is indicated by a dotted line. Furthermore, the resistor R, the first ring 1R, and the second ring TIV are embedded in an insulating layer provided on the semiconductor substrate, but the insulating layer is not shown.

[0056] The processing circuit 20P is formed inside a semiconductor substrate. The processing circuit 20P includes an amplifier that amplifies the voltage output from the resistor R, and an exemplary circuit configuration is as shown in FIG.

[0057] FIG. 8 is a diagram showing the vertical end face configuration of the combined resistor chip.

[0058] This resistor chip is shown in FIG. 7, and the resistor R and the processing circuit 20P are electrically connected by internal wiring TIV3. The other structures are the same as those shown in FIG. 5. Note that, when focusing only on the conductivity of the second ring TIV, the second ring TIV does not need to be ring-shaped, but may be made of a conductive material. That is, the resistor chip 10 includes a conductive material (second ring TIV) that electrically connects the semiconductor substrate 1 and the resistor R. The resistor chip 10 also includes a processing circuit 20P provided on the semiconductor substrate 1 and internal wiring TIV3 provided in the insulating layer 2 that electrically connects the resistor R and the processing circuit 20P. The potential of this electrical connection point can also be set to ground potential.

[0059] FIG. 9 is a diagram showing the vertical end face configuration of the combined resistor chip.

[0060] This figure shows a more detailed configuration of the structure shown in FIG.

[0061] The structure and material of the insulating layer 2 are basically the same as those shown in FIG. 6, but a first dielectric layer 2A is added as the bottom layer of the insulating layer 2. The structures and materials of the first protective film 4A and the second protective film 4B formed on the insulating layer 2 are also the same as those shown in FIG. 6. In the region directly above the first electrode E1, the upper dielectric layer 2A H The first protective film 4A and the second protective film 4B have been removed, exposing the upper surface of the first electrode E1. Wiring (bonding wire, wiring pattern) is connected to the upper surface of the first electrode E1 (electrode pad). The structure of the second electrode side is the same as the structure of the first electrode E1 side, and the upper surface of the second electrode E2 (FIG. 2) is exposed.

[0062] The structures and materials of the plurality of linear resistors 3, the first via electrode VE5, the second via electrode VE7, and the buried electrodes BE that constitute the resistor are the same as those shown in FIG.

[0063] The resistor chip 10 includes a first ring 1R (annular conductor) embedded in the upper region of the insulating layer 2. The first ring 1R includes a peripheral electrode 1R1, a peripheral via electrode 1R2, and a peripheral resistor 1R3. The peripheral via electrode 1R2 connects the upper surface of the peripheral electrode 1R1 to the lower surface of the peripheral resistor 1R3. The material of the peripheral electrode 1R1 may be the same as the material of the buried electrode BE. The material of the peripheral via electrode 1R2 may be the same as the material of the first via electrode VE5. The material of the resistive layer constituting the peripheral resistor 1R3 may be the same as the material of the linear resistor 3. The planar shape of the peripheral resistor 1R3 may be a continuous annular shape or an intermittent annular shape. When the peripheral resistor 1R3 has an annular shape formed by intermittently arranging multiple linear resistors, the peripheral electrode 1R1 may connect the ends of adjacent linear resistors via the peripheral via electrode 1R2.

[0064] The buried electrode BE and the peripheral electrode 1R1 are formed on the lower dielectric layer 2A. L The insulating layer 2 is formed on the semiconductor substrate 1 and is embedded in the insulating layer 2.

[0065] The first ring 1R may be configured to include only the annular peripheral electrode 1R1.

[0066] The second ring TIV comprises a plurality of rings stacked along the thickness direction of the insulating layer 2. The upper ring T2 is an annular body having a rectangular shape in a plan view, and the upper surface of the upper ring T2 is connected to the lower surface of the peripheral electrode 1R1 through the via electrode T1. The lower ring T3 is an annular body having a rectangular shape in a plan view, and the upper surface of the lower ring T3 is connected to the lower surface of the upper ring T2. An example of the material of the upper ring T2 and the lower ring T3 is Cu (copper), but other conductive materials can also be used.

[0067] The lower surface of the lower ring T3 is connected to the upper surface of another ring T5 via a via electrode T4. The other ring T5 is an annular body having a rectangular shape in a plan view, and the lower surface of the other ring T5 is connected to the upper surface of yet another ring T7 via a via electrode T6. The yet another ring T7 is an annular body having a rectangular shape in a plan view, and the lower surface of the yet another ring T7 is connected to the surface of the semiconductor substrate 1 via a via electrode T8. The semiconductor substrate 1 may have a contact region 1C1 doped with a P-type or N-type impurity to reduce resistance. The lowest via electrode T8 may be connected to the contact region 1C1. Each via electrode may be an annular body.

[0068] The first output electrode EP is formed on the upper dielectric layer 2A. H The first output electrode EP is electrically connected to a connection buried electrode BE10 provided in the insulating layer 2. The connection buried electrode BE10 is connected to the processing circuit 20P via a via electrode T1', an upper through electrode T2', a lower through electrode T3', a via electrode T4', a buried electrode T5', a via electrode T6', a buried electrode T7', and a via electrode T8', which are buried in the insulating layer 2 in this order. Therefore, the first output electrode EP is electrically connected to the processing circuit 20P via these through electrodes, via electrodes, and buried electrodes.

[0069] The second output electrode is electrically connected to the processing circuit, similarly to the first output electrode EP. That is, similarly to the first output electrode EP, the second output electrode is connected to the processing circuit 20P via a connection buried electrode (not shown) buried in the insulating layer 2, a via electrode (not shown), an upper through electrode (not shown), a lower through electrode (not shown), a via electrode (not shown), a buried electrode (not shown), a via electrode (not shown), a buried electrode (not shown), a via electrode (not shown), a buried electrode T7", and a via electrode T8", in this order.

[0070] FIG. 10 is a diagram showing the vertical end face configuration of the combined resistor chip.

[0071] The resistor chip 10 includes, in a plan view (XY plane), a first ring 1R that surrounds the entire area where the resistor R and the processing circuit 20P are formed, and a second ring TIV that is provided below the first ring 1R (on the semiconductor substrate side). The planar shapes of the first ring 1R and the second ring TIV are approximately the same, both having rectangular annular shapes, and overlapping in a planar view. This figure is a schematic diagram, and for clarity of explanation, the first ring 1R is indicated by a dotted line. Furthermore, the resistor R, the first ring 1R, and the second ring TIV are embedded in an insulating layer provided on the semiconductor substrate, but the insulating layer is not shown.

[0072] The processing circuit 20P is formed inside a semiconductor substrate. The processing circuit 20P includes an amplifier that amplifies the voltage output from the resistor R, and an exemplary circuit configuration is as shown in FIG.

[0073] In this example, in plan view, the formation region of the processing circuit 20P partially overlaps the formation region of the resistor R. In this example, the size of the resistor chip 10 can be further reduced.

[0074] FIG. 11 is a diagram showing the vertical end face configuration of the combined resistor chip.

[0075] This resistor chip is shown in FIG. 10, in which the resistor R and the processing circuit 20P are electrically connected by internal wiring TIV3 in the insulating layer 2. The other structures are the same as those shown in FIG. 5. Note that, when focusing only on the conductivity of the second ring TIV, the second ring TIV does not need to be ring-shaped, and may be made of a conductive material. That is, the resistor chip 10 includes a conductive material (second ring TIV) that electrically connects the semiconductor substrate 1 and the resistor R. The resistor chip 10 also includes a processing circuit 20P provided on the semiconductor substrate 1, and internal wiring TIV3 provided in the insulating layer 2 that electrically connects the resistor R and the processing circuit 20P.

[0076] FIG. 12 is a diagram showing a planar configuration for explaining the electrical connection relationship of the voltage dividing circuit formed on the resistor chip.

[0077] A first positive potential is applied to the first electrode E1 of the resistor chip 10 from the first input terminal HV(+), and a second negative potential is applied to the second electrode E2 from the second input terminal HV(-). Between the first electrode E1 and the second electrode E2, the first resistor RP, the first voltage detection resistor RPS, the second voltage detection resistor RNS, and the second resistor RN are connected in series. The planar shape (XY planar shape) of the resistor chip 10 is a rectangle having four side surfaces (edges: 10U, 10L, 10R, 10D), and a first ring 1R is formed along each side surface. In plan view, there is a gap between these side surfaces and the first ring 1R. In a plan view, the first dummy wiring region DM1, the first electrode E1, the first resistor RP, the first voltage detection resistor RPS, the second voltage detection resistor RNS, the second resistor RN, the second electrode E2, the first output electrode EP, the second output electrode EN, and the reference electrode EG are arranged inside the first ring 1R. The first ring 1R prevents moisture from entering the insulating layer in which the resistance layer and the electrodes are embedded, and prevents cracks from penetrating due to dicing.

[0078] The first output electrode EP is connected to a connection point (node) between the first resistor RP and the first voltage detection resistor RPS. The second output electrode EN is connected to a connection point (node) between the second resistor RN and the second voltage detection resistor RNS. The reference electrode EG is connected to a connection point (node) between the first voltage detection resistor RPS and the second voltage detection resistor RNS. These connection points can be formed by buried electrodes connecting the resistors.

[0079] FIG. 13 is a diagram showing an example of a detailed structure of a resistor portion in a voltage dividing circuit formed on a resistor chip.

[0080] The first resistor RP includes a plurality of linear resistors 3(n) (resistance layers) (n is a natural number (1, 2, 3, etc.)). The linear resistors extend linearly. In this example, each linear resistor included in the entire resistor extends along the Y-axis direction. One end of the linear resistor 3(n) is electrically connected to one end of the adjacent linear resistor 3(n+1) by a via electrode and a connection embedded electrode BE(n). The other end of the linear resistor 3(n+1) is electrically connected to the other end of the adjacent linear resistor 3(n+2) by a via electrode and a connection embedded electrode BE(n+1). The order (n) of the first resistor RP increases in value in the direction away from the first electrode E1.

[0081] The second resistor RN includes a plurality of linear resistors 3(m) (resistance layers) (m is a natural number (1, 2, 3, etc.)). The linear resistors are resistors that extend linearly. In this example, n=m. The connection relationship among the plurality of linear resistors 3(m) is the same as the connection relationship among the plurality of linear resistors 3(n). One end of the linear resistor 3(m) is electrically connected to one end of the adjacent linear resistor 3(m+1) by a via electrode and a connection embedded electrode BE(m). The other end of the linear resistor 3(m+1) is electrically connected to the other end of the adjacent linear resistor 3(m+2) by a via electrode and a connection embedded electrode BE(m+1). The order (m) of the second resistors RN increases in value in the direction away from the second electrode E2.

[0082] The first voltage detection resistor RPS includes a plurality of linear resistors 3(s) (resistive layers) (where s is a natural number (1, 2, 3...)). The linear resistor is a resistor that extends linearly. In this example, s < n. Except for the small number of linear resistors, the connection relationship of the plurality of linear resistors 3(s) is the same as that of the plurality of linear resistors 3(n), and adjacent linear resistors are electrically connected by via electrodes and embedded electrodes for connection. The order (s) regarding the first voltage detection resistor RPS may increase numerically in the direction away from the first electrode E1. The number of the plurality of linear resistors 3(s) is considerably less than the number of the linear resistors 3(n). The maximum value of s can be set, for example, to be 1 or more and 10 or less.

[0083] The second voltage detection resistor RNS includes a plurality of linear resistors 3(t) (resistive layers) (where t is a natural number (1, 2, 3...)). The linear resistor is a resistor that extends linearly. In this example, t < m and t = s. Except for the small number of linear resistors, the connection relationship of the plurality of linear resistors 3(t) is the same as that of the plurality of linear resistors 3(m), and adjacent linear resistors are electrically connected by via electrodes and embedded electrodes for connection. The order (t) regarding the second voltage detection resistor RNS may increase numerically in the direction away from the second electrode E2. The number of the plurality of linear resistors 3(t) is considerably less than the number of the linear resistors 3(m). The maximum value of t can be set, for example, to be 1 or more and 10 or less.

[0084] FIG. 14 is a diagram showing a longitudinal sectional configuration (YZ cross-section) of a portion along the line A-A in FIG. 12 or FIG. 13. FIGS. 14 to 17 correspond to the resistance chip (FIGS. 5 and 6) when a processing circuit is not formed in the semiconductor substrate 1. When a processing circuit is formed in the resistance chip, as shown in FIG. 9, the thickness of the insulating layer 2 becomes thick, and depending on the position of the longitudinal section, a configuration in which internal wiring for connection to the processing circuit is observed is obtained.

[0085] The resistor chip 10 (semiconductor device) includes a semiconductor substrate 1, an insulating layer 2, a resistor R, a first electrode E1, and a plurality of first dummy wirings 5(n) (first dummy wiring region).

[0086] The semiconductor substrate 1 may have conductivity. For example, the impurity concentration of the semiconductor substrate 1 may be 5×10 13 (cm -3 ) or more 5 × 10 14 (cm -3 The thickness of the semiconductor substrate 1 may be 50 μm or more and 800 μm or less. The material of the semiconductor substrate 1 may be silicon (Si), but it is also possible to use a compound semiconductor such as SiC or SiGe.

[0087] The resistor R is embedded in the insulating layer 2 and is formed by electrically connecting multiple resistive layers (wire resistors). The resistor R (multiple wire resistors: resistive layers) is made of a resistive material with a higher resistivity than polysilicon. Specifically, the material of the resistor R (resistive layer) is a material containing chromium (Cr) and silicon (Si), such as CrSi, CrSiC, or CrSiN. Other materials can also be used. Specifically, the material of the resistive layer constituting the resistor R can contain at least one metal compound selected from the group consisting of CrSi, CrSiN, CrSiO, TaN, and TiN. The resistive layer constituting the resistor R can be formed using a sputtering method using a target containing a resistive material. Depending on the type of material of the resistor R, a plating method can also be used. The resistor R can be made of a single resistive material or a combination of multiple resistive materials. The thickness Rd of each resistive layer constituting the resistor R can be 1 nm≦Rd≦5 nm. When the thickness Rd is equal to or less than the upper limit, the resistance value can be made sufficiently high, and when the thickness Rd is equal to or more than the lower limit, the resistance and strength of the resistance layer can be maintained.

[0088] The first electrode E1 is electrically connected to a first end (the end in the X-axis direction) of the resistor R. The lower surface of the first electrode E1 is electrically connected to the upper dielectric layer 2A. HThe first buried electrode BE1 is connected to the upper surface of the first buried electrode BE1 through a first via electrode VE1 extending downward in the upper dielectric layer 2A. H The first electrode E1 extends horizontally within the via electrode VE1, and its end is connected to the underside of one end of the resistive layer constituting the resistor R via a second via electrode (not shown). Although the resistive layer is thin, forming the resistive layer after forming the second via electrode makes it easy to contact them. The first electrode E1 can be made of a metal material such as Al (aluminum) or Cu (copper). The various dummy wiring materials may contain Al, Cu, W, or Ti, which have lower resistivity than the resistive layer. The first via electrode VE1 can be made of a high-melting-point metal such as tungsten (W), but other electrode materials can also be used. The via electrode and resistive layer are embedded in the insulating layer 2.

[0089] The plurality of first dummy wirings 5(n) are formed in the above-mentioned first dummy wiring region DM1 (FIGS. 12 and 13). The plurality of first dummy wirings 5(n) are arranged around the first electrode E1 in a plan view, and are capacitively coupled to the plurality of resistive layers of the resistor R, respectively.

[0090] FIG. 15 is a diagram showing a longitudinal cross-sectional configuration (XZ cross-section) of a portion taken along line BB in FIG. 12 or FIG.

[0091] The resistor R (first resistor RP) includes a plurality of linear resistors 3(n). Each linear resistor 3(n) extends along the Y axis. The plurality of linear resistors 3(n) are aligned along the X axis. One end of the linear resistor 3(n) and one end of the adjacent linear resistor 3(n+1) are connected to the lower dielectric layer 2A. L The first ring 1R is electrically connected to the second ring 1C through the via electrodes and the buried electrodes formed thereon. This connection structure is the same as the connection structure of the first ring 1R.

[0092] FIG. 16 is a diagram showing a longitudinal cross-sectional configuration (YZ cross-section) of a portion taken along line CC in FIG. 12 or 13. In FIG.

[0093] The resistor chip 10 includes a second electrode E2 and a plurality of second dummy wirings 5(m).

[0094] The second electrode E2 is electrically connected to the second end (the end in the X-axis direction) of the resistor R. The lower surface of the second electrode E2 is electrically connected to the upper dielectric layer 2A. H The second buried electrode BE2 is connected to the upper surface of the second buried electrode BE2 through a third via electrode VE3 extending downward in the upper dielectric layer 2A. H The second electrode E2 extends horizontally within the via electrode VE3, and its end is connected to the underside of one end of the resistive layer constituting the resistor R via another fourth via electrode (not shown). Although the resistive layer is thin, forming the resistive layer after forming the fourth via electrode makes it easy to bring them into contact. Metal materials such as Al (aluminum) or Cu (copper) can be used as the material for the second electrode E2. High-melting-point metals such as tungsten (W) can be used as the material for the third via electrode VE3, but other electrode materials can also be used.

[0095] The second dummy wirings 5(m) are formed in the second dummy wiring region DM2 (FIGS. 12 and 13) described above. The second dummy wirings 5(m) are arranged around the second electrode E2 in a plan view, and are capacitively coupled to the resistive layers of the resistor R, respectively.

[0096] FIG. 17 is a diagram showing a longitudinal cross-sectional configuration (XZ cross-section) of a portion taken along line DD in FIG. 12 or 13. In FIG.

[0097] The resistor R (second resistor RN) includes a plurality of linear resistors 3(m). Each linear resistor 3(m) extends along the Y axis. The plurality of linear resistors 3(m) are aligned along the X axis. One end of the linear resistor 3(m) and one end of the adjacent linear resistor 3(m+1) are connected to the lower dielectric layer 2A. L The first ring 1R is electrically connected to the second ring 1C through the via electrodes and the buried electrodes formed thereon. This connection structure is the same as the connection structure of the first ring 1R.

[0098] 18A and 18B are a plan view of the first type dummy wiring near the first electrode (FIG. 18A) and a plan view of the second type dummy wiring near the first electrode (FIG. 18B).

[0099] 18(A) shows a specific dummy wiring pattern. One end of this dummy wiring is electrically connected to one end (or to the buried electrode located at) of one end of a linear resistor 3 constituting resistor R (electrical connection type). The other end of this dummy wiring is electrically connected to the other end (or to the buried electrode located at) of a linear resistor 3 adjacent to the linear resistor 3 in question. Alternatively, one end of this dummy wiring is capacitively coupled to one end of a linear resistor 3 constituting resistor R (capacitive coupling type). In this case, the other end of the dummy wiring is capacitively coupled to the other end of a linear resistor 3 adjacent to the linear resistor 3 in question.

[0100] 18(B) shows another specific pattern of dummy wiring. One end of this dummy wiring is electrically connected to (the buried electrode located at) one end of the linear resistor 3 constituting the resistor R (electrical connection type). Alternatively, one end of this dummy wiring is capacitively coupled to one end of the linear resistor 3 constituting the resistor R (capacitive coupling type). The other end of this dummy wiring is located on the opposite side of the resistor R from the first electrode E1. One end of another dummy wiring is electrically connected or capacitively coupled to the other end of the linear resistor 3 adjacent to the linear resistor 3, and the other end is located on the opposite side of the resistor R from the first electrode E1. At the position opposite the resistor R from the first electrode E1, the ends of the dummy wiring face each other with a first space SP1 between them.

[0101] 19 is a plan view of a resistor chip equipped with capacitively coupled dummy wiring. Since each element is embedded in an insulating layer 2, the insulating layer located above the necessary elements is omitted from the illustration.

[0102] The first dummy wiring region DM1 includes a group of dummy wirings capacitively coupled to the first resistors RP. The first resistors RP extend along the X-axis direction as a whole. At the capacitive coupling positions between the dummy wirings and the first resistors RP, the dummy wirings extend along the Y-axis direction. That is, at the capacitive coupling positions, the longitudinal direction of the first resistors RP and the extension direction of each dummy wiring are perpendicular to each other.

[0103] The first dummy wiring region DM1 is the first electrode side region DM1 T and the first output electrode side region DM1 E An example of actual dummy wirings arranged in the first dummy wiring region DM1 is as shown in FIG.

[0104] 1st electrode side area DM1 T consists of a group of dummy wirings surrounding the first electrode E1. These dummy wirings extend along the first arrow AR1 to surround the first electrode E1. Of the dummy wirings surrounding the first electrode E1, there is a gap between the dummy wirings located at the outermost periphery and the first ring 1R (second ring TIV), and in plan view, the shortest distance between them along the Y-axis direction is ΔY. There is a gap between this dummy wiring located at the outermost periphery and the first ring 1R (second ring TIV), and the shortest distance between them along the X-axis direction ΔX can be set to ΔX = ΔY.

[0105] Assume that the voltage Vα of the linear resistor 3 located at a position ΔXα along the X-axis is, for example, Vα = 2500V. The shortest distance ΔY in the Y-axis direction between the dummy wiring 5 and the annular conductor 1R is set so that the voltage gradient (Vα / ΔY) in the region defined by ΔY is 100 (V / μm) or less (Vα / ΔY≦100 (V / μm)). By reducing the voltage gradient below this threshold, the electric field strength near the substrate side of the resistor chip is reduced, further improving the withstand voltage of the resistor chip. Since Vα / 100 (μm) ≦ ΔY (μm), when Vα = 2500V, 25 (μm) ≦ ΔY (μm) is satisfied. A Vα of 10,000V can be used as a specific instantaneous maximum voltage expected in electric vehicles or hybrid vehicles. Similarly, a lower limit of Vα can be assumed to be 500V. That is, the resistor chip can be designed with 500 V≦Vα≦10000 V. When Vα is in this range, 5 (μm)≦ΔY≦100 (μm) can be satisfied.

[0106] 1st output electrode side area DM1 E consists of a group of dummy wirings that do not surround the first electrode E1. These dummy wirings extend along the fifth arrow AR5, away from the first resistor RP, and approach the first ring 1R. There is a gap between their tips and the first ring 1R (second ring TIV) along the Y-axis direction, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY.

[0107] The second dummy wiring region DM2 includes a group of dummy wirings capacitively coupled to the second resistors RN. The second resistors RN extend along the X-axis direction as a whole. At the capacitive coupling positions between the dummy wirings and the second resistors RN, the dummy wirings extend along the Y-axis direction. That is, at the capacitive coupling positions, the longitudinal direction of the second resistors RN and the extension direction of each dummy wiring are perpendicular to each other.

[0108] The second dummy wiring region DM2 is the second electrode side region DM2 T and the second output electrode side region DM2 EAn example of actual dummy wirings arranged in the second dummy wiring region DM2 is the same as the structure symmetrical with respect to the YZ plane of the structure in FIG.

[0109] 2nd electrode side area DM2 T consists of a group of dummy wirings surrounding the second electrode E2. These dummy wirings extend along the second arrow AR2 to surround the second electrode E2. Of the dummy wirings surrounding the second electrode E2, there is a gap between the dummy wirings located on the outermost periphery and the first ring 1R (second ring TIV), and in plan view, the shortest distance between them along the Y-axis direction is ΔY. There is a gap between this dummy wiring located on the outermost periphery and the first ring 1R, and the shortest distance between them along the X-axis direction ΔX can be set to ΔX = ΔY.

[0110] 2nd output electrode side area DM2 E consists of a group of dummy wirings that do not surround the second electrode E2. These dummy wirings extend along the sixth arrow AR6 away from the second resistor RN and approach the first ring 1R, with a gap between their tips and the first ring 1R along the Y-axis direction, and the shortest distance between them along the Y-axis direction is ΔY as described above.

[0111] 20 is a plan view of a resistor chip equipped with electrically connected dummy wiring. Since each element is embedded in an insulating layer 2, the insulating layer located above the necessary elements is omitted.

[0112] The first dummy wiring region DM1 includes a group of dummy wirings electrically connected to the first resistors RP. The first resistors RP extend along the X-axis direction as a whole. At the electrical connection positions between the dummy wirings and the first resistors RP, the dummy wirings extend along the Y-axis direction. That is, at the electrical connection positions, the longitudinal direction of the first resistors RP and the extension direction of each dummy wiring are perpendicular to each other.

[0113] The first dummy wiring region DM1 is the first electrode side region DM1 T and the first output electrode side region DM1 EAn example of actual dummy wirings arranged in the first dummy wiring region DM1 is as shown in FIG.

[0114] 1st electrode side area DM1 T consists of a group of dummy wirings surrounding the first electrode E1. These dummy wirings extend along the first arrow AR1 so as to surround the first electrode E1, but are separated by a first space SP1 in the region of the first electrode E1 opposite the first resistor RP. Of the dummy wirings that extend to the position of the first space SP1, there is a gap between the dummy wirings located at the outermost periphery and the first ring 1R (second ring TIV), and in plan view, the shortest distance between them along the Y-axis direction is the above-mentioned ΔY. There is a gap between this dummy wiring located at the outermost periphery and the first ring 1R (second ring TIV), and the shortest distance between them along the X-axis direction ΔX can be set to ΔX = ΔY.

[0115] 1st output electrode side area DM1 E consists of a group of dummy wirings that do not surround the first electrode E1 and do not reach the first space SP1. These dummy wirings extend along the fifth arrow AR5, away from the first resistor RP, and approach the first ring 1R (second ring TIV). In plan view, there is a gap between their tips and the first ring 1R along the Y-axis direction, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY.

[0116] In this example, the first output electrode side region DM1 E Some of the dummy wirings in are also arranged around the first output electrode EP.

[0117] The second dummy wiring region DM2 includes a group of dummy wirings electrically connected to the second resistors RN. The second resistors RN extend along the X-axis direction as a whole. At the electrical connection positions between the dummy wirings and the second resistors RN, the dummy wirings extend along the Y-axis direction. That is, at the electrical connection positions, the longitudinal direction of the second resistors RN and the extension direction of each dummy wiring are perpendicular to each other.

[0118] The second dummy wiring region DM2 is the second electrode side region DM2 T and the second output electrode side region DM2 E An example of actual dummy wirings arranged in the second dummy wiring region DM2 is the same as the structure shown in FIG. 18(B) which is plane-symmetric with respect to the YZ plane.

[0119] 2nd electrode side area DM2 T consists of a group of dummy wirings surrounding the second electrode E2. These dummy wirings extend along the second arrow AR2 so as to surround the second electrode E2, but are separated by a second space SP2 in the region of the second electrode E2 opposite the second resistor RN. Of the dummy wirings that extend to the position of the second space SP2, there is a gap between the dummy wirings located at the outermost periphery in plan view and the first ring 1R (second ring TIV), and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY. There is a gap between this dummy wiring located at the outermost periphery and the first ring 1R (second ring TIV), and the shortest distance between them along the X-axis direction ΔX can be set to ΔX = ΔY.

[0120] 2nd output electrode side area DM2 E consists of a group of dummy wirings that do not surround the second electrode E2 and do not reach the second space SP2. These dummy wirings extend along the sixth arrow AR6 away from the second resistor RN and approach the first ring 1R (second ring TIV), and there is a gap between their tips and the first ring 1R (second ring TIV) in the Y-axis direction in plan view, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY.

[0121] In this example, the second output electrode side region DM2 E Some of the dummy wirings in are also arranged around the second output electrode EN.

[0122] The third dummy wiring region DM3 includes a group of dummy wirings electrically connected to the first voltage detection resistors RPS. At the electrical connection positions between the dummy wirings and the first voltage detection resistors RPS, the dummy wirings extend along the Y-axis direction.

[0123] The dummy wiring group included in the third dummy wiring area DM3 extends along the third arrow AR3, away from the first voltage detection resistor RPS, and approaches the first ring 1R (second ring TIV), and there is a gap between their tips and the first ring 1R along the Y-axis direction in a planar view, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY.

[0124] The fourth dummy wiring region DM4 includes a group of dummy wirings electrically connected to the second voltage detection resistors RNS. At the electrical connection positions between the dummy wirings and the second voltage detection resistors RNS, the dummy wirings extend along the Y-axis direction.

[0125] The dummy wiring group included in the fourth dummy wiring area DM4 extends along the fourth arrow AR4, away from the second voltage detection resistor RNS, and approaches the first ring 1R (second ring TIV).In a planar view, there is a gap between their tips and the first ring 1R along the Y-axis direction, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY.

[0126] The third and fourth dummy wiring regions can also be provided in a resistor chip of the type shown in FIG. 19. The number of dummy wirings surrounding the electrodes can be, for example, about K1 (e.g., K1=6). In other words, the first electrode side region DM1 T , or the second electrode side region DM2 T The number of dummy wirings coupled or connected to one long side (X-axis) of the rectangular resistor included in the rectangular resistor is K1, and may be 3≦K1≦30. The length of the dummy wiring may also be shorter the closer it is to the reference electrode EG from the first electrode E1 or the second electrode E2. The reference electrode EG may also have ground potential. When the dummy wiring and the linear resistor are located at different depths, a configuration in which the dummy wiring and the linear resistor overlap over the entire length of the linear resistor (Y-axis direction) in a plan view is possible, but from the standpoint of voltage resistance, it is considered preferable that the overlap rate between them is small (e.g., the overlap rate along the Y-axis direction is 10% or less).

[0127] 21A and 21B are a longitudinal sectional view of the second ring TIV having the first structure (FIG. 21A) and a longitudinal sectional view of the second ring TIV having the second structure (FIG. 21B).

[0128] As shown in FIG. 21(A), the second ring TIV is made of the core material TIV. C and core material TIV C The surrounding material (inner surrounding material TIV) P1 and outer surrounding material TIV P2 ) Core material TIV C is the inner peripheral material TIV located inside the annular body P1 and an outer peripheral material TIV located outside the annular body. P2 Located between the core material TIV C The inner peripheral material TIV can contain Cu or W, which have excellent electrical conductivity. P1 and outer peripheral material TIV P2 Each of the insulating layer and the insulating layer may contain TaN or TiN, which have excellent waterproof properties. This structure has the effect of providing excellent electrical conductivity and waterproof properties.

[0129] As a more specific combination, the core material TIV C Contains Cu as inner peripheral material TIV P1 and outer peripheral material TIV P2 The core material TIV may contain TaN. C Contains W as inner surrounding material TIV P1 and outer peripheral material TIV P2 TiN may be included as the ferrite.

[0130] As shown in FIG. 21(B), the second ring TIV is made of the main body material TIV. B And the main body material TIV B Protective material located on top of the TIV G It is equipped with protective material TIV G The main body material is TIV B It may be located at the bottom of the body material TIV B Contains highly conductive aluminum (Al). GThe material contains TiN, which can also function as an anti-reflection film during manufacturing. This structure has the effect of being excellent in electrical conductivity and waterproofing.

[0131] The second ring TIV can be made of aluminum (Al) alone. The second ring TIV can be made of polysilicon (with boron doping of 1×10 18 cm ―3 ~1×10 22 cm ―3 The second ring TIV may include Ru (ruthenium). (Addendum)

[0132] (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0133] [A1] A semiconductor device comprising: a semiconductor substrate 1; an insulating layer 2 provided on the semiconductor substrate 1; a resistor R embedded in the insulating layer 2; a conductive first ring 1R provided around the resistor R; and a second ring TIV provided in the insulating layer 2 and connecting the semiconductor substrate 1 and the first ring 1R in the thickness direction of the insulating layer 2.

[0134] [A2] The semiconductor device according to [A1], wherein the second ring TIV includes a conductive material.

[0135] [A3] The semiconductor device according to [A1], wherein the second ring TIV contains at least one conductive material selected from the group consisting of Cu, W, Al, Si, and TiN.

[0136] [A4] The second ring TIV is a core material TIV containing Cu or W. C and core material TIV C The surrounding material containing TaN or TiN (inner surrounding material TIV P1 and outer peripheral material TIV P2 The semiconductor device according to [A1],

[0137] [A5] The second ring TIV is made of aluminum (Al)-containing main body material TIV. B And the main body material TIV B TiN-containing protective material TIV located on top or bottom of G The semiconductor device according to [A1], comprising:

[0138] [A6] The semiconductor device according to [A1], wherein the second ring TIV includes at least one waterproof material selected from the group consisting of SiN, SiCON, and SiC.

[0139] [A7] The semiconductor device according to [A2], comprising a processing circuit 20P provided on the semiconductor substrate 1, and internal wiring TIV3 provided in the insulating layer 2 and electrically connecting the resistor R and the processing circuit 20P.

[0140] [A8] The semiconductor device according to [A7], wherein the second ring TIV surrounds the resistor R and the processing circuit 20P in plan view.

[0141] [A9] The semiconductor device according to any one of [A1] to [A8], wherein the second ring TIV comprises a plurality of rings stacked along the thickness direction of the insulating layer 2.

[0142] [A10] A semiconductor device comprising a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate, a resistor R embedded in the insulating layer 2, a conductive first ring 1R provided around the resistor R, and a conductive material (second ring TIV) provided in the insulating layer 2 and connecting the semiconductor substrate 1 and the first ring 1R in the thickness direction of the insulating layer 2.

[0143] [A11] The semiconductor device according to [A10], further comprising a processing circuit 20P provided on the semiconductor substrate 1, wherein the conductive material (second ring TIV) electrically connects the resistor R and the semiconductor substrate 1.

[0144] Various modifications to the above-described embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the present disclosure. Various features of the described embodiments may be combined. Although individual features may be included in different claims, they may also be combined. The present invention should not be construed as limited by the embodiments, but rather should be construed according to the scope of the claims. [Explanation of symbols]

[0145] 1...Semiconductor substrate 1R…1st ring 2...Insulating layer 10...Resistor chip 20...Amplifier chip 20P...Processing circuit R…Resistor T2, T3, T5, T7...Rings TIV…Second Ring TIV B …Main body material TIV C …Core material TIV G …protective material TIV P1 …Inner surrounding material 1C1...contact area 1R…1st ring 1R1...peripheral electrode 1R2...peripheral via electrode 1R3...peripheral resistor 2A...First dielectric layer 2A H ,2A L ...dielectric layer 2AB...Substrate side dielectric layer 2B: Second dielectric layer 3…Wire resistor 4...Protective film 4A…First protective film 4B…Second protective film 5...First dummy wiring (n) 5...Second dummy wiring (m) 10...Resistor chip 10a…1st inner lead 10b…Second inner lead 10c…3rd inner lead 10d…4th inner lead 10e…5th Inner Lead 10f...6th inner lead 10g...7th inner lead 10h…8th inner lead 10i…9th inner lead 10j...10th inner reed 20D...Differential amplifier 21N...Second voltage follower 21P...1st voltage follower 29...Second voltage adjustment circuit 100...Semiconductor package 101...Case 110...First die pad 120...Second die pad 200...battery BE...buried electrode BE1...first buried electrode BE2: Second buried electrode BE10...Buried electrode for connection D1...recess DM1: First dummy wiring area DM1 E ...First output electrode side area DM1 T …First electrode side area DM2: Second dummy wiring area DM2 E ...Second output electrode side area DM2 T ...Second electrode side area DM3: Third dummy wiring area DM4: Fourth dummy wiring area E1…1st electrode E2…Second electrode EG…Reference electrode EN: Second output electrode EP…1st output electrode HV(+)...First input terminal HV(-)...Second input terminal RN…Second resistor RNS: Second voltage detection resistor RP…1st resistor RPS: First voltage detection resistor SP1: First Space SP2: Second space T1,T1',T4,T4',T6,T6',T8,T8'...Via electrode T2',T3'...Through electrode T5', T7'...Buried electrodes TIV P1 …Inner peripheral material TIV P2 …Outer surrounding material TIV3…Internal wiring VCC…power supply potential VE1, VE3, VE5, VE7...Via electrodes V-MONI: Voltage monitor signal Vout: Output voltage V-REG…Reference potential ΔX…Shortest distance

Claims

1. a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a resistor embedded within the insulating layer; a first conductive ring disposed around the resistor; a second ring provided in the insulating layer and connecting the semiconductor substrate and the first ring in a thickness direction of the insulating layer; A semiconductor device comprising:

2. the second ring comprises a conductive material; The semiconductor device according to claim 1 .

3. the second ring includes at least one conductive material selected from the group consisting of Cu, W, Al, Si, and TiN; The semiconductor device according to claim 1 .

4. The second ring is a core material comprising Cu or W; a peripheral material including TaN or TiN sandwiching the core material; Prepare, The semiconductor device according to claim 1 .

5. The second ring is a body material containing Al; a protective material located above or below the body material and including TiN; Equipped with The semiconductor device according to claim 1 .

6. The second ring includes at least one waterproof material selected from the group consisting of SiN, SiCON, and SiC. The semiconductor device according to claim 1 .

7. a processing circuit provided on the semiconductor substrate; an internal wiring provided within the insulating layer and electrically connecting the resistor and the processing circuit; Equipped with The semiconductor device according to claim 2 .

8. In a plan view, the second ring surrounds the resistor and the processing circuit. The semiconductor device according to claim 7 .

9. The second ring includes a plurality of rings stacked along the thickness direction of the insulating layer. The semiconductor device according to any one of claims 1 to 8.

10. a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a resistor embedded within the insulating layer; a first conductive ring disposed around the resistor; a conductive material provided in the insulating layer and connecting the semiconductor substrate and the first ring in a thickness direction of the insulating layer; A semiconductor device comprising:

11. a processing circuit disposed on the semiconductor substrate, the conductive material electrically connecting the resistor and the processing circuit; The semiconductor device according to claim 10.

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