Semiconductor device and manufacturing method of semiconductor device
A semiconductor device with a closed curve-shaped contact ring and specific bonding pad configurations addresses integration density limits and reliability issues, ensuring stability and protection against contamination and damage.
Patent Information
- Application Number
- JP2024159166
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-03-21
- Filing Date
- 2024-09-13
- Publication Date
- 2025-10-03
AI Technical Summary
The integration density of semiconductor devices with memory cells in a single layer on a substrate has reached its limit, and there is a need for improved operational reliability and stability in three-dimensional semiconductor structures.
A semiconductor device with a substrate featuring a chip region and a seal region, including a closed curve-shaped contact ring and specific bonding pad configurations, along with a method of manufacturing that involves forming wafers with distinct regions and bonding them to create a stable structure.
The solution provides a semiconductor device with enhanced reliability and stability by preventing delamination and damage during manufacturing processes, while protecting against external contamination and moisture.
Smart Images
Figure 2025146604000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to an electronic device and a method for manufacturing an electronic device, and more particularly to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]
[0002] The integration density of a semiconductor device is primarily determined by the area occupied by a unit memory cell. Recently, the integration density of semiconductor devices in which memory cells are formed in a single layer on a substrate has reached its limit. Therefore, three-dimensional semiconductor devices in which memory cells are stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention [Problem to be solved by the invention]
[0003] One embodiment of the present invention provides a semiconductor device and a method for manufacturing the semiconductor device having a stable structure and improved characteristics. [Means for solving the problem]
[0004] A semiconductor device according to one embodiment of the present invention may include a substrate including a chip region and a seal region surrounding the chip region, a first bonding pad located on the substrate, a second bonding pad located in the chip region and bonded to the first bonding pad, an interlayer insulating film located on the first bonding pad, and a closed curve-shaped contact ring located in the seal region, extending through the interlayer insulating film and connected to the first bonding pad.
[0005] A method for manufacturing a semiconductor device according to one embodiment of the present invention may include the steps of: forming a first wafer including a peripheral circuit region and a first sealing region surrounding the peripheral circuit region, and including a first bonding pad located in the peripheral circuit region and the first sealing region; forming a second wafer including a cell region and a second sealing region surrounding the cell region, and including an interlayer insulating film located in the cell region and the second sealing region, and a second bonding pad located in the cell region; bonding the first wafer and the second wafer so that the peripheral circuit region faces the cell region and the first sealing region faces the second sealing region; forming a first opening in a closed curve shape through the interlayer insulating film of the second sealing region to expose the first bonding pad in the first sealing region; and forming a contact ring in the first opening. [Effects of the Invention]
[0006] According to the present technology, it is possible to provide a semiconductor device having a stable structure and improved reliability. [Brief explanation of the drawings]
[0007] [Figure 1A] 1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention; [Figure 1B] 1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3A] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3B] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4A] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4B] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5A] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5B] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6A] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6B] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the accompanying drawings.
[0009] 1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention.
[0010] 1A, the semiconductor device may include a substrate 100. The substrate 100 may include a chip region CHR and a seal region SER. The substrate 100 may further include a scribe lane region SLR.
[0011] The chip region CHR may be a region in which a semiconductor chip is formed. The semiconductor chips may be repeatedly formed on the substrate 100, and the chip regions CHR may be arranged in a first direction I and a second direction II intersecting the first direction I.
[0012] The scribe lane regions SLR may be located between the chip regions CHR. The scribe lane regions SLR may be regions that are cut out in a dicing process to separate the semiconductor chips. The substrate 100 can be cut along the scribe lane regions SLR to separate each of the chip regions CHR.
[0013] The seal regions SER may surround each of the chip regions CHR. A seal structure SES may be located in the seal region SER. For example, the seal structure SES located in the seal region SER may protect the chip regions CHR from external contamination or moisture. In addition, the seal structure SES may prevent or reduce damage to the chip regions CHR during cutting of the substrate 100 along the scribe lane regions SLR.
[0014] 1B, the semiconductor device may include at least one of a substrate 100, a first interconnection structure IC1, a second interconnection structure IC2, a third interconnection structure IC3, a first bonding pad 120, a second gate structure 130, a channel structure 140, a contact plug 150, a second bonding pad 160, a contact ring 170, a first contact via 180, a second contact via 190, and a source structure SS. The semiconductor device may further include at least one of a peripheral circuit PC, a slit structure SLS, an isolation film ISO, a first interlayer insulating film IL1, a second interlayer insulating film IL2, a third interlayer insulating film IL3, and a fourth interlayer insulating film IL4.
[0015] The peripheral circuit PC may be located on the substrate 100. For example, the peripheral circuit PC may be located in a chip region CHR of the substrate 100. The peripheral circuit PC may include a transistor 1. The transistor 1 may include junctions 1A and 1B, a gate electrode 1D, and a gate insulating film 1C. Here, the gate insulating film 1C may be located between the gate electrode 1D and the substrate 100. An element isolation film ISO may be located in the substrate 100, and the active region of the transistor 1 can be defined by the element isolation film ISO.
[0016] The first interconnection structure IC1 may be located on the substrate 100. For example, the first interconnection structure IC1 may be located in at least one of the chip region CHR, the seal region SER, and the scribe lane region SLR. The first interconnection structure IC1 may be located in a first interlayer insulating film IL1. Here, the first interlayer insulating film IL1 may be located on the substrate 100. The first interconnection structure IC1 may include a first via 110A and a first wiring 110B.
[0017] The first interconnection structure IC1 may be connected to the peripheral circuit PC. For example, at least one of the first vias 110A may be connected to the transistor 1. At least one of the first vias 110A may interconnect the first wirings 110B. The first interconnection structure IC1 may contact the substrate 100. For example, at least one of the first vias 110A may contact the substrate 100. The first wirings 110B may interconnect the first vias 110A. The first interconnection structure IC1 may include a conductive material such as tungsten, copper, or aluminum. The first interlayer insulating film IL1 may include an insulating material such as an oxide or a nitride.
[0018] The first bonding pad 120 may be located on the substrate 100. For example, the first bonding pad 120 may be located in the chip region CHR and the seal region SER. The first bonding pad 120 may be coupled to the peripheral circuit PC via a first interconnection structure IC1 in the chip region CHR. The first bonding pad 120 may be coupled to the substrate 100 via a first interconnection structure IC1 in the seal region SER. The first bonding pad 120 may include a conductive material such as copper.
[0019] The second bonding pad 160 may be located on the first bonding pad 120. For example, the second bonding pad 160 may be located in the chip region CHR and bonded to the first bonding pad 120. The second bonding pad 160 may be located in a second interlayer insulating film IL2. Here, the second interlayer insulating film IL2 may be located on the first interlayer insulating film IL1. The second bonding pad 160 may not be present in the sealing region SER. The second bonding pad 160 may include a conductive material such as copper. The second interlayer insulating film IL2 may include an insulating material such as an oxide or a nitride.
[0020] In a process for manufacturing a semiconductor device, the first bonding pad 120 and the second bonding pad 160 may be bonded together. The first bonding pad 120 and the second bonding pad 160 may contain copper, and the first bonding pad 120 and the second bonding pad 160 may expand during the bonding process, which may cause delamination at the bonding interface.
[0021] The bonding strength at the bonding interface can be greater as the area occupied by the first interlayer insulating film IL1 and the second interlayer insulating film IL2 becomes larger. For example, the bonding strength at the bonding interface can be greater as the area occupied by the first interlayer insulating film IL1 and the second interlayer insulating film IL2 becomes larger than the area occupied by the first bonding pad 120 and the second bonding pad 160, which contain copper.
[0022] According to one embodiment of the present invention, the second bonding pad 160 may not be present in the sealing region SER. That is, the area occupied by the first interlayer insulating film IL1 and the second interlayer insulating film IL2 in the sealing region SER may be larger than that in the chip region CHR, and the bonding strength at the bonding interface may be larger than that in the chip region CHR. Therefore, even if the first bonding pad 120 expands in the sealing region SER, peeling at the bonding interface does not occur.
[0023] The gate structure 130 may be located in the chip region CHR. The gate structure 130 may be located on the peripheral circuit PC. The gate structure 130 may include an insulating film 130A and a conductive film 130B that are alternately stacked. The insulating film 130A may include an insulating material such as an oxide, and the conductive film 130B may include a conductive material such as tungsten, polysilicon, or molybdenum. Channel structures 140 may extend through the gate structure 130. Each of the channel structures 140 may include at least one of a channel film 140A, a memory film 140B surrounding the channel film 140A, and an insulating core 140C within the channel film 140A. A slit structure SLS may extend through the gate structure 130. The slit structure SLS may include an insulating material, a conductive material, or a semiconductor material.
[0024] The conductive film 130B may be a gate line such as a source select line, a word line, or a drain select line. A source select transistor, a memory cell, or a drain select transistor may be located in the region where the channel structure 140 and the conductive film 130B intersect. As an example, at least one source select transistor, a plurality of memory cells, and at least one drain select transistor stacked along the channel structure 140 may form one memory string.
[0025] The source structure SS may be located on the gate structure 130. The source structure SS may be located on the second bonding pad 160. The source structure SS may be coupled to the channel structure 140. For example, the source structure SS may be coupled to the channel film 140A of the channel structure 140.
[0026] The contact plug 150 may be located on the peripheral circuit PC. The contact plug 150 may be located in the second interlayer insulating film IL2. The contact plug 150 may be electrically connected to the peripheral circuit PC. For example, the contact plug 150 may be electrically connected to the peripheral circuit PC via the second bonding pad 160 and the first bonding pad 120. The contact plug 150 may include a conductive material such as tungsten, copper, or aluminum.
[0027] The second interconnection structure IC2 may be located on the first interconnection structure IC1. The second interconnection structure IC2 may be located in the second interlayer insulating film IL2. The second interconnection structure IC2 may include second vias 110C and second wirings 110D. At least one of the second vias 110C may be connected to the channel structure 140. At least one of the second vias 110C may be connected to the contact plug 150. The second wirings 110D may be connected to at least one of the second vias 110C. The second interconnection structure IC2 may include a conductive material such as tungsten, copper, or aluminum.
[0028] The contact ring 170 may be located on the substrate 100. For example, the contact ring 170 may be located in the seal region SER of the substrate 100. The contact ring 170 may extend through the second interlayer insulating film IL2 and be connected to the first bonding pad 120. The contact ring 170 may have a closed curve shape that surrounds the chip region CHR along the seal region SER. The contact ring 170 may include a conductive material such as tungsten, copper, or aluminum.
[0029] The first contact via 180 may be located on the source structure SS. The first contact via 180 may be located in a third interlayer insulating film IL3. Here, the third interlayer insulating film IL3 may include an insulating material such as oxide or nitride. An upper surface of the first contact via 180 may be located at substantially the same level as an upper surface of the contact ring 170. The first contact via 180 may include substantially the same material as the contact ring 170. For example, the first contact via 180 may include a conductive material such as tungsten, copper, or aluminum.
[0030] The second contact via 190 may be located on the contact plug 150. The second contact via 190 may be located in the third interlayer insulating film IL3. An upper surface of the second contact via 190 may be located at substantially the same level as an upper surface of the contact ring 170. The second contact via 190 may include substantially the same material as the contact ring 170. For example, the second contact via 190 may include a conductive material such as tungsten, copper, or aluminum.
[0031] The third interconnection structure IC3 may be located on the second interconnection structure IC2. The third interconnection structure IC3 may be located in a fourth interlayer insulating film IL4. Here, the fourth interlayer insulating film IL4 may be located on the third interlayer insulating film IL3 and may include an insulating material such as oxide or nitride. The third interconnection structure IC3 may include third wirings 110E. However, without being limited thereto, the third interconnection structure IC3 may further include third vias. At least one of the third wirings 110E may be located on the contact ring 170. At least one of the third wirings 110E may be connectable to the first contact via 180. At least one of the third wirings 110E may be connectable to the second contact via 190. The third interconnection structure IC3 may include a conductive material such as tungsten, copper, or aluminum.
[0032] The third interconnection structure IC3, the contact ring 170, the first bonding pad 120, and the first interconnection structure IC1 in the seal region SER may constitute a seal structure SES. The seal structure SES may protect the chip region CHR from external contamination and moisture. The seal structure SES may also prevent or reduce cracks from occurring in the chip region CHR during the process of cutting the substrate 100 along the scribe lane region SLR.
[0033] According to the above-described structure, the semiconductor device may include a contact ring 170 having a closed curve shape that surrounds the chip region CHR along the seal region SER of the substrate 100. The semiconductor device may also include a seal structure SES that includes the contact ring 170, a first interconnection structure IC1, a third interconnection structure IC3, and a first bonding pad 120. The seal structure SES can prevent or reduce damage to the chip region CHR from external impact, contamination, or moisture during the manufacturing process of the semiconductor device.
[0034] In addition, the second bonding pad 160 may not be present in the seal region SER, and the area occupied by the first interlayer insulating film IL1 and the second interlayer insulating film IL2 may be relatively larger than that of the chip region CHR, so that peeling does not occur during the bonding process between the first bonding pad 120 and the second bonding pad 160.
[0035] 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The following description will omit any content that overlaps with the content previously described.
[0036] 2, a first wafer including a peripheral circuit region and a first sealing region surrounding the peripheral circuit region may be formed (S210). A peripheral circuit may be formed in the peripheral circuit region. First bonding pads may be formed in the peripheral circuit region and the first sealing region.
[0037] Next, a second wafer including a cell region and a second sealing region surrounding the cell region may be formed (S220). A gate structure and a channel structure extending through the gate structure may be formed in the cell region. An interlayer insulating film may be formed in the cell region and the second sealing region. A contact plug may be formed in the cell region, and a second bonding pad may be formed.
[0038] Next, the first wafer and the second wafer can be bonded (S230). For example, the first wafer and the second wafer can be bonded so that the peripheral circuit region and the cell region face each other and the first sealing region and the second sealing region face each other. Here, the first bonding pad in the peripheral circuit region can be bonded to the second bonding pad in the cell region. The first bonding pad in the first sealing region can be bonded to the interlayer insulating film in the second sealing region.
[0039] Next, a seal structure may be formed (S240). For example, a contact ring may be formed extending through the interlayer insulating film in the second seal region and connected to the first bonding pad in the first seal region. The contact ring may be formed in a closed curve shape surrounding the peripheral circuit region and the cell region. The contact ring in the second seal region and the third interconnection structure may constitute a seal structure together with the first bonding pad and the first interconnection structure in the first seal region. The seal structure may protect the peripheral circuit region and the cell region from external contamination and moisture.
[0040] Next, the wafer can be cut along the scribe lane area (S250). When cutting the wafer, the peripheral circuit area and the cell area may be damaged. The seal structure can prevent or reduce damage to the peripheral circuit area and the cell area during the wafer cutting process.
[0041] 3A to 7 are diagrams illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. The following description will omit content that overlaps with the content previously described.
[0042] 3A and 3B, a first wafer WF1 may be formed. For example, the first wafer WF1 may include a peripheral circuit region PER and a first seal region SER1 surrounding the peripheral circuit region PER. A scribe lane region SLR may be located between the peripheral circuit regions PER.
[0043] The first wafer WF1 may include a first substrate 300A. A peripheral circuit PC may be formed on the first substrate 300A. The peripheral circuit PC may be formed in a peripheral circuit region PER. The peripheral circuit PC may include a transistor 1. An element isolation film ISO may be formed in the first substrate 300A to define an active region of the transistor 1.
[0044] Next, a first interconnection structure IC1 may be formed on the first substrate 300A. The first interconnection structure IC1 may be formed in the peripheral circuit region PER and the first sealing region SER1. The first interconnection structure IC1 may be formed in a first interlayer insulating film IL1. Here, the first interlayer insulating film IL1 may be formed on the first substrate 300A. The first interconnection structure IC1 may include a first via 310A and a first wiring 310B. The first via 310A may be connected to the peripheral circuit PC. The first via 310A may be connected to the first wiring 310B. The first via 310A may contact the first substrate 300A. The first interconnection structure IC1 may include a conductive material such as tungsten, copper, or aluminum. The first interlayer insulating film IL1 may include an insulating material such as an oxide.
[0045] Next, first bonding pads 320 may be formed in the peripheral circuit region PER and the first sealing region SER1. For example, the first bonding pads 320 may be formed on the first interconnection structure IC1. The first bonding pads 320 may be formed in the first interlayer insulating film IL1. At least one of the first bonding pads 320 may be connected to the peripheral circuit PC via the first interconnection structure IC1. The first bonding pads 320 may include a conductive material such as copper.
[0046] 4A and 4B, a second wafer WF2 may be formed. For example, the second wafer WF2 may include a cell region CER and a second seal region SER2 surrounding the cell region CER. A scribe lane region SLR may be located between the cell regions CER.
[0047] The second wafer WF2 may include a second substrate 300B. A first material film 330A and a second material film 330B may be alternately stacked on the second substrate 300B to form a stacked structure 330S. Here, the first material film 330A may include an insulating material such as an oxide, and the second material film 330B may include a sacrificial material such as a nitride. Channel structures 340 may be formed extending into the second substrate 300B through the stacked structure 330S. Each of the channel structures 340 may include a channel film 340A, a memory film 340B surrounding the channel film 340A, and an insulating core 340C within the channel film 340A.
[0048] Next, a slit SL may be formed through the stack 330S. The second material film 330B of the stack 330S may be replaced with a third material film 330C through the slit SL. This may define a gate structure 330G including alternatingly stacked first and third material films 330A and 330C. Here, the third material film 330C may include a conductive material, such as tungsten. For reference, if the second material film 330B includes a conductive material, the process of replacing the second material film 330B with the third material film 330C may be omitted. Next, a slit structure SLS may be formed within the slit SL. The slit structure SLS may include an insulating material, a conductive material, or a semiconductor material.
[0049] A second interlayer insulating film IL2 may be formed on the second substrate 300B. For example, the second interlayer insulating film IL2 may be formed in the cell region CER and the second sealing region SER2. Contact plugs 350 may be formed on the second substrate 300B. The contact plugs 350 may be formed in the second interlayer insulating film IL2. The contact plugs 350 may include a conductive material such as tungsten, copper, or aluminum. The second interlayer insulating film IL2 may include an insulating material such as an oxide or a nitride.
[0050] Next, a third interlayer insulating film IL3 may be formed on the second interlayer insulating film IL2. Next, a second interconnection structure IC2 may be formed in the cell region CER. For example, the second interconnection structure IC2 may be formed to be connected to at least one of the channel structure 340 and the contact plug 350. The second interconnection structure IC2 may not be formed in the second sealing region SER2. The second interconnection structure IC2 may include a second via 310C and a second wiring 310D. The second interconnection structure IC2 may include a conductive material such as tungsten, copper, or aluminum. The third interlayer insulating film IL3 may include an insulating material such as an oxide or a nitride.
[0051] Next, a second bonding pad 360 may be formed in the cell region CER. For example, the second bonding pad 360 may be formed to be connected to the second interconnection structure IC2. The second interconnection structure IC2 does not necessarily have to be formed in the second sealing region SER2. The second bonding pad 360 may be formed in the third interlayer insulating film IL3. The second bonding pad 360 may include a conductive material such as copper.
[0052] The second interlayer insulating film IL2 and the third interlayer insulating film IL3 may be formed in the second sealing region SER2. That is, structures other than the second interlayer insulating film IL2 and the third interlayer insulating film IL3 may not be formed in the second sealing region SER2. For example, the second bonding pad 360 may not be formed in the second sealing region SER2. Therefore, in a subsequent process, the third interlayer insulating film IL3 and the second interlayer insulating film IL2 may be etched to form a first opening for forming a contact ring.
[0053] 5A and 5B, the first wafer WF1 and the second wafer WF2 can be bonded together. For example, the first wafer WF1 and the second wafer WF2 can be bonded together so that the peripheral circuit region PER of the first wafer WF1 faces the cell region CER of the second wafer WF2, and the first sealing region SER1 of the first wafer WF1 faces the second sealing region SER2 of the second wafer WF2. That is, the first bonding pad 320 of the peripheral circuit region PER can be bonded to the second bonding pad 360 of the cell region CER, and the first interlayer insulating film IL1 on which the first bonding pad 320 of the first sealing region SER1 is formed can be bonded to the third interlayer insulating film IL3 of the second sealing region SER2. Here, the peripheral circuit region PER and the cell region CER can be defined as a chip region CHR, and the first sealing region SER1 and the second sealing region SER2 can be defined as a sealing region SER.
[0054] During the bonding process between the first wafer WF1 and the second wafer WF2, the first bonding pad 320 and the second bonding pad 360 may expand. In this case, delamination may occur at the bonding interface. The bonding strength at the bonding interface may increase as the areas occupied by the first interlayer insulating film IL1 and the third interlayer insulating film IL3 increase. For example, the bonding strength at the bonding interface may increase as the areas occupied by the first interlayer insulating film IL1 and the second interlayer insulating film IL3 increase compared to the areas occupied by the first bonding pad 320 and the second bonding pad 360, which contain copper.
[0055] According to one embodiment of the present invention, the second bonding pad 360 may not be formed in the second sealing region SER2. In this case, the area occupied by the first interlayer insulating film IL1 and the third interlayer insulating film IL3 in the sealing region SER is relatively larger than that in the chip region CHR, and the bonding strength at the bonding interface may be relatively larger than that in the chip region CHR. Therefore, even if the first bonding pad 320 expands during bonding, peeling at the bonding interface does not occur.
[0056] Next, the second substrate 300B may be removed. Next, a source structure SS connected to the channel structure 340 may be formed. Before forming the source structure SS, the memory film 340B of the channel structure 340 may be partially removed to expose the channel film 340A. A fourth interlayer insulating film IL4 may be formed on the second interlayer insulating film IL2. For example, the fourth interlayer insulating film IL4 may be formed on the contact plug 350. The fourth interlayer insulating film IL4 may include an insulating material such as an oxide or a nitride.
[0057] 6A and 6B, a contact ring 370 may be formed on the first bonding pad 320. First, a first opening OP1 having a closed curve shape may be formed through the fifth interlayer insulating film IL5, the fourth interlayer insulating film IL4, the second interlayer insulating film IL2, and the third interlayer insulating film IL3 in the second sealing region SER2 to expose the first bonding pad 320 in the first sealing region SER1. Therefore, the first opening OP1 may be formed in the sealing region SER surrounding the chip region CHR. Next, a contact ring 370 may be formed in the first opening OP1. The contact ring 370 may include a conductive material such as tungsten, copper, or aluminum. Before forming the contact ring 370, a fifth interlayer insulating film IL5 may be formed on the fourth interlayer insulating film IL4. The fifth interlayer insulating film IL5 may include an insulating material such as an oxide or a nitride.
[0058] A first contact via 380 connected to the source structure SS may be formed. First, a second opening OP2 exposing the source structure SS may be formed. For example, the second opening OP2 exposing the source structure SS may be formed through a fifth interlayer insulating film IL5. Next, the first contact via 380 may be formed in the second opening OP2. The first contact via 380 may include a conductive material such as tungsten, copper, or aluminum.
[0059] A second contact via 390 connected to the contact plug 350 may be formed. First, a third opening OP3 exposing the contact plug 350 may be formed. For example, the third opening OP3 exposing the contact plug 350 may be formed through a fifth interlayer insulating film IL5 and a fourth interlayer insulating film IL4. Next, a second contact via 390 may be formed in the third opening OP3. The second contact via 390 may include a conductive material such as tungsten, copper, or aluminum.
[0060] When forming the first opening OP1, the second opening OP2 and the third opening OP3 can be formed. That is, when forming the first opening OP1, the second opening OP2 can be formed. When forming the first opening OP1, the third opening OP3 can be formed. However, this is not limitative, and the second opening OP2 and the third opening OP3 can be formed after forming the first opening OP1. Alternatively, the first opening OP1 can be formed after forming the second opening OP2 and the third opening OP3.
[0061] When forming the contact ring 370, the first contact via 380 and the second contact via 390 may be formed. That is, when forming the contact ring 370, the first contact via 380 may be formed. When forming the contact ring 370, the second contact via 390 may be formed. For example, a conductive material may be formed to fill the first opening OP1, the second opening OP2, and the third opening OP3. Next, the contact ring 370, the first contact via 380, and the second contact via 390 may be formed by planarizing the fifth interlayer insulating film IL5 to expose the top surface thereof. Therefore, the contact ring 370, the first contact via 380, and the second contact via 390 may include substantially the same material. For example, the contact ring 370, the first contact via 380, and the second contact via 390 may include a conductive material such as tungsten, copper, or aluminum.
[0062] Next, a third interconnection structure IC3 may be formed. The third interconnection structure IC3 may be formed on the contact ring 370, the first contact via 380, and the second contact via 390. Here, the third interconnection structure IC3 may be formed in a sixth interlayer insulating film IL6. The sixth interlayer insulating film IL6 may be formed on a fifth interlayer insulating film IL5. The third interconnection structure IC3 may include a third wiring 310E. However, without being limited thereto, the third interconnection structure IC3 may further include a third via. The third interconnection structure IC3 may include a conductive material such as tungsten, copper, or aluminum.
[0063] In the seal region SER, the third interconnection structure IC3, the contact ring 370, the first bonding pad 320, and the first interconnection structure IC1 may form a seal structure SES. The seal structure SES may protect the chip region CHR from external contamination and moisture. The seal structure SES may prevent or reduce damage to the chip region CHR in subsequent processes.
[0064] 7, the first wafer WF1 and the second wafer WF2 can be cut along the scribe lane region SLR. By cutting the first wafer WF1 and the second wafer WF2 along the scribe lane region SLR, the chip region CHR can be separated.
[0065] During the cutting process, cracks may occur in the chip region CHR. According to one embodiment of the present invention, a contact ring 370 having a closed curve shape may be formed in the seal region SER surrounding the chip region CHR. The third interconnection structure IC3, the contact ring 370, the first bonding pad 320, and the first interconnection structure IC1 may constitute a seal structure SES. Therefore, the seal structure SES can prevent or reduce damage to the chip region CHR. The seal structure SES can also protect the chip region CHR from external contamination and moisture after cutting. For example, the seal structure SES can prevent or reduce damage to the chip region CHR from external contamination and moisture.
[0066] According to the manufacturing method described above, it is not necessary to form the second bonding pad 360 in the second sealing region SER2, so peeling does not occur at the bonding interface during the process of bonding the first wafer WF1 and the second wafer WF2.
[0067] A contact ring 370 may be formed along the seal region SER to surround the chip region CHR. The contact ring 370 may constitute a seal structure SES together with the third interconnection structure IC3, the first bonding pad 320, and the first interconnection structure IC1. The seal structure SES may protect the chip region CHR from external contamination and moisture. The seal structure SES may also prevent or reduce damage to the chip region CHR during the process of cutting the first wafer WF1 and the second wafer WF2.
[0068] While the embodiments according to the technical concept of the present invention have been described above with reference to the accompanying drawings, these are merely for the purpose of illustrating the embodiments according to the concept of the present invention, and the present invention is not limited to the above-described embodiments. Various substitutions, modifications, and alterations to the embodiments may be made by a person skilled in the art to which the present invention pertains, within the scope of the technical concept of the present invention as set forth in the claims, and these also fall within the scope of the present invention. [Explanation of symbols]
[0069] 100, 300A, 300B: PCB 110A, 110C, 310A, 310C: Via 110B, 110D, 110E, 310B, 310D, 310E: Wiring 120, 160, 320, 360: Bonding pads 130, 330G: Gate structure 130A: insulating film, 130B: conductive film 140, 340: channel structure, 140A, 340A: channel membrane 140B, 340B: memory film, 140C, 340C: insulating core 150, 350: Contact plug, 170, 370: Contact ring 180, 190, 380, 390: Contact vias, 330S: Laminates 330A: First material film, 330B: Second material film 330C: Third material film, OP: Opening IC: interconnection structure, PC: peripheral circuit ISO: element isolation film, IL: interlayer insulating film SL: Slit, SLS: Slit structure SS: source structure, WF: wafer PER: Peripheral circuit area, CER: Cell area CHR: Chip area, SER: Seal area SLR: Scribe lane area, SES: Seal structure
Claims
1. a substrate including a chip area and a seal area surrounding the chip area; a first bonding pad located on the substrate; a second bonding pad located in the chip area and bonded to the first bonding pad; an interlayer insulating film located on the first bonding pad; a contact ring having a closed curve shape, the contact ring being located in the sealing region, extending through the interlayer insulating film, and connected to the first bonding pad; A semiconductor device comprising:
2. the contact ring has a closed curve shape that surrounds the tip region along the seal region; The semiconductor device according to claim 1 .
3. a source structure located on the second bonding pad; a first contact via located on the source structure; The semiconductor device according to claim 1 , further comprising:
4. the contact ring comprises substantially the same material as the first contact via; The semiconductor device according to claim 3 .
5. the contact ring and the first contact via comprise tungsten, copper, or aluminum; The semiconductor device according to claim 4 .
6. an upper surface of the contact ring located at substantially the same level as an upper surface of the first contact via; The semiconductor device according to claim 4 .
7. peripheral circuits located in the chip area; contact plugs located on the peripheral circuit; a second contact via located on the contact plug; The semiconductor device according to claim 1 , further comprising:
8. The contact plug is electrically connected to the peripheral circuit. The semiconductor device according to claim 7 .
9. the contact ring comprises substantially the same material as the second contact via; The semiconductor device according to claim 7 .
10. the contact ring and the second contact via comprise tungsten, copper, or aluminum; The semiconductor device according to claim 9 .
11. an upper surface of the contact ring located at substantially the same level as an upper surface of the second contact via; The semiconductor device according to claim 7 .
12. a gate structure located in the chip region; a channel structure extending through the gate structure; a source structure located on the gate structure. The semiconductor device according to claim 1 .
13. the channel structure is coupled to the source structure; The semiconductor device according to claim 12.
14. forming a first wafer including a peripheral circuit region and a first sealing region surrounding the peripheral circuit region, the first wafer including first bonding pads located in the peripheral circuit region and the first sealing region; forming a second wafer including a cell region and a second sealing region surrounding the cell region, the second wafer including an interlayer insulating film located in the cell region and the second sealing region, and a second bonding pad located in the cell region; bonding the first wafer and the second wafer together so that the peripheral circuit region faces the cell region and the first seal region faces the second seal region; forming a first opening having a closed curve shape through the interlayer insulating film in the second sealing region to expose the first bonding pad in the first sealing region; forming a contact ring within the first opening; A method for manufacturing a semiconductor device comprising:
15. The step of bonding the first wafer and the second wafer includes: bonding the first bonding pad in the peripheral circuit region to the second bonding pad in the cell region, and bonding the first bonding pad in the first sealing region to the interlayer insulating film in the second sealing region; The method for manufacturing a semiconductor device according to claim 14.
16. The second wafer is A substrate; a stack positioned on the substrate; and a channel structure extending through the laminate into the substrate; The method for manufacturing a semiconductor device according to claim 14, comprising:
17. removing the substrate after bonding the first wafer and the second wafer; forming a source structure coupled to the channel structure; forming a second opening exposing the source structure; forming a first contact via in the second opening; The method for manufacturing a semiconductor device according to claim 16, further comprising:
18. When forming the first opening, the second opening is formed. The method for manufacturing a semiconductor device according to claim 17.
19. forming the first opening and then forming the second opening; The method for manufacturing a semiconductor device according to claim 17.
20. When forming the contact ring, the first contact via is formed. The method for manufacturing a semiconductor device according to claim 17.
21. the contact ring comprises substantially the same material as the first contact via; The method for manufacturing a semiconductor device according to claim 17.
22. the contact ring and the first contact via comprise tungsten, copper, or aluminum; The method for manufacturing a semiconductor device according to claim 21.
23. The second wafer is A substrate; a contact plug located on the substrate; The method for manufacturing a semiconductor device according to claim 14, comprising:
24. forming a third opening exposing the contact plug after bonding the first wafer and the second wafer; forming a second contact via in the third opening; The method for manufacturing a semiconductor device according to claim 23, further comprising:
25. When forming the first opening, the third opening is formed. The method for manufacturing a semiconductor device according to claim 24.
26. After forming the first opening, the third opening is formed. The method for manufacturing a semiconductor device according to claim 24.
27. forming the second contact via when forming the contact ring; The method for manufacturing a semiconductor device according to claim 24.
28. the contact ring comprises substantially the same material as the second contact via; The method for manufacturing a semiconductor device according to claim 24.
29. the contact ring and the second contact via comprise tungsten, copper, or aluminum; 29. The method for manufacturing a semiconductor device according to claim 28.