Semiconductor device assembly including monolithic silicon structure for thermal dissipation and method of making the same

Abstract

To provide improved thermal management.SOLUTION: A semiconductor assembly includes: a first semiconductor device including an upper surface; a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface into a body of the monolithic silicon structure; a second semiconductor device directly coupled to the first semiconductor device and disposed in the cavity such that a rear surface and a plurality of side walls of the second semiconductor device are completely enclosed within the cavity; and a third semiconductor device disposed on the top surface of the monolithic silicon structure. The monolithic silicon structure includes a plurality of TSVs. The plurality of TSVs extend between the cavity and the top surface of the monolithic silicon structure, and electrically couple the second semiconductor device to the third semiconductor device.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] Cross-reference to related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 274,427, filed November 1, 2021, the disclosure of which is incorporated herein by reference in its entirety.

[0002] This application contains subject matter related to a U.S. patent application entitled "SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MONOLITHIC SILICON STRUCTURES FOR THERMAL DISSIPATION AND METHODS OF MAKING THE SAME" filed on November 1, 2021 by Kunal R. Parekh. The related applications, the disclosures of which are incorporated herein by reference, are assigned to Micron Technology, Inc. and are identified as U.S. Application Nos. 63 / 274,426 and 63 / 274,447.

[0003] Technical Field FIELD OF THE DISCLOSURE The present disclosure relates generally to semiconductor device assemblies, and more particularly to semiconductor device assemblies including monolithic silicon structures for heat dissipation and methods for fabricating the same. [Background technology]

[0004] Microelectronic devices typically have a die (i.e., chip) that contains an integrated circuit with a high density of very small components. The die typically includes an array of very small bond pads that are electrically connected to the integrated circuit. Bond pads are external electrical contacts through which supply voltages, signals, etc., are transferred to and from the integrated circuit. After the dies are formed, they are "packaged" to connect the bond pads to a larger array of electrical terminals that can be more easily connected to various power, signal, and ground lines. The conventional process for packaging a die involves electrically connecting the bond pads on the die to an array of leads, ball pads, or other types of electrical terminals and encapsulating the die to protect it from environmental factors (e.g., moisture, particulates, static electricity, and physical influences). [Brief explanation of the drawings]

[0005] [Figure 1] 1 is a simplified schematic cross-sectional view of a monolithic silicon structure for heat dissipation according to one embodiment of the present disclosure. [Figure 2] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 3] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 4] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 5] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 6] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 7] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 8] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 9] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 10] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 11] 1A-1C are simplified schematic cross-sectional views of a monolithic silicon structure for heat dissipation at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 12] 1A-1C are simplified schematic cross-sectional views of a monolithic silicon structure for heat dissipation at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 13] 1A-1C are simplified schematic cross-sectional views of a monolithic silicon structure for heat dissipation at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 14] 1A-1C are simplified schematic cross-sectional views of a monolithic silicon structure for heat dissipation at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 15] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 16] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 17] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 18] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 19]1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 20] 1A-1D are simplified schematic cross-sectional views of a semiconductor device assembly at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 21] 1A-1C are simplified schematic cross-sectional views of a monolithic silicon structure for heat dissipation at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 22] 1A-1C are simplified schematic cross-sectional views of a monolithic silicon structure for heat dissipation at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 23] 1A-1C are simplified schematic cross-sectional views of a monolithic silicon structure for heat dissipation at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 24] 1A-1C are simplified schematic cross-sectional views of a monolithic silicon structure for heat dissipation at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 25] 1A-1C are simplified schematic cross-sectional views of a monolithic silicon structure for heat dissipation at various stages of a manufacturing process according to an embodiment of the present disclosure. [Figure 26] 1 is a simplified schematic cross-sectional view of a semiconductor device assembly according to one embodiment of the present disclosure. [Figure 27] FIG. 1 is a schematic diagram illustrating a system including a semiconductor device assembly configured in accordance with one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] Specific details of several embodiments of semiconductor devices and related systems and methods are described below. Those skilled in the relevant art will recognize that appropriate steps of the methods described herein may be performed at the wafer level or the die level. Thus, depending on the context, the term "substrate" may refer to a wafer-level substrate or a singulated die-level substrate. Furthermore, unless the context dictates otherwise, the structures disclosed herein may be formed using conventional semiconductor fabrication techniques. Materials may be deposited using, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed using, for example, plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0007] Some semiconductor device assemblies include structures configured to assist in the extraction of heat from one or more semiconductor devices within the assembly. These structures are often formed from metals with high thermal conductivity, such as copper, silver, aluminum, or alloys thereof. Because the coefficient of thermal expansion (CTE) of these metals can differ significantly from the CTE of the semiconductor devices within the assembly, delamination, cracking, or other types of mechanical damage due to thermal cycling can pose challenges to these assemblies. Furthermore, the manufacturing techniques used to form structures from these metals and to shape them to accommodate additional devices within the assembly require different tooling than those used for most other assembly processes, which can significantly increase the cost of the assembly in which they are incorporated.

[0008] To address these and other drawbacks, various embodiments herein provide a semiconductor device assembly having a monolithic silicon structure for heat dissipation disposed between a surface of a lower die of a multi-die structure and an outer (e.g., upper) surface of the assembly. The monolithic silicon structure may include a cavity extending partially or completely therethrough, within which an additional semiconductor device (e.g., die, die stack, package, assembly, etc.) may be disposed. The additional semiconductor device may be electrically coupled (e.g., by oxide-oxide bonding, hybrid bonding, adhesive, interconnect, etc.) to the same surface of the lower die to which the monolithic silicon structure is attached. The monolithic silicon structure, due to its high thermal conductivity and close matching of its thermal expansion coefficient to that of the lower die, provides improved thermal management without the risk of damage associated with other thermal management structures.

[0009] 1 is a simplified schematic partial cross-sectional view of a monolithic silicon structure 100 according to one embodiment of the present disclosure. The monolithic silicon structure 100 includes one or more cavities (two are shown) extending at least partway through the thickness (e.g., into the body) of the monolithic silicon structure 100. The structure 100 may be formed, for example, from a blank silicon wafer having cavities formed therein (e.g., by masking and directional etching, laser ablation, etc.). The structure 100 may be maintained at the wafer level for subsequent wafer-level processing steps, or may optionally be singulated prior to subsequent processing steps.

[0010] According to one aspect of the present disclosure, a monolithic silicon structure 100 may be pre-loaded with semiconductor devices within its cavities prior to incorporation into a larger semiconductor device assembly. FIG. 2 is a simplified schematic cross-sectional view of a monolithic silicon structure 100 having several semiconductor devices disposed therein according to one embodiment of the present disclosure. As can be seen with reference to FIG. 2 , semiconductor devices 102 (e.g., individual dies, vertical stacks of interconnected dies, device packages, device assemblies, etc.) are disposed within cavities in the monolithic silicon structure 100. Each semiconductor device 102 may be secured within a corresponding cavity by an adhesive (e.g., thermal interface material) between a backside surface of the semiconductor device and an opposing inner surface of the cavity. The cavities may be sized such that a small gap 103 (optionally filled, for example, with an adhesive, underfill, encapsulant, etc.) remains surrounding the semiconductor device 102 to facilitate the process of disposing the semiconductor device 102 within the cavity. In other embodiments, the gap 103 may be minimized or even eliminated through careful matching of the outer dimensions of the semiconductor device 102 and the cavity. To facilitate incorporation of the semiconductor device 102 and the monolithic silicon structure 100 into a larger assembly, a redistribution layer 104 including one or more thermal pads 105 (e.g., comprising copper, silver, aluminum, or other metal compatible with metal-metal bonding operations) aligned with the monolithic silicon structure 100 and one or more interconnects 106 (e.g., pads, pillars, UBMs, pins, solder balls, etc.) operably coupled to the semiconductor device 102 may be formed. In other embodiments, the redistribution layer may be omitted, and the semiconductor device 102 may be provided with interconnects (e.g., coplanar with the bonding surface of the monolithic silicon structure 100) prior to mounting in the monolithic silicon structure 100.

[0011] Referring to FIG. 3 , the packaged monolithic silicon structure 100 is shown aligned for bonding to another semiconductor device (e.g., the aforementioned lower semiconductor device in an assembly) according to one embodiment of the present disclosure. The lower semiconductor device 110 includes a dielectric layer 109 having electrical contacts 107 and thermal contacts 108 disposed thereon. The packaged monolithic silicon structure 100 can be bonded to the lower semiconductor device 110 such that the thermal pad 105 is bonded to the thermal contact 107 and the interconnects 106 are bonded to the electrical contacts 108 to form a semiconductor device assembly 400, as shown according to one embodiment of the disclosure in FIG. 4 . The bonding operation can be a hybrid bonding operation in which a dielectric-dielectric bond (e.g., an oxide-oxide bond) is formed between the dielectric of the redistribution layer 104 and the dielectric layer 109 formed above the lower semiconductor device 110, and a metal-metal bond is formed between the corresponding thermal pads 105 and thermal contacts 107, and between the corresponding interconnects 106 and electrical contacts 108.

[0012] Although in the foregoing exemplary embodiment, the semiconductor device assembly 400 is described as being formed through a hybrid bonding operation, in other embodiments, the bond between the mounted monolithic silicon structure and the underlying semiconductor device may be achieved using an adhesive layer (e.g., a thermal interface material (TIM)), solder interconnects with or without underfill, or any other bonding method familiar to those skilled in the art.

[0013] According to additional aspects of the present disclosure, the semiconductor device assembly 400 may optionally undergo further processing to remove portions of the monolithic silicon structure 100 overlying the cavities in which the semiconductor devices 102 are disposed in order to reduce the height of the assembly and / or provide additional connectivity options. In this regard, Figure 5 is a simplified schematic cross-sectional view of a semiconductor device assembly 500 in which an assembly such as that shown in Figure 4 has undergone a backside thinning operation (e.g., by chemical mechanical polishing (CMP), grinding, etc.) to remove a portion of material from the monolithic silicon structure 100 to expose the backside of the semiconductor devices 102 and to reduce the overall height of the assembly 500.

[0014] In embodiments in which the semiconductor device 102 includes a backside contact for further connectivity, removing a portion of material from the monolithic silicon structure 100 overlying the backside of the semiconductor device 102 may allow additional devices to be incorporated into the semiconductor device assembly. One such configuration is shown in FIG. 6, which illustrates a simplified schematic cross-sectional view of a semiconductor device assembly 600. Referring to FIG. 6, an assembly such as that shown in FIG. 5 has an additional semiconductor device 111 (e.g., an individual die, a vertical stack of interconnected die, a device package, a device assembly, etc.) connected to the exposed backside contact of the semiconductor device 102 (e.g., through conventional flip-chip interconnects, a solder ball array, a hybrid bond, etc.). The additional semiconductor device 111 may then be encapsulated with a layer of molding material 112 to provide it with mechanical protection.

[0015] Alternatively, rather than individually connecting additional semiconductor devices to the exposed backside contacts of semiconductor device 102 as shown in Figure 6, in another embodiment, one or more additional pre-mounted monolithic silicon structures (e.g., as shown in Figure 2) can be bonded to semiconductor assembly 500 shown in Figure 5 to provide an assembly with a high density of devices while maintaining good thermal performance. One such assembly is shown in Figure 7, which shows a simplified schematic cross-sectional view of a semiconductor device assembly 700, in which an assembly such as that shown in Figure 5 has additional monolithic silicon structures 113 mounted with bonded semiconductor devices.

[0016] As will be readily understood by those skilled in the art, in accordance with one aspect of the present disclosure, the process illustrated in FIGS. 5 and 7 may be repeated iteratively so that the additional packaged monolithic silicon structure may itself undergo another backside thinning operation to expose the backside contacts of the semiconductor devices therein for bonding to yet another packaged monolithic silicon structure.

[0017] Alternatively or additionally, rather than a backside thinning operation that completely removes the material of the monolithic silicon structure covering the backside of the semiconductor device mounted within the cavity, in another embodiment, the material of the monolithic silicon structure covering the backside of the semiconductor device mounted within the cavity need only be thinned sufficiently to allow the formation of a via (e.g., a through-silicon via (TSV)) through the thinned material to connect to the backside contact of the semiconductor device. This can be more easily understood with reference to Figure 8, which shows an assembly such as that of Figure 4 that has undergone a backside thinning operation that removes a portion of the material covering the backside of the semiconductor device within the cavity, and that has also undergone a TSV formation operation (e.g., forming an opening through the silicon material, passivating the opening, removing the passivation from the bottom of the opening to expose the backside contact, plating a conductor into the opening, etc.) to provide a TSV 114 extending through the thinned material to contact the backside contact of the semiconductor device to facilitate further connectivity.

[0018] 9, there is shown a simplified schematic cross-sectional view of a semiconductor device assembly 900 in which an assembly such as that shown in FIG. 8 has an additional semiconductor device 111 (e.g., an individual die, a vertical stack of interconnected dies, a device package, a device assembly, etc.) connected to a TSV 114 that extends (e.g., via conventional flip-chip interconnects, a solder ball array, a hybrid bond, etc.) through the monolithic silicon structure 100 to the semiconductor device 102. The additional semiconductor device 111 may be encapsulated by a layer of molding material 112 to provide it with mechanical protection, as described in more detail above with reference to FIG.

[0019] Alternatively, rather than individually connecting additional semiconductor devices to TSVs 114 as shown in Figure 9, in another embodiment, one or more additional pre-populated monolithic silicon structures (e.g., as shown in Figure 2) can be bonded to the semiconductor assembly shown in Figure 8 to provide an assembly with a high density of devices while maintaining good thermal performance. One such assembly is shown in Figure 10, which shows a simplified schematic cross-sectional view of a semiconductor device assembly 100 such as that shown in Figure 8, with additional monolithic silicon structures 113 populated with bonded semiconductor devices.

[0020] As mentioned above, monolithic silicon structures may be fabricated from blank silicon wafers via conventional etching techniques to form openings or cavities in the silicon. Alternatively or additionally, methods for fabricating monolithic silicon structures may include highly controllable and high-rate etching processes, as described in further detail below, in accordance with various embodiments of the present disclosure.

[0021] Referring to FIG. 11 , a precursor structure from which a monolithic silicon structure will be formed is shown in a simplified partial cross-sectional view at one step in a formation process according to one embodiment of the present disclosure. The precursor structure includes a silicon wafer 1100 on which a passivation layer 1101 (e.g., a dielectric material) is formed, and one or more thermal pads 1102 are formed within the silicon wafer 1100. A mask layer 1103 is formed above the passivation layer 1101 in a pattern corresponding to the cavities to be formed within the silicon wafer 1100. More specifically, the mask layer 1103 includes a pattern of small openings (e.g., corresponding to narrow pillar-like or fin-like structures) overlying the areas within the silicon wafer 1100 where the cavities will be formed. As can be seen with reference to FIG. 12 , the small openings 1104 can be etched at least partially into the thickness of the silicon wafer 1100 to remove some of the material from where the cavities will be formed. The advantage of etching a smaller amount of material from the cavity, rather than the entire cavity, is that the directional etching operation can be completed more quickly than if the mask opening corresponded to the full size of the final cavity opening. After anisotropically etching these "slivers" of material from the silicon wafer 1100, a subsequent isotropic (e.g., wet) etching operation can be performed to remove the remaining material from the silicon wafer 1100 in which the cavity is to be formed. The result of such an operation is shown in FIG. 13, which illustrates the cavity 1105 formed by this two-step anisotropic and isotropic etching process according to one embodiment of the present disclosure. After removing the residue of the mask layer 1103 (e.g., via a chemical and / or mechanical removal process), the monolithic silicon structure 1400 with the thermal pad 1102 and cavity 1105, as shown in FIG. 14, is ready to undergo the processes previously described in more detail above with reference to FIGS. 2-10.

[0022] 1 or 14 before attaching the monolithic silicon structure to an underlying semiconductor device in an assembly, some embodiments of the present disclosure may include attaching the monolithic silicon structure to the semiconductor device, thinning the backside of the monolithic silicon structure to expose a cavity in the monolithic silicon structure, and then placing the semiconductor device within the cavity. One such approach to forming a semiconductor device assembly is shown at various stages of the process in FIGS. 15-20, according to various embodiments of the present disclosure.

[0023] 15 , the monolithic silicon structure 1400 of FIG. 14 is shown after being bonded to a lower semiconductor device 1401 in accordance with one aspect of the disclosure. In this regard, the monolithic silicon structure 1400 is bonded to the lower semiconductor device 1401 such that the thermal pad 1102 is coupled to the thermal contact 1402 of the lower semiconductor device 1401. The bonding operation may be a hybrid bonding operation in which a dielectric-dielectric bond (e.g., an oxide-oxide bond) is formed between the dielectric 1101 of the monolithic silicon structure and a dielectric layer 1403 formed above the lower semiconductor device 1401, and a metal-metal bond is formed between the thermal pad 1102 and the corresponding thermal pad 1102.

[0024] After bonding to the lower semiconductor device 1401, the monolithic silicon structure 1400 may undergo a backside thinning process (e.g., by chemical mechanical polishing (CMP), grinding, etc.) to remove a portion of material from the monolithic silicon structure 1400 to expose the cavity 1105, as shown in Figure 16. With the cavity 1105 thus opened, a semiconductor device (e.g., an individual die, a vertical stack of interconnected dies, a device package, a device assembly, etc.) 1701 may be placed within the cavity 1105, and an encapsulant (e.g., molding material) 1702 may be placed over (and optionally around, depending on the relative sizes of the semiconductor device 1701 and the cavity 1105) to yield a semiconductor device assembly, as shown in Figure 17. Subsequent processing steps (e.g., singulating the assembly 1700 from the wafer level or panel level, thinning, and providing external connections to the lower semiconductor device 1401, etc.) may be performed at this point (not described to maintain clarity of the disclosure).

[0025] Alternatively, semiconductor device assembly 1700 may be subjected to additional processing operations to remove overlying portions of encapsulant 1702 and expose the backside of semiconductor device 1701, similar to the processes described above with reference to Figures 4 and 5, in order to thin assembly 1700 and / or prepare the assembly for additional connectivity. In this regard, Figure 18 is a simplified schematic cross-sectional view of semiconductor device assembly 1800, in which an assembly such as that shown in Figure 17 has been subjected to a backside thinning process (e.g., by chemical mechanical polishing (CMP), grinding, etc.) to remove overlying portions of encapsulant 1702 to expose (and optionally planarize) the backside of semiconductor device 1701, as well as to reduce the overall height of assembly 1800.

[0026] In embodiments in which semiconductor device 1701 includes backside contacts for further connectivity, removing a portion of material from encapsulant 1702 covering the backside of semiconductor device 1701 may allow additional devices to be incorporated into the semiconductor device assembly, as described in more detail above with respect to Figures 6 and 7. In this regard, the additional semiconductor devices may be attached directly to the exposed backside contacts of semiconductor device 1701 and subsequently encapsulated with a layer of molding material (e.g., similar to the configuration shown in Figure 6). Alternatively, rather than individually connecting the additional semiconductor devices to the exposed backside contacts of semiconductor device 1701, in another embodiment, one or more additional pre-mounted monolithic silicon structures (e.g., as shown in Figure 2) may be bonded to semiconductor assembly 1800 shown in Figure 18 to provide an assembly with a high density of devices while maintaining good thermal performance. In yet another embodiment, the processes illustrated in the preceding sections of Figure 18 (e.g., placing another monolithic silicon structure 1400 above assembly 1800, thinning monolithic silicon structure 1400 to open cavities 1105 in monolithic silicon structure 1400, placing additional semiconductor devices in the exposed cavities, encapsulating with molding material, and optionally thinning the overlying molding material) may be repeated on assembly 1800 of Figure 18 to provide an assembly with a high density of devices while maintaining good thermal performance. As one skilled in the art will readily appreciate, the foregoing processes may be mixed, adapted, and repeated iteratively so that additional tiers of semiconductor devices can be provided until a desired device density is achieved.

[0027] The semiconductor device assembly is shown as being formed above a lower semiconductor device 1401 that has not yet been thinned or provided with backside contacts (e.g., on its underside in the orientation shown). FIG. 19 illustrates a process by which the lower semiconductor device 1401 may be thinned and provided with TSVs and backside contacts according to one aspect of the present disclosure. As can be seen with reference to FIG. 19 , the semiconductor device assembly 1800 is bonded to a temporary carrier wafer 1901 by a layer of adhesive 1902 disposed above the exposed backside surfaces of the monolithic silicon structure 1400 and the semiconductor device 1701. While mechanically supported by the carrier wafer 1901, the backside of the lower semiconductor device 1401 may be thinned (e.g., by CMP, grinding, etc.) to reduce the overall height of the assembly and to enable the formation of TSVs 1903 through the remaining thickness of the lower semiconductor device 1401. Backside contacts (e.g., pads, pillars, under bump metallization (UBM), etc.), such as contacts carrying solder ball array 1904, may be formed using any one of many methods known to those skilled in the art. In another embodiment, rather than forming vias 1904 after thinning lower semiconductor device 1401, buried TSVs already formed in lower semiconductor device 1401 at an earlier stage of processing may simply be exposed by the thinning operation shown in FIG. 19. Once thinning and contact formation are complete, temporary carrier wafer 1901 and adhesive 1902 may be removed, resulting in completed semiconductor device assembly 2000, as shown in FIG. 20.

[0028] While the silicon material of the aforementioned monolithic silicon structures enjoys high thermal conductivity, in some circumstances it may be advantageous to include copper, silver, aluminum, or other highly thermally conductive metals in some regions of the monolithic silicon structure to further enhance its thermal management capabilities while minimizing the CTE difference between the structure and the semiconductor devices in the assembly. In this regard, Figures 21-26 illustrate the fabrication and incorporation of one embodiment of a monolithic silicon structure including a metallic heat extraction structure.

[0029] 21 , a precursor structure from which a monolithic silicon structure will be formed is shown in a simplified partial cross-sectional view at a step in a formation process according to one embodiment of the present disclosure. The precursor structure includes a silicon wafer 2100 having formed thereon a passivation layer 2101 (e.g., a dielectric material) upon which one or more optional thermal pads (not shown) may be formed. A mask layer 2102 is formed above the passivation layer 2101 in a pattern corresponding to both the cavities and the metallic heat extraction structures to be formed in the silicon wafer 2100. More specifically, the mask layer 2102 includes a pattern of small openings (e.g., corresponding to narrow pillar-like or fin-like structures) that overlie both the regions in the silicon wafer 2100 where the cavities will be formed and the regions in the silicon wafer 2100 where the metallic heat extraction structures will be formed.

[0030] 22 , small openings 2103 can be etched at least partially into the thickness of the silicon wafer 2100 to remove some of the material from where the cavities will be formed and to create openings into which the metallic heat extraction structures can be plated. After anisotropically etching these “slivers” of material from the silicon wafer 2100, a plating operation can then be formed to fill the small openings 2103 with metallic structures both in the areas where the cavities will be formed and in the areas where the metallic heat extraction structures 2105 will remain. Excess metallic material can be removed (e.g., by a CMP operation, a grinding operation, a wet etching operation, etc.), and another mask structure 2106 can be placed over the silicon wafer 2100, with openings that expose the metallic material in the areas where the cavities will be formed, but not the metallic heat extraction structures 2105.

[0031] A subsequent isotropic (e.g., wet) etching operation can be performed to remove the metal structures and remaining silicon material from the silicon wafer 2100 in which the cavities are formed. The result of such an operation is shown in FIG. 25, which illustrates the cavity 2107 and metallic heat extraction structure 2105 formed by this process in accordance with one embodiment of the present disclosure. After removing the residue of the mask layer 2106 (e.g., via a chemical and / or mechanical removal process), the monolithic silicon structure 2500, including the metallic heat extraction structure 2105 and cavity 2107, is ready to undergo the processes described in more detail above with reference to FIGS. 2-10 and / or 15-20. In this regard, FIG. 26 illustrates a simplified schematic cross-sectional view of a semiconductor device assembly 2600 in accordance with one embodiment of the present disclosure. Assembly 2600 includes a monolithic silicon structure 2500 having a metallic heat extraction structure 2105 disposed therein for extracting heat from a lower semiconductor device 2602 (e.g., through contact with thermal contacts in lower semiconductor device 2602). Assembly 2600 further includes one or more semiconductor devices (two shown) coupled to lower semiconductor device 2602 within a cavity of the monolithic silicon structure.

[0032] As will be readily understood by those skilled in the art, while the foregoing examples are described using partial cross-sectional views of a single lower semiconductor device bonded to a single monolithic structure, embodiments of the present disclosure contemplate wafer-level processing in which an unsingulated wafer containing multiple lower semiconductor devices is bonded to a wafer-level monolithic silicon structure to provide a wafer-level intermediate structure from which individual assemblies can be singulated. Alternatively, in another embodiment, the singulated monolithic silicon structure may be individually bonded to an unsingulated wafer containing multiple lower semiconductor devices. In yet another embodiment, the singulated monolithic silicon structure may be individually bonded to the singulated lower semiconductor devices.

[0033] Although in the foregoing exemplary embodiments the monolithic silicon structure is shown and described as including thermal pads or metallic heat extraction structures that contact corresponding thermal contacts on the underlying semiconductor device, in other embodiments these features may be omitted and the monolithic silicon structure may be bonded to the surface of the underlying semiconductor device without any intermediate metallic structures.

[0034] While in the foregoing exemplary embodiment the monolithic silicon structure is shown and described as including two cavities of the same depth and plan area with similarly sized semiconductor devices therein, those skilled in the art will readily appreciate that the number of cavities is not so limited and that the monolithic silicon structure in other embodiments may have more or fewer cavities, cavities of different plan areas and / or depths to accommodate semiconductor devices (or other electrical components, including passive circuit components) of different sizes and shapes.

[0035] Furthermore, although in the foregoing exemplary embodiments, the monolithic silicon structure is shown and described as being disposed above a lower semiconductor die having the same plan area as the monolithic silicon structure, those skilled in the art will readily appreciate that the monolithic silicon structure may be used in other configurations (e.g., bonded to multiple lower dies, bonded to a device substrate, etc.) and need not have the same plan area as the device on which it is mounted.

[0036] According to one aspect of the present disclosure, the semiconductor device assembly shown and described above may include memory dies such as dynamic random access memory (DRAM) dies, not-and (NAND) memory dies, not-or (NOR) memory dies, magnetic random access memory (MRAM) dies, phase change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, or static random access memory (SRAM) dies. In embodiments in which multiple dies are provided in a single assembly, the semiconductor devices may be memory dies of the same type (e.g., both NAND, both DRAM, etc.) or different types (e.g., one DRAM and one NAND, etc.). According to another aspect of the present disclosure, the semiconductor dies of the assembly shown and described above may include logic dies (e.g., controller dies, processor dies, etc.) or a mix of logic and memory dies (e.g., a memory controller die and a memory die controlled by it).

[0037] Any one of the semiconductor devices and semiconductor device assemblies described above may be incorporated into any of a myriad of larger and / or more complex systems, a representative example of which is system 2700 shown generally in FIG. 27 . System 2700 may include a semiconductor device assembly (e.g., or individual semiconductor devices) 2702, a power supply 2704, a driver 2706, a processor 2708, and / or other subsystems or components 2710. Semiconductor device assembly 2702 may include features substantially similar to those of the semiconductor devices described above. The resulting system 2700 may perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 2700 may include, without limitation, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of system 2700 may be housed within a single unit or distributed across multiple interconnected units (e.g., via a communications network). Components of system 2700 may also include remote devices and any of a wide variety of computer-readable media.

[0038] The devices discussed herein, including memory devices, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate may be controlled through doping using various chemical species, including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

[0039] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and the accompanying claims. The mechanisms that implement the functionality may be physically located in various locations, including being distributed such that portions of the functionality are implemented in different physical locations.

[0040] As used herein, including in the claims, "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one" or "one or more") refers to an inclusive list, such as, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an example step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" will be construed the same as the phrase "based at least in part on."

[0041] As used herein, the terms "vertical," "lateral," "top," "bottom," "above," and "below" may refer to the relative direction or position of features within a semiconductor device given the orientation shown in the figures. For example, "top" or "top" may refer to a feature that is positioned closer to the very top of the page than another feature. These terms, however, should be interpreted broadly to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, up / down, upper / lower, top / bottom, and left / right may be interchanged depending on the orientation.

[0042] It should be noted that the methods described above describe possible implementations, and that operations and steps may be rearranged or modified, and other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined.

[0043] From the foregoing, it will be understood that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without departing from the scope of the invention. Rather, in the foregoing description, numerous specific details are discussed to provide a thorough and working description of embodiments of the present technology. Those skilled in the art will recognize, however, that the disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the technology. In general, it should be understood that in addition to the specific embodiments disclosed herein, various other devices, systems, and methods may be within the scope of the present technology.

Claims

1. a first semiconductor device including a top surface; a monolithic silicon structure having a bottom surface in contact with the top surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the bottom surface into a body of the monolithic silicon structure; a second semiconductor device directly bonded to the first semiconductor device and disposed within the cavity such that a back surface and a plurality of sidewalls of the second semiconductor device are completely enclosed within the cavity; a third semiconductor device disposed on a top surface of the monolithic silicon structure; Including, the monolithic silicon structure includes a plurality of TSVs, the plurality of TSVs extending between the cavity and the top surface of the monolithic silicon structure and electrically coupling the second semiconductor device and the third semiconductor device; Semiconductor device assembly.

2. The semiconductor device assembly of claim 1 , wherein the third semiconductor device is encapsulated by a molding material.

3. 2. The semiconductor device assembly of claim 1, wherein the third semiconductor device is surrounded by a second cavity of a second monolithic silicon structure disposed above the first monolithic silicon structure.

4. The semiconductor device assembly of claim 1 , wherein a back surface of the second semiconductor device is adhered to an inner surface of the cavity by an adhesive material.

5. The semiconductor device assembly of claim 4 , wherein the plurality of TSVs extend through the adhesive material.

6. 2. The semiconductor device assembly of claim 1, wherein the second semiconductor device has a bonding surface that is coplanar with the lower surface of the monolithic silicon structure.

7. The semiconductor device assembly of claim 1 , wherein the monolithic silicon structure includes a plurality of outer surfaces that are coplanar with an outer surface of the first semiconductor device.

8. a first semiconductor device including a top surface; a second semiconductor device carried directly by a top surface of the first semiconductor device; a monolithic silicon structure having a bottom surface in contact with the top surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the bottom surface into a body of the monolithic silicon structure and enclosing the second semiconductor device; a third semiconductor device disposed on a top surface of the monolithic silicon structure; Including, the monolithic silicon structure includes a plurality of TSVs, the plurality of TSVs extending between the cavity and the top surface of the monolithic silicon structure and electrically coupling the second semiconductor device and the third semiconductor device; Semiconductor device assembly.

9. 9. The semiconductor device assembly of claim 8, wherein the plurality of TSVs is a first plurality of TSVs, the second semiconductor device includes a second plurality of TSVs, and the second plurality of TSVs extends between the first semiconductor device and the first plurality of TSVs.

10. The semiconductor device assembly of claim 8 , wherein the third semiconductor device is encapsulated by a molding material.

11. 9. The semiconductor device assembly of claim 8, wherein the third semiconductor device is surrounded by a second cavity of a second monolithic silicon structure disposed above the first monolithic silicon structure.

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