Semiconductor device and electronic apparatus

Abstract

To provide a novel semiconductor device.SOLUTION: A memory string extending in a Z direction and including a conductor and an oxide semiconductor, and a plurality of wires CG extending in a Y direction intersect with each other. The conductor is disposed along a central axis of the memory string and the oxide semiconductor is disposed concentrically outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection between the memory string and the wires CG functions as a transistor. In addition, the intersection functions as a memory cell.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] NAND flash memory is widely used as a large-capacity storage device for computers. In recent years, technology has become widespread that increases the integration density of NAND flash memory by arranging memory cells three-dimensionally (Patent Document 1). In this specification and elsewhere, NAND flash memory with memory cells arranged three-dimensionally is referred to as "3D-NAND."

[0004] While 3D-NAND memory strings often use polycrystalline silicon for their body portions, Patent Document 2 discloses an example in which an oxide semiconductor is used for the body portion of a memory string. Note that the body portion here refers to the semiconductor layer that functions as the channel or source / drain of the transistors that make up the memory string. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2007-266143 [Patent Document 2] Patent Publication No. 2016-225614 Summary of the Invention [Problem to be solved by the invention]

[0006] The erase operation of 3D-NAND is performed by injecting holes into the body region. Patent Document 1 discloses three methods for injecting holes into the body region: (1) generating holes using a gate-induced drain leak (GIDL), (2) injecting holes from a P-well in a semiconductor substrate, and (3) injecting holes from a contact layer made of p-type polysilicon.

[0007] However, when an oxide semiconductor is used for the body, none of the above methods (1) to (3) can be used. For example, method (1) cannot be used because oxide semiconductors have a wide band gap and do not generate GIDL. Furthermore, methods (2) and (3) cannot be used because the energy barrier when injecting holes from p-type polysilicon into the oxide semiconductor is high. Therefore, 3D-NAND cannot perform an erase operation simply by replacing the body from polysilicon with an oxide semiconductor.

[0008] An object of one embodiment of the present invention is to provide a novel memory device. Another object of one embodiment of the present invention is to provide a memory device with high operation speed. Another object of one embodiment of the present invention is to provide a highly reliable memory device. Another object of one embodiment of the present invention is to provide a memory device with large storage capacity. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high operation speed. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with large storage capacity.

[0009] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device having a first conductor extending in a first direction and a structure extending in a second direction, the structure having a second conductor, an oxide semiconductor, a functional layer, a first insulator, a second insulator, and a third insulator, the second conductor being electrically connected to the oxide semiconductor, the first insulator, the oxide semiconductor, the second insulator, the functional layer, and the third insulator being concentrically arranged outside the second conductor at an intersection between the first conductor and the structure, and the third insulator being thicker than the second insulator at the intersection.

[0011] (2) Another aspect of the present invention is a semiconductor device having a first conductor of n layers (n is an integer of 2 or more) extending in a first direction and a structure extending in a second direction, the structure having a second conductor, an oxide semiconductor, a functional layer, a first insulator, a second insulator, and a third insulator, the second conductor being electrically connected to the oxide semiconductor, and at each intersection of the first conductor of the n layers and the structure, the first insulator, the oxide semiconductor, the second insulator, the functional layer, and the third insulator are each concentrically arranged outside the second conductor, and at each intersection, the third insulator is thicker than the second insulator.

[0012] The first direction is perpendicular to the second direction. The intersections can function as transistors. The intersections can also function as memory cells.

[0013] The functional layer can function as a charge storage layer. An insulator or a semiconductor can be used as the functional layer. When an insulator is used as the functional layer, for example, an insulator containing nitrogen and silicon can be used. When a semiconductor is used as the functional layer, for example, a semiconductor containing silicon can be used. The oxide semiconductor preferably contains at least one of indium and zinc.

[0014] Another aspect of the present invention is a method for driving a semiconductor device as described in (2) above, which includes a first operation of supplying a first potential to a first conductor in the nth layer and a second potential to a second conductor, and a second operation of supplying a third potential to a first conductor in the i-th layer (i is an integer greater than or equal to 1 and less than or equal to n), supplying a fourth potential to each of the first conductors except for the first conductor in the i-th layer, and supplying the first potential to the second conductor, and the second operation is performed after the first operation.

[0015] The potential difference between the first potential and the second potential is preferably two to six times the potential difference between the first potential and the fourth potential, and the potential difference between the first potential and the third potential is preferably two to four times the potential difference between the first potential and the fourth potential. [Effects of the Invention]

[0016] According to one embodiment of the present invention, a novel memory device can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a memory device with high reliability can be provided. According to one embodiment of the present invention, a memory device with large storage capacity can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with large storage capacity can be provided.

[0017] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0018] [Figure 1] 1A and 1B are cross-sectional and circuit diagrams of a memory string. [Figure 2] 2A and 2B are cross-sectional views of a memory string. [Figure 3] 3A and 3B are cross-sectional views of a memory string. [Figure 4] 4A and 4B are cross-sectional and circuit diagrams of a memory string. [Figure 5] 5A and 5B are cross-sectional and circuit diagrams of a memory string. [Figure 6] 6A and 6B are cross-sectional and circuit diagrams of a memory string. [Figure 7] FIG. 7 is a cross-sectional view of a memory string. [Figure 8] 8A and 8B are cross-sectional views of a memory string. [Figure 9] 9A and 9B are cross-sectional and circuit diagrams of a memory string. [Figure 10] 10A and 10B are cross-sectional and circuit diagrams of a memory string. [Figure 11]Figure 11A is a diagram explaining the classification of crystal structures, Figure 11B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 11C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 12] 12A and 12B are cross-sectional views of a semiconductor device. [Figure 13] 13A and 13B are cross-sectional views of the semiconductor device. [Figure 14] Fig. 14A is a circuit diagram of a memory string, and Fig. 14B is a diagram illustrating an example of the Id-Vg characteristics of a transistor. [Figure 15] Fig. 15A is a timing chart illustrating the erase operation of the memory string, and Fig. 15B is a circuit diagram showing the operating state of the memory string. [Figure 16] FIG. 16 is a cross-sectional view of a memory cell. [Figure 17] Fig. 17A is a timing chart illustrating a write operation of a memory string, and Fig. 17B is a circuit diagram illustrating the operating state of the memory string. [Figure 18] FIG. 18 is a cross-sectional view of a memory cell. [Figure 19] Fig. 19A is a timing chart illustrating a read operation of a memory string, and Fig. 19B is a circuit diagram illustrating the operating state of the memory string. [Figure 20] FIG. 20 is a cross-sectional view of a memory string. [Figure 21] 21A and 21B are cross-sectional views of a memory string. [Figure 22] FIG. 22 is a circuit diagram of a memory string. [Figure 23] FIG. 23 is a cross-sectional view of a memory string. [Figure 24] FIG. 24 is a cross-sectional view of a memory string. [Figure 25] FIG. 25 is a cross-sectional view of a memory string. [Figure 26] FIG. 26 is a circuit diagram of a memory string. [Figure 27] FIG. 27 is a cross-sectional view of a memory string. [Figure 28] FIG. 28 is a cross-sectional view of a memory string. [Figure 29] FIG. 29 is a cross-sectional view of a memory string. [Figure 30] FIG. 30 is a cross-sectional view of a memory string. [Figure 31] FIG. 31 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 32] FIG. 32 is a diagram illustrating a configuration example of a semiconductor device. [Figure 33] FIG. 33 is a diagram illustrating an example of an information processing system constructed using a plurality of storage devices. [Figure 34] FIG. 34 is a block diagram illustrating the CPU. [Figure 35] 35A and 35B are perspective views of the semiconductor device. [Figure 36] 36A and 36B are perspective views of the semiconductor device. [Figure 37] 37A and 37B are perspective views of the semiconductor device. [Figure 38] FIG. 38A is a perspective view showing an example of a semiconductor wafer, FIG. 38B is a perspective view showing an example of a chip, and FIGS. 38C and 38D are perspective views showing an example of an electronic component. [Figure 39] 39A to 39J are perspective views or schematic diagrams illustrating examples of electronic devices. [Figure 40] 40A to 40E are perspective views or schematic diagrams illustrating an example of an electronic device. [Figure 41] 41A to 41C are diagrams illustrating an example of an electronic device. [Figure 42] FIG. 42 is a diagram illustrating an example of the configuration of a computer system. [Figure 43] Figure 43 shows the hierarchical structure of IoT networks and trends in required specifications. [Figure 44]Figure 44 is an image diagram of factory automation. [Figure 45] FIG. 45 is an equivalent circuit diagram of a memory string assumed in the device simulation. [Figure 46] FIG. 46 is a cross-sectional view of a memory string assumed in the device simulation. [Figure 47] Figure 47A is a circuit diagram for explaining a write operation, and Figure 47B is a diagram for explaining changes in the threshold voltage of a memory transistor before and after writing. [Figure 48] Fig. 48A is a circuit diagram for explaining an erase operation, and Fig. 48B is a diagram for explaining changes in the threshold voltage of a memory transistor before and after erasure. [Figure 49] 49A and 49B are graphs showing the calculation results of the device simulation. DETAILED DESCRIPTION OF THE INVENTION

[0019] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0020] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0021] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling its on and off states. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0022] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0023] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0024] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0025] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "electrically connected" also includes such cases where one conductive film has the functions of multiple components.

[0026] Furthermore, in this specification and the like, the term "resistance element" can refer to, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value can be, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0027] When a wiring is used as a resistor, the resistance value may be determined by the length of the wiring, or a conductor having a different resistivity from that of the wiring may be used as the resistor, or the resistance value may be determined by doping impurities into a semiconductor.

[0028] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also parasitic capacitance appearing between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0029] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are the input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the transistor's conductivity type (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the transistor structure, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as the first gate, and the other of the gate or backgate of the transistor may be referred to as the second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0030] Furthermore, in this specification and the like, the term "node" can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Furthermore, the term "node" can be rephrased as a terminal, wiring, etc.

[0031] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0032] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply high-level potentials," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply low-level potentials," the low-level potentials provided by both wirings do not have to be equal to each other.

[0033] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move, and the amount of current is expressed as a positive value. In other words, the direction in which negative carriers move is opposite to the direction of current, and the amount of current is expressed as a negative value. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0034] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment, in the claims, etc. Furthermore, for example, a component referred to as "first" in one embodiment of this specification, etc. may be omitted in another embodiment, in the claims, etc.

[0035] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0036] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0037] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0038] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0039] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0040] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can, for example, increase the defect level density of the semiconductor, decrease carrier mobility, or decrease crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

[0041] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Examples include electrical switches and mechanical switches. In other words, the switch is not limited to a specific type as long as it can control a current.

[0042] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0043] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0044] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0045] In this specification, "parallel" refers to a state in which two lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. "Substantially parallel" or "roughly parallel" refers to a state in which two lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" refers to a state in which two lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. "Substantially perpendicular" or "approximately perpendicular" refers to a state in which two lines are arranged at an angle of 60° or more and 120° or less. "Orthogonal" refers to a state in which two lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less.

[0046] In this specification and elsewhere, when referring to counting and measurement values, or to objects, methods, and events that can be converted into counting or measurement values, terms such as "identical," "same," "equal," or "uniform" are used, they include a margin of error of plus or minus 20%, unless otherwise specified.

[0047] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply "OSs"), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor that has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor.

[0048] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0049] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0050] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0051] Note that the content described in the embodiments refers to the content described in each embodiment (or example) using various figures, or the content described using text in the specification.

[0052] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0053] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, top views, etc.

[0054] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations, etc. may be included.

[0055] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[i]", or "[m,n]" may be added to the symbol. For example, one of two wirings CG may be described as wiring CG_1, and the other as wiring CG_2.

[0056] (Embodiment 1) A memory string 100 according to one embodiment of the present invention will be described with reference to the drawings. The memory string 100 is a semiconductor device that functions as a 3D-NAND memory device. Note that in the drawings, arrows indicating the X, Y, and Z directions may be added. The X, Y, and Z directions intersect with each other. More specifically, the X, Y, and Z directions are perpendicular to each other. In this specification and the like, one of the X, Y, and Z directions may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining may be referred to as the "third direction" or "third direction." In FIG. 1 and the like, the Z direction is defined as the direction perpendicular to the top surface of the conductor 101.

[0057] <Memory string configuration example> FIG. 1A is a cross-sectional view of the memory string 100 as viewed from the Y direction. Note that FIG. 1A also shows a central axis 131 of the memory string 100 extending in the Z direction. FIG. 1B is an equivalent circuit diagram of the memory string 100. FIG. 2A is a cross-sectional view of a portion A1-A2 indicated by a dashed line in FIG. 1A as viewed from the Z direction. FIG. 2B is a cross-sectional view of a portion B1-B2 indicated by a dashed line in FIG. 1A as viewed from the Z direction.

[0058] The memory string 100 has a conductor 101, m layers (m is an integer of 2 or more) of insulators 102, and n layers (n is an integer of 2 or more) of conductors 103, all arranged above a substrate (not shown). The insulators 102 and conductors 103 are alternately stacked above the substrate. In FIG. 1A and other figures, the first layer of insulator 102 is referred to as insulator 102_1, and the mth layer of insulator 102 is referred to as insulator 102_m. Similarly, the first layer of conductor 103 is referred to as conductor 103_1, and the nth layer of conductor 103 is referred to as conductor 103_n. Note that in this embodiment and other figures, any insulator 102 is simply referred to as "insulator 102." Similarly, any conductor 103 is simply referred to as "conductor 103."

[0059] The insulators 102 and the conductors 103 extend in the Y direction. The memory string 100 has a structure in which the insulators 102 and the conductors 103 are alternately stacked. For example, in FIG. 1A , an insulator 102_1 is provided on the conductor 101, a conductor 103_1 is provided on the insulator 102_1, an insulator 102_2 is provided on the conductor 103_1, a conductor 103_2 is provided on the insulator 102_2, an insulator 102_3 is provided on the conductor 103_2, a conductor 103_3 is provided on the insulator 102_3, and an insulator 102_4 is provided on the conductor 103_3. Furthermore, an insulator 102_m is provided on the conductor 103_n.

[0060] The memory string 100 also includes a conductor 104, an insulator 105, a structure 110, and an insulator 121. The structure 110 extends along the Z direction. The structure 110 is provided between the conductor 101 and the conductor 104 so as to penetrate the insulators 102_1 to 102_m and the conductors 103_1 to 103_n.

[0061] The structure 110 has a columnar structure including a conductor 106, an insulator 111, a semiconductor 112, an insulator 113, a functional layer 114, and an insulator 115. Specifically, the conductor 106 extends along a central axis 131, and the insulator 111 is provided adjacent to a side surface of the conductor 106. The semiconductor 112 is provided adjacent to a side surface of the insulator 111. The insulator 113 is provided adjacent to the semiconductor 112. The functional layer 114 is provided adjacent to the insulator 113. The insulator 115 is provided adjacent to the functional layer 114. As shown in FIGS. 2A and 2B , the insulator 111, the semiconductor 112, the insulator 113, and the functional layer 114 are each concentrically arranged outside the conductor 106.

[0062] 2 shows a case where the cross-sectional shape of the structure 110 is circular, but the cross-sectional shape of the structure 110 is not limited to a circle. The cross-sectional shape of the structure 110 may be triangular, rectangular, or a polygon with pentagons or more sides. In addition, the cross-sectional shape of the structure 110 may be curved, or may be a combination of straight lines and curved lines.

[0063] The insulator 121 is provided to cover the side surfaces of the insulators 102_1 to 102_m and the conductors 103_1 to 103_n. The conductor 104 is provided on the insulator 102_m. The conductors 101 and 104 are electrically connected to the semiconductor 112. The conductor 101 is electrically connected to the conductor 106. Thus, the conductor 106 is electrically connected to the semiconductor 112. The insulator 105 is provided on the insulator 102_m, the insulator 121, and the conductor 104.

[0064] In a direction perpendicular to the Z direction, a region (intersection) where the structure 110 and the conductor 103 overlap functions as a transistor Tr. Therefore, in a direction perpendicular to the Z direction, a region (intersection) where the structure 110 and the conductor 103 overlap functions as a memory cell (also referred to as a "storage element").

[0065] The conductor 103 functions as the gate of the transistor Tr. The memory string 100 shown in FIG. 1A has n regions (intersections) where the structures 110 and the conductors 103 overlap. Therefore, the memory string 100 shown in FIG. 1A has n transistors Tr. Therefore, the memory string 100 shown in FIG. 1A has n memory cells. In addition, the conductor 106 can function as the back gate of the transistor Tr.

[0066] FIG. 2A corresponds to a cross-sectional view of a transistor Tr in the memory string 100 when viewed from the Z direction.

[0067] 1A, the first transistor Tr is denoted as transistor Tr_1, and the nth transistor Tr is denoted as transistor Tr_n. In the present embodiment and the like, any transistor Tr is simply referred to as "transistor Tr."

[0068] Generally, a memory cell that stores data by storing charges in a charge storage layer has a stacked structure of a block layer, a charge storage layer, a tunnel layer, and a semiconductor layer. Such a memory cell may be called by various names depending on the stacked structure from the control gate to the semiconductor. For example, if the control gate, block layer, charge storage layer, tunnel layer, and semiconductor layer are made of metal, oxide, nitride, oxide, or semiconductor, it is called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell.

[0069] Furthermore, when n-type silicon or p-type silicon is used for the control gate in a MONOS-type memory cell, it is called a SONOS (Silicon Oxide Nitride Oxide Semiconductor)-type memory cell.

[0070] Similarly, when tantalum nitride is used for the control gate and aluminum oxide is used for the block layer, the memory cell is called a TANOS (Tantalum nitride Aluminium oxide Nitride Oxide Semiconductor) type memory cell.

[0071] When tantalum nitride is used for the control gate and hafnium oxide for the block layer, the memory cell is called a THNOS (Tantalum nitride Hafnium oxide Nitride Oxide Semiconductor) type memory cell.

[0072] The transistor Tr according to one embodiment of the present invention functions as, for example, a MONOS memory cell. The memory string 100 functions as a NAND memory device having n memory cells.

[0073] The conductor 103 functions as a memory cell control gate. The insulator 113 functions as a tunnel layer, the functional layer 114 functions as a charge storage layer, and the insulator 115 functions as a block layer. That is, the block layer is provided on the control gate side, and the tunnel layer is provided on the semiconductor side.

[0074] As shown in FIG. 1B, the gate of the transistor Tr is electrically connected to a wiring CG. In FIG. 1B, the wiring CG electrically connected to the gate of the transistor Tr_1 is shown as wiring CG_1. Note that part or all of the conductor 103 may function as the wiring CG. Note that the wiring CG is also called a "control gate" or a "control gate wiring."

[0075] In addition, among the transistors Tr_2 to Tr_n-1, the source of one of the adjacent transistors Tr is electrically connected to the drain of the other transistor Tr.

[0076] One of the source or drain of the transistor Tr_1 is electrically connected to a wiring SL, and the other is electrically connected to one of the source or drain of the transistor Tr_2. One of the source or drain of the transistor Tr_n is electrically connected to a wiring BL, and the other is electrically connected to one of the source or drain of the transistor Tr_n-1. The conductor 101 is electrically connected to the wiring SL, and the conductor 104 is electrically connected to the wiring BL. Note that the conductor 101 may function as the wiring SL, and the conductor 104 may function as the wiring BL.

[0077] The back gates of the transistors Tr (transistors Tr_1 to Tr_n) are electrically connected to the wiring SL through the wiring BGL. Note that the conductor 106 can function as the wiring BGL.

[0078] The functional layer 114, which functions as a charge storage layer, uses a material with a smaller band gap than the insulators 113 and 115. The thickness of the insulator 113 (length in a direction perpendicular to the Z direction) is preferably 1 nm or more and 10 nm or less. The thickness of the functional layer 114 is preferably 5 nm or more and 20 nm or less. The thickness of the insulator 115 is preferably 5 nm or more and 50 nm or less. Furthermore, the thickness of the insulator 113 is preferably thinner than the insulator 115. In other words, the thickness of the insulator 115 is preferably thicker than the insulator 113.

[0079] An insulator may be used for the functional layer 114. For example, silicon oxide may be used for the insulators 113 and 115, and silicon nitride may be used for the functional layer 114. Each of the insulators 113 to 115 may be a stack of multiple insulators. For example, the insulator 115 may be a stack of silicon oxide and aluminum oxide.

[0080] Furthermore, for example, silicon nitride may be used for the insulators 113 and 115. In this case, silicon nitride having a higher silicon content than the silicon nitride used for the insulators 113 and 115 may be used for the functional layer 114.

[0081] As described above, polycrystalline silicon is often used for the body portion of a 3D-NAND memory string. In the memory string 100 according to one embodiment of the present invention, the semiconductor 112 corresponds to the body portion. The semiconductor 112 can be a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either singly or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Alternatively, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.

[0082] The semiconductor 112 functions as a semiconductor layer in which a channel of the transistor Tr is formed. The semiconductor used for the transistor may be a stack of semiconductors. When stacking semiconductor layers, semiconductors having different crystalline states or different semiconductor materials may be used.

[0083] The transistor Tr is preferably a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The oxide semiconductor has a band gap of 2 eV or more, and therefore has a significantly small off-state current. Therefore, the power consumption of the memory string 100 can be reduced. Therefore, the power consumption of a semiconductor device including the memory string 100 can be reduced.

[0084] Furthermore, a memory cell including an OS transistor can be called an “OS memory.” Furthermore, a memory string 100 including the memory cell can also be called an “OS memory.”

[0085] Furthermore, OS transistors can have a lower on-resistance than transistors that use polycrystalline silicon for the semiconductor layer in which the channel is formed. That is, the conductivity of the body can be increased. By using OS transistors for the transistors Tr, the operating speed of the memory string 100 can be increased.

[0086] Furthermore, by using an OS transistor having a back gate as an OS transistor functioning as a memory cell, a more reliable erase operation of the OS memory can be realized, thereby improving the reliability of the erase operation of the OS memory. Note that the erase operation will be described in detail later.

[0087] Furthermore, while polycrystalline silicon transistors exhibit variations in threshold voltage due to grain boundaries, OS transistors are less affected by grain boundaries and exhibit smaller variations in threshold voltage. Therefore, by using OS transistors for the transistors Tr, the memory string 100 can suppress malfunctions due to variations in threshold voltage.

[0088] Furthermore, OS transistors operate stably even in high-temperature environments, with little fluctuation in their characteristics. For example, the off-state current hardly increases even in high-temperature environments. Specifically, the off-state current hardly increases even in ambient temperatures above room temperature and below 200°C. Furthermore, the on-state current is unlikely to decrease even in high-temperature environments. Therefore, the memory string 100 including the OS memory operates stably even in high-temperature environments, and high reliability is achieved. Furthermore, OS transistors have a high dielectric strength voltage between the source and drain. By using OS transistors as the transistors constituting the memory string 100, a memory string 100 with stable operation and good reliability can be realized, even in high-temperature environments. Therefore, the reliability of a semiconductor device including the memory string 100 can be improved.

[0089] A NAND type storage device including an OS memory is also referred to as an "OS NAND type" or "OS NAND type storage device." Furthermore, a 3D-NAND type storage device including an OS memory is also referred to as a "3D OS NAND type" or "3D OS NAND type storage device." Therefore, the memory string 100 according to one embodiment of the present invention can be said to be a 3D OS NAND type storage device.

[0090] Furthermore, if it is desired to increase the storage capacity of a semiconductor device using memory strings 100, multiple memory strings 100 may be arranged in a staggered pattern (see FIG. 3A) or a grid pattern (see FIG. 3B). Figure 3 is a cross-sectional view corresponding to Figure 2A.

[0091] [Variation 1] Fig. 4A shows a cross-sectional view of a memory string 100A, which is a modification of the memory string 100. Fig. 4B is an equivalent circuit diagram of the memory string 100A.

[0092] The memory string 100A has a transistor TrS_1 between the transistor Tr_1 and the conductor 101, and a transistor TrS_2 between the transistor Tr_n and the conductor 104. That is, the memory string 100 has the transistor TrS_1 at one end and the transistor TrS_2 at the other end.

[0093] 4A, the conductor 103 functioning as the gate of the transistor TrS_1 is denoted as conductor 103_s1, and the conductor 103 functioning as the gate of the transistor TrS_2 is denoted as conductor 103_s2. The conductor 103_s1 is electrically connected to the wiring SEL_1, and the conductor 103_s2 is electrically connected to the wiring SEL_2 (see FIG. 4B).

[0094] In the memory string 100A, the conductor 103_s1 is provided between the insulators 102_1 and 102_2, and the conductor 103_1 is provided between the insulators 102_2 and 102_3. In addition, in the memory string 100A, the conductor 103_s2 is provided between the insulators 102_m and 102_m-1, and the conductor 103_n is provided between the insulators 102_m-1 and 102_m-2.

[0095] 3, in a structure in which one conductor 103 intersects with multiple memory strings, there is a risk that when reading information contained in a specific memory string, the information contained in other memory strings may interfere with the reading, preventing accurate reading. Also, when writing information to a specific memory string, there is a risk that the information may also be written to other memory strings.

[0096] By providing a transistor TrS that functions as a selection transistor at at least one, and preferably both, of the ends of the memory string, it is possible to read and write information only from and to a specific memory string, thereby enabling more accurate reading and writing of information.

[0097] In the memory string 100A, the transistor TrS has the same structure as the transistor Tr. However, since the transistor TrS functions as a selection transistor, it is not necessary to perform a read operation, a write operation, or the like on the transistor TrS.

[0098] The material used to form the conductor 103_s1 and the conductor 103_s2 may be the same as the material used to form the other conductors 103, or may be a different material.

[0099] [Variation 2] Fig. 5A shows a cross-sectional view of a memory string 100B, which is a modification of the memory string 100. Fig. 5B is an equivalent circuit diagram of the memory string 100B.

[0100] 5, one of the source or drain of the transistor Tr_1 may be electrically connected to a wiring BL, and the other may be electrically connected to one of the source or drain of the transistor Tr_2. Alternatively, one of the source or drain of the transistor Tr_n may be electrically connected to a wiring SL, and the other may be electrically connected to one of the source or drain of the transistor Tr_n-1.

[0101] Therefore, the conductor 101 is electrically connected to the wiring BL, and the conductor 104 is electrically connected to the wiring SL. Note that the conductor 101 may function as the wiring BL, and the conductor 104 may function as the wiring SL.

[0102] 5, the back gates of the transistors Tr (transistors Tr_1 to Tr_n) are electrically connected to the wiring SL. In the memory string illustrated in FIG. 5, the conductor 106 is not electrically connected to the conductor 101 but is electrically connected to the conductor 104.

[0103] [Variation 3] Fig. 6A shows a cross-sectional view of a memory string 100C, which is a modification of the memory string 100. Fig. 6B is an equivalent circuit diagram of the memory string 100C.

[0104] The memory string 100C has an insulator 107 and a conductor 108. The insulator 107 is provided on the insulator 102_m. The conductor 108 is provided so as to be embedded in a part of the insulator 107. In the memory string 100C, the conductor 104 is provided on the insulator 107, and an insulator 105 is provided to cover the conductor 104. The semiconductor 112 is electrically connected to the conductor 104 via the conductor 108.

[0105] 6, the conductor 106 functioning as the wiring BGL may be electrically connected to a wiring 109 (not shown in FIG. 6A) without being connected to either the wiring SL or the wiring BL. With this configuration, an arbitrary potential can be supplied to the wiring BGL. The threshold voltage of the transistor Tr can be controlled by controlling the potential of the wiring BGL.

[0106] [Variation 4] Figure 7 shows a cross-sectional view of memory string 100D, which is a modified example of memory string 100. Figure 8A is a cross-sectional view of portion C1-C2 indicated by the dashed dotted line in Figure 7, viewed from the Z direction. Figure 8B is a cross-sectional view of portion D1-D2 indicated by the dashed dotted line in Figure 7, viewed from the Z direction. Figure 8A corresponds to a cross-sectional view of transistor Tr in memory string 100D, viewed from the Z direction.

[0107] The memory string 100D has a structure 110A instead of the structure 110. The structure 110A has a structure obtained by removing the functional layer 114 and the insulator 115 from the structure 110. The functional layer 114 and the insulator 115 are provided for each transistor Tr.

[0108] In the present embodiment and the like, the functional layer 114 included in the transistor Tr_1 is referred to as the functional layer 114_1. Furthermore, the insulator 115 included in the transistor Tr_1 is referred to as the insulator 115_1. Similarly, the functional layer 114 included in the transistor Tr_n is referred to as the functional layer 114_n, and the insulator 115 included in the transistor Tr_n is referred to as the insulator 115_n. Furthermore, when referring to the functional layer 114 included in any transistor Tr, it is simply referred to as the "functional layer 114." Similarly, when referring to the insulator 115 included in any transistor Tr, it is simply referred to as the "insulator 115."

[0109] For example, the insulator 115_3 is provided adjacent to the conductor 103_3. Therefore, the insulator 115_3 has a region that overlaps with the structure 110A in a direction perpendicular to the Z direction.

[0110] The insulator 115_3 has a region overlapping with the bottom surface of the conductor 103_3. The conductor 103_3 overlaps with the insulator 102_3 through this region.

[0111] The insulator 115_3 has a region overlapping with the top surface of the conductor 103_3. The conductor 103_3 overlaps with the insulator 102_4 through this region.

[0112] The functional layer 114_3 is provided adjacent to the insulator 115_3. The functional layer 114_3 has a region overlapping with the structure 110A in a direction perpendicular to the Z direction.

[0113] The functional layer 114_3 has a region that overlaps with the lower surface of the conductor 103_3 via a part of the insulator 115_3. The conductor 103_3 overlaps with the insulator 102_3 via this region.

[0114] The functional layer 114_3 has a region that overlaps with the top surface of the conductor 103_3 via a part of the insulator 115_3. The conductor 103_3 overlaps with the insulator 102_4 via this region.

[0115] Therefore, the cross-sectional view shown in FIG. 8A is the same as the cross-sectional view shown in FIG. 2A, but the cross-sectional view shown in FIG. 8B is different from the cross-sectional view shown in FIG. 2B.

[0116] In the memory string 100, the functional layer 114 is shared between adjacent transistors Tr, so there is a possibility that the charge stored in the functional layer 114 may interfere with the adjacent transistors Tr. On the other hand, in the memory string 100D, the functional layer 114 that functions as a charge storage layer is provided independently for each transistor Tr, so the possibility of interference with the adjacent transistors Tr can be reduced. This reduces noise and improves the reliability of data retention. Furthermore, the memory string 100D can more easily retain multi-valued information than the memory string 100.

[0117] In addition, in the memory string 100D, a semiconductor may be used for the functional layer 114 that functions as an accumulation layer. By using a semiconductor for the accumulation layer, a floating gate type memory cell can be realized. The semiconductor material used for the accumulation layer may be silicon, germanium, or the like. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor may be used.

[0118] [Variation 5] FIG. 9A shows a cross-sectional view of memory string 100E, which is a modified example of memory string 100. FIG. 9A is a cross-sectional view of memory string 100E as viewed from the Y direction. FIG. 9B is an equivalent circuit diagram of memory string 100E. Memory string 100E has ferroelectric 118 instead of insulator 113, functional layer 114, and insulator 115 that memory string 100 has.

[0119] Materials used as the ferroelectric 118 include a mixed crystal of hafnium oxide and zirconium oxide (also called "HZO"), or a material in which an element X (the element X is silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), or the like) is added to hafnium oxide.

[0120] Alternatively, a piezoelectric ceramic having a perovskite structure may be used as the ferroelectric 118. For example, lead zirconate titanate (also referred to as "PZT"), strontium tantalate bismuthate (also referred to as "SBT"), bismuth ferrite (also referred to as "BFO"), or barium titanate may be used as the ferroelectric 118.

[0121] Alternatively, the ferroelectric 118 may be an organic ferroelectric such as polyvinylidene fluoride (also called "PVDF") or a copolymer of vinylidene fluoride (also called "VDF") and trifluoroethylene (also called "TrFE").

[0122] The transistor Tr that makes up the memory string 100E functions as a ferroelectric transistor (FeFET). A ferroelectric transistor is a transistor that uses a ferroelectric as the insulator that functions as the gate insulator. Here, we will explain ferroelectrics. When an electric field is applied to a dielectric, positively charged and negatively charged areas are created within the dielectric. This phenomenon is called "polarization." A dielectric whose polarization disappears when the electric field is removed is called a "paraelectric," while a dielectric whose polarization remains even when the electric field is removed is called a "ferroelectric." Furthermore, the direction of polarization of a ferroelectric changes when the direction of an electric field applied above a certain strength is changed. A ferroelectric transistor can change its threshold voltage by changing the voltage applied to the gate electrode.

[0123] By using ferroelectric transistors as the transistors Tr that make up the memory string 100E, a NAND type ferroelectric memory can be realized.

[0124] [Variation 6] FIG. 10 shows a cross-sectional view of the memory string 100F. FIG. 10A is a cross-sectional view of the memory string 100F as viewed from the Y direction. FIG. 10B is an equivalent circuit diagram of the memory string 100F. The memory string 100F is a modified example of the memory string 100 that differs from the memory string 100E. The memory string 100F has a ferroelectric layer 118 instead of the functional layer 114 of the memory string 100.

[0125] The ferroelectric material 118 of the memory string 100F is sandwiched between the insulator 113 and the insulator 115. The ferroelectric material 118 can be made of the same material as that of the memory string 100E.

[0126] By sandwiching the ferroelectric 118 between the insulators 113 and 115, the polarization of the ferroelectric 118 after data rewriting is stabilized, thereby improving the reliability of the memory string 100F. By providing the insulator 113 between the semiconductor 112 and the ferroelectric 118, the interface of the semiconductor 112 on the ferroelectric 118 side is stabilized, thereby improving the speed of writing and reading data.

[0127] <Memory cell constituent materials> Next, constituent materials that can be used for the memory string 100 and the like will be described.

[0128] [substrate] The memory string 100 can be provided on a substrate. Examples of the substrate include an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride (GaN). Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0129] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0130] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0131] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0132] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0133] Furthermore, the electrical characteristics of an OS transistor can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0134] In this specification and the like, the term "oxynitride" refers to a material that contains more oxygen than nitrogen as a main component. For example, "silicon oxynitride" refers to a material that contains more oxygen than nitrogen and that contains silicon, nitrogen, and oxygen. In this specification and the like, the term "nitride oxide" refers to a material that contains more nitrogen than oxygen as a main component. For example, "aluminum nitride oxide" refers to a material that contains more nitrogen than oxygen and that contains aluminum, nitrogen, and oxygen.

[0135] When an oxide semiconductor is used for the semiconductor 112, the insulator adjacent to the semiconductor 112 is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor 112, oxygen vacancies in the semiconductor 112 can be compensated for.

[0136] Furthermore, the insulator may be a single layer made of the above-mentioned material, or a plurality of insulating layers made of the above-mentioned material may be stacked.

[0137] For example, when an insulator is provided in contact with a conductor, an insulator having a function of suppressing oxygen permeation may be used as the insulator to prevent oxidation of the conductor, and examples of the insulator that may be used include hafnium oxide, aluminum oxide, and silicon nitride.

[0138] When an insulator is stacked adjacent to a conductor, it is preferable to use an insulator that has a function of suppressing oxygen permeation as the insulator in contact with the conductor. For example, an insulator in contact with the conductor may be formed using hafnium oxide, and an insulator in contact with the insulator using silicon oxynitride may be formed.

[0139] [conductor] The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0140] Furthermore, a conductive layer formed of the above-mentioned material may be used as a single layer as a conductor, or multiple conductive layers formed of the above-mentioned material may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0141] [Oxide semiconductor] An oxide semiconductor, which is a type of metal oxide, is preferably used as the semiconductor 112. An oxide semiconductor that can be used as an OS transistor will be described below.

[0142] The oxide semiconductor preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0143] Here, we consider a case where the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements that can be used for the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of two or more of the above elements.

[0144] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 11A. Fig. 11A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0145] As shown in FIG. 11A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0146] The structure within the bold frame in Figure 11A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "amorphous" and "crystal."

[0147] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 11B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 11B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 11B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 11B is 500 nm.

[0148] As shown in Figure 11B, a peak (intensity) clearly indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 11B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0149] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 11C. Figure 11C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 11C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0150] As shown in Figure 11C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0151] [Oxide semiconductor structure] Note that oxide semiconductors may be classified differently from those shown in FIG. 11A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) and nanocrystalline oxide semiconductor (nc-OS). Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0152] Next, we will explain the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS.

[0153] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0154] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0155] In the In-M-Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0156] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0157] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0158] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0159] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current and field-effect mobility of transistors. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in transistor semiconductor layers. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0160] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0161] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0162] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0163] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0164] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0165] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0166] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0167] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0168] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0169] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0170] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0171] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0172] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0173] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0174] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is preferably 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 100 . Note that in order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may be referred to as an i-type or substantially i-type.

[0175] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0176] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0177] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0178] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0179] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon and carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0180] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0181] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0182] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0183] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0184] [Other semiconductor materials] The semiconductor material that can be used for the semiconductor 112 is not limited to the above-described oxide semiconductor. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor 112. For example, a semiconductor of an element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) may be used as the semiconductor material. In particular, a layered material that functions as a semiconductor is preferably used as the semiconductor material.

[0185] In this specification, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0186] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0187] The semiconductor material used in the semiconductor device according to one embodiment of the present invention may be, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0188] [Film formation method] Conductors, insulators, and semiconductors can be formed using methods such as sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0189] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0190] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0191] The ALD method is also a film formation method that can reduce plasma damage to the workpiece, and because no plasma damage occurs during film formation, the ALD method also produces films with fewer defects.

[0192] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0193] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened by the time required for transportation and pressure adjustment compared to when forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0194] Alternatively, the ALD method may be used to deposit a film by sequentially introducing source gases into a chamber under atmospheric or reduced pressure and repeating this gas introduction sequence. For example, two or more source gases may be sequentially supplied to the chamber by switching between switching valves (also called high-speed valves). To prevent mixing of the multiple source gases, an inert gas (e.g., argon or nitrogen) may be introduced simultaneously with or after the first source gas, followed by the second source gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and may also be introduced simultaneously with the introduction of the second source gas. Alternatively, instead of introducing an inert gas, the first source gas may be evacuated by vacuum evacuation before the second source gas is introduced. The first source gas adsorbs onto the substrate surface to form a first thin layer, which then reacts with the second source gas introduced later, forming a thin film. Repeating this gas introduction sequence multiple times until the desired thickness is achieved allows for the formation of a thin film with excellent step coverage. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing for precise film thickness adjustment, making this method suitable for fabricating fine FETs.

[0195] Thermal CVD methods such as MOCVD and ALD can form a variety of films, including metal films, semiconductor films, and inorganic insulating films. For example, to form an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used. Furthermore, the combinations are not limited to these; trimethylgallium can be replaced with triethylgallium (Ga(C2H5)3), and dimethylzinc can be replaced with diethylzinc (Zn(C2H5)2).

[0196] For example, when forming a hafnium oxide film using a film-forming system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamidohafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizer. Other materials include tetrakis(ethylmethylamido)hafnium.

[0197] For example, when forming an aluminum oxide film using a film formation system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizer. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0198] For example, when forming a silicon oxide film using a film formation apparatus that uses ALD, hexachlorodisilane is adsorbed onto the surface to be filmed, and radicals of oxidizing gas (O2, dinitrogen monoxide) are supplied to react with the adsorbed material.

[0199] For example, when forming a tungsten film using an ALD deposition system, WF6 gas and B2H6 gas are introduced in sequence and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced in sequence and repeatedly to form the tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0200] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film formation system using ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers may also be formed using these gases. While HO gas obtained by bubbling water with an inert gas such as Ar may be used instead of O3 gas, it is preferable to use O3 gas that does not contain H. Furthermore, In(CH3)3 gas may be replaced with In(C2H5)3 gas. Furthermore, Ga(CH3)3 gas may be replaced with Ga(C2H5)3 gas. Moreover, Zn(C2H5)2 gas may be used instead of Zn(CH3)2 gas.

[0201] <Example of connection to peripheral circuits> The memory string 100 according to one embodiment of the present invention may have peripheral circuits such as a read circuit and a precharge circuit formed below it. The transistor TrS shown in FIG. 4 may also be provided in the peripheral circuit. In this case, Si transistors may be formed on a silicon substrate or the like to form the peripheral circuit, and then the memory string 100 according to one embodiment of the present invention may be formed on the peripheral circuit. FIG. 12A is a cross-sectional view of a semiconductor device 200 in which the peripheral circuit is formed of planar Si transistors (transistors TrS_1P and TrS_2P) and the memory string 100 according to one embodiment of the present invention is formed above it. FIG. 13A is a cross-sectional view of a semiconductor device 200A in which the peripheral circuit is formed of FIN Si transistors (transistors TrS_1F and TrS_2F) and the memory string 100 according to one embodiment of the present invention is formed above it.

[0202] The transistors TrS_1P, TrS_2P, TrS_1F, and TrS_2F function as selection transistors, which allow selection of a memory string for reading or writing data.

[0203] Note that the memory string that can be used in the semiconductor device 200 and the semiconductor device 200A is not limited to the memory string 100. Instead of the memory string 100, the memory string 100A, the memory string 100B, or the memory string 100C may be used.

[0204] 12A and 13A, Si transistors constituting the peripheral circuit are formed on a substrate 1700. Element isolation layers 1701 are formed between multiple Si transistors. Conductors 1712 are formed as the sources and drains of the Si transistors. Conductors 1730 are formed to extend in the channel width direction and are connected to other Si transistors or the conductors 1712 (not shown).

[0205] The substrates described above can be used as the substrate 1700. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used.

[0206] The substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Alternatively, a semiconductor element may be formed using a substrate and then transferred to another substrate. Figures 12A and 13A show an example in which a single crystal silicon wafer is used as the substrate 1700.

[0207] 12A, the transistor TrS_1P is electrically connected to the transistor Tr_1, and the transistor TrS_2P is electrically connected to the transistor Tr_n. Also, in FIG. 13A, the transistor TrS_1F is electrically connected to the transistor Tr_1, and the transistor TrS_2F is electrically connected to the transistor Tr_n.

[0208] The gate of the transistor TrS_1 is electrically connected to the wiring SEL_1. One of the source or drain of the transistor TrS_1 is electrically connected to the wiring SL, and the other is electrically connected to one of the source or drain of the transistor Tr_1. The gate of the transistor TrS_2 is electrically connected to the wiring SEL_2. One of the source or drain of the transistor TrS_2 is electrically connected to the wiring BL, and the other is electrically connected to one of the source or drain of the transistor Tr_2n via the conductor 715 and the conductor 752. The conductor 752 is provided so as to be embedded in the insulator 726.

[0209] 12A and 13A, an insulator 1203 is formed to cover the conductor 104, the memory string 100, and the like. It is preferable to use an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen as the insulator 1203. By using an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen as the insulator 1203, it is possible to suppress the diffusion of impurities from the outside (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.)) into the memory string 100.

[0210] Here, the Si transistor will be described in detail. Fig. 12A shows a cross-sectional view of planar Si transistors (transistors TrS_1P and TrS_2P) in the channel length direction, and Fig. 12B shows a cross-sectional view of the planar Si transistor in the channel width direction. The Si transistor has a channel formation region 1793 provided in a well 1792, a low-concentration impurity region 1794 and a high-concentration impurity region 1795 (collectively referred to as impurity regions), a conductive region 1796 provided in contact with the impurity region, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, and sidewall insulating layers 1798 and 1799 provided on the side surfaces of the gate electrode 1790. Note that the conductive region 1796 may be made of a metal silicide or the like.

[0211] 13A shows a cross-sectional view of FIN-type Si transistors (transistors TrS_1F and TrS_2F) in the channel length direction, and FIG. 13B shows a cross-sectional view of the FIN-type Si transistor in the channel width direction. The Si transistor shown in FIGS. 13A and 13B has a channel formation region 1793 having a convex shape, and a gate insulating film 1797 and a gate electrode 1790 are provided along the side and upper surfaces of the channel formation region 1793. In this embodiment, a case has been shown in which a convex portion is formed by processing a part of a semiconductor substrate, but a semiconductor layer having a convex shape may also be formed by processing an SOI substrate. Note that the reference numerals shown in FIGS. 13A and 13B are the same as those shown in FIGS. 12A and 12B.

[0212] <Memory string operation example> Next, an operation example of a memory string according to one embodiment of the present invention will be described with reference to the drawings. Here, the operation example of the memory string will be described using a memory string 250 having three memory cells and two select transistors as an example. FIG. 14A shows a circuit diagram of the memory string 250.

[0213] The configuration of memory string 250 corresponds to the configuration of memory string 100A. Therefore, in this embodiment, an example of the operation of memory string 100A will be described, but the operations of memory string 100, memory string 100B, and memory string 100C can be understood in a similar manner.

[0214] As described above, the transistor Tr functions as a memory cell. Data is written by injecting charges into the charge storage layer (functional layer 114) included in the transistor Tr. The transistor Tr is preferably a transistor that functions as a normally-on type transistor after data erasure. Furthermore, the transistors TrS_1 and TrS_2 are preferably normally-off type transistors.

[0215] Here, the Id-Vg characteristics of the transistor will be described. FIG. 14B is a diagram for explaining an example of the Id-Vg characteristics of the transistor. The horizontal axis in FIG. 14B represents the gate voltage (Vg), and the vertical axis represents the drain current (Id). Characteristic 251 shows the Id-Vg characteristics of a normally-off transistor, and characteristic 252 shows the Id-Vg characteristics of a normally-on transistor.

[0216] For a normally-off transistor, the channel resistance value (the resistance value between the source and the drain) when Vg is 0V is extremely large and almost no Id flows. On the other hand, for a normally-on transistor, the channel resistance value when Vg is 0V is small, and more Id flows compared to the normally-off transistor. Generally, when the transistor is an n-channel type transistor, the threshold voltage VthD of the normally-on transistor and the threshold voltage VthE of the normally-off transistor satisfy the relationship VthD < VthE.

[0217] [Erase operation] When writing information to any memory cell, it is necessary to first erase the previously written data. In this embodiment, it is assumed that electrons corresponding to the data "1" are injected into the charge storage layers of transistors Tr_1 to Tr_3. The Id-Vg characteristics of transistors Tr_1 to Tr_3 at this time correspond to characteristic 251 shown in FIG. 14B.

[0218] FIG. 15A is a timing chart for explaining the erase operation. FIG. 15B is a circuit diagram showing the operating state of the memory string 250 during period T12. Also, in circuit diagrams showing the operating state, etc., in order to clearly show the potential of wirings, etc., symbols such as "H" indicating the H potential or "L" indicating the L potential may be marked adjacent to the wirings. Also, symbols such as the aforementioned "H" or the aforementioned "L" may be enclosed in characters and marked on wirings where potential changes occur. Also, an "×" symbol may be marked over the off-state transistor.

[0219] In the period T11, an L potential (0 V) is supplied to the wirings BL, SL, SEL_1, SEL_2, CG_1 to CG_3, and BGL.

[0220] In period T12, the VE potential is supplied to the wiring BL, the wiring SL, the wiring SEL_1, the wiring SEL_2, and the wiring BGL. The VE potential is a potential higher than the H potential. For example, if the H potential is 5 V, the VE potential is preferably 10 to 30 V, more preferably 15 to 25 V. The VE potential is preferably 2 to 6 times the H potential, more preferably 3 to 5 times the H potential. The VE potential is a potential that allows electrons to be emitted from the charge storage layer (functional layer 114) to the semiconductor 112 through the tunnel layer (insulator 113) due to the potential difference between the VE potential and the L potential.

[0221] Oxide semiconductors are almost unable to generate holes. Therefore, when an oxide semiconductor is used for the semiconductor 112, data cannot be erased by injecting holes. Therefore, data must be erased by extracting electrons from the charge storage layer. However, erasure by extracting electrons takes longer than erasure by injecting holes.

[0222] By supplying the L potential to the wiring CG and a potential higher than the H potential to the wiring BGL, electrons can be extracted from the charge storage layer to the semiconductor layer quickly and reliably.

[0223] 16 shows a cross-sectional view of a part of the transistor Tr_2 (memory cell) during the period T12, and schematically shows the movement of electrons during the period T12.

[0224] In the period T13, an L potential is supplied to the wirings BL, SL, SEL_1, SEL_2, CG_1 to CG_3, and BGL. In this manner, the data stored in the transistor Tr_2 can be erased. By erasing the data, the threshold voltage of the transistor Tr shifts in the negative direction, and the transistor Tr becomes a normally-on transistor. The Id-Vg characteristics of the transistor Tr at this time correspond to the characteristics 252 shown in FIG. 14B. Therefore, it can be considered that the transistor Tr stores data "0."

[0225] Furthermore, the memory strings for which data erasure is performed share the wirings BL, SL, SEL_1, and SEL_2, but for memory strings for which data erasure is not performed, the wiring CG connected to the latter memory strings can be set to a floating state, or the VE potential can be supplied to the wiring CG connected to the latter memory strings.

[0226] [Write operation] Next, a write operation will be described. The write operation is performed after the erase operation. In this embodiment, an example of a write operation to the transistor Tr_2 will be described. In this embodiment, an operation of writing data "1" to the transistor Tr_2 will be described.

[0227] Fig. 17A is a timing chart for explaining the write operation, and Fig. 17B is a circuit diagram showing the operating state of the memory string 250 during period T22.

[0228] In the period T21, an L potential is supplied to the wirings BL, SL, BGL, SEL_1, and SEL_2. An H potential is supplied to the wirings CG_1 to CG_3. Note that the H potential is a potential that can turn on a normally-off transistor. The H potential may be 5 V or more and 10 V or less. Supplying the H potential to the wirings CG_1 to CG_3 can turn on the transistors Tr_1 to Tr_3.

[0229] In period T22, an H potential is supplied to the wiring SEL_1 and the wiring SEL_2. A VP potential is supplied to the wiring CG_2. The VP potential is a potential higher than the H potential. The VP potential is a potential that allows electrons to be injected from the semiconductor 112 to the charge storage layer (functional layer 114) through the tunnel layer (insulator 113) due to the potential difference between the VP potential and the L potential. For example, if the H potential is 5 V, the VP potential should be 10 V or more and 20 V or less. The VP potential should be two to four times the H potential.

[0230] In a period T22, the VP potential is supplied to the wiring CG_2, thereby injecting electrons into the charge storage layer (functional layer 114).

[0231] 18 shows a cross-sectional view of a part of the transistor Tr_2 (memory cell) during the period T22, and schematically shows the movement of electrons and holes during the period T22.

[0232] In the period T23, an L potential is supplied to the wirings BL, SL, BGL, SEL_1, SEL_2, and CG_1 to CG_3. In this manner, data "1" can be written to the transistor Tr_2. By writing data "1," the threshold voltage of the transistor Tr_2 is shifted in the positive direction, and the transistor Tr_2 becomes a normally-off transistor. The Id-Vg characteristics of the transistor Tr_2 at this time correspond to the characteristics 251 shown in FIG. 14B.

[0233] [Read operation] Next, a read operation will be described. In this embodiment, a read operation of data held in transistor Tr_2 will be described. Fig. 19A is a timing chart for explaining the read operation. Fig. 19B is a circuit diagram showing the operating state of the memory string 250 during period T32.

[0234] In the period T31, an L potential is supplied to the wirings SL, BGL, SEL_1, SEL_2, and CG_1 to CG_3. A VDD potential is supplied to the wiring BL. The VDD potential may be higher than the L potential. For example, the VDD potential may be higher than the L potential and lower than the H potential. For example, when the L potential is 0 V and the H potential is 5 V, the VDD potential may be 3 V.

[0235] In a period T32, while the VDD potential is still supplied to the wiring BL, the H potential is supplied to the wirings SEL_1, SEL_2, CG_1, and CG_3, and the L potential is maintained on the wiring CG_2.

[0236] When transistor Tr_2 (memory cell) holds data "0," it functions as a normally-on transistor and does not turn off even if wiring CG_2 is at an L potential. On the other hand, when transistor Tr_2 holds data "1," it functions as a normally-off transistor and turns off when wiring CG_2 is at an L potential. Therefore, the magnitude of the current flowing between wiring BL and wiring SL changes depending on the data held by transistor Tr_2 (memory cell). In other words, the magnitude of the current flowing through wiring BL or the magnitude of the current flowing through wiring SL changes. By measuring the current value of wiring BL or wiring SL, the information held (stored) in the memory cell can be read.

[0237] In the period T33, an L potential is supplied to the wirings BL, SL, BGL, SEL_1, SEL_2, and CG_1 to CG_3. In this manner, data held in the transistor Tr_2 can be read.

[0238] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0239] (Embodiment 2) A memory string 300 according to one embodiment of the present invention will be described with reference to the drawings. The memory string 300 is a modified example of the memory string 100A described in the above embodiment. Therefore, in this embodiment, the description overlapping with the above embodiment will be kept to a minimum.

[0240] Fig. 20 is a cross-sectional view of the memory string 300 as viewed from the Y direction. Fig. 21A is a cross-sectional view of a portion G1-G2 indicated by a dashed line in Fig. 20 as viewed from the Z direction. Fig. 21B is a cross-sectional view of a portion H1-H2 indicated by a dashed line in Fig. 20 as viewed from the Z direction.

[0241] The memory string 300 has a structure 110U. FIG. 20 shows a central axis 131U of the memory string 300. The central axis 131U corresponds to the central axis 131 of the memory string 100A. The structure 110U is a structure 110 that has a U-shape when viewed from the Y direction (also referred to as a "U-shape"). The structure 110U has two portions (portion 141, portion 142) that extend in the Z direction and a portion (portion 143) that extends in the X direction. The central axis 131U extends in the Z direction at portion 141 and portion 142, and in the X direction at portion 143.

[0242] Similar to the structure 110, the structure 110U includes a conductor 106, an insulator 111, a semiconductor 112, an insulator 113, a functional layer 114, and an insulator 115. In the structure 110U, the conductor 106 extends along the central axis 131U, the insulator 111 is provided adjacent to a side surface of the conductor 106, and the semiconductor 112 is provided adjacent to a side surface of the insulator 111. The insulator 113 is provided adjacent to the semiconductor 112, and the functional layer 114 is provided adjacent to the insulator 113. The insulator 115 is provided adjacent to the functional layer 114. The insulator 111, the semiconductor 112, the insulator 113, the functional layer 114, and the insulator 115 form a U-shape when viewed from the Y direction. As shown in FIGS. 21A and 21B, the semiconductor 112, the insulator 113, the functional layer 114, the insulator 115, and the insulator 111 are each provided concentrically outside the conductor 106.

[0243] The memory string 300 has an insulator 126 instead of the conductor 101 shown in FIG. 1 and the like. The portions 141 and 142 are provided above the insulator 126. The portion 143 is provided so as to be embedded in the insulator 126.

[0244] One end of the structure 110U is connected to the conductor 104a, and the other end is connected to the conductor 104b. In particular, one end of the semiconductor 112 included in the structure 110U is electrically connected to the conductor 104a, and the other end is electrically connected to the conductor 104b. Furthermore, the conductor 106 is electrically connected to the conductor 104b, but is not connected to the conductor 104a.

[0245] An insulator 105 is provided on the conductor 104a and the conductor 104b, and a conductor 124 is provided on the insulator 105. An insulator 123 is provided on the conductor 124. The conductor 104a and the conductor 124 are electrically connected via a conductor 122.

[0246] In the regions 141 and 142, the regions (intersections) where the structure 110U and the conductor 103 overlap function as transistors Tr. Therefore, the regions (intersections) where the structure 110U and the conductor 103 overlap function as memory cells. In FIG. 20, n transistors Tr are provided in each of the regions 141 and 142. In FIG. 20, the transistor Tr closest to the conductor 104a in the region 141 is designated as "transistor Tr_1," and the transistor Tr closest to the region 143 is designated as "transistor Tr_n." In the region 142, the transistor Tr closest to the conductor 104b is designated as "transistor Tr_2n," and the transistor Tr closest to the region 143 is designated as "transistor Tr_n+1." In FIG. 20, the conductor 103 that can function as the gate electrode of transistor Tr_1 is designated as conductor 103_1. In addition, the conductor 103 that can function as the gate electrode of transistor Tr_2n is designated as conductor 103_2n.

[0247] The transistors Tr functioning as memory cells are provided in a portion overlapping with portion 141 of the memory string 300 and a portion overlapping with portion 142. Therefore, the portion of the memory string 300 overlapping with portion 141 can be considered to be the memory string 100A. Similarly, the portion of the memory string 300 overlapping with portion 142 can be considered to be the memory string 100A. Furthermore, portion 143 can be considered to be a connecting portion for electrically connecting two memory cells. Therefore, it can be said that the memory string 300 has a configuration in which two adjacent memory strings 100A are electrically connected via a connecting portion.

[0248] The memory string 300 also has a region between the transistor Tr_1 and the conductor 104a where the structure 110U and the conductor 103_s1 overlap. The conductor 103_s1 extends in the Y direction. This region functions as the transistor TrS_1. The memory string 300 also has a region between the transistor Tr_2n and the conductor 104b where the structure 110U and the conductor 103_s2 overlap. This region functions as the transistor TrS_2. The transistors TrS_1 and TrS_2 function as selection transistors.

[0249] One of the conductor 124 and the conductor 104b is electrically connected to a wiring SL, and the other is electrically connected to a wiring BL. For example, the conductor 104b is electrically connected to a wiring SL, and the other is electrically connected to a wiring BL. Alternatively, one of the conductor 124 and the conductor 104b may function as the wiring SL, and the other may function as the wiring BL.

[0250] The memory string 300 has select transistors provided on the peripheral circuit side provided inside the memory string 300. This makes it possible to reduce the number of transistors on the peripheral circuit side, thereby improving the degree of freedom in designing the peripheral circuit side.

[0251] 22 shows an equivalent circuit diagram of the memory string 300. For the equivalent circuit diagram, the explanation of the equivalent circuit diagram shown in FIG. 4 may be referred to.

[0252] Increasing the number of stacked transistors Tr to increase the storage capacity per memory string increases the aspect ratio, making structures more likely to collapse during the manufacturing process. Because the memory string 300 according to one embodiment of the present invention has a U-shaped structure, collapse of structures during the manufacturing process is unlikely to occur if the storage capacity per memory string is the same. Therefore, productivity of a semiconductor device including a memory string according to one embodiment of the present invention can be improved.

[0253] 23, an insulator 1203 may be provided to cover the memory string 300. The insulator 1203 is preferably an insulator that has a function of suppressing permeation of impurities such as hydrogen and oxygen.

[0254] 24 is a cross-sectional view showing an example of connection between two adjacent memory strings 300 (memory string 300_1 and memory string 300_2). In FIG. 24, the structure 110U included in memory string 300_1 is shown as structure 110U_1, and the structure 110U included in memory string 300_2 is shown as structure 110U_2.

[0255] One end of the structure 110U_1 is connected to the conductor 104a, and the other end is connected to the conductor 125. Furthermore, one end of the structure 110U_2 is connected to the conductor 104b, and the other end is connected to the conductor 125. The conductor 125 is provided in the same layer as the conductor 104 (the conductor 104a and the conductor 104b). Furthermore, the conductor 104a is electrically connected to the conductor 124 via the conductor 122a, and the conductor 104b is electrically connected to the conductor 124 via the conductor 122b.

[0256] One of the conductor 124 and the conductor 125 functions as a wiring SL, and the other functions as a wiring BL. Alternatively, one of the conductor 124 and the conductor 125 is electrically connected to the wiring SL, and the other is electrically connected to the wiring BL.

[0257] 24, the transistor TrS_1 provided near one end of the structure 110U_1 is indicated as a transistor TrS_1a, and the transistor TrS_2 provided near the other end is indicated as a transistor TrS_2a. Also, the transistor TrS_1 provided near one end of the structure 110U_2 is indicated as a transistor TrS_1b, and the transistor TrS_2 provided near the other end is indicated as a transistor TrS_2b.

[0258] By controlling the operation of the selection transistors (transistor TrS_1 and transistor TrS_2), data can be read from or written to only one of the two memory strings 300.

[0259] [Variation 1] Figure 25 shows a cross-sectional view of memory string 300A, which is a modified example of memory string 300. Figure 26 is an equivalent circuit diagram of memory string 300A shown in Figure 25. As shown in Figure 25, conductor 106 and conductor 104a may be electrically connected, but conductor 106 and conductor 104b may not be connected. In other words, conductor 106 may be electrically connected to wiring BL.

[0260] [Variation 2] 27 shows a cross-sectional view of memory string 300B, which is a modified example of memory string 300. Memory string 300B uses the transistor Tr shown in memory string 100C as the transistor Tr. Memory string 300B has a structure 110AU instead of structure 110U. Structure 110AU has a structure obtained by removing functional layer 114 and insulator 115 from structure 110U.

[0261] [Variation 3] Fig. 28 shows a cross-sectional view of a memory string 300C, which is a modified example of the memory string 300. Fig. 29 is a cross-sectional view of the portion J1-J2 indicated by the dashed dotted line in Fig. 28, as viewed from the Z direction.

[0262] 28 and 29, the functional layer 114 and the insulator 115 may not be provided at the intersection of the structure 110U and the conductor 103_s (the conductor 103_s1 and the conductor 103_s2) that functions as the transistor TrS (the transistor TrS_1 and the transistor TrS_2). By not providing the functional layer 114 and the insulator 115 at the intersection, the operating speed of the transistor TrS can be improved.

[0263] [Variation 4] 30 shows a cross-sectional view of memory string 300D, which is a modification of memory string 300 and memory string 300C. In memory string 300D, at the intersection of structure 110U and conductor 103_s (conductor 103_s1 and conductor 103_s2) that functions as transistor TrS, insulator 113, functional layer 114, and insulator 115 are not provided, and instead, insulator 136 is provided between conductor 103_s and semiconductor 112.

[0264] The insulator 136 functions as a gate insulating film of the transistor TrS. It is preferable to use a thermal oxide film or the like for the insulator 136. For example, the conductor 103_s is formed from low-resistance silicon, and the surface of the conductor 103_s is oxidized in a high-temperature atmosphere containing oxygen to form silicon oxide (thermal oxide film), which can then be used as the insulator 136. The silicon oxide has excellent dielectric strength and can be thinned. This can improve the operating speed of the transistor TrS.

[0265] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0266] (Embodiment 3) In this embodiment, a semiconductor device 400 including a memory device or a semiconductor device according to one embodiment of the present invention will be described.

[0267] Fig. 31 is a block diagram showing an example configuration of a semiconductor device 400. The semiconductor device 400 shown in Fig. 31 has a drive circuit 410 and a memory array 420. The memory array 420 has one or more memory strings 100. Fig. 31 shows an example in which the memory array 420 has a plurality of memory strings 100 arranged in a matrix.

[0268] The drive circuit 410 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 415. The peripheral circuit 415 includes a peripheral circuit 411, a control circuit 412, and a voltage generation circuit 428.

[0269] In the semiconductor device 400, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0270] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by control circuit 412.

[0271] The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 400. Alternatively, the control circuit 412 generates a control signal for the peripheral circuit 411 so that this operation mode is executed.

[0272] The voltage generating circuit 428 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 428. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 428, and the voltage generating circuit 428 generates a negative voltage.

[0273] The peripheral circuit 411 is a circuit for writing and reading data to and from the memory string 100. The peripheral circuit 411 includes a row decoder 441, a column decoder 442, a row driver 423, a column driver 424, an input circuit 425, an output circuit 426, and a sense amplifier 427.

[0274] The row decoder 441 and the column decoder 442 have the function of decoding the signal ADDR. The row decoder 441 is a circuit for specifying a row to access, and the column decoder 442 is a circuit for specifying a column to access. The row driver 423 has the function of selecting the wiring CG specified by the row decoder 441. The column driver 424 has the function of writing data to the memory string 100, reading data from the memory string 100, and holding the read data.

[0275] The input circuit 425 has a function of holding a signal WDA. The data held by the input circuit 425 is output to the column driver 424. The output data of the input circuit 425 is data (Din) to be written to the memory string 100. The data (Dout) read from the memory string 100 by the column driver 424 is output to the output circuit 426. The output circuit 426 has a function of holding Dout. In addition, the output circuit 426 has a function of outputting Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is a signal RDA.

[0276] The PSW241 has a function of controlling the supply of VDD to the peripheral circuit 415. The PSW242 has a function of controlling the supply of VHM to the row driver 423. In this example, the high power supply voltage of the semiconductor device 400 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW241 is controlled by a signal PON1, and the on / off of the PSW242 is controlled by a signal PON2. In FIG. 31, the number of power domains to which VDD is supplied in the peripheral circuit 415 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0277] The drive circuit 410 and memory array 420 of the semiconductor device 400 may be provided on the same plane. Alternatively, as shown in FIG. 32, the drive circuit 410 and memory array 420 may be provided overlapping each other. By providing the drive circuit 410 and memory array 420 overlapping each other, the signal propagation distance can be shortened. FIG. 32 also includes an enlarged perspective view of a portion of the semiconductor device 400.

[0278] Furthermore, the semiconductor device 400 may use an arithmetic processing device such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) as the control circuit 412 of the drive circuit 410. By using a CPU and / or a GPU, the semiconductor device 400 can be realized with an arithmetic processing function.

[0279] By using the memory string 100 according to one embodiment of the present invention, a part of the memory array 420 can function as a main memory or a cache memory. The memory string 100 can also function like a flash memory. Therefore, a part of the memory array 420 can function like a flash memory. The semiconductor device 400 according to one embodiment of the present invention can function as a universal memory.

[0280] Furthermore, according to one aspect of the present invention, the functions of a CPU, a cache memory, and a storage can be realized on the same chip.

[0281] 32 includes a driver circuit 410 including a CPU and a 3D OS NAND memory device according to one embodiment of the present invention in a memory array 420. The 3D OS NAND memory device according to one embodiment of the present invention functions as a cache memory and a storage.

[0282] 33 shows how a host 450 manages a plurality of semiconductor devices 400. Each semiconductor device 400 has an arithmetic processing function and can perform parallel writing and reading to a cache memory and storage. By having the host 450 manage a plurality of semiconductor devices 400, an information processing system that realizes non-von Neumann computing can be constructed.

[0283] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0284] (Fourth embodiment) In this embodiment mode, an example of a processing unit that can include a semiconductor device such as the memory device described in the above embodiment mode will be described.

[0285] 34 is a block diagram of the arithmetic processing device 1100. In FIG. 34, an example of the configuration of a CPU is shown as an example of the configuration that can be used for the arithmetic processing device 1100.

[0286] The arithmetic processing device 1100 shown in FIG. 34 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a cache 1199, and a cache interface 1189 on a substrate 1190. The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 may also be provided on separate chips.

[0287] The cache 1199 is connected to a main memory provided on a separate chip via a cache interface 1189. The cache interface 1189 has a function of supplying a portion of the data held in the main memory to the cache 1199. The cache 1199 has a function of holding that data.

[0288] The arithmetic processing device 1100 shown in Figure 34 is merely one example of a simplified configuration, and actual arithmetic processing devices 1100 have a wide variety of configurations depending on their applications. For example, the arithmetic processing device 1100 shown in Figure 34 or a configuration including an arithmetic circuit may be used as one core, and a configuration may be used in which multiple such cores operate in parallel, i.e., a GPU-like configuration. Furthermore, the number of bits that the arithmetic processing device 1100 can handle in its internal arithmetic circuit or data bus may be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0289] An instruction input to the processor 1100 via the bus interface 1198 is input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0290] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Furthermore, the interrupt controller 1194 processes interrupt requests from external input / output devices and peripheral circuits based on their priority and mask status while the arithmetic processing unit 1100 is executing a program. The register controller 1197 generates addresses for the register 1196 and reads and writes data from and to the register 1196 depending on the state of the arithmetic processing unit 1100.

[0291] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0292] 34, a memory device is provided in the register 1196 and the cache 1199. As the memory device, for example, the memory device described in the above embodiment can be used.

[0293] In the arithmetic processing device 1100 shown in FIG. 34, the register controller 1197 selects the holding operation of the register 1196 in accordance with an instruction from the ALU 1191. That is, it selects whether to hold data in a flip-flop or a capacitive element in the memory cell of the register 1196. If holding data in a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. If holding data in a capacitive element is selected, the data is rewritten to the capacitive element, and the supply of power supply voltage to the memory cell in the register 1196 can be stopped.

[0294] The arithmetic processing device 1100 is not limited to a CPU, but may be a GPU, a DSP (Digital Signal Processor), an FPGA (Field-Programmable Gate Array), or the like.

[0295] The semiconductor device 400 and the processing unit 1100 described in the above embodiment can be provided overlapping each other. FIGS. 35A and 35B show perspective views of a semiconductor device 1150A. The semiconductor device 1150A has a semiconductor device 400 functioning as a memory device on the processing unit 1100. The processing unit 1100 and the semiconductor device 400 have overlapping regions. To make the configuration of the semiconductor device 1150A easier to understand, the processing unit 1100 and the semiconductor device 400 are shown separately in FIG. 35B.

[0296] By stacking the semiconductor device 400 and the arithmetic processing device 1100, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0297] Furthermore, multiple semiconductor devices 400 may be provided on top of the arithmetic processing device 1100. Perspective views of a semiconductor device 1150B are shown in FIGS. 36A and 36B. The semiconductor device 1150B has a semiconductor device 400a and a semiconductor device 400b on the arithmetic processing device 1100. The arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions. To make the configuration of the semiconductor device 1150B easier to understand, the arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately in FIG. 36B.

[0298] The semiconductor device 400a and the semiconductor device 400b function as memory devices. For example, one of the semiconductor device 400a and the semiconductor device 400b may be a NOR memory device, and the other may be a NAND memory device. Both the semiconductor device 400a and the semiconductor device 400b may be NAND memory devices. Examples of NOR memory devices include DRAM and SRAM. Since NOR memory devices can operate faster than NAND memory devices, for example, part of the semiconductor device 400a can be used as the main memory and / or cache 1199. Note that the stacking order of the semiconductor device 400a and the semiconductor device 400b may be reversed.

[0299] 37A and 37B show perspective views of semiconductor device 1150C. Semiconductor device 1150C has a configuration in which arithmetic processing device 1100 is sandwiched between semiconductor device 400a and semiconductor device 400b. The arithmetic processing device 1100, semiconductor device 400a, and semiconductor device 400b have overlapping regions. To make the configuration of semiconductor device 1150C easier to understand, FIG. 37B shows arithmetic processing device 1100, semiconductor device 400a, and semiconductor device 400b separately.

[0300] The configuration of the semiconductor device 1150C can increase the communication speed between the semiconductor device 400a and the arithmetic processing unit 1100 and the communication speed between the semiconductor device 400b and the arithmetic processing unit 1100. In addition, the power consumption can be reduced compared to the semiconductor device 1150B.

[0301] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0302] (Embodiment 5) In this embodiment mode, an example of a semiconductor wafer on which the semiconductor device or the like described in the above embodiment mode is formed and an electronic component in which the semiconductor device is incorporated will be described.

[0303] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 38A.

[0304] 38A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of wafer 4801. Note that on the upper surface of wafer 4801, a portion where circuit portions 4802 are not present is spacing 4803, which is an area for dicing.

[0305] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0306] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0307] By performing a dicing process, chips 4800a as shown in FIG. 38B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0308] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 38A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the device for manufacturing the element.

[0309] <Electronic components> 38C is a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 38C includes a chip 4800a in a mold 4711. A memory device according to one embodiment of the present invention or the like can be used as the chip 4800a.

[0310] 38C omits some parts to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0311] 38D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0312] The semiconductor device 4710 may be, for example, a chip 4800a, the semiconductor device described in the above embodiment, or a high bandwidth memory (HBM). The semiconductor device 4735 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0313] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0314] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0315] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0316] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0317] Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0318] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0319] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. Fig. 38D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0320] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0321] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0322] (Sixth embodiment) In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0323] A storage device according to one embodiment of the present invention can be applied to, for example, storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0324] 39A to 39J and 40A to 40E illustrate examples of electronic devices including a memory device according to one embodiment of the present invention, each of which includes an electronic component 4700 or an electronic component 4730 including the memory device.

[0325] [mobile phone] 39A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0326] By applying a storage device according to one embodiment of the present invention, the information terminal 5500 can store temporary files (such as caches when using a web browser) generated when an application is executed.

[0327] [Wearable devices] 39B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0328] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0329] [Information terminal] 39C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0330] Like the information terminal 5500 described above, the desktop information terminal 5300 can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0331] 39A to 39C are taken as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0332] [electric appliances] 39D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. Electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0333] A storage device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the storage device.

[0334] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0335] [Game consoles] 39E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0336] FIG. 39F further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 39F, the controller 7522 can include a display unit that displays game images, and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 39F, and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0337] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0338] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0339] Furthermore, by applying the storage device described in the above embodiments to the portable game console 5200 or the stationary game console 7500, temporary files and the like required for calculations that occur during game execution can be stored.

[0340] As an example of a game machine, a portable game machine is shown in FIG. 39E. Also, a home-use stationary game machine is shown in FIG. 39F. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0341] [Moving object] The storage device described in the above embodiment can be applied to a vehicle, which is a moving object, and to the vicinity of the driver's seat of the vehicle.

[0342] FIG. 39G illustrates an automobile 5700 as an example of a moving object.

[0343] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0344] In particular, the display device can compensate for the view obstructed by pillars and the blind spot of the driver's seat by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby improving safety. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, it is possible to compensate for the blind spot and improve safety.

[0345] The storage device described in the above embodiment can temporarily store information, and therefore, for example, the storage device can be used to store necessary temporary information in an automatic driving system for the automobile 5700, a system that provides road guidance, hazard prediction, or the like. The display device may be configured to display temporary information such as road guidance and hazard prediction. The display device may also be configured to store video images from a driving recorder installed in the automobile 5700.

[0346] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0347] [camera] The storage device described in the above embodiment can be applied to a camera.

[0348] 39H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, here, the digital camera 6240 is configured so that the lens 6246 can be detached from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured so that a strobe device, a viewfinder, etc. can be separately attached.

[0349] A low-power digital camera 6240 can be realized by applying the storage device described in the above embodiment to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0350] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0351] 39I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0352] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the storage device described above, the video camera 6300 can store temporary files generated during encoding.

[0353] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0354] 39J is a cross-sectional schematic diagram showing an example of an ICD. ICD main body 5400 has at least battery 5401, electronic components 4700, a regulator, a control circuit, antenna 5404, wire 5402 to the right atrium, and wire 5403 to the right ventricle.

[0355] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0356] The ICD main unit 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (such as in the case of rapid ventricular tachycardia or ventricular fibrillation), treatment with an electric shock is administered.

[0357] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 4700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration, and so on.

[0358] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 can also function as an auxiliary power source.

[0359] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0360] [PC expansion device] The storage devices described in the above embodiments can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0361] Figure 40A shows an example of such an expansion device: a portable expansion device 6100 that is external to a PC and equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). Note that while Figure 40A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan or the like.

[0362] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with circuits that drive the storage devices and the like described in the above embodiments. For example, the board 6104 is equipped with an electronic component 4700 and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to an external device.

[0363] [SD card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0364] FIG. 40B is a schematic diagram of the external appearance of an SD card, and FIG. 40C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the circuit board 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, and the like provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0365] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.

[0366] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0367] FIG. 40D is a schematic diagram of the external appearance of an SSD, and FIG. 40E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a storage device and a circuit for driving the storage device. For example, the circuit board 5153 is equipped with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0368] [Calculator] 41A is an example of a large-scale computer. The computer 5600 has a rack 5610 storing a plurality of rack-mounted computers 5620.

[0369] Computer 5620 can have the configuration shown in the perspective view in Fig. 41B, for example. In Fig. 41B, computer 5620 has motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

[0370] PC card 5621 shown in FIG. 41C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 41C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0371] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0372] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0373] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0374] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0375] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. The semiconductor device 5628 can be, for example, a memory device. The electronic component 4700 can be used as the semiconductor device 5628.

[0376] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0377] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller, faster, or consume less power. Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which reduces heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0378] Next, a configuration example of a computer system applicable to the calculator 5600 will be described. Fig. 42 is a diagram illustrating a configuration example of a computer system 700. The computer system 700 is configured to include software and hardware. Note that the hardware included in a computer system may be referred to as an information processing device.

[0379] The software that makes up the computer system 700 includes an operating system including device drivers, middleware, various development environments, AI-related application programs (AI applications), and application programs unrelated to AI.

[0380] The device driver includes an application program for controlling an auxiliary storage device, a display device, a printer, and other externally connected devices.

[0381] The hardware that constitutes the computer system 700 includes a first processor, a second processor, a first storage device, etc. The second processor also includes a second storage device.

[0382] The first processing unit may be, for example, a central processing unit such as a Noff OS CPU. The Noff OS CPU has a storage means (e.g., nonvolatile memory) using OS transistors, and has a function of storing necessary information in the storage means and stopping the power supply to the central processing unit when operation is not required. Using a Noff OS CPU as the first processing unit can reduce the power consumption of the computer system 700.

[0383] The second arithmetic processing device can be, for example, a GPU or an FPGA. It is preferable to use an AI OS Accelerator as the second arithmetic processing device. The AI ​​OS Accelerator is configured using OS transistors and has arithmetic means such as a product-sum operation circuit. The AI ​​OS Accelerator consumes less power than a general GPU. Using the AI ​​OS Accelerator as the second arithmetic processing device can reduce the power consumption of the computer system 700.

[0384] It is preferable to use a storage device according to an embodiment of the present invention as the first storage device and the second storage device. For example, it is preferable to use a 3D OS NAND type storage device. The 3D OS NAND type storage device can function as a cache, a main memory, and a storage. Furthermore, using a 3D OS NAND type storage device makes it easier to realize a non-von Neumann type computer system.

[0385] A 3D OS NAND type storage device consumes less power than a 3D NAND type storage device that uses Si transistors. Using a 3D OS NAND type storage device as a storage device can reduce the power consumption of the computer system 700. In addition, because a 3D OS NAND type storage device can function as a universal memory, the number of parts required to configure the computer system 700 can be reduced.

[0386] By configuring the semiconductor device constituting the hardware with a semiconductor device including an OS transistor, it becomes easy to monolithically integrate the hardware including the central processing unit, the processing unit, and the storage device. Monolithic integration of the hardware not only makes it possible to reduce the size, weight, and thickness of the hardware, but also facilitates further reduction in power consumption.

[0387] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0388] (Embodiment 7) A normally-off CPU (also referred to as an "Noff-CPU") can be realized by using the OS memory described in this specification. Note that an Noff-CPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an "off state") even when the gate voltage is 0 V.

[0389] The Noff-CPU can stop the power supply to circuits within the Noff-CPU that are not in operation, putting those circuits into a standby state. When the power supply is stopped and the circuit is in a standby state, no power is consumed. Therefore, the Noff-CPU can minimize power consumption. Furthermore, the Noff-CPU can retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite setting conditions, etc. In other words, it is possible to quickly return from the standby state. In this way, the Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0390] The Noff-CPU can be suitably used in small-scale systems such as IoT terminal devices (also called "endpoint microcomputers") 803 in the field of IoT (Internet of Things).

[0391] Figure 43 shows the hierarchical structure of an IoT network and trends in required specifications. In Figure 43, power consumption 804 and processing performance 805 are shown as required specifications. The hierarchical structure of an IoT network is broadly divided into an upper-level cloud field 801 and a lower-level embedded field 802. The cloud field 801 includes, for example, servers. The embedded field 802 includes, for example, machines, industrial robots, in-vehicle devices, and home appliances.

[0392] The higher the layer, the more processing performance is required rather than low power consumption. Therefore, in the cloud field 801, high-performance CPUs, high-performance GPUs, large-scale SoCs (System on a Chip), etc. are used. Furthermore, the lower the layer, the more power consumption is required rather than processing performance, and the number of devices increases explosively. A semiconductor device according to one embodiment of the present invention can be suitably used for a communication device of an IoT terminal device that requires low power consumption.

[0393] The term "endpoint" refers to the terminal area of ​​the embedded field 802. Devices used as endpoints include, for example, microcomputers used in factories, home appliances, infrastructure, agriculture, and the like.

[0394] FIG. 44 illustrates an image of factory automation as an application example of an endpoint microcontroller. A factory 884 is connected to a cloud 883 (server) via an Internet line. The cloud 883 is connected to a home 881 and an office 882 via the Internet line. The Internet line may be a wired communication system or a wireless communication system. For example, in the case of a wireless communication system, a semiconductor device according to one embodiment of the present invention may be used in a communication device to perform wireless communication in accordance with a communication standard such as a fourth-generation mobile communication system (4G) or a fifth-generation mobile communication system (5G). The factory 884 may be connected to factories 885 and 886 via the Internet line.

[0395] The factory 884 has a master device (control device) 831. The master device 831 has a function of connecting to a cloud 883 and transmitting and receiving information. The master device 831 is also connected to a plurality of industrial robots 842 included in an IoT terminal device 841 via an M2M (Machine to Machine) interface 832. As the M2M interface 832, for example, industrial Ethernet ("Ethernet" is a registered trademark), which is a type of wired communication method, or local 5G, which is a type of wireless communication method, may be used.

[0396] A factory manager can connect to a factory 884 via a cloud 883 from a home 881 or office 882 to know the operating status, etc. He can also check for incorrect or missing items, give instructions on where to put them, measure takt time, etc.

[0397] In recent years, the introduction of IoT into factories has been progressing worldwide under the name of "smart factories." In smart factory cases, there have been reported cases where endpoint microcomputers are used not only for simple inspection and auditing but also for fault detection and anomaly prediction.

[0398] In small-scale systems such as endpoint microcontrollers, the overall system power consumption during operation is often low, so the CPU tends to account for a large proportion of power consumption. For this reason, the power reduction effect of Noff-CPUs during standby operation is significant in small-scale systems such as endpoint microcontrollers. On the other hand, in the embedded field of IoT, quick response is sometimes required, and the use of Noff-CPUs makes it possible to achieve fast recovery from standby operation.

[0399] Note that this embodiment mode can be combined as appropriate with other embodiment modes and examples described in this specification. [Example]

[0400] The write operation and erase operation of the memory string according to one embodiment of the present invention were verified by device simulation.

[0401] 45 shows an equivalent circuit of a memory string MS assumed in the device simulation. The memory string MS has a configuration in which a transistor STr1, transistors MTr1 to MTr8, and a transistor STr2 are connected in series. The gate of the transistor STr1 is electrically connected to a terminal SG1, the gates of the transistors MTr1 to MTr8 are electrically connected to terminals CLG1 to CLG8, respectively, and the gate of the transistor STr2 is electrically connected to a terminal SG2. Furthermore, of the two ends of the memory string MS, a wiring BL functioning as a bit line is connected to the transistor STr2 side, and a wiring SL functioning as a source line is connected to the transistor STr1 side. Furthermore, all of the transistors constituting the memory string MS have back gates BG, which are electrically connected to the wiring SL.

[0402] The configuration of the memory string MS shown in this embodiment corresponds to the configuration of the memory string 100A shown in the above embodiment. In the memory string MS, the transistors STr1 and STr2 correspond to the transistors TrS_1 and TrS_2. Therefore, the transistors STr1 and STr2 function as selection transistors. Furthermore, the transistors MTr1 to MTr8 correspond to the transistors Tr_1 to Tr_8. Therefore, the transistors MTr1 to MTr8 function as memory cells (also called "memory transistors").

[0403] Figure 46 shows a cross-sectional view of the memory string MS assumed in the device simulation. Synopsys' TCAD Sentaurus was used for the device simulation. By using the cylindrical command in Sentaurus, the two-dimensional structure in Figure 46 was assumed to be a cylindrical structure rotated 360° around axis 991.

[0404] We assumed that the semiconductor in which the channel of the transistor constituting the memory string MS is formed is In-Ga-Zn oxide (IGZO). The donor concentration of IGZO is 1×10 17 cm-3 was assumed.

[0405] 46 also includes an enlarged view of a portion of the memory string MS. The memory string MS is made of SiO x (4 nm) and SiN acting as a charge storage layer x (5 nm) and SiO acting as a blocking layer x (10 nm).

[0406] In this example, the channel length (also referred to as "L") of the transistors MTr1 to MTr8 was assumed to be 30 nm, and the channel length L of the transistors STr1 and STr2 was assumed to be 60 nm.

[0407] The work functions of the gates SG1, SG2, CG1 to CG8 were all set to 4.6 eV, and the wiring BL and source line SL were assumed to be in ohmic contact with the IGZO. Other parameters and physical properties assumed in the device simulation are shown in Table 1.

[0408] [Table 1]

[0409] <Simulation of data write and erase operations> FIG. 47A is an equivalent circuit of the memory string MS. In FIG. 47A, the voltages in the write operation are also shown. In FIG. 47A, V PROG represents the write voltage. V PROG The time for applying the voltage was set to 0.3 milliseconds. In this example, negative charges were written into the charge storage layer of the transistor MTr4, and the change in threshold voltage (ΔVth) of the transistor MTr4 before (initial) and after (programmed) writing was calculated (FIG. 47B).

[0410] FIG. 48A is an equivalent circuit of the memory string MS. The voltages in the erase operation are also shown in FIG. 48A. In FIG. 48A, V ERASErepresents the erase voltage. V ERASE The time for applying the voltage was set to 3 milliseconds. In this example, a negative charge was assumed in advance in the charge storage layer of the transistor MTr4, and the threshold voltage change (ΔVth) of the transistor MTr4 before (programmed) and after (erased) erasure was calculated (FIG. 48B).

[0411] The results of the write operation simulation are shown in Figure 49A. The horizontal axis of Figure 49A is the V PROG 47B, and the vertical axis represents ΔVth in Fig. 47B. Fig. 49A shows the calculation results when the potential (VBL) of the wiring BL is 0V (VBL=0V) and 3V (VBL=3V). VBL=0V corresponds to writing data "1," and VBL=3V corresponds to writing data "0."

[0412] From Figure 49A, when VBL=0V, V PROG exceeds 12V, V PROG It can be seen that ΔVth changes in the positive direction depending on the value of VBL. On the other hand, when VBL=3V, V PROG It can be seen that ΔVth does not change regardless of the value of

[0413] That is, it can be seen that when VBL=0V, data "1" is written to the transistor MTr4, and when VBL=3V, data "0" is written to the transistor MTr4.

[0414] The simulation results of the erase operation are shown in FIG. 49B. The horizontal axis of FIG. 49B is the V ERASE 48B, and the vertical axis represents ΔVth in FIG. 48B.

[0415] From Figure 49B, V ERASE When V is 18V or more, ERASE It can be seen that ΔVth changes in the negative direction according to the value of . In other words, it can be seen that the charge written to the transistor MTr4 is erased.

[0416] As described above, the results of the device simulation shown in this example confirm that data can be written and erased correctly in the memory string according to one embodiment of the present invention. [Explanation of symbols]

[0417] 100: memory string, 101: conductor, 102: insulator, 103: conductor, 104: conductor, 105: insulator, 106: conductor, 107: insulator, 108: conductor, 109: wiring, 110: structure, 111: insulator, 112: semiconductor, 113: insulator, 114: functional layer, 115: insulator, 121: insulator, 122: conductor, 123: insulator, 124: conductor, 125: conductor, 126: insulator, 131: central axis, 136: insulator

Claims

1. n layers (n is an integer of 2 or more) of first conductors extending in a first direction; a structure extending in the second direction; The structure is a second conductor, an oxide semiconductor, a functional layer, a first insulator, a second insulator, and a third insulator; the first conductor has a region that functions as a memory cell control gate; the second conductor has a region that functions as a back gate; the oxide semiconductor has a region that functions as a channel formation region, the functional layer has a region that functions as a charge storage layer, the first insulator has a region that functions as a gate insulating layer; the second insulator has a region that functions as a tunnel layer; the third insulator has a region that functions as a blocking layer; the second conductor is electrically connected to the oxide semiconductor; At each intersection of the n-layer first conductor and the structure, the first insulator, the oxide semiconductor, the second insulator, the functional layer, and the third insulator are each concentrically arranged outside the second conductor; At each intersection, The semiconductor device, wherein the third insulator is thicker than the second insulator.

2. In claim 1, The semiconductor device, wherein the first direction is a direction perpendicular to the second direction.

3. In claim 1 or claim 2, The intersection functions as a memory cell.

4. A semiconductor device according to any one of claims 1 to 3; At least one of an operation switch, a battery, and a display unit; An electronic device having:

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