Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suppressing characteristic variation due to misalignment between a deep layer and a trench gate structure.SOLUTION: A semiconductor device includes: a p-type deep layer 3 in which multiple lines are spaced apart in one direction; and an n-type current dispersion layer 4 placed between multiple deep layers 3. The semiconductor device also includes: a p-type base region 5 having a p-type contact region 5a on the p-type deep layer 3; and an n+ type source region 6 is formed on a portion of the p-type base region 5 different from the p-type contact region 5a. Furthermore, a trench gate structure including a gate insulating film 8 and a gate electrode 9 is formed in the gate trench 7 reaching from the surface of the n+ type source region 6 to the p-type base region 5. The n-type current spreading layer 4 is constituted of an ion-implanted layer disposed below the trench gate structure and formed with a thickness from the bottom of the gate trench 7 to the bottom of the p-type deep layer 3 or below.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a vertical semiconductor element with a trench gate structure and a manufacturing method thereof, and is particularly suitable for application to a semiconductor device using a wide bandgap semiconductor such as silicon carbide (hereinafter referred to as SiC) and a manufacturing method thereof. [Background technology]

[0002] Conventionally, a semiconductor device provided with a vertical MOSFET having a trench gate structure has been known (see, for example, Patent Document 1). + n-type substrate - A plurality of trench gate structures are formed on the surface of the drift layer, with the longitudinal direction in one direction. A p-type base region and an n-type base region are formed between the trench gate structures. + The structure has a source region formed. + The p-type source region is formed on both sides of the trench gate structure in the width direction, and extends along the longitudinal direction of the trench gate structure. + The p-type contact region is partially formed with a high impurity concentration in a portion located between the p-type source regions.

[0003] In semiconductor devices with this structure, if an electric field concentrates at the bottom of the trench gate structure, the gate insulating film will undergo dielectric breakdown. For this reason, a p-type deep layer is placed deeper than the p-type base region at a position corresponding to the p-type contact region. By forming this p-type deep layer, the electric field at the bottom of the trench gate structure is suppressed, thereby preventing dielectric breakdown of the gate insulating film.

[0004] In the structure in which p-type deep layers are formed, adjacent p-type deep layers are arranged at a predetermined interval, n-type current spreading layers are formed between each p-type deep layer, and trench gate structures are formed at positions corresponding to the n-type current spreading layers. Specifically, after forming p-type deep layers by ion implantation or the like, p-type base regions and n-type current spreading layers are formed. + A source region is formed, and then trench etching is performed to form a gate trench. A gate insulating film and a gate electrode are then formed in the trench gate to form a trench gate structure. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-66780 Summary of the Invention [Problem to be solved by the invention]

[0006] However, misalignment between the p-type deep layer and the trench gate structure can occur, which can cause variations in the characteristics of the MOSFET, and since separate manufacturing processes are required for each, the manufacturing process becomes complicated and increases manufacturing costs.

[0007] A first object of the present disclosure is to provide a semiconductor device that can suppress variations in characteristics due to misalignment between a deep layer and a trench gate structure. A second object of the present disclosure is to simplify the manufacturing process while suppressing variations in characteristics due to misalignment between the deep layer and the trench gate structure in a manufacturing method for a semiconductor device with a trench gate structure that includes a deep layer. [Means for solving the problem]

[0008] A semiconductor device including a vertical semiconductor element (100) having a trench gate structure according to one aspect of the present disclosure includes: a first semiconductor layer (1) of a first conductivity type or a second conductivity type; a second semiconductor layer (2) of the first conductivity type formed on the first semiconductor layer; In a cell region (RC) provided with a vertical semiconductor element, a second conductivity type deep layer (3) is formed on the second semiconductor layer and arranged in one direction with a plurality of lines spaced apart from each other; In the cell region, a current spreading layer (4) of a first conductivity type is formed on the second semiconductor layer and arranged between a plurality of deep layers arranged apart from each other; a second conductivity type base region (5) formed on and in contact with the deep layer and having a contact region (5a) in which the impurity concentration is partially increased at least in the surface portion; a first conductivity type high concentration region (6) formed on a portion of the base region different from the contact region and having a first conductivity type impurity concentration higher than that of the second semiconductor layer; a trench gate structure including a gate trench (7) formed from the surface of the high concentration region and reaching the base region, a gate insulating film (8) covering the inner wall surface of the gate trench, and a gate electrode (9) disposed on the gate insulating film; an interlayer insulating film (10) that covers the gate electrode and the gate insulating film and has contact holes formed therein; a first electrode (11) electrically connected to the high concentration region and the contact region through a contact hole; a second electrode (12) formed on the first semiconductor layer on the side opposite to the second semiconductor layer, The current spreading layer is disposed below the trench gate structure and is composed of an ion-implanted layer formed to a thickness that extends from the bottom of the gate trench to the bottom of the deep layer or below the bottom.

[0009] In this way, the current spreading layer is disposed below the trench gate structure and is composed of an ion-implanted layer formed to a thickness extending from the bottom of the gate trench to the bottom of the deep layer or below the bottom. In this structure, there is no misalignment between the trench gate structure and the deep layer. Therefore, the paths of the current flowing along the current spreading layer and the side surfaces of the gate trench are the same on both sides of the trench gate structure, making it possible to suppress characteristic variations.

[0010] Furthermore, in a semiconductor device according to one aspect of the present disclosure, the bottom of the base region is located deeper than the bottom of the gate trench.

[0011] In this way, the bottom of the base region is located deeper than the bottom of the gate trench, so that a current path can be formed by inverting only the surface portion of the base region located on the side of the gate trench to form a channel.

[0012] The reference numerals in parentheses for the above-mentioned means indicate an example of the correspondence with the specific means described in the embodiments to be described later. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 2 is a top view layout diagram of the SiC semiconductor device according to the first embodiment. [Figure 2A] FIG. 2 is a cross-sectional view taken along line IIA-IIA in FIG. 1. [Figure 2B] FIG. 2 is a cross-sectional view taken along the line IIB-IIB in FIG. [Figure 2C] FIG. 2 is a cross-sectional view taken along the line IIC-IIC in FIG. [Figure 3A] 10A and 10B are partial cross-sectional views showing the structure and operation of a MOSFET in a comparative structure. [Figure 3B] 1 is a partial cross-sectional view showing the structure and operation of a MOSFET according to a first embodiment. [Figure 4A] 4 is a cross-sectional view taken along the line IV-IV in FIG. 1, illustrating a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 4B] 4B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4A. [Figure 4C] 4C is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4B. [Figure 4D] 4D is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4C. [Figure 4E] 4D and 4C are cross-sectional views showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 4D. [Figure 4F] 4F is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4E. [Figure 4G] 4F is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4F. [Figure 4H] 4G and 4G are cross-sectional views showing the manufacturing process of the SiC semiconductor device. [Figure 4I] 4H is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4H. [Figure 5A] 5A to 5C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device according to the second embodiment. [Figure 5B] 5B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 5A. [Figure 5C] 5C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5B. [Figure 5D] 5D is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5C. [Figure 5E] FIG. 5E is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5D. [Figure 6] FIG. 10 is a cross-sectional view of a vertical MOSFET provided in the SiC semiconductor device according to the third embodiment. [Figure 7A] 7A to 7C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device shown in FIG. 6 according to the third embodiment. [Figure 7B] 7B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 7A. [Figure 7C] 7C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 7B. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0015] (First embodiment) A first embodiment will be described below, taking as an example an SiC semiconductor device in which an inversion-type vertical MOSFET is formed as a vertical semiconductor element with a trench gate structure.

[0016] The SiC semiconductor device shown in Fig. 1 has a cell region RC in which a trench-gate MOSFET 100 is formed, and an outer periphery region RO surrounding the cell region RC. The outer periphery region RO has a guard ring portion RG and a connecting portion RJ disposed inside the guard ring portion RG, i.e., between the cell region RC and the guard ring portion RG. Note that Fig. 1 is not a cross-sectional view, but is partially hatched to make the drawing easier to see.

[0017] As shown in FIGS. 2A to 2C, the SiC semiconductor device is a n-type semiconductor device made of SiC. + It is formed using a mold substrate 1. + On the main surface of the mold substrate 1, a n-type silicon carbide (SiC) - A mold layer 2 is formed. + The n-type substrate 1 corresponds to the first semiconductor layer. - The mold layer 2 corresponds to the second semiconductor layer.

[0018] n + The substrate 1 has an n-type impurity concentration of, for example, 1.0×10 19 / cm 3 The surface is the (0001) Si plane, and the off-axis direction is the <11-20> direction. - Mold layer 2 is n + The impurity concentration is lower than that of the n-type substrate 1, for example, the n-type impurity concentration is 5.0×10 15 ~2.0×10 16 / cm 3It is said that...

[0019] In the cell area RC, n - A p-type deep layer 3 and an n-type current spreading layer 4 are disposed on the n-type layer 2. Furthermore, a p-type base region 5 is formed on the p-type deep layer 3, and an n-type current spreading layer 4 is disposed on the surface of the p-type base region 5, which corresponds to a high concentration region. + An n-type source region 6 is formed in the n-type current spreading layer 4. A trench gate structure is then disposed on the n-type current spreading layer 4.

[0020] The p-type deep layer 3 has a p-type impurity concentration that is the same as or higher than that of the p-type base region 5. The p-type deep layer 3 is formed from the bottom of the p-type base region 5 to a deeper n - The mold layer 2 is formed to a predetermined depth. - The p-type deep layer 3 is formed by ion-implanting p-type impurities into the type layer 2 .

[0021] In the cell region RC, the p-type deep layers 3 are arranged in a stripe pattern with multiple stripes spaced equally apart in one direction, positioned on both sides of the trench gate structure. The uppermost side of the p-type deep layers 3, i.e., the p-type base region 5 side, is located deeper than the trench gate structure and is spaced apart from the bottom of the trench gate structure. The spacing between adjacent p-type deep layers 3 is equal to the width of the trench gate structure, i.e., the horizontal dimension in FIG. 2A. The boundary between the p-type deep layers 3 and the n-type current spreading layer 4 is located at a position corresponding to both ends of the width of the bottom of the trench gate structure.

[0022] In this embodiment, the p-type deep layer 3 is formed to have the same impurity concentration and the same depth throughout the entire region. For example, the p-type impurity concentration is 1.0×10 17 ~1.0×10 19 / cm 32A ) and a thickness of about 0.3 to 2 μm. The width of the p-type deep layer 3, i.e., the dimension in the left-right direction of the paper of FIG. 2A , is constant, and the interval between adjacent p-type deep layers 3, i.e., the distance in the left-right direction of the paper of FIG. 2A , is also constant. For example, the interval between adjacent p-type deep layers 3 is 0.3 to 1.5 μm, and the remaining portion is the width of the p-type deep layer 3. The extension direction of the p-type deep layers 3 is arbitrary as long as it is the same direction as the trench gate structure, but in this embodiment it is the <11-20> direction, the same as the off direction. Note that "plural p-type deep layers 3 arranged at intervals in one direction" may be arranged in such a manner in a direction intersecting the trench gate structure as shown in Fig. 2A. For example, adjacent p-type deep layers 3 shown in Fig. 2A may be connected in a portion other than the cross section of Fig. 2A.

[0023] The n-type current spreading layer 4 is disposed below the trench gate structure and is made of an ion-implanted layer formed in a self-aligned manner with the gate trench 7 described later. The n-type current spreading layer 4 has an n-type impurity concentration of n - It may be the same as the mold layer 2, but preferably - The height is set higher than the mold layer 2, for example, 1.0 x 10 16 ~1.0×10 18 / cm 3 The n-type impurity concentration of the n-type current spreading layer 4 may be uniform in the depth direction, or may have a gradient. - The n-type impurity concentration may be low at the position on the side of the n-type layer 2, and high at a shallower position, i.e., at the position on the trench gate structure side. In this way, a design that prioritizes reducing the channel resistance can be achieved. Also, the n-type impurity concentration may be low at a shallower position of the n-type current spreading layer 4, i.e., at the position on the trench gate structure side, and high at a deeper position, i.e., - The n-type impurity concentration may be higher at the position on the side of the type layer 2. In this way, a design that emphasizes reducing the resistance on the exit side of the p-type deep layer 3, i.e., on the lower side, can be achieved.

[0024] The thickness of the n-type current spreading layer 4 is set to be, for example, 0.5 to 2.2 μm, greater than that of the p-type deep layer 3. Specifically, the n-type current spreading layer 4 has a thickness from the bottom of the trench gate structure to the bottom of the p-type deep layer 3 or below, that is, - The n-type current spreading layer 4 is formed to a depth that reaches the n-type layer 2. - The p-type deep layers 3 are connected to the n-type layer 2. The distance between the adjacent p-type deep layers 3 is the width of the n-type current spreading layer 4. The center position of the n-type current spreading layer 4 in the width direction coincides with the center position of the trench gate structure in the width direction.

[0025] In this embodiment, the n-type current spreading layer 4 and the n - The mold layer 2 constitutes a drift layer.

[0026] The p-type base region 5 is an n-type + The p-type base region 5 is a portion that constitutes a channel region connecting the n-type source region 6 and the n-type current spreading layer 4, and is disposed on both sides of the trench gate structure, in contact with the side surfaces of the trench gate structure. The p-type base region 5 has a p-type impurity concentration of, for example, 2.0×10 17 / cm 3 In this embodiment, the thickness of the p-type base region 5 is set to a thickness that allows the p-type base region 5 to cover the corner portions of the gate trench 7, which will be described later. Here, the bottom of the p-type base region 5 is set to be deeper than the bottom of the trench gate structure, and the portion that contacts the side surface of the trench gate structure is set to be 300 nm deep, for example. Therefore, the p-type base region 5 is connected to the n-type current spreading layer 4 at the portion located below the gate trench 7.

[0027] In addition, the n-type region of the surface of the p-type base region 5 + The portion different from the n-type source region 6, specifically, the n-type source region of each adjacent cell in the MOSFET 100 +The area sandwiched between the source regions 6 is a p-type contact region 5a partially containing a high concentration of p-type impurities. In this embodiment, the p-type contact region 5a is formed up to a position where it contacts the p-type deep layer 3, but only the surface layer portion of the p-type base region 5 may be the p-type contact region 5a.

[0028] n + The n-type source region 6 - The impurity concentration in the surface layer is higher than that in the n-type layer 2 and the n-type current spreading layer 4, and the n-type impurity concentration in the surface layer is, for example, 2.5×10 18 ~1.0×10 19 / cm 3 , and is about 0.5 μm thick. + The source regions 6 are arranged on both sides of the trench gate structure, in contact with the side surfaces of the trench gate structure.

[0029] The trench gate structure is configured with the left-right direction of the paper in Figure 2A as the width direction, the direction perpendicular to the paper as the depth direction, and the up-down direction of the paper as the depth direction, and is arranged in a line with the depth direction as the length direction. Figure 2A only shows the trench gate structure for one cell, but as shown in Figure 1, multiple trench gate structures are arranged in a stripe pattern by being aligned at equal intervals. Note that in Figure 1, the number of trench gate structures has been reduced to make the illustration easier to understand, but in reality, many similar structures are arranged.

[0030] The trench gate structure is + The gate trench 7 penetrates the p-type source region 6 and reaches a depth of the p-type base region 5 to a position midway in the thickness direction, and a gate insulating film 8 and a gate electrode 9 are buried in the gate trench 7 .

[0031] The gate trench 7 has a bottom surface and a side surface, and the n-type current spreading layer 4 is formed on the bottom surface, and the p-type base region 5 and the n-type current spreading layer 4 are formed on the side surface. +A type source region 6 is formed. The side surfaces of the gate trench 7 are slightly inclined with respect to the SiC surface, but may be formed perpendicularly. The bottom of the gate trench 7 is flat, and the corners at the boundaries between the side surfaces and the bottom surface of the gate trench 7 are angular, but the bottom and corners may be rounded. Rounded bottoms and corners of the gate trench 7 are preferable because this makes it easier to make the film thickness of the gate insulating film 8 more uniform.

[0032] The gate insulating film 8 is made of, for example, an oxide film, and is formed to cover at least the portion of the p-type base region 5 located on the side of the gate trench 7, i.e., the inner wall surface of the gate trench 7 including the channel region.

[0033] The gate electrode 9 is made of doped polysilicon and is formed in the gate trench 7 via a gate insulating film 8. In the present embodiment, the cell region RC has a structure in which the gate electrode 9 is disposed only in the gate trench 7, but the gate electrode 9 may be formed to extend outside the gate trench 7.

[0034] Furthermore, an interlayer insulating film 10 is formed so as to cover the gate electrode 9. + n for type substrate 1 - The opposite side of the mold layer 2, specifically n + A source electrode 11 corresponding to a first electrode is formed on the surface of the p-type source region 6 and the p-type contact region 5a. In a cross section different from that of FIG. 2A, a gate wiring layer (not shown) and the like are formed on the surface of the gate electrode 9. The source electrode 11 and the gate wiring layer are made of a plurality of metals, for example, Ni / Al. Among the plurality of metals, at least n-type SiC, specifically n +The portion in contact with n-type source region 6 is made of a metal that can make ohmic contact with n-type SiC. At least the portion of the plurality of metals that contacts p-type SiC, specifically the p-type contact region 5a and the p-type hole extraction layer 31 described below, is made of a metal that can make ohmic contact with p-type SiC.

[0035] The source electrode 11 and the gate wiring layer are electrically insulated by being separated on the interlayer insulating film 10. The source electrode 11 is connected to the n-type semiconductor layer 11 through a contact hole formed in the interlayer insulating film 10. + The gate wiring layer is in electrical contact with the gate electrode 9 .

[0036] Furthermore, n + The back side of the mold substrate 1 is + A drain electrode 12 corresponding to a second electrode is formed and electrically connected to the mold substrate 1. This structure constitutes an n-channel inversion trench gate MOSFET 100. A plurality of such MOSFETs 100 are arranged to form a cell region RC.

[0037] On the other hand, as shown in Figure 1, in the guard ring part RG, n - A plurality of p-type guard rings 21 are provided on the surface of the gate layer 2 so as to surround the cell region RC and the connecting portion RJ. In this embodiment, the p-type guard rings 21 are rectangular with rounded corners, but may be formed in other frame shapes such as a circle. As shown in FIG. 2C, the p-type guard rings 21 are - The p-type guard ring 21 is formed from the surface of the n-type layer 2 to a predetermined depth. The lower layer 21a of the p-type guard ring 21 has the same depth and p-type impurity concentration as the p-type deep layer 3, and the upper layer 21b has the same depth and p-type impurity concentration as the p-type contact region 5a. The p-type guard ring 21 is - The layer 2 is formed by ion-implanting p-type impurities into the mold layer 2 .

[0038] Although not shown, an EQR structure may be provided on the outer periphery of the p-type guard ring 21 as required, thereby forming a guard ring portion RG that has a peripheral breakdown withstand structure surrounding the cell region RC.

[0039] Furthermore, the area from the cell region RC to the guard ring portion RG is defined as a connecting portion RJ, and in the connecting portion RJ, as shown in FIGS. 1 and 2B, n - A p-type deep layer 30 and a p-type hole extraction layer 31 are formed in the surface portion of the source layer 2. The provision of the p-type deep layer 30 suppresses the rise of the electric field in the connecting portion RJ, improving the breakdown voltage. The p-type deep layer 30 is formed by ion implantation together with the p-type deep layer 3, and is configured to the same depth and with the same p-type impurity concentration as the p-type deep layer 3. The provision of the p-type hole extraction layer 31 also allows holes generated in the peripheral region to be extracted to the source electrode 11 when avalanche breakdown occurs in the cell region RC or in the guard ring portion RG or connecting portion RJ. This prevents holes from flowing into the cell region RC, thereby preventing device breakdown. The p-type hole extraction layer 31 is formed by ion implantation together with the p-type contact region 5a, and is configured to the same depth and with the same p-type impurity concentration as the p-type contact region 5a.

[0040] The p-type deep layer 30 and the p-type hole extraction layer 31 are connected to the p-type base region 5. An interlayer insulating film 10 is also formed on the surface of the p-type hole extraction layer 31, but in the cross section of FIG. 2B, this is the region where a contact hole is formed, and the p-type hole extraction layer 31 is electrically connected to the source electrode 11. Therefore, the p-type deep layer 30 and the p-type hole extraction layer 31 are fixed to the source potential. In this embodiment, as shown by the hatching in FIG. 1, a connecting portion RJ is formed to surround the cell region RC, and multiple p-type guard rings 21, each having a rectangular shape with rounded corners, are formed to surround the outside of the connecting portion RJ.

[0041] The SiC semiconductor device according to this embodiment is configured as described above. When the SiC semiconductor device configured as described above turns on the MOSFET 100, a channel region is formed in the surface portion of the p-type base region 5 located on the side surface of the gate trench 7 by controlling the gate voltage applied to the gate electrode 9. As a result, the n + the n-type source region 6, the channel region, the n-type current spreading layer 4 and the n-type - A current flows between the source electrode 11 and the drain electrode 12 using the mold layer 2 as a current path.

[0042] In the MOSFET 100 of this embodiment, the p-type base region 5 is formed to a position deeper than the trench gate structure, but below the trench gate structure, the p-type base region 5 and the n-type current spreading layer 4 are connected. Therefore, when a channel region is formed in the part of the p-type base region 5 that contacts the side surface of the trench gate structure, it connects to the n-type current spreading layer 4, and - A current can be passed between the source electrode 11 and the drain electrode 12 via the mold layer 2 .

[0043] Furthermore, when the MOSFET 100 is turned off, even if a high voltage is applied, the p-type deep layer 3 and the p-type deep layer 30, which are formed to a position deeper than the trench gate structure, prevent the electric field from penetrating into the bottom of the trench gate structure. This reduces the electric field concentration at the bottom of the trench gate structure, thereby preventing breakdown of the gate insulating film 8.

[0044] Furthermore, at the connecting portion RJ, the equipotential lines are prevented from rising upward, and are directed toward the guard ring portion RG. At the guard ring portion RG, the equipotential lines are gradually terminated toward the outer periphery by the p-type guard ring 21, and the desired breakdown voltage can be obtained at the guard ring portion RG as well.

[0045] In the conventional MOSFET shown in the comparative structure of FIG. 3A, a layout is created in which the p-type deep layers 3 are arranged in a stripe shape, and then the p-type base region 5 and the n+ In this case, a mask misalignment occurs between the p-type deep layer 3 and the trench gate structure. - The path of the current flowing from the mold layer 2 along the side surface of the gate trench 7 may differ between the left and right sides of the trench gate structure, which may cause variations in characteristics.

[0046] In contrast, in the MOSFET according to this embodiment shown in FIG. 3B, the n-type current spreading layer 4 is formed from the bottom of the gate trench 7 below the trench gate structure, and there is no misalignment between the trench gate structure and the p-type deep layer 3. As a result, the paths of the current flowing along the n-type current spreading layer 4 and the side surfaces of the gate trench 7 are the same on both sides of the trench gate structure, and there is almost no variation in characteristics. This makes it possible to suppress variation in characteristics.

[0047] Next, a method for manufacturing a SiC semiconductor device according to this embodiment will be described with reference to FIGS. 4A to 4I.

[0048] [Step shown in Figure 4A] First, as the semiconductor substrate, + A n-type substrate 1 is formed on the main surface of the n-type substrate 1. - The mold layer 2 is prepared by epitaxial growth. + On the main surface of the substrate 1, - The semiconductor substrate may be prepared by epitaxially growing the dopant layer 2, or by pre-forming an n + On the main surface of the substrate 1, - A so-called epitaxial substrate on which the mold layer 2 is epitaxially grown may be prepared as the semiconductor substrate.

[0049] [Step shown in Figure 4B] Next, n -A mask 50 is placed on the n-type layer 2, and the mask is opened in the areas where the p-type deep layer 3, the p-type deep layer 30, and the p-type guard ring 21 are to be formed. Then, p-type impurities are ion-implanted using the mask 50. At this time, the range of the ion implantation is adjusted so that the p-type impurities are n-type. - The ions are implanted to a predetermined depth, which is deeper than the surface of the p-type layer 2. As a result, a p-type layer 101 is formed, which corresponds to the first layer constituting the p-type deep layer 3, the p-type deep layer 30, and the lower layer 21a of the p-type guard ring 21.

[0050] Thereafter, the mask 50 used previously is used to implant p-type impurities again. At this time, the ion implantation range is adjusted so that the p-type impurities are implanted into n - The ions are implanted to a predetermined depth from the surface of the mold layer 2. This forms a p-type layer 102 corresponding to the second layer that constitutes the p-type base region 5, the p-type hole extraction layer 31, and the upper layer 21b of the p-type guard ring 21. Thereafter, the mask 50 is removed.

[0051] In this example, the p-type layer 101 is formed first, and then the p-type layer 102 is formed, but the order may be reversed.

[0052] [Step shown in Figure 4C] The p-type hole extraction layer 31 and the p-type guard ring 21 are formed on the p-type layer 102. - A mask 51 is placed on the mold layer 2, and the mask 51 is opened in a predetermined area. The area where the mask 51 is opened is at least n + Although it is sufficient if the mask 51 includes a region where the n-type source region 6 is to be formed, in this example, the mask 51 is opened in the cell region RC. Then, n-type impurities are ion-implanted using the mask 51. As a result, n + The n-type source region 6 corresponds to the first conductivity type layer. + The mold layer 103 is formed, and then the mask 51 is removed.

[0053] [Step shown in Figure 4D] n +n-type layer 103 and p-type layer 102 - A mask 52 is placed on the mold layer 2. Next, openings are made in the mask 52 in regions where the p-type contact region 5a, the p-type hole extracting layer 31, and the upper portion 21b of the p-type guard ring 21 are to be formed. Then, p-type impurities are ion-implanted using the mask 52 to form a p-type layer 104, which corresponds to the second conductivity type layer and has a higher impurity concentration than the p-type layer 102. This p-type layer 104 forms the p-type contact region 5a, the p-type hole extracting layer 31, and the upper portion 21b of the p-type guard ring 21. Then, the mask 52 is removed.

[0054] [Step shown in Figure 4E] n + The n-type source region 6 and the p-type hole extraction layer 31 are included. - A mask 53 is formed on the mold layer 2, and then an opening is made in the mask 53 in a region where the gate trench 7 is to be formed. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask 53 to form the gate trench 7 to a depth reaching a midpoint in the thickness direction of the p-type base region 5.

[0055] [Step shown in Figure 4F] The mask used to form the gate trench 7 is used to implant n-type impurities into the gate trench 7. As a result, an n-type current spreading layer 4 is formed at the bottom of the gate trench 7. Since the gate trench 7 is deep enough to reach the middle of the p-type base region 5 in the thickness direction, the n-type current spreading layer 4 can be connected to the portion of the p-type base region 5 that will become the channel region.

[0056] The ion implantation at this time can be performed so that the direction of ion implantation is perpendicular to the mask surface, or it can be performed obliquely with respect to the normal direction of the mask surface. In addition, ion implantation may also be performed on the side surface of the gate trench 7, but the ion-implanted portion formed on the side surface of the gate trench 7 can be removed by etching the side wall of the gate trench 7 after ion implantation or by performing sacrificial oxidation and etching.

[0057] Here, ion implantation to form the n-type current spreading layer 4 is performed after the formation of the gate trench 7, but it can also be performed before the formation of the gate trench 7. In other words, ion implantation to form the n-type current spreading layer 4 may be performed first using a mask for forming the gate trench 7, and then the gate trench 7 may be formed using that mask. In this case, however, the range of ion implantation to form the n-type current spreading layer 4 becomes large, and therefore high ion implantation energy is required.

[0058] [Step shown in Figure 4G] After removing the mask, a gate insulating film 8 is formed by depositing, for example, an oxide film. The gate insulating film 8 covers the inner wall surface of the gate trench 7 and the n-type insulating film. + The polysilicon covers the surface of the source region 6 and the like. Polysilicon doped with p-type or n-type impurities is then deposited and etched back to leave the polysilicon at least in the gate trench 7, thereby forming the gate electrode 9. This completes the trench gate structure.

[0059] [Step shown in Figure 4H] An interlayer insulating film 10 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 9 and the gate insulating film 8. Then, a mask (not shown) is formed on the surface of the interlayer insulating film 10, and then a portion of the mask located in the cell region RC, at least the p-type contact region 5a and the n-type contact region 5b, is removed. + The mask is then opened in a portion corresponding to the p-type source region 6 and in the vicinity thereof. At the same time, the mask is also opened in a portion corresponding to the p-type hole extraction layer 31. Thereafter, the mask is used to pattern the interlayer insulating film 10, thereby forming the p-type contact region 5a and the n-type + A contact hole exposing the n-type source region 6 and a contact hole exposing the p-type hole extraction layer 31 are formed. Here, in the trench gate structure, the upper surface of the interlayer insulating film 10 is + Although the interlayer insulating film 10 is made flush with the SiC surface of the mold source region 6 and the like, it may remain on the SiC surface.

[0060] [Step shown in Figure 4I] An electrode material having a laminated structure of, for example, multiple metals is formed on the surface of the interlayer insulating film 10. Then, the electrode material is patterned to form a source electrode 11 and a gate wiring (not shown).

[0061] The subsequent steps are not shown, but + By carrying out processes such as forming a drain electrode 12 on the back surface of the mold substrate 1, the SiC semiconductor device according to this embodiment is completed.

[0062] As described above, in this embodiment, the n-type current spreading layer 4 is formed by ion implanting n-type impurities using the same mask used to form the gate trench 7 for constituting the trench gate structure. This allows the n-type current spreading layer 4 to be formed in a self-aligned manner with the trench gate structure, thereby almost eliminating misalignment between the p-type deep layer 3 and the trench gate structure and suppressing characteristic variations. Furthermore, since there is no need to design a margin that takes misalignment of the n-type current spreading layer 4 into consideration, it is possible to narrow the cell pitch, i.e., the spacing between each cell, which can contribute to the miniaturization of elements.

[0063] Furthermore, since the mask used to form the gate trench 7 is used as the mask when forming the n-type current spreading layer 4, the manufacturing process can be simplified and manufacturing costs can be reduced.

[0064] Similarly, the same mask 50 is used as the mask for forming the p-type deep layer 3, the p-type deep layer 30, and the lower layer 21a of the p-type guard ring 21, and as the mask for forming the p-type base region 5. This allows for a reduction in the number of masks compared to when these masks are formed separately. This further simplifies the manufacturing process and reduces manufacturing costs.

[0065] (Second embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that the manufacturing method of the semiconductor device is changed, but the other aspects are the same as those of the first embodiment, so only the differences from the first embodiment will be described.

[0066] In this embodiment, the p-type deep layer 3, the p-type deep layer 30, the lower layer 21a of the p-type guard ring 21, the p-type base region 5, etc. are formed by a method other than ion implantation using a mask. A method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 5A to 5E.

[0067] [Step shown in Figure 5A] First, similarly to the process shown in FIG. 3A described in the first embodiment, a semiconductor substrate having n + On the main surface of the substrate 1, - The mold layer 2 is prepared by epitaxial growth. - On the n-type layer 2, a p-type layer 101 and a p-type layer 102 having different impurity concentrations are formed in this order. - In a maskless state, p-type impurities are ion-implanted into the surface of the n-type layer 2, and the range and dose of the ion implantation are changed to sequentially form p-type layers 101 and 102 with different impurity concentrations. - P-type impurities are ion-implanted without placing a mask on the mold layer 2. This eliminates the need for a mask formation step when implanting p-type impurities, thereby simplifying the process.

[0068] Also, n - It is also possible to epitaxially grow p-type layers 101 and 102, each having a different impurity concentration, in that order on the surface of type layer 2. The impurity concentration of the epitaxial film can be changed by changing the concentration of the dopant gas during epitaxial growth, and therefore the impurity concentrations of p-type layers 101 and 102 can be appropriately set by adjusting the concentration of the dopant gas.

[0069] [Step shown in Figure 5B] Next, n-type layer 102 is formed on the p-type layer 102. + n type source region 6 + Form a mold layer 103. For example, n + The p-type layer 103 can also be formed by ion-implanting n-type impurities into the surface layer of the p-type layer 102. In this case, if the ion implantation is performed in a maskless state, the mask formation process for implanting the n-type impurities can be eliminated, and the process can be simplified. + The mold layer 103 may be formed by epitaxial growth.

[0070] Of course, on the p-type layer 102, + Ion implantation is performed with a mask that opens at the planned location for forming the source region 6 placed, and n is implanted only at the desired location from the beginning. + A type source region 6 may also be formed.

[0071] [Step shown in Figure 5C] n + On top of the mold layer 103 + After placing a mask 60 covering the planned location for forming the source region 6, p-type impurities are ion-implanted to counter the n-type portion, forming a p-type layer 104. The p-type layer 104 is a portion that constitutes the p-type contact region 5a, etc., and has a higher impurity concentration than the p-type layer 102, and is connected to the p-type layer 102. The p-type layer 104 is made of n-type impurities. + The mask 60 is then removed. Here, the p-type layer 104 is formed by ion implantation using the mask 60, and the n-type layer 104 is formed by ion implantation using the mask 60. + Although the case where the p-type layer 103 is formed by ion implantation in a maskless state has been described, the reverse may also be true. That is, the p-type layer 104 is formed by ion implantation in a maskless state, and the n-type layer 105 is formed by ion implantation in a maskless state. + The mold layer 103 may be formed by ion implantation using a mask.

[0072] [Step shown in Figure 5D] n +A mask 61 is formed on the source region 6 and the p-type layer 104, and then openings are made in the mask 61 in areas where gate trenches 7 are to be formed and in areas between the portions that will become the p-type guard rings 21. That is, multiple frame-shaped openings are formed concentrically in the mask 61. Then, anisotropic etching such as RIE is performed using the mask 61 to form gate trenches 7 that reach a depth that reaches a position midway in the thickness direction of the p-type layer 102 that constitutes the p-type base region 5. Isolation trenches 105 are also formed between the p-type guard rings 21.

[0073] [Step shown in Figure 5E] The mask used to form the gate trench 7 and the isolation trench 105 is used to implant n-type impurities into the gate trench 7. As a result, an n-type current spreading layer 4 is formed at the bottom of the gate trench 7. Since the gate trench 7 is deep enough to reach the middle of the p-type base region 5 in the thickness direction, the n-type current spreading layer 4 can be connected to the portion of the p-type base region 5 that will become the channel region.

[0074] At the same time, an isolation n-type layer 106 is formed at the bottom of isolation trench 105. As a result, in peripheral region RO, the upper positions of p-type layer 104 and p-type layer 102 are isolated by isolation trench 105, and the lower positions of p-type layer 102 and p-type layer 101 are isolated by isolation n-type layer 106, which corresponds to the isolation layer, thereby forming p-type guard ring 21.

[0075] That is, the p-type deep layer 3, the p-type deep layer 30, and the lower layer 21a of the p-type guard ring 21 are formed by the p-type layer 101, and the p-type layer 102 forms the p-type base region 5. The p-type layer 102 and the p-type layer 104 form the upper layer 21b of the p-type guard ring 21, and the p-type layer 104 forms the p-type contact region 5a and the p-type hole extraction layer 31.

[0076] Thereafter, similarly to the first embodiment, a trench gate structure is formed by performing the steps of forming a gate insulating film 8 and a gate electrode 9. Furthermore, the steps of forming an interlayer insulating film 10, a source electrode 11, a drain electrode 12, etc. are performed, whereby the SiC semiconductor device of this embodiment can be manufactured.

[0077] As described above, in the manufacturing method of this embodiment, the p-type deep layer 3, the p-type deep layer 30, the lower layer 21a of the p-type guard ring 21, the p-type base region 5, and the like are formed by a method other than ion implantation using a mask. Specifically, they are formed by maskless ion implantation or epitaxial growth. In this way, the masks used to form the p-type layer 101 and the p-type layer 102 in the first embodiment are no longer necessary. This makes it possible to simplify the manufacturing process.

[0078] Also, n + n type source region 6 + Ion implantation is performed in a maskless state when forming the mold layer 103. This eliminates the need for a mask formation process when implanting n-type impurities, thereby simplifying the process.

[0079] Furthermore, since the isolation trench 105 is formed when the gate trench 7 is formed, and the isolation n-type layer 106 is also formed when the n-type current spreading layer 4 is formed, the p-type guard ring 21 can be formed without any additional process.

[0080] (Third embodiment) The third embodiment will be described. This embodiment is different from the first and second embodiments in that the structure of the n-type current spreading layer 4 is changed, but the rest is the same as the first and second embodiments, so only the parts that are different from the first and second embodiments will be described.

[0081] 6, in this embodiment, the n-type current spreading layer 4 is formed so as to cover not only the bottom but also the corners of the trench gate structure. Specifically, the n-type current spreading layer 4 has a structure including a lower bottom portion 4a located at the bottom of the gate trench 7 and a wide portion 4b that is wider than the lower bottom portion 4a. The lower bottom portion 4a has approximately the same width as the bottom of the gate trench 7, and the wide portion 4b is wider than the bottom of the gate trench 7.

[0082] The wide portion 4b is formed to cover the corners of the gate trench 7, and its thickness is arbitrary. That is, the wide portion 4b may have any thickness as long as its upper surface is shallower than the bottom of the gate trench 7 and its lower surface is deeper than the bottom of the gate trench 7. The n-type impurity concentration of the wide portion 4b is also arbitrary. As described below, the wide portion 4b and the lower bottom portion 4a are formed by ion implantation. When forming the wide portion 4b, ions are also implanted into the upper layer of the lower bottom portion 4a. Therefore, the n-type impurity concentration of the upper layer of the lower bottom portion 4a is higher than the n-type impurity concentrations of the wide portion 4b and the lower layer of the lower bottom portion 4a. Furthermore, it is preferable to make the n-type impurity concentration of the wide portion 4b higher than that of the portion of the n-type current spreading layer 4 located below the wide portion 4b, since this further reduces on-resistance.

[0083] The n-type current spreading layer 4 is formed using the mask used to form the gate trench 7, but if the n-type current spreading layer 4 is formed only at the bottom of the gate trench 7, it becomes difficult to form a channel at the corners of the gate trench 7. For this reason, if wide portions 4b are formed so that the corners of the gate trench 7 are covered with the n-type current spreading layer 4, these portions can be used as a current path, and if a channel can be formed only on the side surfaces of the gate trench 7, current can flow satisfactorily. This structure makes it possible to further reduce the on-resistance.

[0084] The method for manufacturing the SiC semiconductor device having the structure of this embodiment is generally similar to that of the first and second embodiments, but an ion implantation step for forming the wide portion 4b is added.

[0085] For example, as shown in FIG. 7A , a mask 53 for forming the gate trench 7 is used to ion-implant n-type impurities before forming the gate trench 7, thereby forming the wide portion 4b. In this way, the wide portion 4b can be formed without being affected by the shape of the gate trench 7. A longer ion implantation range requires higher energy, but since only the wide portion 4b is formed rather than forming the entire n-type current spreading layer 4 before forming the gate trench 7, the increase in ion implantation energy can be limited. In this case, to further increase the width of the wide portion 4b, oblique ion implantation can be performed, in which the direction of ion implantation is tilted with respect to the normal direction to the mask surface.

[0086] 7B and 7C, steps similar to those shown in FIGS. 4E and 4F are performed to form gate trench 7 and the bottom lower portion 4a of n-type current spreading layer 4. This completes the manufacture of the SiC semiconductor device of this embodiment.

[0087] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment and encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0088] For example, in the above embodiment, the bottom of the gate trench 7 is located midway in the thickness direction of the p-type base region 5. + Since it is sufficient that a channel is formed to connect the p-type source region 6 and the n-type current spreading layer 4 , the bottom of the gate trench 7 may be located deeper than the p-type base region 5 .

[0089] In each of the above embodiments, the intervals between the p-type guard rings 21 may be constant, or the width of each p-type guard ring 21 may be structured to increase toward the periphery. - A lower layer portion 21a formed at a predetermined depth from the surface of the mold layer 2, and - It is sufficient that the p-type guard ring 21 is formed of at least one of the lower layer 21a and the upper layer 21b formed in contact with the surface of the mold layer 2. If the p-type guard ring 21 is formed of only the lower layer 21a, the conductivity type on the surface side of the outer circumferential region RO will be n-type, but the purpose of ensuring the breakdown voltage can be achieved.

[0090] In each of the above embodiments, the n + On the substrate 1, a second semiconductor layer corresponding to n - Although the structure in which the mold layer 2 is formed has been given as an example, the second semiconductor layer may be configured as a semiconductor substrate, and the first semiconductor layer may be formed by ion-implanting impurities into the back surface side of the second semiconductor layer.

[0091] Furthermore, in each of the above embodiments, n - A p-type deep layer 3 is formed on the surface of the n-type layer 2. - The n-type current spreading layer 4 is formed so as to reach the n-type layer 2. However, this is merely an example, and other configurations may be included. For example, - A saturation current suppression layer may be provided on the type layer 2 by alternately arranging multiple n-type layers and p-type layers in a stripe pattern, and a p-type deep layer 3 and an n-type current spreading layer 4 may be provided on the saturation current suppression layer.

[0092] Furthermore, in the above-described embodiments, structural examples of the connecting portion RJ and the peripheral region RO in addition to the cell region RC are given, but the structural examples of the connecting portion RJ and the peripheral region RO are merely given as examples. In other words, as long as an n-type current spreading layer is formed at the bottom of the trench gate structure relative to the structure of the cell region RC, the structures of the connecting portion RJ and the peripheral region RO are arbitrary. For example, in the above-described first embodiment, the peripheral region RO can be recessed to form a mesa structure in which the cell region RC and the connecting portion RJ protrude beyond the peripheral region RO.

[0093] In the above embodiment, an n-channel type MOSFET 100 in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example of a semiconductor element provided in the cell region RC of the SiC semiconductor device. However, this is merely an example, and a p-channel type MOSFET 100 in which the conductivity types of each component are reversed may also be used. Also, instead of the MOSFET 100, an IGBT with a trench gate structure may also be used. Note that the IGBT may be an n-channel type MOSFET in the above embodiments. + The only difference is that the conductivity type of the substrate 1 is changed from n-type to p-type, and the other structures and manufacturing methods are the same as those of the above-described embodiments.

[0094] Furthermore, in each of the above embodiments, the case where SiC is used as the semiconductor material has been described, but the present disclosure can also be applied to semiconductor devices that use other semiconductor materials such as Si.

[0095] When indicating the crystal orientation, a bar (-) should normally be placed above the desired number. However, due to limitations on expression based on electronic filing, in this specification, a bar will be placed before the desired number. [Explanation of symbols]

[0096] 1n + Mold board 2n - mold layer 3 p-type deep layer 4 n-type current distribution layer 5 p-type base region 6n + Type Source Area 7 Gate Trench 9 Gate electrode 11 Source electrode 12 Drain electrode

Claims

1. A semiconductor device comprising a vertical semiconductor element (100) having a trench gate structure, A first semiconductor layer (1) of a first conductivity type or a second conductivity type; a second semiconductor layer (2) of the first conductivity type formed on the first semiconductor layer; In the cell region (RC) provided with the vertical semiconductor element, a second conductivity type deep layer (3) is formed on the second semiconductor layer and arranged in one direction with a plurality of lines spaced apart from each other; In the cell region, a current spreading layer (4) of a first conductivity type is formed on the second semiconductor layer and arranged between the plurality of deep layers arranged apart from each other; a second conductivity type base region (5) formed on and in contact with the deep layer and having a contact region (5a) in which the impurity concentration is partially increased at least in the surface portion; a first conductivity type high concentration region (6) formed on a portion of the base region different from the contact region and having a first conductivity type impurity concentration higher than that of the second semiconductor layer; a trench gate structure including a gate trench (7) formed from the surface of the high concentration region and reaching the base region, a gate insulating film (8) covering the inner wall surface of the gate trench, and a gate electrode (9) arranged on the gate insulating film; an interlayer insulating film (10) that covers the gate electrode and the gate insulating film and has a contact hole formed therein; a first electrode (11) electrically connected to the high concentration region and the contact region through the contact hole; a second electrode (12) formed on the first semiconductor layer on the side opposite to the second semiconductor layer, the current spreading layer is disposed below the trench gate structure and is composed of an ion-implanted layer formed to a thickness extending from a bottom of the gate trench to a bottom of a deep layer or below the bottom, The semiconductor device, wherein the bottom of the base region is located deeper than the bottom of the gate trench.

2. 2. The semiconductor device according to claim 1, wherein the current spreading layer has a wide portion (4b) at the bottom of the gate trench that is wider than the bottom, the wide portion covering a corner portion that is a boundary between the bottom and a lower portion of the gate trench, and only the base region is arranged on the opposite side of the gate trench across the wide portion.

3. 3. The semiconductor device according to claim 1, wherein the wide portion has a higher first conductivity type impurity concentration than a portion of the current spreading layer located below the wide portion.

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