Semiconductor element and method for manufacturing the same

Abstract

To provide a method for manufacturing a semiconductor device that can reduce the probability of cracking at positions displaced from a groove.SOLUTION: A method for manufacturing a semiconductor element comprises: a process for preparing a laminate comprising a substrate having a crystal structure and a plurality of semiconductor layers laminated on the substrate; and a process for forming a groove with a branched tip shape in the laminate and dividing it starting from the groove.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Patent Document 1 describes a method for obtaining individual elements by forming division guide grooves in a wafer including a group III nitride semiconductor substrate and dividing the wafer along the division guide grooves. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-81428 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a method for manufacturing a semiconductor device that can reduce the probability of cracking at positions outside the grooves, and also provides a semiconductor device with a reduced incidence of appearance defects. [Means for solving the problem]

[0005] One aspect of a method for manufacturing a semiconductor element according to the present disclosure includes the steps of preparing a stack including a substrate having a crystalline structure and a plurality of semiconductor layers stacked on the substrate, and forming a groove having a branched tip in the stack and dividing the stack using the groove as a starting point.

[0006] One aspect of a semiconductor element according to the present disclosure comprises a laminate having a longitudinal side, a lateral side, a first main surface, and a second main surface, wherein the longitudinal side has a first region including a rough surface and a second region including a plurality of streak-like steps extending from the first region toward the second main surface, and a plurality of recesses are provided at the boundary between the first region and the second region. [Effects of the Invention]

[0007] According to the above-described method for manufacturing a semiconductor element, it is possible to reduce the probability of cracking at positions outside the grooves, and to obtain a semiconductor element with a reduced incidence of appearance defects. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 2] 1A to 1C are schematic plan views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] 1A to 1C are schematic plan views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are schematic plan views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5. [Figure 7] FIG. 4 is a partially enlarged view showing an example of the shape of a groove. [Figure 8] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor element according to an embodiment. [Figure 9] FIG. 1 is a schematic plan view showing a semiconductor element according to an embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. [Figure 11] 1 is a schematic perspective view showing a semiconductor element according to an embodiment; [Figure 12] FIG. 2 is a schematic diagram showing a side surface of a semiconductor element according to an embodiment. [Figure 13] 10 is an optical microscope photograph of a groove in the semiconductor element manufacturing method of Example 2. [Figure 14] 1 is a scanning electron microscope (SEM) photograph of a side surface of a semiconductor element of Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment of the present invention will now be described with reference to the drawings, in which like elements are designated by like reference numerals.

[0010] Fig. 1 is a flowchart showing a method for manufacturing a semiconductor device according to this embodiment. Fig. 2 to Fig. 8 are schematic views for explaining the method for manufacturing a semiconductor device according to this embodiment. Fig. 9 to Fig. 12 are schematic views for explaining the semiconductor device according to this embodiment.

[0011] 1, the method for manufacturing a semiconductor device according to this embodiment includes a laminate preparation step S101 and a dividing step S103. In the laminate preparation step S101, a laminate 10 is prepared, which includes a substrate 11 having a crystalline structure and a plurality of semiconductor layers 12 stacked on the substrate 11. In the dividing step S103, grooves 20 with branched ends are formed in the laminate 10, and the laminate is divided using the grooves 20 as starting points. According to the method for manufacturing a semiconductor device according to this embodiment, it is possible to reduce the probability of cracking at positions other than the grooves 20. The method for manufacturing a semiconductor device according to this embodiment may further include a cleaving step S102.

[0012] In a dividing method in which an object is divided starting from a groove, the deeper the groove, the easier it is to divide the object. However, the easier it is to divide, the greater the possibility of the object cracking at an unintended time, such as when being transported. On the other hand, if the groove depth is too small, the object may crack at a position outside the groove. In a case where a substrate 11 having a crystalline structure, such as the laminate 10 of this embodiment, is included, if the groove depth is too shallow, the crystalline structure of the substrate 11 may cause the object to crack in an unintended direction.

[0013] As a result of an investigation focusing on the shape of the grooves 20, it was found that, when dividing a laminate 10 including a substrate 11 having a crystalline structure, the probability of cracking at a position away from the grooves 20 can be reduced by forming the grooves 20 in a shape with branched ends. This is thought to be because the branched ends of the grooves 20 allow a crack to propagate from any position, thereby reducing the possibility of cracking at a position away from the grooves 20. In other words, it is thought that the branched ends of the grooves 20 increase the effective width over which the grooves 20 can act as a division guide.

[0014] (Laminate preparation step S101) First, a laminate preparation step S101 is performed. In the laminate preparation step S101, a laminate 10 is prepared as shown in FIGS. 2 and 3. FIG. 2 is a schematic plan view showing a method for manufacturing a semiconductor device. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. In each drawing, the X direction, Y direction, and Z direction are shown. The plan view is a view seen from the Z direction. The X direction is the cleavage direction in the cleavage step S102 described later. The Y direction is the division direction in the division step S103 described later. The X direction, Y direction, and Z direction are all perpendicular to each other.

[0015] The laminate 10 includes a substrate 11 having a crystalline structure and a plurality of semiconductor layers 12 laminated on the substrate 11. Ridges 12a may be formed on the plurality of semiconductor layers 12. The laminate 10 has a first main surface 10a and a second main surface 10b. The direction from the second main surface 10b toward the first main surface 10a is the Z direction. The ridges 12a may be formed on the second main surface 10b. The laminate 10 may be a wafer, or may be pieces obtained by dividing a wafer into a plurality of parts.

[0016] The thickness of the laminate 10 can be, for example, 150 μm or less. The thickness of the laminate 10 is preferably 70 μm or less. This allows for a reduced drive voltage of the resulting semiconductor device 100. For example, when a first electrode 31 and a second electrode 32 are provided sandwiching the laminate 10 in the thickness direction as shown in FIG. 3, reducing the thickness of the laminate 10 can reduce the resistance of the current path and the drive voltage of the resulting semiconductor device 100. The thickness of the laminate 10 can be 30 μm or more. The thickness of the laminate 10 can be 30 μm or more and 100 μm or less, or may be 30 μm or more and 70 μm or less. The thickness of the laminate 10 is the distance from the second main surface 10b to the first main surface 10a in the Z direction. If the first main surface 10a and / or the second main surface 10b is not flat, the thickness of the laminate 10 is defined as the position where the thickness is greatest.

[0017] The substrate 11 preferably has an easy cleavage direction. This allows at least one of the side surfaces of the semiconductor device 100 to be obtained by cleavage. The easy cleavage direction of the substrate 11 preferably coincides with part of the direction forming the side surfaces of the semiconductor device 100 but does not coincide with other parts. By forming the grooves 20 in the direction that does not coincide and dividing the substrate 11, the grooves 20 have substantially enlarged effective widths that function as dividing guides, reducing the possibility of the substrate 11 being pulled in the easy cleavage direction and breaking at a position outside the grooves 20. When the resulting semiconductor device 100 has a rectangular shape in a planar view, the substrate 11 preferably has a hexagonal crystal structure. Examples of such substrates 11 include nitride semiconductor substrates with a wurtzite structure. Examples of nitride semiconductor substrates include Group III nitride semiconductor substrates. Examples of Group III nitride semiconductors include GaN, InGaN, AlGaN, and AlN. For example, a GaN substrate can be used as the substrate 11. The easy cleavage plane of a nitride semiconductor having a wurtzite structure is the m-plane (i.e., the {10-10} plane). In this case, it is preferable that one of the main surfaces of the substrate 11 is the c-plane (i.e., the (0001) plane or the (000-1) plane). In the present disclosure, the c-plane is not limited to a plane that strictly coincides with the (0001) plane or the (000-1) plane, but also includes a plane having an off-angle within the range of ±0.03 to 1 degree.

[0018] The semiconductor layers 12 are made of semiconductors that can be formed on the substrate 11. The easy cleavage direction of the semiconductors constituting the semiconductor layers 12 preferably coincides with the easy cleavage direction of the substrate 11. This ensures that the easy cleavage directions coincide throughout the entire stack 10, enabling favorable cleavage. The semiconductors constituting the semiconductor layers 12 may be nitride semiconductors, and may be Group III nitride semiconductors. Examples of Group III nitride semiconductors include GaN, InGaN, AlGaN, and AlN. By epitaxially growing the semiconductor layers 12 on the surface of the substrate 11 made of a Group III nitride semiconductor, the crystal orientations of the semiconductor layers 12 can be substantially aligned. The semiconductor layers 12 can be formed by, for example, metalorganic chemical vapor deposition (MOCVD). The ridge 12a can be formed in the semiconductor layers 12 by, for example, removing portions of the semiconductor layers 12 using photolithography and etching after the semiconductor layers 12 are grown. The thickness of the semiconductor layers 12 may be smaller than the thickness of the substrate 11. The thickness of the semiconductor layers 12 may be 10 μm or less. The thickness of the semiconductor layers 12 may be 1 μm or more. The thickness of the semiconductor layers 12 is the distance from one main surface of the semiconductor layers 12 to the other main surface in the Z direction. If the main surfaces are not flat, the thickness of the semiconductor layers 12 is determined as the position where the thickness is greatest.

[0019] As shown in FIG. 10 (described later), the multiple semiconductor layers 12 may include a first-conductivity-type semiconductor layer 121, a second-conductivity-type semiconductor layer 122, and an active layer 123 sandwiched between the first-conductivity-type semiconductor layer 121 and the second-conductivity-type semiconductor layer 122. The semiconductor device 100 may be a semiconductor laser device. When the semiconductor device 100 is a semiconductor laser device, an optical waveguide may be defined by a ridge 12a. The ridge 12a may have, for example, a stripe shape. Side surfaces formed across the ridge 12a become the light-emitting end face and the light-reflecting end face of the semiconductor device 100. The resulting semiconductor device 100 may have a shape having a short side and a long side in a planar view. The resulting semiconductor device 100 may have one or more short side faces and one or more long side faces. When the semiconductor device 100 has a rectangular shape in a planar view, it has two short side faces and two long side faces. For example, one of the side surfaces in the short side direction is set as the end face on the light emitting side, and in this case, another of the side surfaces in the short side direction is set as the end face on the light reflecting side.

[0020] The laminate 10 may be provided with a first electrode 31 and a second electrode 32. The first electrode 31 and the second electrode 32 are preferably arranged in a plan view so as not to overlap the cleavage position in the cleaving step S102 described below and the division position in the dividing step S103. This reduces the possibility of the first electrode 31 and the second electrode 32 adhering to the cleaved or divided surfaces. One of the first electrode 31 and the second electrode 32 may be an n-electrode, and the other may be a p-electrode. In FIG. 3, the second electrode 32 has a contact electrode 32a provided on the ridge 12a and a pad electrode 32b in contact therewith.

[0021] The first electrode 31 and the second electrode 32 can each be formed by laminating one or more layers of a metal or alloy such as Ni, Rh, Cr, Au, W, Pt, Ti, Al, or Pd. The first electrode 31 and the second electrode 32 may contain a conductive oxide. The contact electrode 32a may be a single-layer or multi-layer film of a metal or alloy such as Ni, Rh, Cr, Au, W, Pt, Ti, or Al, or a conductive oxide containing at least one selected from Zn, In, and Sn. An example of the conductive oxide is ITO (indium tin oxide).

[0022] The laminate 10 may be provided with an insulating film 33. The insulating film 33 may be formed of a single layer or a multilayer film of an oxide or nitride of, for example, Si, Al, Zr, Ti, Nb, Ta, or the like.

[0023] (Cleavage process S102) Next, a cleaving step S102 can be performed. In the cleaving step S102, the laminate 10 is divided by cleavage. In this embodiment, cleavage is performed in the X direction in the figure. This allows for the cleaved laminate 10 to be obtained, as shown in FIG. 4. FIG. 4 is a schematic plan view showing a method for manufacturing the semiconductor element 100. When the semiconductor element 100 is a semiconductor laser element, it is preferable to form the light-emitting side end face and the light-reflecting side end face by cleavage, thereby allowing for the obtaining of good end faces.

[0024] The surfaces obtained by the cleaving step S102 may be surfaces that become the short-side surfaces of the semiconductor element 100. When the short-side surfaces of the semiconductor element 100 are formed by the cleaving step S102, the laminate 10 is divided at a first interval in the cleaving step S102, and then the laminate 10 is divided at a second interval that is smaller than the first interval in the dividing step S103 described below.

[0025] Cleavage can be performed, for example, by first forming a groove in a portion of the desired cleavage position, and then pressing the laminate 10 with a blade. The groove can be formed, for example, using a laser scribing device. The groove may be formed only outside the region that will become the semiconductor element 100. For example, a groove can be formed in one end of the laminate 10, which is a wafer or a divided piece obtained by dividing a wafer, and the laminate 10 can be cleaved along the groove by applying an external force.

[0026] When the substrate 11 has a wurtzite structure, it is preferable that the cleavage direction coincides with the m-plane in plan view. This allows for accurate cleavage. In the present disclosure, "coinciding with the m-plane" does not necessarily mean strictly coinciding with the m-plane, but also includes cases where the angle with respect to the m-plane is 0.1 degrees or less. In the present embodiment, the cleavage direction coincides with the X-direction, but the cleavage direction does not have to coincide with the X-direction.

[0027] If the semiconductor element 100 is a semiconductor laser element, a light-reflecting film or a protective film may be formed on the surface obtained by cleavage after the cleaving step S102. When forming a film such as a light-reflecting film or a protective film on some of the side surfaces of the semiconductor element 100, it is preferable to first perform division to form the side surface on which the film will be provided, and then perform division in a different direction after the film is provided. This makes it easier to form the film on the side surface of the semiconductor element 100.

[0028] (Dividing process S103) In the dividing step S103, as shown in FIGS. 5 to 8, grooves 20 having branched ends are formed in the laminate 10, and the laminate 10 is divided using the grooves 20 as starting points. FIG. 5 is a schematic plan view showing a method for manufacturing the semiconductor element 100. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5. FIG. 7 is a partially enlarged view showing an example of the shape of the grooves 20. FIG. 8 is a schematic cross-sectional view showing a method for manufacturing the semiconductor element 100. In this embodiment, the division is performed in the Y direction in the drawing. Note that, although the dividing direction coincides with the Y direction in this embodiment, the dividing direction does not have to coincide with the Y direction. When the dividing step S103 is performed after the cleaving step S102, the laminate 10 in which the grooves 20 are formed is the laminate 10 after being cleaved in the cleaving step S102.

[0029] As shown in FIG. 7 , the grooves 20 have a branched shape at the tip. The grooves 20 have a shape with multiple tips. Such a groove shape can be observed from the direction along the extension direction of the grooves 20 (from the Y direction in the figure). If the laminate 10 is translucent, the groove shape can be observed from the side of the laminate 10 using an optical microscope. The groove shape may also be observed in a cross section in a direction intersecting the extension direction of the grooves. The number of branches at the tip of the grooves 20 is two or more. The number of branches at the tip of the grooves 20 may be ten or less, or may be five or less. The grooves 20 may have branched tip portions 20a and connecting portions 20b connecting the tip portions 20a to the surface of the laminate 10. It is preferable that the depth of the connecting portions 20b account for more than half of the total depth of the grooves 20. This allows the laminate 10 to be divided more stably. The depth of the groove 20 refers to the length in the direction from the second main surface 10b of the laminate 10 toward the first main surface 10a.

[0030] The depth of the groove 20 can be 10 μm or more. The depth of the groove 20 is preferably 15 μm or more. This allows for better division. The depth of the groove 20 can be 50 μm or less, preferably 40 μm or less, and more preferably 20 μm or less. This further reduces the possibility of unintended cracking. The depth of the groove 20 can be 10 μm or more and 50 μm or less, preferably 10 μm or more and 40 μm or less, and more preferably 10 μm or more and 20 μm or less. The depth of the groove 20 can be 10 μm or more and 15 μm or less.

[0031] The ratio of the depth of the grooves 20 to the thickness of the laminate 10 in the thickness direction of the laminate 10 can be 10% or more, and preferably 20% or more. This allows for better division. The ratio of the depth of the grooves 20 to the thickness of the laminate 10 can be less than 50%, and preferably 40% or less. This further reduces the possibility of unintended cracking. The ratio of the depth of the grooves 20 to the thickness of the laminate 10 can be 10% or more and less than 50%, and preferably 10% or more and 40% or less. The ratio of the depth of the grooves 20 to the thickness of the laminate 10 can be 20% or more and 40% or less.

[0032] The grooves 20 preferably have a depth that reaches the first main surface 10a but does not reach the second main surface 10b. In the dividing step S103, the grooves 20 are formed so that they reach the first main surface 10a but not the second main surface 10b. By pressing the laminate 10 with the grooves 20 from the second main surface 10b side, cracks are generated starting from the grooves 20, and the laminate 10 can be divided. When dividing by pressing in this manner, cracks tend to occur outside the grooves 20. However, providing the grooves 20 can reduce the likelihood of this phenomenon. Pressing is performed, for example, by pressing a pressing member 40 against the second main surface 10b directly or via a protective sheet, as shown in FIG. 8 . The pressing member 40 is, for example, a cutter or a blade. The pressing member 40 can be pressed directly above the grooves 20.

[0033] The first main surface 10a of the laminate 10 can be the surface of the substrate 11. The second main surface 10b of the laminate 10 can be the surfaces of the plurality of semiconductor layers 12. In this case, it is preferable that the grooves 20 are provided only in the substrate 11, and not in the plurality of semiconductor layers 12. This can further reduce the possibility of unintended cracking. The first main surface 10a can be the surface of the plurality of semiconductor layers 12, and the second main surface 10b can be the surface of the substrate 11. In this case, it is preferable that the grooves 20 are formed from the plurality of semiconductor layers 12 to a portion of the substrate 11. This can form grooves 20 of sufficient depth, allowing for better division.

[0034] The width of the groove 20 can be 50% or less of the depth of the groove 20, and may be 30% or less. The width of the grooves 20 refers to the maximum length in a direction perpendicular to the extension direction of the grooves 20. The width of the grooves 20 can be, for example, 20 μm or less. The width of the grooves 20 can be 1 μm or more, and may be 3 μm or more. The width of the grooves 20 may be determined by observing the grooves from the side of the laminate 10 using an optical microscope, or by observing a cross section of the grooves 20 in a direction intersecting the extension direction. The grooves 20 can also be observed from the side of the first main surface 10a using an optical microscope. The maximum width of the grooves 20 in such a planar view may be 50 μm or less, or may be 30 μm or less.

[0035] The grooves 20 do not have to be formed over the entire length of the division in the division step S103. In Fig. 5, the grooves 20 are formed over a portion of the length of the division in the division step S103. By arranging the grooves 20 so that they do not reach the cleaved surfaces, it is possible to reduce the possibility that debris will adhere to the cleaved surfaces when the grooves 20 are formed.

[0036] The direction in which the laminate 10 is divided is preferably a direction different from the easy cleavage direction of the substrate 11. When dividing in a direction different from the easy cleavage direction, the laminate is likely to break away from the grooves 20, but providing the grooves 20 can reduce the possibility of this phenomenon occurring.

[0037] The dividing step S103 may be a step of forming the side surfaces of the semiconductor element 100 in the longitudinal direction. The length of the side surfaces of the semiconductor element 100 formed by the dividing step S103 is preferably 1 mm or more. The length of the side surfaces of the semiconductor element 100 refers to the length along the dividing direction. The longer the dividing distance, the more likely the element is to break away from the grooves 20, but providing the grooves 20 can reduce the possibility of the element breaking away from the grooves 20. The length of the side surfaces of the semiconductor element 100 formed by the dividing step S103 can be 10 mm or less, and may be 5 mm or less.

[0038] The groove 20 can be formed by laser processing. The groove 20 can be formed by laser processing using a pulsed laser beam. The groove 20 can be formed using a laser scribing device. The groove 20 with a branched tip can be formed by changing the laser processing conditions from those for forming a V-shaped groove to those for increasing the repetition rate and decreasing the peak output. The laser processing conditions for forming a V-shaped groove are those for ablation processing. From these conditions, by adjusting the repetition rate to increase and the peak output to decrease, it is believed that although the processing is primarily ablation, the influence of thermal processing at the tip becomes greater, and therefore it is believed that the groove 20 with a branched tip can be formed.

[0039] The laser processing conditions for forming the grooves 20 are selected so that the grooves can be formed in the laminate 10 mainly by ablation. When a GaN substrate is used as the substrate 11, for example, a nanosecond laser of UV light can be used. The laser processing conditions can be adjusted, for example, within the ranges of a pulse width of nanoseconds or picoseconds, a repetition frequency of 40 kHz to 200 kHz, an average power of 0.5 W to 10 W, and a focused beam diameter at the focused position of 2 μm to 20 μm. Since the depth of the grooves 20 formed can change depending on the repetition frequency, the depth of the grooves 20 can be adjusted by adjusting the scanning speed. The scanning speed can be adjusted, for example, within the range of 5 mm / s to 500 mm / s. The laser processing conditions for forming the grooves 20 can be the same as the laser processing conditions for forming V-shaped grooves, but with a higher repetition frequency and a lower peak output.

[0040] By going through the above steps, the semiconductor device 100 can be obtained.

[0041] (Semiconductor element 100) 9 to 12 show a semiconductor element 100 of this embodiment. FIG. 9 is a schematic plan view showing the semiconductor element 100. FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. FIG. 11 is a schematic perspective view showing the semiconductor element 100. FIG. 12 is a schematic view showing a side surface of the semiconductor element 100.

[0042] The semiconductor device 100 includes a laminate 10 having a longitudinal side surface 10c, a lateral side surface 10d, a first main surface 10a, and a second main surface 10b. The longitudinal side surface 10c has a first region 51 including a rough surface and a second region 52 including a plurality of streak-like steps extending from the first region 51 toward the second main surface 10b. A plurality of recesses 53 are provided at the boundary between the first region 51 and the second region 52.

[0043] The first region 51 and the multiple recesses 53 are thought to be portions that were once grooves 20. The recesses 53 are thought to be the branched portions at the ends of the grooves 20 that remain. In this way, the shape of the ends of the grooves 20 may remain as traces. The recesses 53 are recesses that are recessed toward the inside of the laminate 10. The second region 52 is thought to be a portion that was broken by a crack extending from the groove 20. In the second region 52, multiple streak-like marks extending from the first region 51 toward the second main surface 10b are observed as crack marks. The multiple streak-like steps (multiple streak-like marks) are mostly linear. The first region 51 has a randomly roughened surface compared to the second region 52. The first region 51 has irregularities that are smaller in size than the streak-like steps in the second region 52. Such a side surface state may be observed using an optical microscope or a scanning electron microscope (SEM). The recesses 53 can be confirmed using SEM photographs.

[0044] The laminate 10 has at least one side surface 10c in the longitudinal direction and one side surface 10d in the lateral direction. In this embodiment, the laminate 10 has two side surfaces 10c in the longitudinal direction and two side surfaces 10d in the lateral direction.

[0045] The longitudinal side surface 10c has a first side 54 that intersects with the first main surface 10a, a second side 55 that intersects with the lateral side surface 10d, and a third side 56 that intersects with the second main surface 10b. The first region 51 has a first boundary 51a that coincides with the first side 54, a second boundary 51b that is spaced apart from the second side 55 and faces the second side, and a third boundary 51c that is spaced apart from the third side 56 and faces the third side 56. The plurality of recesses 53 are provided at the third boundary 51c. The first region 51 may be an inverted trapezoid in which the first boundary 51a is longer than the third boundary 51c.

[0046] The recesses 53 are distributed over the entire third boundary 51c. The number of recesses 53 tends to be smaller than the number of recesses processed by laser processing when the grooves 20 are formed. The number of recesses 53 within a 20 μm width may be four or more at at least five different locations on the side surface 10c in the longitudinal direction. In an SEM photograph, the recesses 53 are observed as areas that are darker than the first region 51 and the second region 52. For the SEM photograph, a secondary electron (SE) image at a magnification of 2,500 times and an acceleration voltage of 5 kV may be used. The number of recesses 53 within a 20 μm width may be four or more, or may be seven or more, within each observation range. The number of recesses 53 within a 20 μm width may be 15 or less, or may be 11 or less, within each observation range. The spacing between the recesses 53 may be 0.5 μm or more and 10 μm or less. The length of the recess 53 in the thickness direction of the laminate 10 may be 2 μm or less.

[0047] The length of the first region 51 in the thickness direction of the laminate 10 can be in the same range as the depth of the groove 20. In this embodiment, the side surface 10c in the longitudinal direction is the surface on which the trace of the groove 20 remains, but depending on the shape of the semiconductor element 100, a side surface other than the side surface 10c in the longitudinal direction may be the surface on which the trace of the groove 20 remains.

[0048] The multiple semiconductor layers 12 may include a first conductivity type semiconductor layer 121, a second conductivity type semiconductor layer 122, and an active layer 123 sandwiched between the first conductivity type semiconductor layer 121 and the second conductivity type semiconductor layer 122. The first conductivity type semiconductor layer 121 is, for example, an n-type semiconductor layer. The second conductivity type semiconductor layer 122 is, for example, a p-type semiconductor layer. The substrate 11, the first conductivity type semiconductor layer 121, the active layer 123, and the second conductivity type semiconductor layer 122 may be in direct contact with each other, or another semiconductor layer may be disposed between them. For example, an undoped layer may be disposed between the second conductivity type semiconductor layer 122 and the active layer 123. The active layer 123 may have a multiple quantum well structure or a single quantum well structure. The multiple semiconductor layers 12 include, for example, an n-side cladding layer, an n-side optical guide layer, an active layer 123, a p-side electron confinement layer, a p-side optical guide layer, a p-side cladding layer, and a p-side contact layer, in that order from the substrate 11 side. For example, the n-side cladding layer is a first conductivity type semiconductor layer 121, and the p-side cladding layer is a second conductivity type semiconductor layer 122.

[0049] The semiconductor element 100 can have a first electrode 31 and a second electrode 32. The semiconductor element 100 may have an insulating film 33. If the semiconductor element 100 is a semiconductor laser element, the semiconductor element 100 may have a light-reflecting film or a protective film provided on the side surface 10d in the short side direction. The length of the semiconductor element 100 in the longitudinal direction may be two or more times the length of the short side direction. The length of the semiconductor element 100 in the longitudinal direction may be 50 or less times the length of the short side direction.

[0050] Examples 1 to 5 As the semiconductor elements of Examples 1 to 5, semiconductor laser elements having a shape in a planar view having a longitudinal direction and a lateral direction were fabricated. First, a stack made of a group III nitride semiconductor was prepared as a stack. A GaN substrate was used as the substrate. The thickness of the stack was about 60 μm. Next, the laminate was cleaved to form the surfaces that would become the short-side surfaces. Next, grooves were formed in the laminate by laser processing, and the laminate was divided using the grooves as starting points to form the long-side surfaces. The grooves were formed on the first main surface of the laminate, and then the second main surface of the laminate was pressed with a pressing member. The length of the semiconductor element 100 in the long-side direction was 1.2 mm. The grooves were formed using a nanosecond laser with a center wavelength of 355 nm. The average output of the laser processing using the nanosecond laser was 1 W, and the groove depth and repetition frequency were as shown in Table 1.

[0051] (Comparative Examples, Reference Examples) As the semiconductor elements of the comparative example and the reference example, semiconductor laser elements were fabricated in the same manner as in Example 1 except for the repetition frequency shown in Table 1.

[0052] [Table 1]

[0053] (Evaluation of groove shape) During the production of the semiconductor elements of each Example, Comparative Example, and Reference Example, the shape of the grooves was observed after they were formed and before they were pressed and divided. An optical microscope was used to photograph the side of the laminate, focusing on the grooves, and the image was used to determine the shape of the grooves. The results are shown in Table 1. As shown in Table 1, in Examples 1 to 5, the grooves had a shape with two or more branches at the tip. Figure 13 shows an optical microscope photograph of the grooves in Example 2. In the Comparative Example and Reference Example, the grooves were V-shaped, and no branching at the tip was observed.

[0054] (Appearance evaluation) Multiple semiconductor elements of each Example, Comparative Example, and Reference Example were fabricated and subjected to appearance evaluation. The appearance evaluation was performed from the perspectives of abnormal cracking and visual chipping, and the incidence of each was evaluated. Abnormal cracking was determined by whether or not a crack had occurred that had escaped from the groove and reached the first electrode of the semiconductor element. Visual chipping was determined by whether or not the shortest distance between the longitudinal side of the semiconductor element and the first electrode in a planar view was less than a predetermined distance, even if it could not be considered an abnormal crack. The results are shown in Table 1. Abnormal cracking occurred in the Comparative Example and Reference Example, but no abnormal cracking was observed in Examples 1 to 5. Regarding visual chipping, the incidence of visual chipping was lower in all Examples 1 to 5 than in the Comparative Example. In Examples 1 to 4, the incidence of visual chipping was less than 1%, which was lower than both the Comparative Example and the Reference Example.

[0055] (Side view) When the semiconductor elements of each example, comparative example, and reference example were observed with an optical microscope, a first region including a rough surface believed to be a groove trace and a second region including multiple streak-like steps extending from the first region toward the second main surface were confirmed. SEM photographs of the longitudinal side of the semiconductor elements of Examples 2, 5, and the comparative example were taken. Secondary electron (SE) images were taken at a magnification of 2,500x and an acceleration voltage of 5 kV. Using the SEM photographs, the number of recesses located at the boundary between the first and second regions was counted at five different locations within a 20 μm-wide area in the longitudinal direction of the semiconductor element. The results are shown in Table 2. Evaluation points A to E in Table 2 are the locations used to determine the number of recesses. Note that evaluation point A in Example 2, evaluation point A in Example 5, and evaluation point A in the comparative example are the first evaluation points, and are not necessarily the same location. Similarly, evaluation points B to E are not necessarily the same location. As shown in Table 2, no recesses were observed in the comparative example in which V-shaped grooves were formed. In Examples 2 and 5 in which grooves with branched ends were formed, multiple recesses were observed in each area. Figure 14 shows an SEM photograph of the longitudinal side of the semiconductor element of Example 2. In the SEM photograph, the roughly circular areas located at the boundary between the first and second regions, which are darker than those regions, are recesses. These recesses are thought to be the remaining branched portions of the groove ends.

[0056] [Table 2]

[0057] Through the contents described so far in this disclosure, the following technical matters are disclosed. (Section 1) A step of preparing a laminate including a substrate having a crystalline structure and a plurality of semiconductor layers laminated on the substrate; forming a groove having a branched tip in the laminate and dividing the laminate starting from the groove. (Section 2) the laminate has a first major surface and a second major surface; Item 2. A method for manufacturing a semiconductor element according to item 1, wherein in the dividing step, the groove is formed so as to reach the first main surface but not the second main surface, and the laminate in which the groove is formed is pressed from the side of the second main surface, thereby generating a crack starting from the groove and dividing the laminate. (Section 3) Item 3. The method for manufacturing a semiconductor device according to item 1 or 2, wherein in the dividing step, the direction in which the laminate is divided is a direction different from the easy cleavage direction of the substrate. (Section 4) the semiconductor element has a shape in a plan view having a short side direction and a long side direction, 4. The method for manufacturing a semiconductor element according to any one of items 1 to 3, wherein the dividing step is a step of forming side surfaces in the longitudinal direction. (Section 5) Item 5. A method for manufacturing a semiconductor device according to item 4, further comprising the step of dividing the laminate by cleavage to form the side surfaces in the short-side direction. (Section 6) the plurality of semiconductor layers include a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer sandwiched between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; 6. The method for manufacturing a semiconductor device according to any one of items 1 to 5, wherein the semiconductor device is a semiconductor laser device. (Section 7) 7. The method for manufacturing a semiconductor element according to any one of items 1 to 6, wherein the length of a side surface of the semiconductor element formed by the dividing step is 1 mm or more. (Section 8) Item 8. The method for manufacturing a semiconductor device according to any one of items 1 to 7, wherein the thickness of the laminate is 70 μm or less. (Section 9) A laminate having a side surface in a longitudinal direction, a side surface in a lateral direction, a first main surface, and a second main surface, The longitudinal side surface is a first region including a roughened surface; a second region including a plurality of streak-like steps extending from the first region toward the second main surface, A semiconductor element, wherein a plurality of recesses are provided at the boundary between the first region and the second region. (Section 10) the side surface in the longitudinal direction has a first side intersecting with the first main surface, a second side intersecting with the side surface in the lateral direction, and a third side intersecting with the second main surface, the first region has a first boundary coinciding with the first side, a second boundary spaced apart from the second side and facing the second side, and a third boundary spaced apart from the third side and facing the third side, Item 10. The semiconductor element according to item 9, wherein the recesses are provided at the third boundary. (Section 11) Item 11. The semiconductor element according to item 9 or 10, wherein the number of the recesses in a width of 20 μm is 4 or more at at least five different locations on the side surface in the longitudinal direction. [Explanation of symbols]

[0058] 10 Laminate 10a First principal surface 10b Second principal surface 10c Longitudinal side 10d Short side 11 Circuit Board 12 Multiple semiconductor layers 12a Ridge 121 First conductivity type semiconductor layer 122 second conductive type semiconductor layer 123 Active layer 20 grooves 20a Tip 20b Connecting part 31 1st electrode 32 2nd electrode 32a Contact electrode 32b Pad electrode 33 Insulating film 40 Pressing member 51 First area 51a 1st boundary 51b Second boundary 51c third boundary 52 Second area 53 Recess 54 Side 1 55 Side 2 56 Third Side 100 Semiconductor element

Claims

1. A step of preparing a laminate including a substrate having a crystalline structure and a plurality of semiconductor layers laminated on the substrate; forming a groove having a branched tip in the laminate and dividing the laminate starting from the groove.

2. the laminate has a first major surface and a second major surface; 2. The method for manufacturing a semiconductor element according to claim 1, wherein in the dividing step, the groove is formed so as to reach the first main surface but not the second main surface, and the laminate in which the groove is formed is pressed from the side of the second main surface to cause a crack to start from the groove, thereby dividing the laminate.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the dividing step, the direction in which the laminate is divided is different from the easy cleavage direction of the substrate.

4. the semiconductor element has a shape in a plan view having a short side direction and a long side direction, The method for manufacturing a semiconductor device according to claim 1 , wherein the dividing step is a step of forming side surfaces in the longitudinal direction.

5. The method for manufacturing a semiconductor device according to claim 4 , further comprising the step of dividing the laminate by cleavage to form the side surfaces in the short-side direction.

6. the plurality of semiconductor layers include a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer sandwiched between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; The method for manufacturing a semiconductor element according to claim 1 , wherein the semiconductor element is a semiconductor laser element.

7. The method for manufacturing a semiconductor element according to claim 1 , wherein the length of a side surface of the semiconductor element formed by the dividing step is 1 mm or more.

8. The method for manufacturing a semiconductor device according to claim 1 , wherein the thickness of the laminate is 70 μm or less.

9. The laminate has a longitudinal side surface, a lateral side surface, a first main surface, and a second main surface, The longitudinal side surface is a first region including a roughened surface; a second region including a plurality of streak-like steps extending from the first region toward the second main surface, A semiconductor element, wherein a plurality of recesses are provided at the boundary between the first region and the second region.

10. the side surface in the longitudinal direction has a first side intersecting with the first main surface, a second side intersecting with the side surface in the lateral direction, and a third side intersecting with the second main surface, the first region has a first boundary coinciding with the first side, a second boundary spaced apart from the second side and facing the second side, and a third boundary spaced apart from the third side and facing the third side, The semiconductor element according to claim 9 , wherein the plurality of recesses are provided at the third boundary.

11. 11. The semiconductor element according to claim 9, wherein the number of the plurality of recesses in a width of 20 [mu]m is four or more at at least five different locations on the side surface in the longitudinal direction.

Images