Multilayer ceramic capacitor and circuit board

Abstract

To provide a thin multilayer ceramic capacitor having a via conductor structure that penetrates between electrodes inside a stack, and that suppresses a decrease in capacitance due to disconnection caused by peeling at the interface between the via and the electrode, and a circuit board on which the multilayer ceramic capacitor is mounted.SOLUTION: A multilayer ceramic capacitor 100 includes a stack 20 in which ceramic layers 21 and internal electrodes 22 (22a, 22b) are alternately stacked, a rectangular parallelepiped base body 10 having a protective portion 30 covering its surface and a plurality of via conductors 23a, 23b, and a plurality of terminal electrodes 40a, 40b arranged on the surface of the base body and electrically connected to the end portions of the via conductors that reach the surface. The end portions of the via conductors located in the protective portion forms flanges 231 that protrude outward relative to the axis of the via conductors.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a circuit board. [Background technology]

[0002] A wide variety of ceramic electronic components are used in high-frequency communication systems, such as mobile phones. These ceramic electronic components are required to be smaller and thinner, and efforts are being made to make them smaller and thinner in multilayer ceramic capacitors as well.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor that can improve ESL characteristics and filling rate while reducing delamination. Patent Document 1 states that by providing a through electrode that penetrates the body of the multilayer ceramic capacitor with a tapered, trapezoidal cross section, it is possible to improve the ESL characteristics by preventing the cover from being pressed by an external force. Patent Document 1 also states that adjusting the diameter of the through electrode can improve the paste filling of the vias and increase the filling rate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-13008 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, the through electrodes (via conductors) have a shape in which their diameters monotonically increase from the bottom to the top. In multilayer ceramic capacitors in which the via conductors have such a shape, delamination at the interfaces between the via conductors and the ceramic layers and between the via conductors and the internal electrodes, as well as a decrease in capacitance due to disconnection between the via conductors and the internal electrodes caused by such delamination, are suppressed. However, there is a demand for further suppression of delamination and a decrease in capacitance.

[0006] Furthermore, unlike Patent Document 1, in multilayer ceramic capacitors in which external electrodes (terminal electrodes) are formed only on either the first or second principal surface, there is a problem in that, during firing during manufacturing, stress caused by the different shrinkage behavior of the via conductors and the terminal electrodes causes peeling at the interface between the via conductors and the internal electrodes, which breaks the connection between the two and easily leads to a decrease in capacitance.

[0007] The present invention has been made to solve the above problems, and has an object to provide a thin multilayer ceramic capacitor in which a decrease in capacitance is suppressed, and a circuit board on which the multilayer ceramic capacitor is mounted. [Means for solving the problem]

[0008] The inventor conducted various studies to solve the above-mentioned problems and discovered that in a multilayer ceramic capacitor in which internal electrodes are electrically connected to each other through via conductors, the above-mentioned object can be achieved by configuring the via conductor so that one end reaches the surface of the protective portion and the other end is located within the protective portion, and by forming a flange at the end located within the protective portion that protrudes outward relative to the axis of the via conductor, thereby completing the present invention.

[0009] That is, a first aspect of the present invention for solving the above problem is a multilayer ceramic capacitor comprising: a laminate in which ceramic layers formed of ceramic and internal electrodes primarily composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a rectangular parallelepiped element body having a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, electrically connected to the internal electrodes, one end of which reaches the surface of the protective portion and the other end of which is located within the protective portion; and a plurality of terminal electrodes arranged on the surface of the element body and electrically connected to the ends of each of the via conductors that reach the surface of the protective portion, wherein the ends of the via conductors located within the protective portion form flanges that protrude outward relative to the axis of the via conductors.

[0010] A second aspect of the present invention for solving the above problem is a circuit board on which the multilayer ceramic capacitor according to the first aspect is mounted. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a thin multilayer ceramic capacitor in which a decrease in capacitance is suppressed, and a circuit board on which the multilayer ceramic capacitor is mounted. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 2] 2 is a cross-sectional view taken along line AA (LT cross-sectional view) in FIG. 1. [Figure 3] 10A and 10B are diagrams for explaining a procedure for determining whether the end of a via conductor located in a protective part (cover part) forms a flange, and a procedure for determining the dimensions of each part of the via conductor. [Figure 4] FIG. 1 is a schematic diagram (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor including via conductors in which cavities opening to ends located in a protective portion (cover) are formed. [Figure 5]10A and 10B are diagrams for explaining a procedure for determining the dimensions of a cavity formed at an end portion located in a cover portion of a via conductor. [Figure 6] FIG. 1 is a schematic diagram (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor including via conductors whose ends located in a protective portion (cover portion) have a bulging shape at the center. [Figure 7] This is a schematic diagram (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor in which the end of a via conductor that reaches the surface of the mounting surface protrudes in the stacking direction beyond the surface position of the mounting surface and forms a flange that protrudes outward relative to the axis of the via conductor. [Figure 8] 10A and 10B are diagrams for explaining a procedure for determining whether a flange is formed at the end of a via conductor on the mounting surface side, and a procedure for determining the dimensions of the flange. [Figure 9] FIG. 10 is a schematic view (LT cross-sectional view) showing the structure of a modified example of the multilayer ceramic capacitor according to the second embodiment of the present invention. [Figure 10] FIG. 10 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] The configuration and effects of the present invention will be described below, along with the technical concept, with reference to the drawings. However, the mechanism of action includes assumptions, and the correctness of such assumptions does not limit the present invention.

[0014] [Multilayer ceramic capacitors] First Embodiment An embodiment of a multilayer ceramic capacitor according to a first aspect of the present invention is shown in FIGS. 1 and 2 as a first embodiment. The multilayer ceramic capacitor 100 according to the first embodiment has a rectangular parallelepiped shape and includes a pair of faces perpendicular to each of three mutually orthogonal axes, i.e., the L-axis, which is the length direction, the W-axis, which is the width direction, and the T-axis, which is the height direction. The rectangular parallelepiped is not limited to a mathematically defined rectangular parallelepiped, and may have any shape that is recognized as a rectangular parallelepiped when observed as a whole. Therefore, a rectangular parallelepiped in the present disclosure also includes a capacitor with rounded edges and corners, a capacitor with curved edges, and a capacitor with curved faces with a small curvature. The length (L), width (W), and height (T) dimensions of the ceramic capacitor 100 can each independently take any value.

[0015] The dimensions of the multilayer ceramic capacitor 100 are, for example, an L-direction dimension of 200 μm to 2000 μm, a W-direction dimension of 100 μm to 2000 μm, and a T-direction dimension of 30 μm to 220 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.3 to 1.0. It is preferable that the L-direction dimension be 400 μm to 1200 μm, the W-direction dimension be 400 μm to 1200 μm, and the T-direction dimension be 40 μm to 150 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.4 to 1.0. It is more preferable that the T-direction dimension be 100 μm or less, as this is less subject to design constraints on the circuit board on which it is mounted.

[0016] 2 (LT cross section), the multilayer ceramic capacitor 100 according to the first embodiment includes a laminate 20 in which ceramic layers 21 made of ceramic and internal electrodes 22 mainly composed of metal are alternately stacked in the T direction, and an element body 10 having a protective part 30 covering the surface of the laminate 20. The internal electrodes 22 include internal electrodes 22a of one polarity that are electrically connected to each other, and internal electrodes 22b of a polarity different from that of the internal electrodes 22a that are electrically connected to each other.

[0017] A protective portion 30 is arranged on the surface of the element body 10, covering the surface of the laminate 20. The protective portion 30 includes a cover portion 31 arranged on a plane perpendicular to the T direction, and margin portions 32 arranged on a plane perpendicular to the W direction and a plane perpendicular to the L direction, respectively.

[0018] The element body 10 has a plurality of via conductors 23 that are arranged to penetrate the ceramic layers 21 in the stacking direction of the laminate 20 and are electrically connected to the internal electrodes 22, with one end reaching the surface of the protective part 30 (cover part 31) and the other end located within the protective part 30 (cover part 31). The via conductors 23 include a via conductor 23a electrically connected to the internal electrode 22a and a via conductor 23b electrically connected to the internal electrode 22b. Note that although the multilayer ceramic capacitor 100 shown in FIGS. 1 and 2 includes two via conductors 23, the number of via conductors in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0019] The ends of the via conductors 23 (23a, 23b) located inside the cover portion 31 form flanges 231 that protrude outward relative to the axes of the via conductors 23 (23a, 23b). This prevents peeling at the interfaces between the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b), thereby suppressing a decrease in the capacitance of the multilayer ceramic capacitor 100. This is presumably because the presence of the flanges 231 allows the via conductors 23 to follow and displace in the same direction when the laminate 20 displaces in the stacking direction. Details of the shape and structure of the via conductors 23 (23a, 23b) will be described later.

[0020] The multilayer ceramic capacitor 100 according to the first embodiment is arranged at least on a mounting surface 11, which is the surface that faces the circuit board when mounted on the circuit board, among the surfaces that form the surface of the element body 10, and includes a plurality of terminal electrodes 40 electrically connected to via conductors 23 (23a, 23b). The terminal electrodes 40 include a terminal electrode 40a electrically connected to the via conductor 23a and a terminal electrode 40b electrically connected to the via conductor 23b. Note that although the multilayer ceramic capacitor 100 shown in FIGS. 1 and 2 includes two terminal electrodes 40, the number of terminal electrodes in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0021] The thickness of the element body 10, obtained by subtracting the thickness of the terminal electrodes 40 (40a, 40b) from the T-direction dimension of the multilayer ceramic capacitor 100 described above, is, for example, 20 μm to 200 μm, and preferably 30 μm to 180 μm.

[0022] Hereinafter, each component constituting the multilayer ceramic capacitor 100 according to the first embodiment will be described in detail.

[0023] (ceramic layer) The ceramic layer 21 is made of ceramic. The ceramic composition is not particularly limited as long as it forms a dense ceramic layer 21 by co-firing with the internal electrodes 22 described later, and may be appropriately selected depending on the properties required for the multilayer ceramic capacitor. Examples of ceramic compositions include those containing barium titanate (BaTiO3) as the main component, those containing strontium titanate (SrTiO3) as the main component, and those containing BaTiO3 having a perovskite structure. 1-x-y Ca x Sr y Ti 1-z Zr zExamples of such ceramics include those containing O3 as a main component. The ceramic may contain an additive element in addition to the main component. Examples of the additive element include at least one selected from Mo, Nb, Ta, W, Mg, Mn, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), and Co, Ni, Li, B, Na, K, and Si. The additive element may be contained as a simple element or in the form of a compound such as an oxide, nitride, or carbide. The additive element may exist in a solid solution state in the main component, or may form a different phase from the elements constituting the main component or other additive elements.

[0024] (Internal electrode) The internal electrodes 22 (22a, 22b) are primarily composed of a metal. The type of metal is not particularly limited, and nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof can be used. Among these, nickel (Ni) is preferred as the primary element because of its high heat resistance, which allows the firing temperature to be increased when co-firing with the ceramic layer 21 to form a dense ceramic layer 21, and it is relatively inexpensive. Here, the term "primary element" as used herein refers to the element with the highest content expressed in atomic percentage (atomic %).

[0025] The internal electrodes 22 (22a, 22b) may contain, in addition to metal, ceramic particles having the same composition as the ceramic constituting the ceramic layer 21, or a glass component.

[0026] (Protection Department) The protective part 30 has a function of protecting the ceramic layers 21 and the internal electrodes 22. The material of the protective part 30 is not limited as long as it has high electrical insulation and low permeability to deterioration factors such as moisture. From the viewpoints of making shrinkage during firing when manufacturing the multilayer ceramic capacitor 100 uniform and alleviating internal stress within the multilayer ceramic capacitor 100, it is preferable that the main component of the protective part 30 be the same as the ceramic that forms the ceramic layers 21.

[0027] (Via conductor) Like the internal electrodes 22 (22a, 22b), the via conductors 23 (23a, 23b) are primarily composed of metal. Usable metals include those similar to those of the internal electrodes 22 (22a, 22b) described above. The composition of the via conductors may be different from that of the internal electrodes 22 (22a, 22b), but is preferably the same as that of the internal electrodes 22 (22a, 22b). By making the via conductors (23a, 23b) and the internal electrodes 22 (22a, 22b) the same composition, the magnitude of shrinkage caused by firing during manufacturing of the multilayer ceramic capacitor 100 is uniform, suppressing deformation, and the resistivity of the conductive paths of the multilayer ceramic capacitor 100 is uniform, suppressing localized heat generation during use.

[0028] As described above, one end of the via conductor 23 (23a, 23b) reaches the surface of the protective portion 30 (cover portion 31), and the other end is located within the protective portion 30 (cover portion 31), and the end located within the protective portion 30 (cover portion 31) forms a flange 231 that protrudes outward relative to the axis of the via conductor 23 (23a, 23b).

[0029] In a cross section parallel to the stacking direction, the via conductors 23 (23a, 23b) preferably satisfy D1 > D2, where D1 is the dimension in the direction perpendicular to the stacking direction at the surface position of the protective portion 30 (cover portion 31) in the cross section parallel to the stacking direction, and D2 is the minimum dimension in the direction perpendicular to the stacking direction in the protective portion 30 (cover portion 31) located on the opposite side of the protective portion 30 (cover portion 31) with respect to the laminate 20. This effectively suppresses peeling at the interface between the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b), and further suppresses a decrease in the capacitance of the multilayer ceramic capacitor 100. This is presumably due to the fact that as D1 approaches the dimensions of the terminal electrode 40 described below, the contraction behavior of the via conductor 23 (23a, 23b) approaches that of the terminal electrode 40, and as the via conductor 23 (23a, 23b) assumes a tapered shape, the contact area with the laminate 20 and the cover portion 31 increases, thereby increasing frictional resistance.

[0030] In this case, when the via conductors 23 (23a, 23b) have a dimension D3 in a direction perpendicular to the stacking direction of the flange 231 in a cross section parallel to the stacking direction, if the via conductors 23 (23a, 23b) satisfy D3≧D1, the effect of suppressing peeling at the interface between the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b) is greater, and a decrease in the capacitance of the multilayer ceramic capacitor 100 is further suppressed. This is presumably because the large dimension of the flange 231 in the direction perpendicular to the stacking direction significantly increases the resistance force when the via conductors 23 (23a, 23b) are displaced in the stacking direction.

[0031] The values ​​of D1, D2, and D3 are not particularly limited, but in order to ensure the capacitance of the multilayer ceramic capacitor 100 while reducing electrical resistance and suppressing heat generation during circuit operation, the value of D2 is preferably 5 μm or more and 100 μm or less, and more preferably 10 μm or more and 50 μm or less. The value of D3 is preferably 110% or more and 225% or less, and more preferably 150% or more and 180% or less of the value of D2. Furthermore, the value of D3 is preferably 100% or more and 150% or less, and more preferably 100% or more and 120% or less of the value of D1.

[0032] The via conductors 23 (23a, 23b) preferably have a dimension in the stacking direction of the flange 231, i.e., a thickness A1 of the flange 231, of 0.1 μm or more and 10 μm or less. When the thickness of the flange 231 is 0.1 μm or more, sufficient resistance force can be ensured to suppress displacement of the via conductors 23 (23a, 23b) in the stacking direction. On the other hand, when the thickness of the flange 231 is 10 μm or less, the distance from the surface of the element body 10 and the internal electrodes 22 to the via conductors 23 (23a, 23b) is sufficient, ensuring the reliability of the multilayer ceramic capacitor.

[0033] Here, the determination of whether the end of the via conductor 23 (23a, 23b) located in the protective portion 30 forms the flange 231 and the determination of the dimensions D1, D2, D3, and A1 of each portion of the via conductor 23 (23a, 23b) are performed in the following procedure. First, a surface perpendicular to the mounting surface 11 of the multilayer ceramic capacitor 100, i.e., the surface that faces the circuit board when mounted on the circuit board, is ground to expose the vicinity of the center of gravity of the via conductor 23a. Grinding may be performed on a multilayer ceramic capacitor 100 that is embedded in resin. Next, the ground surface where the via conductor 23a is exposed is observed with an optical microscope or a scanning electron microscope (SEM), and an image is obtained in which the boundary between the via conductor 23a and the ceramic layer 21, the mounting surface 11, and the surface facing it are all in the same field of view, as shown in FIG. 3. Next, in the acquired image, line segments v1 and v2 defining both side surfaces of the via conductor 23a in the laminate 20 are drawn, and the intersections between the obtained line segments and the ends of the via conductor 23a located in the cover portion 31 are respectively designated as e 01 and e 02 The end of the via conductor 23a located in the cover is located at a point e 01 and point e 02 If the end portion of the via conductor 23a is located beyond the point e 01 The point on the edge furthest to the side is e 03 and the axis of the via conductor 23a is 02 The point on the edge furthest to the side is e 04 Next, in the image, a line segment h1 that defines the mounting surface 11 is drawn, and the intersections of this line segment with the line segment v1 and the line segment v2 are respectively defined as e 11 and e 12 Then, point e 11 and point e 12 The distance between the point e and the point e is divided by the magnification of the microscope image to obtain a value D1. 03 Line segment v3 that passes through and is perpendicular to line segment h1, and point e 04A line segment v4 passing through each of the lines and perpendicular to the line segment h1 is drawn, and the value obtained by dividing the distance between the line segments v3 and v4 by the magnification of the microscope image is defined as D3. Next, in the image, line segments parallel to the line segment h1 are drawn in the cover portion 31 where the end of the via conductor 23a is located, and the line segment that has the shortest distance between its intersections with both side surfaces of the via conductor 23a is defined as line segment h2, and each of the intersections is defined as e 21 and e 22 Then, point e 21 and point e 22 The distance between the two points is divided by the magnification of the microscope image to obtain the value D2. In this case, the line segment h1 is parallel to the line segment h2. x is point e 11 and point e 12 Point e from the side 21 and point e 22 As we approach the side, the line segment h x and the intersection point e with line segment v1 x1 and the line segment h x and the intersection point e with line segment v2 x2 The distance between x1 e x2 When the length of the line segment h1 decreases, it is determined that the dimension of the via conductor 23a in the direction perpendicular to the stacking direction monotonically decreases from D1 to D2. Next, in the image, a line segment h3 is drawn that is parallel to the line segment h1, contacts the end of the via conductor 23a located in the cover portion 31, and is the longest distance from the line segment h2. The value obtained by dividing the distance between the line segment h3 and the line segment h2 by the magnification of the microscope image is designated as A1. Note that when drawing the line segments v1, v2, and h1, if the side surface and mounting surface 11 of the via conductor 23a observed in the image form a curve or a broken line, the curve or broken line is linearly approximated to form the line segment. Although the above procedure is performed for the vicinity of the via conductor 23a, it goes without saying that it may also be performed for the vicinity of the via conductor 23b, which has a different polarity.

[0034] As shown in Fig. 4, it is preferable that the via conductors 23 (23a, 23b) have cavities formed that open to the ends located in the protective section 30 (cover section 31). This suppresses peeling at the interfaces between the via conductors 23 (23a, 23b) and the cover section 31, in the cover section 31 that contains the ends of the via conductors 23 (23a, 23b). This is presumably because the presence of the cavities reduces the contact area between the via conductors 23 (23a, 23b) and the cover section 31, and reduces stress that occurs at the interfaces between the via conductors 23 (23a, 23b) and the cover section 31 due to the difference in the amount of shrinkage between them during firing during manufacturing.

[0035] It is more preferable that the maximum dimension D4 of the cavity formed at the end of the via conductor 23 (23a, 23b) located in the cover portion 31 in the direction perpendicular to the stacking direction is 10% to 90% of the above-mentioned D2, i.e., the minimum dimension of the portion located in the cover portion 31 in the direction perpendicular to the stacking direction. When D4 is 10% or more of D2, peeling at the interface between the via conductor 23 (23a, 23b) and the cover portion 31 is significantly suppressed. On the other hand, when D4 is 90% or less of D2, the resistance of the via conductor 23 (23a, 23b) to displacement in the stacking direction and in the direction perpendicular to the stacking direction is sufficient, and peeling at the interface between the via conductor 23 (23a, 23b) and the internal electrode 22 (22a, 22b) can be suppressed.

[0036] The maximum dimension A2 in the stacking direction of the cavity formed at the end of the via conductor 23 (23a, 23b) located in the cover portion 31 is preferably 1 μm or more and 20 μm or less, more preferably 1 μm or more and 10 μm or less, and even more preferably 1 μm or more and 5 μm or less. When A2 is 1 μm or more, peeling at the interface between the via conductor 23 (23a, 23b) and the cover portion 31 is significantly suppressed. On the other hand, when A2 is 10 μm or less, sufficient resistance to displacement of the via conductor 23 (23a, 23b) in the stacking direction and in a direction perpendicular to the stacking direction can be obtained, thereby suppressing peeling at the interface between the via conductor 23 (23a, 23b) and the internal electrode 22 (22a, 22b).

[0037] Here, the dimensions D4 and A2 of each part of the cavity formed at the end of the via conductor 23 (23a, 23b) located in the cover part 31 are determined by the following procedure. First, using the same procedure as in determining D1, D2, D3, and A1, an image is obtained in which the boundary between the via conductor 23a and the ceramic layer 21, the mounting surface 11, and the surface facing it are in the same field of view, as shown in Figure 5, and a line segment v1 and a point e are defined in the image. 01 , line segment v2 and point e 02 , and line segment h1 are drawn. Next, in the image, point e 01 and point e 02 Line segment e connecting 01 e 02 The line segment is drawn, and among the points at which the line segment intersects with the contour line of the via conductor 23a that defines the cavity at the end of the via conductor 23a located in the cover portion 31, point e 01 Something close to e 41 Let point e 02 Something close to e 42 At this time, point e 41 If there is no point, the next step is to select the point e 01 Point e 41 and point e 42 If there is no point, the next step is to select the point e 02 Point e 42 Next, in the image, point e 41 Line segment v5 that passes through and is perpendicular to line segment h1, and point e 42 A line segment v6 passing through the line segment h1 and perpendicular to the line segment h1 is drawn, and the value obtained by dividing the distance between the line segment v5 and the line segment v6 by the magnification of the microscope image is defined as D4. Next, in the image, a line segment e 01 e 02 Draw a line segment h4 that has the maximum distance from the line segment h4. 01 e 02 The value obtained by dividing the shortest distance between the two by the magnification of the microscope image is defined as A2.

[0038] The ends of the via conductors 23 (23a, 23b) located in the protective portion 30 (cover portion 31) may have a centrally bulged shape, as shown in FIG. 6 , i.e., a shape with a convex portion protruding in the stacking direction of the laminate 20, as opposed to the aforementioned hollow shape. This shape is formed when, during the manufacturing process of the multilayer ceramic capacitor 100 described below, the conductive paste for forming the via conductors remains without moving toward the mounting surface 11 and pushes back the green sheet for forming the cover portion when the green sheet for forming the cover portion is pressed against the laminate. Therefore, the bulging of the central portions of the ends of the via conductors 23 (23a, 23b) located in the cover portion 31 indicates high adhesion between the via conductors 23 (23a, 23b) and the adjacent cover portion 31, ceramic layer 21, and internal electrode 22 (22a, 22b), thereby obtaining a multilayer ceramic capacitor 100 with high mechanical strength.

[0039] As shown in FIG. 7 , the via conductors 23 (23a, 23b) preferably have ends that reach the surface of the protective section 30 (cover section 31) protruding in the stacking direction beyond the surface of the cover section 31, i.e., beyond the position of the mounting surface 11, and forming flanges 232 that protrude outward relative to the axes of the via conductors 23 (23a, 23b). This prevents peeling at the interfaces between the via conductors 23 (23a, 23b) and the cover section 31, in the cover section 31 where the via conductors 23 (23a, 23b) penetrate to the surface. This is presumably because the flanges 232 in contact with the surface of the cover section 31 make it easier for the via conductors 23 (23a, 23b) to follow the expansion and contraction of the cover section 31 in the direction perpendicular to the stacking direction, and because the direction of stress applied to the interfaces between the via conductors 23 (23a, 23b) and the cover section 31 is dispersed on the surface of the cover section 31.

[0040] The thickness of the flange 232, i.e., the dimension A3 in the stacking direction, is more preferably 0.1 μm or more and 1.0 μm or less, and even more preferably 0.1 μm or more and 0.5 μm or less. When A3 is 0.1 μm or more, peeling at the interface between the via conductors 23 (23a, 23b) and the cover portion 31 is significantly suppressed. On the other hand, when A3 is 1.0 μm or less, a decrease in the strength of the flange is suppressed.

[0041] The dimension D5 of the flange 232 in the direction perpendicular to the stacking direction is preferably 101% to 150% of the above-mentioned D1, i.e., the dimension in the direction perpendicular to the stacking direction at the surface position of the cover portion 31, and more preferably 101% to 120%. When D5 is 101% or more of D1, peeling at the interface between the via conductors 23 (23a, 23b) and the cover portion 31 is significantly suppressed. On the other hand, when D5 is 150% or less of D1, the distance between conductors of opposite polarity is secured, and a decrease in electrical insulation is suppressed.

[0042] Here, the determination of whether a flange 232 is formed at the end of the via conductor 23 (23a, 23b) on the mounting surface 11 side and the determination of the dimensions A3 and D5 of the flange 232 are performed in the following procedure. First, using the same procedure as in determining D1, D2, D3, and A1 above, an image is obtained in which the boundary between the via conductor 23a and the ceramic layer 21, as well as the mounting surface 11 and the surface facing it, are in the same field of view, as shown in Figure 8, and line segments v1, v2, and h1 are drawn in the image. Next, the intersection of line segments v1 and h1 is determined by e. 51 Let the intersection of line segment v2 and line segment h1 be e 52 Next, in the image, a part of the via conductor 23a is present on the opposite side of the line segment h1 from the laminate 20, and a point e is located along the line segment h1 with respect to the axis of the via conductor 23a. 51 and point e with respect to the axis of the via conductor 23a. 52Since a portion of the via conductor 23a is present outside the above, it is determined that a flange 232 is formed at the end of the via conductor 23a on the mounting surface 11 side. The end of the via conductor 23a on the mounting surface 11 side is connected to the terminal electrode 40a, but the via conductor 23a and the terminal electrode 40a have different contrasts in the microscope image, making it easy to distinguish between them. Next, in the image, on the side opposite the laminate 20 with respect to the line segment h1, i.e., on the side where the flange 232 of the via conductor 23a protrudes, a line segment h5 is drawn that is parallel to the line segment h1, contacts the via conductor 23a, and is at the greatest distance from the line segment h1. The value obtained by dividing the distance between the line segment h1 and the line segment h5 by the magnification of the microscope image is designated as A3. Next, in the image, a point e is drawn with respect to the axis of the via conductor 23a. 51 The point e is perpendicular to the line segment h1 and is in contact with the via conductor 23a. 51 A line segment v7 is drawn so that the distance from the point e is the maximum. 52 The point e is perpendicular to the line segment h1 and is in contact with the via conductor 23a. 52 Then, divide the distance between line segments v7 and v8 by the magnification of the microscope image and let the value obtained be D5.

[0043] (terminal electrode) The material of the terminal electrodes 40 (40a, 40b) is not limited as long as it is conductive, and examples of the material include metals such as nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), alloys containing any of these as a main component, and conductive resins.

[0044] The terminal electrodes 40 (40a, 40b) may have an underlying conductor 41 in contact with the element body 10 and a plated conductor 42 formed on the surface of the underlying conductor 41. The terminal electrodes 40 (40a, 40b) having such a structure can improve adhesion to the element body 10 by the underlying conductor 41, and can improve solder wettability by the plated conductor 42 when mounted on a circuit board.

[0045] Ni is an example of the material of the underlying conductor 41. The thickness of the underlying conductor 41 can be set to 0.1 μm or more and 10 μm or less, and preferably 0.5 μm or more and 5 μm or less.

[0046] The plated conductor 42 may be formed of a single layer or multiple layers. When the plated conductor 42 is formed of multiple layers, the number of layers is preferably two to four. An example of the material and structure of the plated conductor 42 is one formed of Cu, Ni, and Sn in this order. The thickness of the plated conductor 42 can be 1 μm to 20 μm, and preferably 3 μm to 10 μm.

[0047] <Second embodiment> In another embodiment (second embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, the internal electrodes are drawn out to a surface perpendicular to the mounting surface, and external electrodes are disposed on the surfaces (drawn-out surfaces) to which the internal electrodes are drawn out, and the internal electrodes are also electrically connected via the external electrodes. An example of a multilayer ceramic capacitor 200 according to the second embodiment is shown in FIG. 9. Note that FIG. 9 shows an example in which two opposing surfaces are drawn out as drawn-out surfaces 12, but the number of drawn-out surfaces is not limited to this. Also, FIG. 9 shows an example in which terminal electrodes 40 (40a, 40b) extending to the drawn-out surfaces 12 form external electrodes 50 (50a, 50b), but the external electrodes 50 (50a, 50b) may be formed separately from the terminal electrodes 40 (40a, 40b). In the multilayer ceramic capacitor 200, the current flowing through the internal electrodes 22 (22a, 22b) is divided between the via conductors 23 (23a, 23b) and the external electrodes 50 (50a, 50b), thereby reducing the current flowing through each of the via conductors 23 (23a, 23b) and the external electrodes 50 (50a, 50b). This reduces heat generation during operation.

[0048] <Third embodiment> In another embodiment (third embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, the number of terminal electrodes arranged on the mounting surface is four or more, and each of the terminal electrodes has a polarity opposite to that of the nearest terminal electrode on the mounting surface. An example of a multilayer ceramic capacitor 300 according to the third embodiment is shown in FIG. 10. Note that FIG. 10 shows an example in which the number of terminal electrodes 40 arranged on the mounting surface 11 is four, but the number of terminal electrodes arranged on the mounting surface is not limited to this. In the multilayer ceramic capacitor 300, the directions of currents flowing through via conductors (not shown) electrically connected to each terminal electrode 40 (40a, 40b) are opposite to those of the nearest conductors, so that magnetic fields generated by the currents cancel each other out, thereby reducing equivalent series inductance (ESL). The above-mentioned effects are remarkable when the multilayer ceramic capacitor 300 has two pairs of surfaces that are parallel to the stacking direction of the laminate and face each other, and when the spacing between one pair, i.e., the L-direction dimension, is L μm and the spacing between the other pair, i.e., the W-direction dimension, is W μm (where L≧W), and the value of W / L, which is the ratio of W to L, is 0.8 or more and 1 or less, i.e., when the mounting surface 11 has a shape that is close to a square.

[0049] [Manufacturing method for multilayer ceramic electronic components] The multilayer ceramic capacitor according to the first aspect of the present invention can be manufactured by the procedure described below.

[0050] (A) Preparation of ceramic powder First, ceramic powder is prepared. Commercially available ceramic powders can be used as appropriate. When producing ceramic powder in-house, various raw material powders containing the constituent elements are mixed in a predetermined ratio and pre-fired (calcined). When mixing the various raw material powders in a predetermined ratio, various additives such as the above-mentioned additive elements and sintering aids may be further added, or these various additives may be further added to the powder after calcination.

[0051] (B) Preparation of raw sheets Next, the ceramic powder is mixed with a binder and a dispersion medium to prepare a slurry, and the slurry is formed into a sheet to obtain a green sheet.

[0052] The binder used should be one that can maintain the shape of the green sheet and volatilizes without leaving any carbon or other residues during the binder removal process prior to firing. Examples of binders that can be used include polyvinyl alcohol, polyvinyl butyral, cellulose, urethane, and vinyl acetate. There are no particular restrictions on the amount of binder used, but since it will be removed in a later process, it is preferable to keep it as low as possible within the range that achieves the desired formability and shape retention, in order to reduce raw material costs.

[0053] The dispersion medium used is one that does not cause aggregation of the calcined powder and binder and can be easily removed by volatilization or the like after forming into a green sheet, as described below. Examples of the dispersion medium that can be used include water and alcohol-based solvents.

[0054] Components for adjusting the properties of the slurry, such as dispersants, plasticizers, and thickeners, may be added to the slurry.

[0055] The method for mixing the mixed powder with the binder and the dispersion medium is not particularly limited as long as the components are mixed uniformly while preventing the inclusion of impurities. One example is ball mill mixing.

[0056] The prepared slurry can be formed into a sheet to obtain a green sheet by a commonly used method such as a doctor blade method or a die coating method.

[0057] ((C) Formation of internal electrode pattern) Next, an internal electrode pattern containing metal is formed on the green sheet. The internal electrode pattern can be formed by printing or applying an internal electrode paste in a predetermined pattern, or by forming a metal film in a predetermined pattern by vapor deposition or sputtering. The internal electrode pattern is formed with a sufficient margin to ensure electrical insulation with the via conductor patterns that will be formed later and that will not come into contact with the via conductor patterns.

[0058] When forming an internal electrode pattern using an internal electrode paste, the internal electrode paste used is obtained by mixing metal particles and a vehicle in a triple roll mill. The internal electrode paste may contain glass frit and ceramic powder in addition to the above-mentioned components.

[0059] The type and amount of binder and solvent contained in the vehicle used are not limited, and may be selected appropriately taking into consideration the viscosity of the internal electrode paste, ease of handling, compatibility with the green sheet, and the like.

[0060] The internal electrode paste can be printed on the green sheet using, for example, a screen mask on which a predetermined internal electrode pattern is formed. When printing, a space may be left to become a margin when the multilayer ceramic capacitor is completed.

[0061] (D) Preparation of green laminate Next, a predetermined number of green sheets on which the internal electrode patterns have been formed are stacked and the green sheets are pressure-bonded together to obtain a green laminate. The stacking and pressure-bonding can be performed by a conventional method, such as pressing the stacked green sheets together in the stacking direction while heating them, and thermo-compression bonding by the action of a binder.

[0062] During lamination and compression bonding, a green sheet that will become a cover when the multilayer ceramic capacitor is completed may be added to the end portion in the lamination direction. In this case, the green sheet to be added may have the same composition as the green sheet on which the internal electrode pattern is printed, or a different composition. From the viewpoint of making the shrinkage rate during firing uniform, it is preferable that the composition of the green sheet to be added is the same as or similar to the green sheet on which the above-mentioned internal electrode precursor is arranged.

[0063] (E) Formation of through holes for via conductors Next, through holes for via conductors are formed in the green laminate. Conventional methods such as drilling or lasers can be used to form the holes. Lasers are preferred because they can produce a smooth surface. After the through holes are formed, a portion of the material forming the green laminate is removed from the periphery of one of the openings to form a void with a shape corresponding to the flange. Examples of methods for removing the green sheet include pressing a mold with a protrusion against the periphery of the opening or polishing.

[0064] (F) Filling of via conductor paste) Next, the through holes are filled with a conductive paste to form a via conductor pattern. Commonly used methods, such as syringe injection or printing using a metal mask, can be used to fill the holes with the conductive paste. Among these, printing using a metal mask is preferred due to its excellent filling ability into small-diameter holes. The components of the conductive paste can be the same as those of the internal electrode paste described above, and the amount of each component can be determined taking into account the hole filling ability. To form a cavity at the end of the via conductor located in the cover, a convex member smaller in size than the through hole can be inserted from the cavity-forming side, followed by filling with the conductive paste. The convex member can then be removed, or the green laminate can be vibrated with the cavity-forming side facing upward after filling the through hole with the conductive paste. On the other hand, to form the end of the via conductor located in the cover into a bulging shape, the conductive paste can be filled so that it protrudes (bulges) above the surface height of the green laminate on the end side. Furthermore, when forming a flange at the end portion that reaches the surface of the cover portion, which protrudes beyond the surface position of the cover portion in the stacking direction and extends outward relative to the axis of the via conductor, a mask material having an opening larger in size than the opening of the through hole is placed around the opening, and then conductive paste is filled into the opening of the mask material as well as the through hole, and then the mask material is removed.

[0065] ((G) Crimping of raw sheet for cover) Next, a green sheet that will become a cover when the laminated ceramic capacitor is fabricated is pressure-bonded to the surface of the green laminate perpendicular to the stacking direction, on the side where a portion of the material forming the green laminate from the periphery of the through-hole opening has been removed in step (E). The green sheet to be pressure-bonded may have the same composition as the green sheet that forms the green laminate, or a different composition. Examples of pressure-bonding methods include pressing using a mold or applying pressure using a roller.

[0066] ((H) Formation of terminal electrode pattern) Next, a terminal electrode pattern is formed on at least one of the surfaces (mounting surface) of the green laminate perpendicular to the lamination direction. The terminal electrode pattern can be formed by printing or applying a terminal electrode paste, or by forming a metal film by vapor deposition or sputtering. In this case, the terminal electrode pattern may be formed using a mask with a predetermined pattern, or by forming a paste film or metal film once on the entire mounting surface of the green laminate and then removing the portion other than the terminal electrode pattern. Face milling, barrel polishing, or the like can be used to remove the portion other than the terminal electrode pattern. When a terminal electrode paste is used to form the terminal electrode pattern, the components thereof can be the same as those of the internal electrode paste described above, and the blending amounts of each component can be determined so as to obtain a uniform pattern with the desired thickness.

[0067] (I) Preparation of pre-fired chips Next, the green laminate is divided into individual pieces to obtain pre-fired chips. For the division, a commonly used means such as a dicing saw or a laser cutting machine can be used. After dividing the green laminate into individual pieces to form surfaces on which the internal electrode precursors are exposed, the surfaces may be coated with a material for forming margins to obtain pre-fired chips.

[0068] (J) Binder Removal Next, the resulting pre-fired chips are heated to volatilize and remove the binder. The heating conditions can be set appropriately taking into account the volatilization temperature and content of the binder. For example, the chips are held in a nitrogen (N2) atmosphere at a temperature of 200 to 500°C for 5 to 20 hours.

[0069] (K) Firing of pre-fired chips Next, the pre-fired chip from which the binder has been removed is heated to a predetermined temperature and fired. When setting the firing conditions, it is preferable to consider the sinterability of the ceramic powder, as well as the heat resistance and oxidation resistance of the metals contained in the internal electrode pattern, via conductor pattern, and terminal electrode pattern. An example of firing conditions is holding the chip at a temperature of 1100°C to 1400°C for 10 minutes to 2 hours in a reducing atmosphere containing a mixture of nitrogen (N2), hydrogen (H2), and water vapor (H2O). After firing, a reoxidation treatment may be performed in which the chip is held at 600°C to 1000°C in a nitrogen (N2) gas atmosphere or a low-oxygen atmosphere.

[0070] The sintered body thus obtained may be used as a multilayer ceramic capacitor as it is, or may be used as a multilayer ceramic capacitor after forming a conductive layer on the surface of the terminal electrode pattern by plating.

[0071] [Circuit board] A circuit board according to a second aspect of the present invention is equipped with the multilayer ceramic capacitor according to the first embodiment. This circuit board is highly reliable and can be installed in a small space because the multilayer ceramic capacitor is a thin type that suppresses a decrease in capacitance.

[0072] This specification also discloses the following techniques.

[0073] (Appendix 1) a laminate in which ceramic layers formed of ceramic and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, electrically connected to the internal electrodes, one end of which reaches the surface of the protective portion and the other end of which is located within the protective portion; A rectangular parallelepiped element having the following structure: a plurality of terminal electrodes disposed on the surface of the element body and electrically connected to ends of the via conductors that reach the surface of the protection portion; Equipped with The end of the via conductor located in the protective portion forms a flange that projects outward relative to the axis of the via conductor. Multilayer ceramic capacitor.

[0074] (Appendix 2) The multilayer ceramic capacitor according to (Appendix 1), wherein, in a cross section parallel to the stacking direction, when the dimension of the via conductor in the direction perpendicular to the stacking direction at the surface position of the protective part is D1 and the smallest dimension in the direction perpendicular to the stacking direction in the protective part located on the opposite side of the laminate from the protective part is D2, the via conductor satisfies D1>D2 and the dimension in the direction perpendicular to the stacking direction monotonically decreases from D1 to D2.

[0075] (Appendix 3) The multilayer ceramic capacitor described in (Appendix 2), wherein, in a cross section parallel to the stacking direction, when the dimension D3 of a flange formed by an end portion located in the protective portion in a direction perpendicular to the stacking direction is taken as D3, satisfies D3≧D1.

[0076] (Appendix 4) The multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 3), wherein the via conductor has a dimension A1 of 0.1 μm or more and 10 μm or less in the lamination direction of the flange.

[0077] (Appendix 5) The multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 4), wherein the via conductor has a cavity that opens to an end located in the protective portion.

[0078] (Appendix 6) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 5), wherein an end of the via conductor that reaches the surface of the protective portion protrudes in the stacking direction beyond the surface position of the protective portion and forms a flange that protrudes outward relative to the axis of the via conductor.

[0079] (Appendix 7) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 6), wherein the dimension in the lamination direction is 100 μm or less.

[0080] (Appendix 8) A circuit board on which the multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 7) is mounted. [Industrial Applicability]

[0081] According to the present invention, it is possible to provide a thin multilayer ceramic capacitor in which a decrease in capacitance is suppressed. Such a multilayer ceramic capacitor is not only highly reliable but also useful in that it can be arranged in a narrow space, thereby reducing restrictions on the design of a circuit board. [Explanation of symbols]

[0082] 100, 200, 300 Multilayer ceramic capacitors 10 Base 11 Mounting surface 12 Drawer surface 20 laminate 21 ceramic layer 22(22a, 22b) Internal electrode 23(23a, 23b) Via conductor 231, 232 flange 30 Protection Department 31 Cover 32 Margin 40(40a, 40b) terminal electrode 41 Undercoat conductor 42 Plated conductor 50(50a, 50b) External electrode

Claims

1. a laminate in which ceramic layers formed of ceramic and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, electrically connected to the internal electrodes, one end of which reaches the surface of the protective portion and the other end of which is located within the protective portion; A rectangular parallelepiped element having the following structure: a plurality of terminal electrodes disposed on the surface of the element body and electrically connected to ends of the via conductors that reach the surface of the protection portion; Equipped with The end of the via conductor located in the protective portion forms a flange that projects outward relative to the axis of the via conductor. Multilayer ceramic capacitor.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein, in a cross section parallel to the stacking direction, when a dimension D1 is a dimension in a direction perpendicular to the stacking direction at a surface position of the protective portion and a minimum dimension D2 is a dimension in a direction perpendicular to the stacking direction in a protective portion located on the opposite side of the laminate from the protective portion, the via conductor satisfies D1 > D2 and the dimension in the direction perpendicular to the stacking direction monotonically decreases from D1 to D2.

3. 3. The multilayer ceramic capacitor according to claim 2, wherein, in a cross section parallel to the stacking direction, when a dimension D3 of a flange formed by an end portion located in the protective portion in a direction perpendicular to the stacking direction is defined as D3, the via conductor satisfies D3≧D1.

4. 2. The multilayer ceramic capacitor according to claim 1, wherein the via conductor has a dimension A1 of 0.1 μm or more and 10 μm or less in the lamination direction of the flange.

5. 2. The multilayer ceramic capacitor according to claim 1, wherein the via conductor has a cavity formed therein that opens to an end located in the protective portion.

6. 2. The multilayer ceramic capacitor according to claim 1, wherein an end of the via conductor that reaches the surface of the protective portion protrudes beyond the surface position of the protective portion in the stacking direction and forms a flange that protrudes outward relative to the axis of the via conductor.

7. 2. The multilayer ceramic capacitor according to claim 1, wherein the dimension in the lamination direction is 100 μm or less.

8. A circuit board having the multilayer ceramic capacitor according to any one of claims 1 to 7 mounted thereon.

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