Semiconductor device

Abstract

To provide a technology capable of properly maintaining a potential between upper electrodes.SOLUTION: A semiconductor device comprises a 1-1 trench gate structure provided in a first trench, a 1-2 trench gate structure and a barrier structure, a second trench gate structure provided in the second trench, and a third trench gate structure provided in the third trench and connected to the 1-2 trench gate structure and the second trench gate structure. The barrier structure includes an insulation film provided at least in part between a 1-1 upper electrode and a 1-2 upper electrode to insulate the 1-1 upper electrode and 1-2 upper electrode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices with a two-stage gate structure having an active trench and a dummy trench are known. For example, in the semiconductor device disclosed in Patent Document 1, the upper and lower electrodes in the active trench are both connected to the gate electrode and are at the gate potential, while the upper electrode in the dummy trench is connected to the emitter electrode and is at the dummy potential, and the lower electrode is connected to the gate electrode and is at the gate potential. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-39138 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the semiconductor device as described above, when an active trench in which the upper electrode is at gate potential and a dummy trench in which the upper electrode is at dummy potential are arranged side by side, there is a problem that the potential of either upper electrode cannot be properly maintained.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that can appropriately maintain the potential between upper electrodes. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a semiconductor substrate provided with a first trench extending in a first direction, a second trench extending in the first direction along the first trench, and a third trench extending in a second direction different from the first direction and connected to the first trench and the second trench, a 1-1 trench gate structure and a 1-2 trench gate structure provided in the first trench, a barrier structure provided in the first trench and between the 1-1 trench gate structure and the 1-2 trench gate structure, a second trench gate structure provided in the second trench, and a third trench gate structure provided in the third trench and connected to the 1-2 trench gate structure and the second trench gate structure, the 1-1 trench gate structure including a first bottom electrode and a 1-1 upper electrode insulated from the first bottom electrode and provided above the first bottom electrode, and the 1-2 trench gate structure including the first bottom electrode and a 1-2 upper electrode insulated from the first bottom electrode. the barrier structure includes the first bottom electrode and an insulating film provided at least partially between the 1-1 top electrode and the 1-2 top electrode and insulating the 1-1 top electrode from the 1-2 top electrode; the second trench gate structure includes a second bottom electrode and a second top electrode insulated from the second bottom electrode and provided above the second bottom electrode; the third trench gate structure includes a third bottom electrode electrically connecting the first bottom electrode and the second bottom electrode, and a third top electrode electrically connecting the 1-2 top electrode and the second top electrode and insulated from the third bottom electrode and provided above the third bottom electrode; the first bottom electrode, the second bottom electrode, the third bottom electrode, the 1-2 top electrode, the second top electrode, and the third top electrode are electrically connected to one of a gate electrode and a dummy electrode, and the 1-1 top electrode is electrically connected to the other of the gate electrode and the dummy electrode. [Effects of the Invention]

[0007] According to the present disclosure, the barrier structure includes an insulating film provided at least partially between the first upper electrode and the second upper electrode, insulating the first upper electrode from the second upper electrode. With this configuration, the potential between the upper electrodes can be appropriately maintained. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 3] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 5] FIG. 10 is a plan view showing the configuration of a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a plan view showing the configuration of a semiconductor device according to a third embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 11] FIG. 10 is a schematic plan view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 12] FIG. 10 is a plan view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fifth embodiment. [Figure 15] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In addition, in the following description, specific positions and directions such as "upper," "lower," "left," "right," "front," or "back" may not necessarily correspond to positions and directions in actual implementation.

[0010] <First Embodiment> Fig. 1 is a plan view showing the configuration of a semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view taken along line A-A' in Fig. 1, Fig. 3 is a cross-sectional view taken along line B-B' in Fig. 1, and Fig. 4 is a cross-sectional view taken along line CC' in Fig. 1.

[0011] The semiconductor device according to the first embodiment includes a semiconductor substrate 1, a D-trench gate structure 10a which is a 1-1 trench gate structure, a 1A-trench gate structure 10b which is a 1-2 trench gate structure, a 2A-trench gate structure 20a which is a second trench gate structure, a 3A-trench gate structure 30a which is a third trench gate structure, and a barrier structure 10c.

[0012] The semiconductor substrate 1 may be made of a normal semiconductor wafer or an epitaxially grown layer. The material of the semiconductor substrate 1 may be normal silicon (Si), or may be a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. When the material of the semiconductor substrate 1 is a wide bandgap semiconductor, stable operation of the semiconductor device under high temperatures and high voltages and high switching speeds are possible.

[0013] 1, a semiconductor substrate 1 is provided with a D trench 10 which is a first trench, an A trench 20 which is a second trench, and an S trench 30 which is a third trench. The D trench 10 extends in a first direction, and the A trench 20 extends in the first direction along the D trench 10. The S trench 30 extends in a second direction different from the first direction, and is connected to the D trench 10 and the A trench 20. In the first embodiment, the second direction is a direction perpendicular to the first direction, but is not limited to this.

[0014] <Dトレンチ10> 1 and 2, a D-trench gate structure 10a, a first A-trench gate structure 10b, and a barrier structure 10c are provided in the D-trench 10. The barrier structure 10c is provided between the D-trench gate structure 10a and the first A-trench gate structure 10b.

[0015] 2, the D trench gate structure 10a, which is an AD structure, includes an A lower electrode 12 that is an electrode having an active function, a D upper electrode 11a that is an electrode having a dummy function, and an insulating film 42. That is, in the first embodiment, the first lower electrode is the A lower electrode 12, and the 1-1 upper electrode is the D upper electrode 11a. The D upper electrode 11a is insulated from the A lower electrode 12 by the insulating film 42 and is provided above the A lower electrode 12.

[0016] The first A trench gate structure 10b, which is an AA structure, includes an A lower electrode 12 which is an electrode having an active function, an A upper electrode 11b which is also an electrode having an active function, and an insulating film 42. That is, in the present embodiment 1, the first-2 upper electrode is the A upper electrode 11b. The A upper electrode 11b is insulated from the A lower electrode 12 by the insulating film 42 and is provided above the A lower electrode 12.

[0017] The barrier structure 10c includes an A lower electrode 12, which is an electrode having an active function, and an insulating film , as will be described in detail later.

[0018] An electrode having an active function is an electrode that is electrically connected to a gate electrode that can be actively controlled, and is active in potential, and is an electrode whose potential can be controlled in accordance with a gate signal. The gate electrode may include a gate pad. On the other hand, an electrode having a dummy function is an electrode that is connected to a dummy electrode whose potential cannot be controlled in accordance with a gate signal. In the example of FIG. 2, the dummy electrode is the emitter electrode 40 that is electrically connected to the D upper electrode 11a via the contact region 70, but it may be any electrode whose electricity cannot be arbitrarily controlled, such as an electrically floating electrode.

[0019] The "A" attached to the 1A trench gate structure 10b, the A lower electrode 12, etc. indicates that the trench gate structure and electrode have an active function. On the other hand, the "D" attached to the D trench gate structure 10a, the D upper electrode 11a, etc. indicates that the trench gate structure and electrode have a dummy function. Note that the trench gate structure having an active function does not necessarily mean that it contributes to controlling the flow of the main current flowing between the emitter and the collector (i.e., forming a channel in the semiconductor substrate 1).

[0020] Whether or not the trench gate structure contributes to controlling the flow of the main current depends on the state of the semiconductor substrate 1 around the trench gate structure and the potential of the upper electrode of the trench gate structure. The conditions for the state of the semiconductor substrate 1 that allow the trench gate structure to contribute to controlling the flow of the main current include: (i) a base layer of a first conductivity type (e.g., P-type) located at the same height as the upper electrode in the trench faces the upper electrode via an insulating film; and (ii) an emitter layer of a second conductivity type (e.g., N-type) connected to the emitter electrode is provided on the base layer, and a drift layer of the second conductivity type (e.g., N-type) is provided below the base layer. The conditions for the potential of the upper electrode that allow the trench gate structure to contribute to controlling the flow of the main current include: (iii) a gate signal can be input to the upper electrode, i.e., the upper electrode has an active function.

[0021] Because the D upper electrode 11a is an electrode with a dummy function, the D trench gate structure 10a does not satisfy (iii) and does not contribute to controlling the flow of the main current. Because the A upper electrode 11b is an electrode with an active function, the first A trench gate structure 10b satisfies (iii) but does not satisfy (i) or (ii), and therefore does not contribute to controlling the flow of the main current. The barrier structure 10c also does not satisfy (i) or (ii), and therefore does not contribute to controlling the flow of the main current. Therefore, the structure within the D trench 10 does not contribute to controlling the flow of the main current.

[0022] As described above, the barrier structure 10c includes the A lower electrode 12 and the insulating film 42. The insulating film 42 is provided in a portion between the D upper electrode 11a and the A upper electrode 11b, and insulates the D upper electrode 11a from the A upper electrode 11b. In the first embodiment, the A lower electrode 12 of the barrier structure 10c is provided up to the top of the D trench 10, and the height of the top of the A lower electrode 12 of the barrier structure 10c is the same as the height of the tops of the D upper electrode 11a and the A upper electrode 11b. The portion of the A lower electrode 12 that is provided up to the top of the D trench 10 is insulated from the D upper electrode 11a and the A upper electrode 11b by the insulating film 42.

[0023] <Aトレンチ20> As shown in FIGS. 1 and 3, the A trench 20 includes a second A trench gate structure 20a.

[0024] 3, the second A trench gate structure 20a, which is an AA structure, includes an A lower electrode 22 which is an electrode having an active function, an A upper electrode 21 which is also an electrode having an active function, and an insulating film 42. That is, in the first embodiment, the second lower electrode is the A lower electrode 22, and the second upper electrode is the A upper electrode 21. The A upper electrode 21 is insulated from the A lower electrode 22 by the insulating film 42 and is provided above the A lower electrode 22.

[0025] The second A trench gate structure 20a satisfies the above (i) to (iii), and therefore contributes to controlling the flow of the main current. Therefore, at least a part of the structure in the A trench 20 functions as the gate of at least one of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), and an RC-IGBT (Reverse Conducting IGBT). In this specification, for example, "at least one of A, B, C, ..., and Z" means any one of all combinations of one or more types selected from the group A, B, C, ..., and Z.

[0026] <Sトレンチ30> As shown in FIGS. 1 and 4, the S-trench 30 includes a third A trench gate structure 30a.

[0027] 4, the third A trench gate structure 30a, which is an AA structure, includes an A lower electrode 32 which is an electrode having an active function, an A upper electrode 31 which is also an electrode having an active function, and an insulating film 42. That is, in the first embodiment, the third lower electrode is the A lower electrode 32, and the third upper electrode is the A upper electrode 31. The A upper electrode 31 is insulated from the A lower electrode 32 by the insulating film 42 and is provided above the A lower electrode 32.

[0028] The A bottom electrode 32 electrically connects the A bottom electrode 12 of the first A trench gate structure 10b to the A bottom electrode 22 of the second A trench gate structure 20a. The A top electrode 31 electrically connects the A top electrode 11b of the first A trench gate structure 10b to the A top electrode 21 of the second A trench gate structure 20a. That is, the electrode in the D trench 10 and the electrode in the A trench 20 are electrically connected by the electrode in the S trench 30. Note that the structure in the S trench 30 may or may not contribute to controlling the flow of the main current.

[0029] <Summary of the First Embodiment> In the first embodiment, the insulating film 42 of the barrier structure 10c is provided in a portion between the D upper electrode 11a and the A upper electrode 11b, and insulates the D upper electrode 11a from the A upper electrode 11b. With this configuration, the A upper electrode 11b, which is electrically isolated from the D upper electrode 11a by the barrier structure 10c, can be electrically connected to the A upper electrode 31 in the S trench 30. This makes it possible to set the A upper electrode 11b to the gate potential of the gate electrode while appropriately maintaining the potentials of the A upper electrode 11b and the D upper electrode 11a by avoiding an electrical short circuit between the A upper electrode 11b and the D upper electrode 11a.

[0030] According to this configuration, the potential of the A upper electrode 11b in the D-trench 10 can be controlled by the barrier structure 10c provided in the D-trench 10 and the third A-trench gate structure 30a of the S-trench 30. This means that even if a break occurs inside a specific trench, electrical connection can be maintained by other trenches, thereby improving reliability or design freedom (freedom of gate wiring arrangement).

[0031] <Modification> In the first embodiment, the first lower electrode, the second lower electrode, the third lower electrode, the 1-2 upper electrode, the second upper electrode, and the third upper electrode were respectively the A lower electrode 12, the A lower electrode 22, the A lower electrode 32, the A upper electrode 11b, the A upper electrode 21, and the A upper electrode 31, which were electrically connected to the gate electrode. The 1-1 upper electrode was the D upper electrode 11a, which was electrically connected to the dummy electrode.

[0032] However, the connections between the gate electrode and the dummy electrode may be reversed. That is, the first lower electrode, the second lower electrode, the third lower electrode, the first-2 upper electrode, the second upper electrode, and the third upper electrode may be electrodes having a dummy function electrically connected to the emitter electrode. The first-1 upper electrode may be an electrode having an active function electrically connected to the gate electrode.

[0033] <Embodiment 2> Fig. 5 is a plan view showing the configuration of a semiconductor device according to the second embodiment. Fig. 6 is a cross-sectional view taken along line D-D' in Fig. 5, and Fig. 7 is a cross-sectional view taken along line E-E' in Fig. 5. The cross-sectional view taken along line C-C' in Fig. 5 is the same as Fig. 4 except that the emitter electrode 40 is not provided on the insulating film 42.

[0034] As shown in FIGS. 5 to 7, in the second embodiment, in addition to the configuration described in the first embodiment, a lower pull-up structure 10d is provided in the D-trench 10, and a lower pull-up structure 20b is provided in the A-trench 20.

[0035] 6, in the lower pull-up structure 10d, the A lower electrode 12 is provided up to the top of the D trench 10 and is connected to the gate electrode 41 via a contact region 71. Then, as shown in FIGS. 5 and 6, the lower pull-up structure 10d, the first A trench gate structure 10b, the barrier structure 10c, and the D trench gate structure 10a are arranged in this order in the first direction.

[0036] 7, in the lower pull-up structure 20b, the A lower electrode 22 is provided up to the top of the A trench 20 and is electrically connected to the gate electrode 41 via a contact region 72. The A upper electrode 21 is connected to the gate electrode 41 via a contact region 73. As shown in FIGS. 5 and 7, the lower pull-up structure 20b and the second A trench gate structure 20a are arranged in the first direction.

[0037] According to the semiconductor device of the second embodiment as described above, in the lower pull-up structure 10d, the A lower electrode 12 is provided up to the upper part of the D trench 10 and can be connected to the gate electrode 41 via the contact region 71. With this configuration, even if the A lower electrode 22 of the A trench 20 is not electrically connected to the gate electrode 41 via the contact region 72 for some reason, the A lower electrode 12 of the D trench 10 can be electrically connected to the gate electrode 41 via the A lower electrode 12 of the D trench 10.

[0038] <Third Embodiment> Fig. 8 is a plan view showing the configuration of a semiconductor device according to the third embodiment. Fig. 9 is a cross-sectional view taken along line FF' in Fig. 8, and Fig. 10 is a cross-sectional view taken along line GG' in Fig. 8.

[0039] 9, in the third embodiment, the portion of the A lower electrode 12 of the barrier structure 10c that protrudes to the top of the D trench 10 is electrically connected to the gate electrode 41 via the contact region 74. That is, the A lower electrode 12 of the barrier structure 10c is provided to penetrate the insulating film 42 to the top of the D trench 10 and is electrically connected to the gate electrode 41.

[0040] According to this configuration, even if, for some reason, the A lower electrode 22 of the A trench 20 is not electrically connected to the gate electrode 41 via the contact region 72, it can be electrically connected to the gate electrode 41 via the barrier structure 10c. In the third embodiment, the A lower electrode 12 of the barrier structure 10c is electrically connected to the gate electrode 41, but in the above-described modified example, the A lower electrode 12 of the barrier structure 10c may be electrically connected to a dummy electrode.

[0041] <Fourth Embodiment> Fig. 11 is a schematic plan view showing the configuration of a semiconductor device according to the fourth embodiment. Fig. 12 is a plan view of a portion enclosed by a dotted square in Fig. 11, and Fig. 13 is a cross-sectional view taken along line HH' in Fig. 12.

[0042] 11, the semiconductor device according to the fourth embodiment is an RC-IGBT, in which an IGBT region 80 having an IGBT function and two or more island-type diode regions 90 having a diode function are provided on one semiconductor substrate 1. The IGBT region 80 is provided between the two diode regions 90. The diode includes at least one of an SBD (Schottky Barrier Diode) and a PND (PN junction diode).

[0043] 11 and 12, the IGBT region 80 includes the same components as those described in the first embodiment. As shown in FIGS. 11 to 13, one diode region 90, one first-A trench gate structure 10b, one barrier structure 10c, a D trench gate structure 10a, another barrier structure 10c, another first-A trench gate structure 10b, and another diode region 90 are arranged in this order in the first direction. With this configuration, the potentials of the D trenches 10 and the A trenches 20 can be appropriately maintained between the island-type diode regions 90 of the RC-IGBT.

[0044] In the examples of Figures 12 and 13, the D upper electrode 11a is electrically connected to the emitter electrode 40 via two contact regions 70, but it may also be electrically connected to the emitter electrode 40 via one or three or more contact regions 70.

[0045] <Fifth Embodiment> 14 is a cross-sectional view showing the configuration of a semiconductor device according to the fifth embodiment, and corresponds to the cross-sectional view of FIG. 2. In the fifth embodiment, the insulating film 42 of the barrier structure 10c is provided over the entire area between the D upper electrode 11a and the A upper electrode 11b. This configuration can improve the insulation reliability of the semiconductor device between the D upper electrode 11a and the A upper electrode 11b.

[0046] <Sixth Embodiment> 15 is a cross-sectional view showing the configuration of a semiconductor device according to the sixth embodiment, corresponding to the cross-sectional view of FIG. 2. In the sixth embodiment, at least one of the portions of the insulating film 42 of the barrier structure 10c that contact the sides and bottom of the D upper electrode 11a and the portions that contact the sides and bottom of the A upper electrode 11b is rounded in cross section. This configuration can prevent an electric field from being locally applied to the insulating film 42, thereby improving the insulation reliability of the semiconductor device.

[0047] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more' and 'at least one' can be used interchangeably.

[0048] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0049] Various aspects of the present disclosure are summarized below as appendices.

[0050] (Appendix 1) a semiconductor substrate provided with a first trench extending in a first direction, a second trench extending in the first direction along the first trench, and a third trench extending in a second direction different from the first direction and connected to the first trench and the second trench; a first trench gate structure and a second trench gate structure provided in the first trench; a barrier structure provided in the first trench and between the 1-1 trench gate structure and the 1-2 trench gate structure; a second trench gate structure disposed within the second trench; a third trench gate structure provided in the third trench and connected to the first and second trench gate structures and the second trench gate structure; Equipped with The 1-1 trench gate structure includes: a first lower electrode; a first upper electrode insulated from the first lower electrode and provided above the first lower electrode; Including, The first and second trench gate structures are the first lower electrode; a first-second upper electrode insulated from the first lower electrode and provided above the first lower electrode; Including, The barrier structure is the first lower electrode; an insulating film provided at least partially between the first upper electrode and the first upper electrode, insulating the first upper electrode and the first upper electrode; Including, The second trench gate structure includes: A second lower electrode; a second upper electrode insulated from the second lower electrode and provided above the second lower electrode; Including, The third trench gate structure includes: a third lower electrode electrically connecting the first lower electrode and the second lower electrode; a third upper electrode electrically connecting the first-second upper electrode and the second upper electrode, and insulated from the third lower electrode and provided above the third lower electrode; Including, the first lower electrode, the second lower electrode, the third lower electrode, the first-second upper electrode, the second upper electrode, and the third upper electrode are electrically connected to one of a gate electrode and a dummy electrode; the 1-1 upper electrode is electrically connected to the other of the gate electrode and the dummy electrode.

[0051] (Appendix 2) 10. The semiconductor device according to claim 1, a lower pull-up structure provided in the first trench, the first lower electrode being provided up to an upper portion of the first trench; The semiconductor device, wherein the lower pull-up structure, the 1-2 trench gate structure, the barrier structure, and the 1-1 trench gate structure are arranged in this order in the first direction.

[0052] (Appendix 3) The semiconductor device according to claim 1 or 2, the first lower electrode of the barrier structure is provided to penetrate the insulating film to an upper portion of the first trench and is electrically connected to one of the gate electrode and the dummy electrode.

[0053] (Appendix 4) 2. The semiconductor device according to claim 1, a diode region provided in the semiconductor substrate; a semiconductor device in which one of the diode regions, one of the first-second trench gate structures, one of the barrier structures, the first-first trench gate structure, another of the barrier structures, another of the first-second trench gate structures, and another of the diode regions are arranged in this order in the first direction.

[0054] (Appendix 5) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 4, a first insulating film of the barrier structure provided over the entire area between the first upper electrode and the second upper electrode;

[0055] (Appendix 6) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 5, A semiconductor device in which at least one of the insulating film of the barrier structure, a portion that contacts the side and bottom of the 1-1 upper electrode, and a portion that contacts the side and bottom of the 1-2 upper electrode, has a rounded shape in a cross-sectional view. [Explanation of symbols]

[0056] 1 semiconductor substrate, 10 D trench, 10a D trench gate structure, 10b 1st A trench gate structure, 10c barrier structure, 10d lower pull-up structure, 11a D upper electrode, 11b A upper electrode, 12 D lower electrode, 20 A trench, 20a 2nd A trench gate structure, 21 A upper electrode, 22 A lower electrode, 30 S trench, 30a 3rd A trench gate structure, 31 A upper electrode, 32 A lower electrode, 40 emitter electrode, 41 gate electrode, 42 insulating film, 90 diode region.

Claims

1. a semiconductor substrate provided with a first trench extending in a first direction, a second trench extending in the first direction along the first trench, and a third trench extending in a second direction different from the first direction and connected to the first trench and the second trench; a first-1 trench gate structure and a first-2 trench gate structure provided in the first trench; a barrier structure provided in the first trench and between the first-1 trench gate structure and the first-2 trench gate structure; a second trench gate structure disposed within the second trench; a third trench gate structure provided in the third trench and connected to the first and second trench gate structures and the second trench gate structure; Equipped with The 1-1 trench gate structure includes: a first lower electrode; a first-1 upper electrode insulated from the first lower electrode and provided above the first lower electrode; Including, The first and second trench gate structures include: the first lower electrode; a first-second upper electrode insulated from the first lower electrode and provided above the first lower electrode; Including, The barrier structure is the first lower electrode; an insulating film provided at least partially between the first-first upper electrode and the first-second upper electrode, insulating the first-first upper electrode and the first-second upper electrode; Including, The second trench gate structure includes: A second lower electrode; a second upper electrode insulated from the second lower electrode and provided above the second lower electrode; Including, The third trench gate structure includes: a third lower electrode electrically connecting the first lower electrode and the second lower electrode; a third upper electrode electrically connecting the first-second upper electrode and the second upper electrode, and insulated from the third lower electrode and provided above the third lower electrode; Including, the first lower electrode, the second lower electrode, the third lower electrode, the first-second upper electrode, the second upper electrode, and the third upper electrode are electrically connected to one of a gate electrode and a dummy electrode; The first-1 upper electrode is electrically connected to the other of the gate electrode and the dummy electrode.

2. 2. The semiconductor device according to claim 1, a lower pull-up structure provided in the first trench, the first lower electrode being provided up to an upper portion of the first trench; the lower pull-up structure, the first-second trench gate structure, the barrier structure, and the first-first trench gate structure are arranged in this order in the first direction.

3. 3. The semiconductor device according to claim 1, the first lower electrode of the barrier structure is provided to penetrate the insulating film to an upper portion of the first trench and is electrically connected to one of the gate electrode and the dummy electrode.

4. 2. The semiconductor device according to claim 1, a diode region provided in the semiconductor substrate; one of the diode regions, one of the first-second trench gate structures, one of the barrier structures, the first-first trench gate structure, another of the barrier structures, another of the first-second trench gate structures, and another of the diode regions are arranged in this order in the first direction.

5. 3. The semiconductor device according to claim 1, the insulating film of the barrier structure is provided over the entire area between the first-first upper electrode and the first-second upper electrode.

6. 3. The semiconductor device according to claim 1, a semiconductor device in which at least one of a portion of the insulating film of the barrier structure that contacts the side and lower portion of the 1-1 upper electrode and a portion that contacts the side and lower portion of the 1-2 upper electrode has a rounded shape in a cross-sectional view;

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