Over-current protection circuit, semiconductor chip, and power source device

Abstract

To confirm over-current protection operation not depending on the variation in manufacture, temperature conditions, or the like.SOLUTION: An over-current protection circuit 10 includes a detection resistor R10 connected between a first terminal VIN and a second terminal VOUT, a detection transistor M11 connected in series to the detection resistor R10 between the first terminal VIN and the second terminal VOUT and applying a driving signal G10 of an output transistor M10 to a control electrode, an amplifier A1 connected between the first terminal VIN and an application end of the driving signal G10 and outputting a differential signal V11 between a detection voltage Vs appearing between opposite ends of the detection resistor R10 and a predetermined upper-limit voltage Vocp, a first output circuit 11 that is connected between the first terminal VIN and the application end of the driving signal G10 and restricts the driving signal G10 in accordance with the differential signal V11, and a second output circuit 12 that outputs a detection signal I12 upon the reception of the input of the differential signal V11.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to an overcurrent protection circuit, a semiconductor chip, and a power supply device. [Background technology]

[0002] Overcurrent protection circuits that limit monitored currents to a predetermined upper limit or less are used in a variety of applications.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-115646

[0005] [overview] In conventional overcurrent protection circuits, it is sometimes difficult to confirm the overcurrent protection operation due to manufacturing variations, temperature conditions, and the like.

[0006] The overcurrent protection circuit according to the present disclosure comprises a detection resistor connected between a first terminal and a second terminal; a detection transistor connected in series with the detection resistor between the first terminal and the second terminal and configured to apply a drive signal for an output transistor to a control electrode; an amplifier connected between the first terminal or the second terminal and an application terminal of the drive signal and configured to output a differential signal between a detection voltage appearing across the detection resistor and a predetermined upper limit voltage; a first output circuit connected between the first terminal or the second terminal and the application terminal of the drive signal and configured to limit the drive signal in accordance with the differential signal; and a second output circuit configured to receive an input of the differential signal and output a detection signal. [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 1 is a diagram showing a comparative example of a power supply device. [Figure 2] FIG. 2 is a diagram showing the output current or test current and the output voltage in the comparative example. [Figure 3] FIG. 3 is a diagram showing a first embodiment of the power supply device. [Figure 4] FIG. 4 is a diagram showing the test current and the detection signal in the first embodiment. [Figure 5] FIG. 5 is a diagram showing a second embodiment of the power supply device. [Figure 6] FIG. 6 is a diagram showing a third embodiment of the power supply device. [Figure 7] FIG. 7 is a diagram showing a test current and a detection signal in the third embodiment. [Figure 8] FIG. 8 is a diagram showing a fourth embodiment of the power supply device. [Figure 9] FIG. 9 is a diagram showing a fifth embodiment of the power supply device. [Figure 10] FIG. 10 is a diagram showing a sixth embodiment of the power supply device. [Figure 11] FIG. 11 is a diagram showing a seventh embodiment of the power supply device.

[0008] [Detailed explanation] <Comparative Example> 1 is a diagram showing a comparative example (i.e., a configuration to be compared with the embodiments described below) of a power supply device 1. The power supply device 1 of this comparative example is a linear power supply (e.g., an LDO [low drop out] regulator) that generates a desired output voltage Vout from an input voltage Vin.

[0009] Referring to the figure, the power supply device 1 includes an output transistor M10, an overcurrent protection circuit 10, an error amplifier 20, a feedback voltage generation circuit 30, and a reference voltage generation circuit 40. Some or all of these components may be integrated into a semiconductor chip SC. The semiconductor chip SC is resin-sealed together with a lead frame (not shown) as a part of a semiconductor device (a so-called power supply control IC [integrated circuit]).

[0010] The semiconductor chip SC includes an input terminal VIN, an output terminal VOUT, a feedback terminal VSNS, a ground terminal GND, and a test input terminal EOCP as means for establishing electrical connections with the outside of the chip. The above terminals may be mounted on the semiconductor chip SC as pads.

[0011] The input terminal VIN is connected to the application terminal of the input voltage Vin. The output terminal VOUT is connected to the application terminal of the output voltage Vout. The feedback terminal VSNS is connected to the application terminal of the output voltage Vout. For example, the output terminal VOUT and the feedback terminal VSNS may be bonded to a common lead frame. A smoothing and phase compensation capacitor Co may be externally connected between the output terminal VOUT and the ground terminal. The ground terminal GND is connected to the ground terminal. The test input terminal EOCP is a terminal for passing a test current Ie through a detection resistor R10 (described later) in the EDS (electric die sorting) process of the semiconductor chip SC. The test input terminal EOCP may also be a non-connect terminal that is not bonded to any lead frame.

[0012] The output transistor M10 is connected between the input terminal VIN and the output terminal VOUT. The output transistor M10 may be a P-channel type. When the output transistor M10 is a PMOSFET (P-channel type metal oxide semiconductor field effect transistor), the source of the output transistor M10 is connected to the input terminal VIN. The drain of the output transistor M10 is connected to the output terminal VOUT. The gate of the output transistor M10 is connected to an application terminal of a drive signal G10. The lower the drive signal G10, the greater the conductivity of the output transistor M10, and the higher the drive signal G10, the smaller the conductivity.

[0013] The overcurrent protection circuit 10 performs an overcurrent protection operation by monitoring the output current Iout flowing through the output transistor M10 (details will be described later).

[0014] The error amplifier 20 generates a drive signal G10 for the output transistor M10 so that the feedback voltage Vfb input to its non-inverting input terminal (+) matches the reference voltage Vref input to its inverting input terminal (-). The drive signal G10 decreases when the feedback voltage Vfb is lower than the reference voltage Vref. This increases the conductivity of the output transistor M10, resulting in an increase in the output current Iout. On the other hand, the drive signal G10 increases when the feedback voltage Vfb is higher than the reference voltage Vref. This decreases the conductivity of the output transistor M10, resulting in a decrease in the output current Iout.

[0015] The feedback voltage generation circuit 30 includes resistors 31 and 32 connected in series between the feedback terminal VSNS and the ground terminal GND. The feedback voltage generation circuit 30 divides the voltage applied to the feedback terminal VSNS (the output voltage Vout in this figure) to generate a feedback voltage Vfb. Note that the feedback voltage generation circuit 30 may be omitted, and the output voltage Vout may be directly input to the non-inverting input terminal (+) of the error amplifier 20.

[0016] The reference voltage generating circuit 40 generates a predetermined reference voltage Vref from the input voltage Vin and outputs it to the inverting input terminal (−) of the error amplifier 20.

[0017] <Overcurrent protection circuit> Continuing with reference to Figure 1, the overcurrent protection circuit 10 will be described in detail. The overcurrent protection circuit 10 of this comparative example includes an amplifier A1, a detection transistor M11 (e.g., a PMOSFET), a transistor M12 (e.g., a PMOSFET), a transistor M13 (e.g., an NMOSFET), a detection resistor R10, and a resistor R11.

[0018] A first end of the detection resistor R10 is connected to the input terminal VIN (= the source of the output transistor M10). Meanwhile, a second end of the detection resistor R10 is connected to the source of the detection transistor M11 and the test input terminal EOCP. A current mirror or the like may be interposed between the second end of the detection resistor R10 and the test input terminal EOCP. A drain of the detection transistor M11 is connected to the output terminal VOUT (= the drain of the output transistor M10). A gate of the detection transistor M11 is connected to the gate of the output transistor M10 (= the application terminal of the drive signal G10). In this way, the detection resistor R10 is connected between the input terminal VIN and the output terminal VOUT. Furthermore, the detection transistor M11 is connected in series with the detection resistor R10 between the input terminal VIN and the output terminal VOUT. The drive signal G10 for the output transistor M10 is applied to the gate of the detection transistor M11.

[0019] The on-resistance (conductivity) of the detection transistor M11 connected in this manner is controlled in the same manner as the on-resistance (conductivity) of the output transistor M10. Therefore, a detection signal Is (=Iout / m, where m>1) proportional to the output current Iout flows through the detection transistor M11. The detection signal Is flows through a current path from the input terminal VIN to the output terminal VOUT via the detection resistor R10 and the detection transistor M11. Therefore, a detection voltage Vs (=Is×R10) corresponding to the detection signal Is appears across the detection resistor R10.

[0020] The upper power supply terminal of the amplifier A1 is connected to the input terminal VIN. Meanwhile, the lower power supply terminal of the amplifier A1 is connected to the terminal to which the drive signal G10 is applied. A voltage (=Vin-Vocp) obtained by subtracting a predetermined upper limit voltage Vocp from the input voltage Vin is applied to the inverting input terminal (-) of the amplifier A1. A voltage (=Vin-Vs) obtained by subtracting a detection voltage Vs from the input voltage Vin is applied to the non-inverting input terminal (+) of the amplifier A1. The amplifier A1 connected in this manner outputs a difference signal V11 between the detection voltage Vs and the upper limit voltage Vocp.

[0021] The source of the transistor M12 and the drain of the transistor M13 are all connected to the input terminal VIN. The drain of the transistor M12, the gate of the transistor M13, and a first end of the resistor R11 are all connected to an application terminal of the voltage signal V12. The source of the transistor M13 and a second end of the resistor R11 are all connected to an application terminal of the drive signal G10. The gate of the transistor M12 is connected to an application terminal of the differential signal V11. The transistors M12 and M13 and the resistor R11 connected in this manner form a first output circuit 11 that limits the drive signal G10 in response to the differential signal V11.

[0022] When the detection voltage Vs is lower than the upper limit voltage Vocp, the differential signal V11 output from amplifier A1 is stuck at a high level (≒ Vin). Therefore, transistor M12 is fully off, and the voltage signal V12 becomes approximately equal to the drive signal G10. As a result, transistor M13 is fully off, and the gate-source of output transistor M10 is open. Therefore, the on-resistance of output transistor M10 is not increased, and no restrictions are placed on the output current Iout flowing through output transistor M10 (i.e., overcurrent protection is deactivated).

[0023] On the other hand, if the output current Iout increases due to an output abnormality or the like, and the detection voltage Vs becomes higher than the upper limit voltage Vocp, the differential signal V11 output from the amplifier A1 according to the difference between the two voltages drops from high level, and the transistor M12 turns on, causing the voltage signal V12 to rise from low level (≒G10).

[0024] At this time, a drive current I11 (equivalent to an overcurrent protection signal) flows between the gate and source of the output transistor M10 via the transistor M13. Therefore, when the drive signal G10 rises, the voltage between the gate and source of the output transistor M10 is pulled down. As a result, the on-resistance of the output transistor M10 increases, and the output current Iout is restricted (= the overcurrent protection operation is activated). Finally, the drive current I11 reaches equilibrium in a state where the detected voltage Vs and the upper limit voltage Vocp are in an imaginary short circuit state.

[0025] In a configuration including such an overcurrent protection circuit 10, even in a situation where an excessive output current Iout can flow through the output transistor M10, the output current Iout can be restricted. Therefore, the power supply device 1 and its peripheral circuits (including the load) can be protected.

[0026] In the overcurrent protection circuit 10 of this comparative example, both the amplifier A1 and the first output circuit 11 are connected between the input terminal VIN and the application terminal of the drive signal G10. With this configuration, the drive current I11 of the overcurrent protection circuit 10 flows from the input terminal VIN to the application terminal of the drive signal G10. Therefore, there is an effect that it does not lead to an increase in the current consumption of the semiconductor chip SC (and thus the power control IC).

[0027] <Consideration Regarding the EDS Process> Incidentally, in the EDS process of the semiconductor chip SC, the operation of the overcurrent protection circuit 10 may be confirmed to select the semiconductor chip SC in the wafer state as either a good product or a defective product. In this case, it is difficult to pass an excessive output current Iout through the output terminal VOUT. Therefore, a test current Ie is drawn from the test input terminal EOCP. At this time, a detected voltage Vs (= (Is + Ie) × R10) corresponding to the test current Ie appears between both ends of the detection resistor R10. When Is ≒ 0, Vs ≒ Ie × R10.

[0028] In this way, by passing the test current Ie through the detection resistor R10, it is possible to activate the same overcurrent protection operation as the original without passing an excessively large output current Iout. Therefore, to check whether the overcurrent protection circuit 10 is operating correctly, a substitute measurement is performed to determine whether the output voltage Vout is shut down when the test current Ie is passed.

[0029] However, in the power supply device 1 of this comparative example, the overcurrent protection circuit 10 is connected between the input terminal VIN and the application terminal of the drive signal G10, which may cause problems in checking the operation of the overcurrent protection circuit 10 in the EDS process.

[0030] FIG. 2 is a diagram showing the relationship between the output current Iout (or test current Ie) and the output voltage Vout in the power supply device 1 of this comparative example.

[0031] In actual applications, when an excessive output current Iout flows through the output transistor M10, the gate-source voltage (=Vin-G10) of the output transistor M10 becomes high, ensuring a sufficient operating voltage for the overcurrent protection circuit 10. Therefore, when the output current Iout becomes excessive, the output voltage Vout is shut down (see the solid line).

[0032] On the other hand, in the EDS process, an excessive output current Iout does not actually flow through the output transistor M10. Therefore, the gate-source voltage of the output transistor M10 does not rise significantly, and the operating voltage of the overcurrent protection circuit 10 is not sufficiently ensured. Therefore, even if the test current Ie is passed through the detection resistor R10 to simulate the operation of the overcurrent protection circuit 10, the current capacity of the transistor M13 may be insufficient, and the output transistor M10 may not be reliably turned off. In other words, depending on manufacturing variations and temperature conditions, the output voltage Vout may not be shut down, making it difficult to confirm the overcurrent protection operation (see the dashed line).

[0033] In view of the above considerations, a novel embodiment is proposed below that allows confirmation of overcurrent protection operation regardless of manufacturing variations, temperature conditions, and the like.

[0034] First Embodiment Fig. 3 is a diagram showing a first embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the comparative example (Fig. 1) described above, with modifications made to the overcurrent protection circuit 10. Referring to this diagram, the overcurrent protection circuit 10 further includes a second output circuit 12 in addition to the components described above.

[0035] The second output circuit 12 receives the differential signal V11 as an input and outputs the detection signal I12. Referring to the figure, the second output circuit 12 includes a transistor M14 (e.g., a PMOSFET), a transistor M15 (e.g., an NMOSFET), and resistors R12 and R13.

[0036] The source of the transistor M14 is connected to the input terminal VIN. The gate of the transistor M14 is connected to the application terminal of the differential signal V11. The drain of the transistor M14, the gate of the transistor M15, and a first terminal of the resistor R12 are all connected to the application terminal of the voltage signal V13. The source of the transistor M15 and a second terminal of the resistor R12 are all connected to the ground terminal GND. The drain of the transistor M15 is connected to a first terminal of the resistor R13. The second terminal of the resistor R13 is connected to the feedback terminal VSNS. The resistor R13 functions as a current limiting resistor that limits the current that flows as the detection signal I12. However, the resistor R13 may be omitted.

[0037] In the EDS process of the semiconductor chip SC, as described above, the test current Ie is extracted from the test input terminal EOCP, causing the differential signal V11 to drop from high level (≈Vin). Therefore, the transistor M14 is turned on, causing the voltage signal V13 to rise from low level (≈GND). At this time, the detection signal I12 flows between the feedback terminal VSNS and the ground terminal GND via the resistor R13 and the transistor M15. That is, in the power supply device 1 of this embodiment, the feedback terminal VSNS is also used as the output terminal for the detection signal I12. This eliminates the need to add unnecessary terminals to the semiconductor chip SC.

[0038] In the EDS process for the semiconductor chip SC, the feedback terminal VSNS may be disconnected from the output terminal VOUT as shown in the figure. Also, a voltage lower than the target value of the output voltage Vout (={(R31+R32) / R32}×Vref, where R31 and R32 are the resistance values ​​of the resistors 31 and 32, respectively) may be applied to the feedback terminal VSNS.

[0039] The transistor M14 is driven by the amplifier A1. Therefore, if the operating voltage (=Vin-G10) of the overcurrent protection circuit 10 is not sufficiently secured, the transistor M14 will not be fully on. However, if the voltage signal V13 is higher than the on-threshold voltage of the transistor M15, the detection signal I12 can be output sufficiently. Therefore, the transistor M14 is not required to have a particularly large current capacity.

[0040] The second output circuit 12 also operates when the output current Iout is in an overcurrent state in an actual application. However, no particular problem occurs even if the current flowing into the feedback terminal VSNS increases slightly when the output current Iout is in an overcurrent state.

[0041] 4 is a diagram showing the relationship between the test current Ie and the detection signal I12 in the power supply device 1 of the first embodiment. As shown in this diagram, the second output circuit 12 outputs the detection signal I12 from the feedback terminal VSS when the overcurrent protection circuit 10 operates. That is, the detection signal I12 increases when the overcurrent protection circuit 10 operates due to the application of the test current Ie.

[0042] Therefore, by measuring whether the detection signal I12 flows when a predetermined test current Ie is passed, it is possible to confirm whether the overcurrent protection circuit 10 is operating correctly. In other words, it does not matter whether the output voltage Vout is actually shut down. Therefore, the overcurrent protection operation can be confirmed regardless of manufacturing variations, temperature conditions, etc. Increasing the stability of the operation confirmation also leads to improved yields of the semiconductor chips SC.

[0043] Second Embodiment 5 is a diagram showing a second embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the first embodiment (FIG. 3) described above, but has a first output circuit 11 with some modifications.

[0044] Referring to this figure, the first output circuit 11 does not include the transistor M13 and resistor R11. That is, the drain of the transistor M12 is directly connected to the node to which the drive signal G10 is applied. Therefore, during overcurrent protection operation, the drive current I11 (corresponding to the overcurrent protection signal) flows through the transistor M12, thereby raising the drive signal G10. Thus, when the second output circuit 12 is introduced, the configuration of the first output circuit 11 is not limited to that of the first embodiment (FIG. 3).

[0045] <Third embodiment> 6 is a diagram showing a third embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the first embodiment (FIG. 3) described above, but has a modification to the second output circuit 12.

[0046] Referring to this figure, the second output circuit 12 includes a Schmitt trigger HYS between the application terminal of the voltage signal V13 and the gate of the transistor M15. The Schmitt trigger HYS has hysteresis in the input threshold value.

[0047] FIG. 7 is a diagram showing the relationship between the test current Ie and the detection signal I12 in the power supply device 1 of the third embodiment.

[0048] For example, when the voltage signal V13 exceeds the upper threshold value VthH, the Schmitt trigger HYS raises the gate signal of the transistor M15 from the low level to the high level. That is, the detection signal I12 flows when the test current Ie exceeds a predetermined upper threshold value IeH.

[0049] On the other hand, when the voltage signal V13 falls below the lower threshold value VthL (<VthH), the Schmitt trigger HYS lowers the gate signal of the transistor M15 from the high level to the low level. That is, the detection signal I12 stops flowing when the test current Ie falls below a predetermined lower threshold value IeL (<IeH).

[0050] With this configuration, chattering of the detection signal I12 due to the influence of external disturbances or the like can be prevented. Therefore, it becomes possible to more stably confirm the operation of the overcurrent protection circuit 10.

[0051] <Fourth Embodiment> FIG. 8 is a diagram showing a fourth embodiment of the power supply device 1. The power supply device 1 of this embodiment further includes a test output terminal VMON for outputting the detection signal I12 while being based on the above-described first embodiment (FIG. 3).

[0052] The test output terminal VMON may be a dedicated terminal for outputting the detection signal I12. Further, the test output terminal VMON may be a terminal that can be used as an output terminal of the detection signal I12 among a plurality of terminals provided on the semiconductor chip SC and that does not cause any trouble in operation even when diverted. Thus, the second output circuit 12 may be connected in addition to the feedback terminal VSNS.

[0053] The test output terminal VMON may be pulled up. In this case, it is possible to check whether the overcurrent protection circuit 10 is operating correctly by measuring whether the terminal voltage of the test output terminal VMON is below a predetermined threshold voltage when a predetermined test current Ie is passed through it.

[0054] Fifth Embodiment 9 is a diagram showing a fifth embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the fourth embodiment (FIG. 8) described above, with a modification made to the second output circuit 12.

[0055] Referring to this figure, the second output circuit 12 does not include the transistor M15 and resistors R12 and R13. That is, the drain of the transistor M14 is directly connected to the test output terminal VMON. Therefore, the detection signal I12 flows from the input terminal VIN to the test output terminal VMON via the transistor M14.

[0056] In this way, the detection signal I12 may be output from the semiconductor chip SC, unlike the first to fourth embodiments (FIGS. 3, 5, 6, and 8).

[0057] Sixth Embodiment Figure 10 is a diagram showing a sixth embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the first embodiment (Figure 3) described above, but includes an N-channel output transistor M20 instead of the P-channel output transistor M10. When the output transistor M20 is an NMOSFET (N-channel type MOSFET), the drain of the output transistor M20 is connected to the input terminal VIN. The source of the output transistor M20 is connected to the output terminal VOUT.

[0058] Furthermore, due to the above changes, the input polarity of the error amplifier 20 is reversed from that described above. That is, the non-inverting input terminal (+) of the error amplifier 20 is connected to the terminal to which the reference voltage Vref is applied. The inverting input terminal (-) of the error amplifier 20 is connected to the terminal to which the feedback voltage Vfb is applied. The error amplifier 20 generates a drive signal G20 so that the feedback voltage Vfb and the reference voltage Vref coincide with each other.

[0059] Furthermore, in accordance with the above changes, there has also been a change in the circuit configuration of the overcurrent protection circuit 10. Referring to this figure, the overcurrent protection circuit 10 includes an amplifier A2, a detection transistor M21 (e.g., an NMOSFET), a transistor M22 (e.g., an NMOSFET), a transistor M23 (e.g., a PMOSFET), a detection resistor R20, and a resistor R21.

[0060] A first end of the detection resistor R20 is connected to the output terminal VOUT (= the source of the output transistor M20). Meanwhile, a second end of the detection resistor R20 is connected to the source of the detection transistor M21 and the test input terminal EOCP. A current mirror or the like may be interposed between the second end of the detection resistor R20 and the test input terminal EOCP. A drain of the detection transistor M21 is connected to the input terminal VIN (= the drain of the output transistor M20). A gate of the detection transistor M21 is connected to the gate of the output transistor M20 (= the application terminal of the drive signal G20). In this way, the detection resistor R20 is connected between the input terminal VIN and the output terminal VOUT. Furthermore, the detection transistor M21 is connected in series with the detection resistor R20 between the input terminal VIN and the output terminal VOUT. The drive signal G20 for the output transistor M20 is applied to the gate of the detection transistor M21.

[0061] The on-resistance (conductivity) of the detection transistor M21 connected in this manner is controlled in the same manner as the on-resistance (conductivity) of the output transistor M20. Therefore, a detection signal Is (=Iout / m, where m>1) proportional to the output current Iout flows through the detection transistor M21. The detection signal Is flows through a current path from the input terminal VIN to the output terminal VOUT via the detection transistor M21 and detection resistor R20. Therefore, a detection voltage Vs (=Is×R20) corresponding to the detection signal Is appears across the detection resistor R20.

[0062] The upper power supply terminal of the amplifier A2 is connected to the terminal to which the drive signal G10 is applied. Meanwhile, the lower power supply terminal of the amplifier A2 is connected to the output terminal VOUT. A voltage (=Vout+Vocp) obtained by adding a predetermined upper limit voltage Vocp to the output voltage Vout is applied to the inverting input terminal (-) of the amplifier A2. A voltage (=Vout+Vs) obtained by adding a detection voltage Vs to the output voltage Vout is applied to the non-inverting input terminal (+) of the amplifier A2. The amplifier A2 connected in this manner outputs a difference signal V21 between the detection voltage Vs and the upper limit voltage Vocp.

[0063] The source of the transistor M22 and the drain of the transistor M23 are all connected to the output terminal VOUT. The drain of the transistor M22, the gate of the transistor M23, and a first end of the resistor R21 are all connected to an application terminal of the voltage signal V22. The source of the transistor M23 and a second end of the resistor R21 are all connected to an application terminal of the drive signal G20. The gate of the transistor M22 is connected to an application terminal of the differential signal V21. The transistors M22 and M23 and the resistor R21 connected in this manner form a first output circuit 11 that limits the drive signal G20 in response to the differential signal V21.

[0064] When the detection voltage Vs is lower than the upper limit voltage Vocp, the differential signal V21 output from the amplifier A2 is stuck at a low level (≒Vout). Therefore, the transistor M22 is fully off, and the voltage signal V22 becomes approximately equal to the drive signal G20. As a result, the transistor M23 is fully off, and the gate-source of the output transistor M20 is open. Therefore, the on-resistance of the output transistor M20 is not increased, and no restriction is placed on the output current Iout flowing through the output transistor M20 (i.e., the overcurrent protection operation is released).

[0065] On the other hand, if the output current Iout increases due to an output abnormality or the like, and the detection voltage Vs becomes higher than the upper limit voltage Vocp, the differential signal V21 output from the amplifier A2 according to the difference between the two voltages rises from low level, and the transistor M22 turns on, causing the voltage signal V22 to fall from high level (≒G20).

[0066] At this time, a drive current I21 (corresponding to the overcurrent protection signal) flows between the gate and source of the output transistor M20 via transistor M23. As a result, the drive signal G20 drops, pulling down the gate-source voltage of the output transistor M20. As a result, the on-resistance of the output transistor M20 increases, and the output current Iout is limited (overcurrent protection operation is activated). Ultimately, the drive current I21 balances when the detection voltage Vs and the upper limit voltage Vocp are imaginarily shorted.

[0067] With a configuration including such an overcurrent protection circuit 10, even in a situation where an excessively large output current Iout may flow through the output transistor M20, the output current Iout can be limited, thereby protecting the power supply device 1 and its peripheral circuits (including the load).

[0068] In the overcurrent protection circuit 10 of this embodiment, the amplifier A2 and the first output circuit 11 are both connected between the application terminal of the drive signal G20 and the output terminal VOUT. With this configuration, the drive current I21 of the overcurrent protection circuit 10 flows from the application terminal of the drive signal G20 to the output terminal VOUT. This has the effect of not increasing the current consumption of the semiconductor chip SC (and therefore the power supply control IC).

[0069] Furthermore, the overcurrent protection circuit 10 includes a second output circuit 12. The second output circuit 12 receives the differential signal V21 and outputs a detection signal I22. Referring to the figure, the second output circuit 12 includes a transistor M24 (e.g., an NMOSFET), a transistor M25 (e.g., a PMOSFET), a transistor M26 (e.g., an NMOSFET), and resistors R22 to R24.

[0070] The source of the transistor M24 is connected to the output terminal VOUT. The gate of the transistor M24 is connected to the application terminal of the differential signal V21. The drain of the transistor M24, the gate of the transistor M25, and the first terminal of the resistor R22 are all connected to the application terminal of the voltage signal V23. The source of the transistor M25 and the second terminal of the resistor R22 are all connected to the input terminal VIN. The drain of the transistor M25, the gate of the transistor M26, and the first terminal of the resistor R23 are all connected to the application terminal of the voltage signal V24. The source of the transistor M26 and the second terminal of the resistor R23 are all connected to the ground terminal GND. The drain of the transistor M26 is connected to the first terminal of the resistor R24. The second terminal of the resistor R24 ​​is connected to the feedback terminal VSNS. The resistor R24 ​​functions as a current limiting resistor that limits the current flowing as the detection signal I22. However, the resistor R24 ​​may be omitted.

[0071] During the EDS process for the semiconductor chip SC, a test current Ie is injected into the test input terminal EOCP, causing the differential signal V21 to rise from a low level (≒Vout). Therefore, the transistor M24 is turned on, causing the voltage signal V23 to fall from a high level (≒VIN). As a result, the transistor M25 is turned on, causing the voltage signal V24 to rise from a low level (≒Vout). At this time, a detection signal I22 flows between the feedback terminal VSNS and the ground terminal GND via the resistor R24 ​​and the transistor M26. Therefore, by measuring whether the detection signal I22 flows when a predetermined test current Ie is applied, it is possible to confirm whether the overcurrent protection circuit 10 is operating correctly.

[0072] Seventh Embodiment FIG. 11 is a diagram showing a seventh embodiment of the power supply device 1. The power supply device 1 of this embodiment is based on the sixth embodiment (FIG. 10) and further includes a test output terminal VMON for outputting a detection signal I22. Furthermore, the second output circuit 12 does not include the transistor M26 and resistors R23 and R24. In other words, the drain of the transistor M25 is directly connected to the test output terminal VMON. Therefore, the detection signal I22 flows from the input terminal VIN to the test output terminal VMON via the transistor M25.

[0073] In this way, the second output circuit 12 may be connected to a terminal other than the feedback terminal VSNS. Also, unlike the sixth embodiment (FIG. 10), the detection signal I12 may be output from the semiconductor chip SC. These points are the same as those in the fourth embodiment (FIG. 8) and the fifth embodiment (FIG. 9).

[0074] <Combination of embodiments> The first to seventh embodiments described above may be combined as appropriate as long as no contradictions are present. For example, although not shown separately, the transistor M23 and resistor R21 of the sixth embodiment (FIG. 10) may be omitted, following the second embodiment (FIG. 5). Alternatively, a Schmitt trigger HYS may be added to the sixth embodiment (FIG. 10), following the third embodiment (FIG. 6).

[0075] <Additional Notes> With the overcurrent protection circuit according to the present disclosure, it is possible to confirm the overcurrent protection operation regardless of manufacturing variations, temperature conditions, etc. The following additional notes are provided regarding the above disclosure.

[0076] [Appendix 1] Detecting resistors (R10, R20) connected between the first terminal (VIN) and the second terminal (VOUT); detection transistors (M11, M21) connected in series with the detection resistors (R10, R20) between the first terminal (VIN) and the second terminal (VOUT), and configured so that drive signals (G10, G20) for output transistors (M10, M20) are applied to control electrodes thereof; an amplifier (A1, A2) connected between the first terminal (VIN) or the second terminal (VOUT) and an application terminal of the drive signal (G10, G20), and configured to output a difference signal (V11, V21) between a detection voltage (Vs) appearing across both ends of the detection resistor (R10, R20) and a predetermined upper limit voltage (Vocp); a first output circuit (11) connected between the first terminal (VIN) or the second terminal (VOUT) and an application terminal of the drive signal (G10, G20), and configured to limit the drive signal (G10, G20) in accordance with the difference signal (V11, V21); a second output circuit (12) configured to receive the differential signals (V11, V21) and output detection signals (I12, I22); An overcurrent protection circuit (10).

[0077] [Appendix 2] 2. The overcurrent protection circuit (10) of claim 1, wherein the second output circuit (12) includes current limiting resistors (R13, R24) configured to limit the current flowing as the detection signal (I12, I22).

[0078] [Appendix 3] 3. The overcurrent protection circuit (10) according to claim 1 or 2, wherein the second output circuit (12) includes a Schmitt trigger (HYS) having hysteresis in its input threshold.

[0079] [Appendix 4] An overcurrent protection circuit (10) according to any one of Supplementary Notes 1 to 3; the first terminal (VIN) and the second terminal (VOUT); The third terminal (VSNS) and the output transistors (M10, M20) connected between the first terminal (VIN) and the second terminal (VOUT); an error amplifier (20) configured to perform feedback control of the drive signals (G10, G20) so that a feedback voltage (Vfb) corresponding to a voltage applied to the third terminal (VSNS) coincides with a reference voltage (Vref); A semiconductor chip (SC) comprising:

[0080] [Appendix 5] 5. The semiconductor chip (SC) according to claim 4, further comprising a fourth terminal (EOCP) configured to pass a test current (Ie) through the detection resistor (R10, R20).

[0081] [Appendix 6] 6. The semiconductor chip (SC) according to claim 4 or 5, wherein the second output circuit (12) outputs the detection signal (I12, I22) from the third terminal (VSS).

[0082] [Appendix 7] The semiconductor chip (SC) according to appendix 4 or 5, further comprising a fifth terminal (VMON) configured to output the detection signal (I12, I22).

[0083] [Appendix 8] The output transistor (M10) is a P-channel type or a PNP type, The semiconductor chip (SC) according to any one of appendices 4 to 7, wherein the amplifier (A1) and the first output circuit (11) are both connected between the first terminal (VIN) and an application terminal of the drive signal (G10).

[0084] [Appendix 9] The output transistor (M20) is an N-channel type or an npn type, The semiconductor chip (SC) according to any one of appendices 4 to 7, wherein the amplifier (A2) and the first output circuit (11) are both connected between the second terminal (VOUT) and an application terminal of the drive signal (G20).

[0085] [Appendix 10] A semiconductor chip (SC) according to any one of Supplementary Notes 4 to 9 is provided, The power supply device (1) generates a desired output voltage (Vout) from an input voltage (Vin) input to the first terminal (VIN) and outputs the output voltage to the second terminal (VOUT).

[0086] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. For example, the NMOSFET and PMOSFET can be replaced with npn-type and pnp-type bipolar transistors, respectively. In such a case, the drain, source, and gate described above can be read as the emitter, collector, and base, respectively.

[0087] As such, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. The technical scope of the present disclosure is defined by the claims, and it should be understood that all modifications that fall within the meaning and scope of the claims are included. [Explanation of symbols]

[0088] 1 Power supply (linear power supply) 10 Overcurrent protection circuit 11 First output circuit 12 Second output circuit 20 Error amplifier 30 Feedback voltage generation circuit 31, 32 Resistor 40 Reference voltage generation circuit A1, A2 amplifiers Co capacitor EOCP test input terminal GND Ground terminal HYS Schmitt trigger M10 Output transistor (PMOSFET) M11 Detect transistor (PMOSFET) M12 Transistor (PMOSFET) M13 Transistor (NMOSFET) M14 Transistor (PMOSFET) M15 Transistor (NMOSFET) M20 Output transistor (NMOSFET) M21 Detect transistor (NMOSFET) M22 transistor (NMOSFET) M23 Transistor (PMOSFET) M24 Transistor (NMOSFET) M25 Transistor (PMOSFET) M26 Transistor (NMOSFET) OUT output terminal R10, R20 detection resistors R11~R13, R21~R24 Resistors SC semiconductor chip VIN input terminal VMON test output terminal VSNS feedback terminal

Claims

1. a sense resistor connected between the first terminal and the second terminal; a detection transistor connected in series with the detection resistor between the first terminal and the second terminal, the detection transistor configured to receive a drive signal for an output transistor at a control electrode thereof; an amplifier connected between the first terminal or the second terminal and an application terminal of the drive signal, and configured to output a differential signal between a detection voltage appearing across both ends of the detection resistor and a predetermined upper limit voltage; a first output circuit connected between the first terminal or the second terminal and an application terminal of the drive signal and configured to limit the drive signal in response to the differential signal; a second output circuit configured to receive the differential signal and output a detection signal; An overcurrent protection circuit comprising:

2. 2. The overcurrent protection circuit of claim 1, wherein the second output circuit includes a current limiting resistor configured to limit a current flowing as the detection signal.

3. 2. The overcurrent protection circuit according to claim 1, wherein the second output circuit includes a Schmitt trigger having hysteresis in its input threshold.

4. an overcurrent protection circuit according to claim 1; the first terminal and the second terminal; A third terminal; the output transistor connected between the first terminal and the second terminal; an error amplifier configured to perform feedback control of the drive signal so that a feedback voltage corresponding to the voltage applied to the third terminal coincides with a reference voltage; A semiconductor chip comprising:

5. The semiconductor chip of claim 4 , further comprising a fourth terminal configured to pass a test current through the sense resistor.

6. The semiconductor chip according to claim 4 , wherein the second output circuit outputs the detection signal from the third terminal.

7. The semiconductor chip according to claim 4 , further comprising a fifth terminal configured to output the detection signal.

8. the output transistor is a P-channel type or a PNP type; The semiconductor chip according to claim 4 , wherein the amplifier and the first output circuit are both connected between the first terminal and an application terminal of the drive signal.

9. the output transistor is an N-channel type or an npn type, The semiconductor chip according to claim 4 , wherein the amplifier and the first output circuit are both connected between the second terminal and an application terminal of the drive signal.

10. A semiconductor chip according to any one of claims 4 to 9, A power supply device that generates a desired output voltage from an input voltage input to the first terminal and outputs the output voltage to the second terminal.

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