Semiconductor device

Abstract

To perform, for a semiconductor device including a plurality of semiconductor chips bonded to each other at a junction, a test for checking whether an appropriate bonding is made at a junction on a supply path of power supply voltage by a simple configuration.SOLUTION: The semiconductor device comprises a first semiconductor chip, and a second semiconductor chip connected to the first semiconductor chip. The first semiconductor chip includes: a first signal output circuit outputting a first signal of a predetermined logical value when power supply voltage is supplied from the second semiconductor chip; and a first logic circuit performing logic operation between a second signal supplied from the second semiconductor chip and the first signal. The second semiconductor chip outputs logic operation results obtained by the first logic circuit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The disclosed technology relates to a semiconductor device. [Background technology]

[0002] The following techniques are known as techniques related to a multi-chip semiconductor device having a plurality of semiconductor chips. For example, Patent Document 1 describes a semiconductor device having: first inter-chip wiring for electrically connecting a first semiconductor chip and a second semiconductor chip; second inter-chip wiring as a backup for the first inter-chip wiring; a test signal generation circuit provided in the first semiconductor chip for transmitting a test signal to the second semiconductor chip via the first inter-chip wiring; a determination circuit provided in the second semiconductor chip for outputting a first control signal when a test signal is received via the first inter-chip wiring and outputting a second control signal that is an inverted signal of the first control signal when the test signal is not received; and a switching circuit provided in the second semiconductor chip for setting the first inter-chip wiring as a path electrically connecting the first semiconductor chip and the second semiconductor chip when the first control signal is input from the determination circuit and setting the second inter-chip wiring as the path when the second control signal is input.

[0003] Patent document 2 describes a semiconductor device in which multiple semiconductor chips are packaged together, including at least a first semiconductor chip having multiple first bonding pads that output signals of a first level, and a second semiconductor chip having second bonding pads that are electrically connected to some of the multiple first bonding pads, and a third bonding pad that changes the level of signals output from some of the first bonding pads to the second bonding pads to a second level that is different from the first level and outputs the signals.

[0004] Patent document 3 describes a semiconductor device that consists of two semiconductor chips wired together, the first semiconductor chip having a circuit for selecting an operation signal and a test signal, and wiring that leads the output of the selection circuit to the second semiconductor chip via the connection between both semiconductor chips, and the second semiconductor chip having an AND gate that inputs the output group of the selection circuit and wiring that connects the output of the AND gate to a detection terminal of the first semiconductor chip, thereby making it possible to test the wiring state of the connection. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2007 / 032184 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-103703 [Patent Document 3] Japanese Patent Application Publication No. 61-35546 Summary of the Invention [Problem to be solved by the invention]

[0006] In a multi-chip semiconductor device having multiple semiconductor chips bonded together using a bonding technique such as D2W (Die to Wafer), a test is performed to confirm whether the bonding state at the bonding joints between the semiconductor chips is appropriate. After the semiconductor chips are connected, access to one semiconductor chip may be possible only through the other semiconductor chip. In this case, one semiconductor chip receives a power supply voltage from the other semiconductor chip. The power supply voltage is supplied through the bonding joints between the semiconductor chips. In this configuration, it is necessary to test the bonding joints present on the power supply voltage supply path.

[0007] The disclosed technology aims to perform a test using a simple configuration to confirm the bonding state of a bonding portion located on a power supply voltage supply path in a semiconductor device having multiple semiconductor chips bonded to each other at bonding portions. [Means for solving the problem]

[0008] A semiconductor device according to the disclosed technology includes a first semiconductor chip and a second semiconductor chip connected to the first semiconductor chip. The first semiconductor chip includes a first signal output circuit that outputs a first signal of a predetermined logic value when a power supply voltage is supplied from the second semiconductor chip, and a first logic circuit that performs a logical operation on a second signal supplied from the second semiconductor chip and the first signal. The second semiconductor chip outputs a result of the logical operation performed by the first logic circuit. [Effects of the Invention]

[0009] According to the disclosed technology, in a semiconductor device having multiple semiconductor chips bonded to each other at bonding portions, it is possible to perform a test to confirm the appropriateness of the bonding state at bonding portions located on the supply path of a power supply voltage using a simple configuration. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a perspective view illustrating an example of a configuration of a semiconductor device according to an embodiment of the disclosed technique; [Figure 2] 1 is a circuit block diagram showing an example of the configuration of a first semiconductor chip and a second semiconductor chip according to an embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals.

[0012] FIG. 1 is a perspective view showing an example of the configuration of a semiconductor device 100 according to an embodiment of the disclosed technology. The semiconductor device 100 has a multi-chip configuration including a first semiconductor chip 1 and a second semiconductor chip 2. The first semiconductor chip 1 is, for example, a general-purpose core chip and has general-purpose functional units such as a CPU and memory. The second semiconductor chip 2 is, for example, a custom chip and has functional units for realizing specific functions according to the application. The applications and functions of the first semiconductor chip 1 and the second semiconductor chip 2 are not particularly limited.

[0013] The first semiconductor chip 1 and the second semiconductor chip 2 each have a plurality of pads arranged in a grid pattern on the surface of a semiconductor substrate. The first semiconductor chip 1 and the second semiconductor chip 2 are electrically and mechanically connected to each other by joining the pads together using a conductive bonding material such as solder. The area of ​​the second semiconductor chip 2 is larger than that of the first semiconductor chip 1, and the first semiconductor chip 1 is stacked on top of the second semiconductor chip 2. After the first semiconductor chip 1 and the second semiconductor chip 2 are connected, access to the first semiconductor chip 1 can only be made via the second semiconductor chip 2. Therefore, supply of power supply voltage and ground voltage to the first semiconductor chip 1 and input / output of various signals are made via the second semiconductor chip 2.

[0014] 2 is a circuit block diagram showing an example of the configuration of the first semiconductor chip 1 and the second semiconductor chip 2. The first semiconductor chip 1 and the second semiconductor chip 2 are bonded to each other at bonding portions 11, 12, 13, 14, 15, 16, 17, 18, and 19. The bonding portions 11 to 19 are formed by bonding pads provided on the first semiconductor chip 1 to pads provided on each of the second semiconductor chips 2.

[0015] An external power supply voltage VDD1 and a ground voltage VG are input to the second semiconductor chip 2. The power supply voltage VDD1 and the ground voltage VG are supplied from the second semiconductor chip 2 to the first semiconductor chip 1 via joints 11 and 13, respectively.

[0016] A power supply voltage VDD2, which is obtained by stepping up or stepping down the power supply voltage VDD1, is generated in the second semiconductor chip 2. The power supply voltage VDD2 is supplied from the second semiconductor chip 2 to the first semiconductor chip 1 via the joint 12.

[0017] The second semiconductor chip 2 has a signal generating circuit 50. The signal generating circuit 50 generates a signal S used in testing the bonding conditions of the bonding parts 11, 12, and 13. 2A , S 2B , S 2C Generates a signal S 2A and S 2B The logical values ​​of the signals S 2C The logical value of signal S is "H". 2A , S 2B , S 2C are supplied to the first semiconductor chip 1 via the junctions 19, 17, and 15, respectively. 2A , S 2B is an example of a "second signal" in the disclosed technology. 2C is an example of a "fourth signal" in the disclosed technology.

[0018] The first semiconductor chip 1 has signal output circuits 20A, 20B, and 20C. The signal output circuit 20A outputs a signal S 1A When the power supply voltage VDD1 is properly supplied from the second semiconductor chip 2 via the joint 11, the signal output circuit 20A outputs a signal S 1A otherwise, it outputs a logic "L" (low level) signal S 1A Output.

[0019] The signal output circuit 20B outputs a signal S according to the potential of the junction 12. 1B When the power supply voltage VDD2 is properly supplied from the second semiconductor chip 2 via the joint 12, the signal output circuit 20B outputs a signal S 1B otherwise, it outputs a logic "L" signal S 1BThe signal output circuits 20A and 20B are examples of the "first signal output circuit" in the disclosed technology. 1A and signal S 1B is an example of a "first signal" in the disclosed technology.

[0020] The signal output circuit 20C outputs a signal S according to the potential of the junction 13. 1C When the ground voltage VG is properly supplied from the second semiconductor chip 2 via the joint 13, the signal output circuit 20C outputs a signal S 1C otherwise, it outputs a logic high signal S 1C The signal output circuit 20C is an example of a "second signal output circuit" in the disclosed technology. 1C is an example of a "third signal" in the disclosed technology.

[0021] The first semiconductor chip 1 has OR circuits 30A and 30B, an AND circuit 30C, and switching circuits 40A, 40B, and 40C. The switching circuit 40A selects the connection destinations of the two input terminals of the OR circuit 30A as a signal S 1A Transmission path and signal S 2A When testing the connection states of the junctions 11, 12, and 13, the switching circuit 40A switches between connecting the two input terminals of the OR circuit 30A to the signal S 1A Transmission path and signal S 2A In this case, the OR circuit 30A receives a signal S 1A and signal S 2A The OR circuit 30A outputs a signal S indicating the result of the logical operation. 3A is transmitted to the second semiconductor chip 2 via the joint 18 and output from the second semiconductor chip 2 to the outside of the semiconductor device 100. When the joint state at the joint 11 is appropriate, in other words, when the power supply voltage VDD1 is properly supplied to the first semiconductor chip 1, the signal S 3A will be output.

[0022] The switching circuit 40B selects the connection destinations of the two input terminals of the OR circuit 30B as signals S 1B Transmission path and signal S 2B When testing the connection states of the junctions 11, 12, and 13, the switching circuit 40B switches between connecting the two input terminals of the OR circuit 30B to the signal S 1B Transmission path and signal S 2B In this case, the OR circuit 30B receives the signal S 1B and signal S 2B The OR circuit 30B outputs a signal S indicating the result of the logical operation. 3B is transmitted to the second semiconductor chip 2 via the joint 16 and output from the second semiconductor chip 2 to the outside of the semiconductor device 100. When the joint state at the joint 12 is appropriate, in other words, when the power supply voltage VDD2 is appropriately supplied to the first semiconductor chip 1, the signal S 3B is output. The OR circuits 30A and 30B are an example of a "first logic circuit" in the disclosed technology. The switching circuits 40A and 40B are an example of a "first switching circuit" in the disclosed technology.

[0023] The switching circuit 40C selects the connection destinations of the two input terminals of the AND circuit 30C to be connected to the signals S 1C Transmission path and signal S 2C When testing the connection states of the junctions 11, 12, and 13, the switching circuit 40C switches between connecting the two input terminals of the AND circuit 30C to the signal S 1C Transmission path and signal S 2C In this case, the AND circuit 30C receives the signal S 1C and signal S 2C The AND circuit 30C outputs a signal S indicating the result of the logical operation. 3Bis transmitted to the second semiconductor chip 2 via the joint 14 and output from the second semiconductor chip 2 to the outside of the semiconductor device 100. When the joint state at the joint 13 is appropriate, in other words, when the ground voltage VG is properly supplied to the first semiconductor chip 1, the signal S 3B is output. The AND circuit 30C is an example of a "second logic circuit" in the disclosed technology. The switching circuit 40C is an example of a "second switching circuit" in the disclosed technology.

[0024] The following describes the operation of the semiconductor device 100. The power supply voltages VDD1, VDD2 and the ground voltage VG are supplied from the second semiconductor chip 2 to the first semiconductor chip 1 via the joints 11, 12 and 13, respectively.

[0025] When the power supply voltage VDD1 is properly supplied from the second semiconductor chip 2 via the joint 11, the signal output circuit 20A outputs a signal S 1A otherwise, it outputs a logic "L" signal S 1A Output.

[0026] When the power supply voltage VDD2 is properly supplied from the second semiconductor chip 2 via the joint 12, the signal output circuit 20B outputs a signal S 1B otherwise, it outputs a logic "L" signal S 1B Output.

[0027] When the ground voltage VG is properly supplied from the second semiconductor chip 2 via the joint 13, the signal output circuit 20C outputs a signal S 1C otherwise, it outputs a logic high signal S 1C Output.

[0028] When the operation mode of the semiconductor device 100 is shifted to a test mode in which the bonding states of the bonding portions 11, 12, and 13 are tested, the signal generating circuit 50 generates a signal S 2A , S 2B and a logic "H" signal S 2CThese signals S 2A , S 2B , S 2C are supplied to the first semiconductor chip 1 via the bonding portions 19, 17, and 15, respectively.

[0029] Furthermore, when the mode is shifted to the test mode, the switching circuit 40A changes the connection destinations of the two input terminals of the OR circuit 30A to the signals S 1A Transmission path and signal S 2A The switching circuit 40B selects the connection destinations of the two input terminals of the OR circuit 30B as the transmission paths of the signals S 1B Transmission path and signal S 2B The two input terminals of the AND circuit 30C are connected to the signal S 1C Transmission path and signal S 2C This is the transmission path.

[0030] In the test mode, the OR circuit 30A receives a signal S 1A and signal S 2A When the power supply voltage VDD1 is properly supplied from the second semiconductor chip 2 via the joint 11, the signal S 1A The logical value of the signal S is "H", so in this case, the OR circuit 30A outputs the signal S 3A In other cases, the signal S 1A The logical value of the signal S is "L". In this case, the OR circuit 30A outputs the signal S 3A The signal S with logic value "H" is output. 3A indicates that the junction state at the junction 11 is proper, and a signal S 3A indicates that the bonding state of the bonding portion 11 is not appropriate (a bonding failure has occurred). 3A is transmitted to the second semiconductor chip 2 via the bonding portion 18 and output from the second semiconductor chip 2 to the outside of the semiconductor device 100.

[0031] In the test mode, the OR circuit 30B receives a signal S 1B and signal S2B When the power supply voltage VDD2 is properly supplied from the second semiconductor chip 2 via the joint 12, the signal S 1B The logical value of the signal S is "H", so in this case, the OR circuit 30B outputs the signal S 3B In other cases, the signal S 1B The logical value of the signal S is "L". In this case, the OR circuit 30B outputs the signal S 3B The signal S with logic value "H" is output. 3B indicates that the junction 12 is in a good state, and a logic "L" signal S 3B indicates that the bonding state of the bonding portion 11 is not appropriate (a bonding failure has occurred). 3B is transmitted to the second semiconductor chip 2 via the bonding portion 16 and output from the second semiconductor chip 2 to the outside of the semiconductor device 100.

[0032] In the test mode, the AND circuit 30C receives the signal S 1C and signal S 2C When the ground voltage VG is properly supplied from the second semiconductor chip 2 via the joint 13, the logical product of the signal S 1C The logical value of the signal S is "L". In this case, the AND circuit 30C outputs the signal S with a logical value of "L". 3C In other cases, the signal S 1C The logical value of the signal S is "H", so in this case, the AND circuit 30C outputs the signal S with a logical value of "H". 3C The signal S with a logic value of "L" is output. 3C indicates that the junction state at the junction 13 is proper, and a signal S 3C indicates that the bonding state of the bonding portion 13 is not appropriate (a bonding failure has occurred). 3C is transmitted to the second semiconductor chip 2 via the bonding portion 14 and output from the second semiconductor chip 2 to the outside of the semiconductor device 100.

[0033] As described above, the semiconductor device 100 according to the embodiment of the disclosed technique makes it possible to perform a test with a simple configuration to check the appropriateness of the junctions 11, 12, and 13 present on the supply paths of the power supply voltages VDD1 and VDD2 and the ground voltage VG between the semiconductor chips. 2A , S 2B , S 2C , S 3A , S 3B , S 3C It is also possible to simultaneously test the junctions 14, 15, 16, 17, 18, and 19 present on the respective transmission paths.

[0034] Furthermore, because the semiconductor device 100 includes switching circuits 40A, 40B, and 40C that switch the connection destinations of the input terminals of the OR circuits 30A and 30B and the AND circuit 30C, it is possible to use the OR circuits 30A and 30B, the AND circuit 30C, and the signal generation circuit 50 for purposes other than testing the joints. In other words, the OR circuits 30A and 30B, the AND circuit 30C, and the signal generation circuit 50, which are provided for purposes other than testing the joints, as well as the signal transmission paths used by these circuits, and the joints 14 to 19 present on these transmission paths, can be used for testing the joints, eliminating the need to provide these components anew.

[0035] The following additional notes are provided regarding the above-described embodiments. (Appendix 1) A semiconductor device including a first semiconductor chip and a second semiconductor chip connected to the first semiconductor chip, The first semiconductor chip comprises: a first signal output circuit that outputs a first signal of a predetermined logic value when a power supply voltage is supplied from the second semiconductor chip; a first logic circuit that performs a logical operation on a second signal supplied from the second semiconductor chip and the first signal; The second semiconductor chip outputs the result of the logical operation performed by the first logic circuit. Semiconductor device.

[0036] (Appendix 2) a first switching circuit that switches the connection destinations of the two input terminals of the first logic circuit between the transmission path of the first signal and the transmission path of the second signal, respectively, or a transmission path of another signal; 2. The semiconductor device according to claim 1.

[0037] (Appendix 3) A junction between the first semiconductor chip and the second semiconductor chip is provided on a supply path of the power supply voltage. 10. The semiconductor device according to claim 1 or 2.

[0038] (Appendix 4) The first semiconductor chip comprises: a second signal output circuit that outputs a third signal of a predetermined logic value when a ground voltage is supplied from the second semiconductor chip; a second logic circuit that performs a logical operation on a fourth signal supplied from the second semiconductor chip and the third signal, The second semiconductor chip outputs a result of the logical operation performed by the second logic circuit. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0039] (Appendix 5) a second switching circuit that switches the connection destinations of the two input terminals of the second logic circuit between the transmission path of the third signal and the transmission path of the fourth signal, respectively, and a transmission path of another signal; 5. The semiconductor device according to claim 4.

[0040] (Appendix 6) A junction between the first semiconductor chip and the second semiconductor chip is provided on the supply path of the ground voltage. 6. The semiconductor device according to claim 4 or 5. [Explanation of symbols]

[0041] 1. The First Semiconductor Chip 2. The second semiconductor chip 11, 12, 13, 14, 15, 16, 17, 18, 19 joint 20A, 20B, 20C signal output circuit 30A, 30B OR circuit 30C AND circuit 40A, 40B, 40C switching circuit 50 Signal generation circuit 100 Semiconductor device

Claims

1. A semiconductor device including a first semiconductor chip and a second semiconductor chip connected to the first semiconductor chip, The first semiconductor chip includes: a first signal output circuit that outputs a first signal of a predetermined logic value when a power supply voltage is supplied from the second semiconductor chip; a first logic circuit that performs a logical operation on a second signal supplied from the second semiconductor chip and the first signal; The second semiconductor chip outputs a result of the logical operation performed by the first logic circuit. Semiconductor device.

2. a first switching circuit that switches the connection destinations of the two input terminals of the first logic circuit between the transmission path of the first signal and the transmission path of the second signal, respectively, or a transmission path of another signal; The semiconductor device according to claim 1 .

3. A junction between the first semiconductor chip and the second semiconductor chip is provided on a supply path of the power supply voltage. The semiconductor device according to claim 1 .

4. The first semiconductor chip includes: a second signal output circuit that outputs a third signal of a predetermined logic value when a ground voltage is supplied from the second semiconductor chip; a second logic circuit that performs a logical operation on a fourth signal supplied from the second semiconductor chip and the third signal, The second semiconductor chip outputs a result of the logical operation by the second logic circuit. The semiconductor device according to claim 1 .

5. a second switching circuit that switches the connection destinations of the two input terminals of the second logic circuit between the transmission path of the third signal and the transmission path of the fourth signal, respectively, and a transmission path of another signal; The semiconductor device according to claim 4 .

6. A junction between the first semiconductor chip and the second semiconductor chip is provided on the supply path of the ground voltage. The semiconductor device according to claim 4 .

Images