Wireless communication device

Abstract

To provide a superheterodyne wireless communication device which suppresses the DC offset component generated in the intermediate frequency signal due to self-mixing, without removing the signal component.SOLUTION: The device includes a mixer that mixes a radio frequency signal and a local oscillator signal to output an intermediate frequency signal. Based on the DC voltage output from the mixer when the radio frequency signal is not supplied and the local oscillator signal is supplied to the mixer, the level of the DC component contained in the intermediate frequency signal is corrected.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The disclosed technology relates to a wireless communication device. [Background technology]

[0002] The following technologies are known as technologies related to wireless communication devices. For example, Patent Document 1 describes a direct conversion receiver that includes a signal source, a local oscillator frequency-modulated by a signal from the signal source, a mixer that receives the output of the local oscillator and an input signal from an antenna, removal means that removes the frequency component of the signal source from the mixer output, and demodulation means that receives the output of the removal means.

[0003] Patent Document 2 describes a frequency conversion circuit that includes a mixer that mixes a local signal for frequency conversion with an input signal whose frequency is converted by this local signal, a coupler that extracts a portion of the local signal input to the mixer according to a predetermined coupling amount, a phase shifter that controls the phase of the signal extracted by the coupler so that it is opposite in phase to the phase of the local signal that has leaked into the signal output from the mixer, a coupler that injects the signal whose phase has been suppressed by the phase shifter into the signal output from the mixer at a coupling amount that cancels the local signal that has leaked into the signal, and a bandpass filter that removes unnecessary frequency components from the signal in which the local signal that has leaked into has been canceled by the coupler. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 9-200072 [Patent Document 2] Japanese Patent Application Publication No. 5-175736 Summary of the Invention [Problem to be solved by the invention]

[0005] The superheterodyne method is widely adopted as a method for processing received signals in transceiver integrated circuits (ICs) used in wireless communications. The superheterodyne method is a receiving method in which a radio frequency signal (hereinafter referred to as RF signal) that is the received signal is mixed with a local oscillation signal (hereinafter referred to as LO signal) output from a local oscillator using a mixer to generate an intermediate frequency signal (hereinafter referred to as IF signal) with a frequency corresponding to the difference between the frequencies of these signals, and the IF signal is then amplified and demodulated.

[0006] Self-mixing is a problem in the superheterodyne system. Self-mixing occurs when the LO signal leaks from the LO signal input terminal of the mixer to the RF signal input terminal, is reflected by a circuit such as a low-noise amplifier located in the upstream stage of the mixer, and is then input back into the mixer, causing an offset in the IF signal output from the mixer.

[0007] One possible solution is to insert a capacitor into the mixer's output line to remove the DC offset component. This solution is effective when the IF signal frequency is high enough that the signal components contained in the IF signal are not included in the removal band. However, in systems where the IF signal frequency is wideband or systems that use the zero-IF method, the above solution cannot be used because there is a risk that the capacitor will remove the signal components.

[0008] The disclosed technology has been developed in consideration of the above points, and aims to suppress DC offset components that occur in intermediate frequency signals due to self-mixing in superheterodyne wireless communication devices without removing the signal components. [Means for solving the problem]

[0009] The wireless communication device according to the disclosed technique has a mixer that mixes a radio frequency signal with a local oscillation signal and outputs an intermediate frequency signal, and corrects the level of the DC component contained in the intermediate frequency signal based on the DC voltage output from the mixer when the radio frequency signal is not input to the mixer but the local oscillation signal is input to the mixer. [Effects of the Invention]

[0010] According to the disclosed technology, in a superheterodyne wireless communication device, it is possible to suppress a DC offset component that occurs in an intermediate frequency signal due to self-mixing without removing the signal component. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of a wireless communication device according to a comparative example. [Figure 2] 10A and 10B are diagrams illustrating a self-offset that occurs in a wireless communication device according to a comparative example. [Figure 3] FIG. 1 is a diagram illustrating an example of a configuration of a wireless communication device according to a comparative example. [Figure 4] 1 is a circuit block diagram illustrating an example of a configuration of a wireless communication device according to an embodiment of the disclosed technology. [Figure 5] 10 is a flowchart illustrating an example of an operation sequence of a wireless communication device operating in a calibration mode according to an embodiment of the disclosed technique. [Figure 6] 10 is a flowchart illustrating an example of an operation sequence of a wireless communication device operating in a normal mode according to an embodiment of the disclosed technique. [Figure 7] FIG. 10 is a circuit block diagram illustrating an example of a configuration of a wireless communication device according to another embodiment of the disclosed technology. [Figure 8] 10A and 10B are diagrams illustrating the states of the switches when a correction value for the positive phase side of the IF signal is generated. [Figure 9] 10A and 10B are diagrams illustrating the states of the switches when a correction value for the reverse phase side of the IF signal is generated. DETAILED DESCRIPTION OF THE INVENTION

[0012] First, a wireless communication device according to a comparative example will be described. FIG. 1 is a diagram showing an example of the configuration of a wireless communication device 10X according to the comparative example. The wireless communication device 10X has a group of circuits that perform reception processing of radio frequency signals. The wireless communication device 10X may constitute a transceiver IC. To improve resistance to external disturbances, the received signal is processed as a differential signal. The differential signal is composed of a pair of positive-phase and negative-phase signals whose phases are inverse to each other. The wireless communication device 10X has an antenna 11, a low-noise amplifier 12, a mixer 13, a local oscillator (LO) 14, an IF amplifier 15, an analog-to-digital converter 16, a filter 17, and a logic circuit 18.

[0013] The low-noise amplifier 12 amplifies the radio frequency signal (hereinafter referred to as RF signal) received from the antenna 11 with low noise.

[0014] The local oscillator (LO) 14 includes, for example, a phase locked loop (PLL) and a voltage-controlled oscillator (VCO), and outputs a local oscillation signal (hereinafter referred to as an LO signal) having a constant frequency.

[0015] Mixer 13 mixes the amplified RF signal output from low-noise amplifier 12 with the LO signal output from local oscillator 14, and outputs an intermediate frequency signal (hereinafter referred to as IF signal) having a frequency lower than that of the RF signal.

[0016] The IF amplifier 15 amplifies the IF signal output from the mixer 13. The analog-to-digital converter (ADC) 16 converts the output signal of the IF amplifier 15 into a digital value. The filter 17 is a channel filter that passes signals having predetermined frequency components among multiple frequency components contained in the IF signal. The filter 17 may be, for example, a low-pass filter or a band-pass filter. The logic circuit 18 is a baseband logic circuit that includes a circuit block that digitally demodulates the IF signal that has passed through the filter 17.

[0017] The frequency conversion performed by mixer 13 will be explained below. Mixer 13 mixes the RF signal and the LO signal by multiplying these signals. Mixing of a signal with frequency f1 and a signal with frequency f2 is expressed by the following equation (1). In equation (1), ω1=2πf1 and ω2=2πf2.

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[0018] As shown in equation (1), when a signal of frequency f1 and a signal of frequency f2 are mixed, a sum component and a difference component of these frequencies are output. In wireless communication device 10, filter 17 extracts only one of the sum component and the difference component, and logic circuit 18 demodulates the extracted component.

[0019] In order to stabilize the frequency conversion gain and noise figure characteristics, which are performance parameters that affect the communication distance, an LO signal with a very large amplitude is input to the mixer 13. This makes the problem of self-mixing more likely to become apparent. As shown in Figure 2, self-mixing is a phenomenon in which the LO signal leaks from the LO signal input terminal of the mixer 13 to the RF signal input terminal, is reflected by circuits such as the low-noise amplifier 12 located upstream of the mixer 13, and is input again to the mixer 13, causing an offset in the IF signal output from the mixer 13.

[0020] When the original LO signal and the leaked LO signal are mixed by mixer 13, the frequency difference component output from mixer 13 becomes a DC component that is not frequency-dependent, and this DC component appears as an offset in the IF signal. This is the case when ω1 = ω2 in equation (1), and can be seen from the fact that the second term, cos(θ-φ)t, is a constant that is not frequency-dependent. If the DC operating point of IF amplifier 15 deviates from the design value due to the offset of the IF signal, gain compression and distortion occur, making it impossible to achieve the expected amplification and noise performance (see Figure 2). As a result, the communication characteristics of wireless communication device 10X will be significantly degraded.

[0021] As shown in Figure 3, one possible measure to remove the DC offset component is to insert a capacitor 19 into the output line of mixer 13. This measure is effective when the frequency of the IF signal is sufficiently high so that the signal components contained in the IF signal are not included in the removal band. However, in systems where the IF signal frequency is wideband or systems that use the zero-IF method, the above measure cannot be adopted because there is a risk that the signal components will be removed by the capacitor.

[0022] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals. [First embodiment] 4 is a circuit block diagram showing an example of the configuration of a wireless communication device 10 according to an embodiment of the disclosed technology. Similar to the wireless communication device 10X according to the comparative example described above, the wireless communication device 10 includes an antenna 11, a low-noise amplifier 12, a mixer 13, a local oscillator (LO) 14, an IF amplifier 15, an analog-to-digital converter 16, a filter 17, and a logic circuit 18. The functions of these circuit blocks are the same as those of the wireless communication device 10X according to the comparative example, and therefore descriptions of these circuit blocks will be omitted.

[0023] The wireless communication device 10 includes difference detection circuits 20A and 20B, correction value generation circuits 21A and 21B, a memory 22, control voltage generation circuits 23A and 23B, and correction circuits 24A and 24B. The difference detection circuit 20A, the correction value generation circuit 21A, the control voltage generation circuit 23A, and the correction circuit 24A are circuit blocks that perform processing related to positive-phase signals among the differential signals processed in the wireless communication device 10. The difference detection circuit 20B, the correction value generation circuit 21B, the control voltage generation circuit 23B, and the correction circuit 24B are circuit blocks that perform processing related to negative-phase signals among the differential signals processed in the wireless communication device 10.

[0024] The wireless communication device 10 has two operating modes: a calibration mode and a normal mode. In the calibration mode, an LO signal is input to the mixer 13, but no RF signal is input. This causes the mixer 13 to output a DC voltage due to self-mixing. This DC voltage corresponds to the offset of the IF signal output from the mixer 13 in the normal mode. In other words, by inputting only the LO signal of the RF signal and the LO signal to the mixer 13, it is possible to extract the offset component of the IF signal generated by self-mixing.

[0025] In the calibration mode, the differential detection circuit 20A detects a DC voltage corresponding to an offset component generated on the positive phase side (positive phase signal) of the IF signal, which is a differential signal, and a reference voltage V ref1 The differential voltage V d1 Similarly, in the calibration mode, the differential detection circuit 20B outputs a DC voltage corresponding to the offset component generated on the reverse phase side (reverse phase signal) of the IF signal, which is a differential signal, and a reference voltage V ref2 The differential voltage V d2 The difference detection circuits 20A and 20B can be configured by, for example, a differential amplifier circuit.

[0026] In the calibration mode, the correction value generating circuit 21A calculates the differential voltage V output from the difference detection circuit 20A. d1Similarly, in the calibration mode, the correction value generation circuit 21B generates a correction value C1, which is a digital value corresponding to the voltage level of the differential voltage V d2 The memory 22 is a non-volatile storage medium such as a flash memory. The correction values ​​C1 and C2 are stored in the memory 22.

[0027] In the normal mode, an RF signal and an LO signal are input to the mixer 13. The mixer 13 mixes the RF signal and the LO signal to output an IF signal. The IF signal contains a DC offset component due to self-mixing. In the normal mode, the control voltage generation circuit 23A reads out a correction value C1 from the memory 22 and generates a control voltage V for controlling the correction circuit 24A based on the correction value C1. c1 Similarly, in the normal mode, the control voltage generating circuit 23B reads out the correction value C2 from the memory 22 and generates a control voltage V for controlling the correction circuit 24B based on the correction value C2. c2 The control voltage generating circuits 23A and 23B generate the control voltage V from the correction values ​​C1 and C2, which are digital values, respectively. c1 , V c2 The decoder includes a decoder for generating the

[0028] In the normal mode, the correction circuit 24A adjusts the control voltage V c1 The DC level of the positive phase side of the IF signal is corrected based on the control voltage V c1 The amount of correction of the DC level based on the control voltage V corresponds to the level of the DC voltage output from the mixer 13 in the calibration mode. That is, the correction circuit 24A operates to remove the offset component occurring on the positive phase side (positive phase signal) of the IF signal output from the mixer 13 in the normal mode. Similarly, the correction circuit 24B operates to remove the offset component occurring on the positive phase side (positive phase signal) of the IF signal output from the mixer 13 in the normal mode. c2 The DC level of the negative phase side of the IF signal is corrected based on the control voltage V c2The amount of correction of the DC level based on this corresponds to the level of the DC voltage output from the mixer 13 in the calibration mode. That is, the correction circuit 24B operates to remove the offset component occurring on the reverse phase side (reverse phase signal) of the IF signal output from the mixer 13 in the normal mode.

[0029] 5 is a flowchart showing an example of an operation sequence of the wireless communication device 10 operating in the calibration mode. In the calibration mode, the IF signal is not input to the mixer 13, but the LO signal is input. As a result, a DC voltage is output from the mixer 13 due to self-mixing. This DC voltage corresponds to the offset of the IF signal output from the mixer 13 in the normal mode.

[0030] In step S1, the difference detection circuits 20A and 20B respectively detect the DC voltage output from the mixer 13 and the reference voltage V ref1 , V ref2 The differential voltage V d1 , V d2 Output.

[0031] In step S2, the correction value generating circuits 21A and 21B respectively calculate the differential voltages V output from the difference detection circuits 20A and 20B in step S1. d1 , V d2 Based on this, digital correction values ​​C1 and C2 are generated.

[0032] In step S3, the correction value generating circuits 21A and 21B store in the memory 22 the correction values ​​C1 and C2 generated in step S2, respectively.

[0033] 6 is a flowchart showing an example of an operation sequence of the wireless communication device 10 operating in normal mode. In normal mode, an RF signal and an LO signal are input to the mixer 13. The mixer 13 mixes the RF signal and the LO signal to output an IF signal. The IF signal contains a DC offset component due to self-mixing.

[0034] In step S11, the control voltage generating circuits 23A and 23B read out the correction values ​​C1 and C2 from the memory 22, respectively.

[0035] In step S12, the control voltage generating circuits 23A and 23B generate the control voltages V based on the correction values ​​C1 and C2 read from the memory 22, respectively. c1 , V c2 and supplies these to the correction circuits 24A and 24B.

[0036] In step S13, the correction circuits 24A and 24B respectively apply the control voltage V c1 , V c2 The DC levels of the positive and negative phase sides of the IF signal are corrected based on the control voltage V c1 , V c2 The amount of DC level correction based on this corresponds to the level of the DC voltage output from mixer 13 in calibration mode. That is, correction circuits 24A and 24B operate to remove offset components that occur in the IF signal output from mixer 13 in normal mode. As a result, the positive and negative phase signals of the IF signal, whose DC level has been corrected, are input to analog-to-digital converter 16.

[0037] In step S14, the analog-to-digital converter 16 converts the output signal of the IF amplifier 15 into a digital value.

[0038] In step S15, the filter 17 performs a filtering process to pass a signal having a predetermined frequency component among a plurality of frequency components contained in the IF signal.

[0039] In step S16, the logic circuit 18 digitally demodulates the IF signal that has passed through the filter 17.

[0040] As is clear from the above description, the wireless communication device 10 according to the embodiment of the disclosed technique can suppress the DC offset component generated in the IF signal due to self-mixing without removing the signal component. Furthermore, since the correction amount for the DC level of the IF signal is determined based on the DC voltage output from the mixer when an LO signal is input without inputting an RF signal, it is possible to appropriately remove the offset component of the IF signal. Furthermore, since the correction amount for the DC level of the IF signal is determined based on the correction values ​​C1 and C2 generated for each individual wireless communication device 10, it is possible to set an optimal correction amount for each individual wireless communication device 10.

[0041] [Second embodiment] 7 is a circuit block diagram showing an example of the configuration of a wireless communication device 10A according to a second embodiment of the disclosed technology. The wireless communication device 10A uses an analog-to-digital converter 16 to perform digital conversion processing required to generate a correction value for correcting the direct current level (DC level) of an IF signal. To achieve this, the wireless communication device 10A has a positive phase side switching circuit 25 and a negative phase side switching circuit 26.

[0042] The positive phase side switching circuit 25 switches whether the signal input to one input terminal of the analog-digital converter 16 is the positive phase side of the IF signal (positive phase signal) or the reference voltage. The positive phase side switching circuit 25 has a switch 27A and a switch 27B. One end of the switch 27A is connected to the positive phase side output terminal of the IF amplifier 15, and the other end is connected to one input terminal of the analog-digital converter 16. The switch 27B has one end connected to the reference voltage V ref3 and the other end is connected to one input end of the analog-to-digital converter 16. The switches 27A and 27B operate such that when one is in the on state, the other is in the off state.

[0043] The negative phase switching circuit 26 switches the signal input to the other input terminal of the analog-digital converter 16 between the negative phase side of the IF signal (negative phase signal) or the reference voltage. The negative phase switching circuit 26 has a switch 28A and a switch 28B. One end of the switch 28A is connected to the negative phase output terminal of the IF amplifier 15, and the other end is connected to the other input terminal of the analog-digital converter 16. The switch 28B has one end connected to the reference voltage V ref4 and the other end is connected to the other input end of the analog-to-digital converter 16. The switches 28A and 28B operate such that when one is in the on state, the other is in the off state.

[0044] 8 is a diagram showing the state of each switch when generating a correction value for the positive phase side of the IF signal in the calibration mode. In this case, the positive phase switch 27A and the negative phase switch 28B are turned on, and the positive phase switch 27B and the negative phase switch 28A are turned off. As a result, a DC voltage corresponding to the offset component generated on the positive phase side (positive phase signal) of the IF signal and a reference voltage V ref4 is input to the analog-to-digital converter 16, and a digital value corresponding to the offset component is output from the analog-to-digital converter 16. In the calibration mode, the correction value generation circuit 21 generates a correction value C1 for removing the offset component occurring on the positive phase side (positive phase signal) of the IF signal based on the digital value output from the analog-to-digital converter 16, and stores this in the memory 22.

[0045] 9 is a diagram showing the state of each switch when generating a correction value for the negative phase side of the IF signal in the calibration mode. In this case, the negative phase side switch 28A and the positive phase side switch 27B are turned on, and the negative phase side switch 28B and the positive phase side switch 27A are turned off. As a result, a DC voltage corresponding to the offset component generated on the negative phase side (negative phase signal) of the IF signal and a reference voltage V ref3is input to the analog-to-digital converter 16, and a digital value corresponding to the offset component is output from the analog-to-digital converter 16. In the calibration mode, the correction value generation circuit 21 generates a correction value C2 for removing the offset component occurring on the negative phase side (negative phase signal) of the IF signal based on the digital value output from the analog-to-digital converter 16, and stores this in the memory 22.

[0046] In the normal mode, as shown in FIG. 7, the positive phase switch 27A and the negative phase switch 28A are turned on, and the positive phase switch 27B and the negative phase switch 28B are turned off.

[0047] In the normal mode, the control voltage generating circuit 23 reads the correction value C1 from the memory 22 and generates a control voltage V for controlling the correction circuit 24A based on the correction value C1. c1 In the normal mode, the control voltage generating circuit 23 reads the correction value C2 from the memory 22 and generates a control voltage V for controlling the correction circuit 24B based on the correction value C2. c2 Generate.

[0048] In the normal mode, the correction circuit 24A adjusts the control voltage V c1 In this embodiment, the correction circuit 24A corrects the output of the IF amplifier 15 on the positive phase side. In the normal mode, the correction circuit 24B corrects the direct current level (DC level) of the IF signal on the positive phase side based on the control voltage V c2 In this embodiment, the correction circuit 24B corrects the output of the negative phase side of the IF amplifier 15. The positive phase signal and the negative phase signal of the IF signal whose DC levels have been corrected are input to the analog-to-digital converter 16.

[0049] According to the wireless communication device 10A of the second embodiment of the disclosed technology, similarly to the wireless communication device 10 of the first embodiment, it is possible to suppress a DC offset component generated in an IF signal due to self-mixing without removing the signal component. Furthermore, since the correction amount of the DC level of the IF signal is determined based on the DC voltage output from the mixer when an LO signal is input without inputting an RF signal, it is possible to appropriately remove the offset component of the IF signal. Furthermore, since the correction amount of the DC level of the IF signal is determined based on correction values ​​C1 and C2 generated for each individual wireless communication device 10, it is possible to set an optimal correction amount for each individual wireless communication device 10. Furthermore, since the digital conversion process required to generate a correction value for correcting the DC level of the IF signal is performed using an analog-to-digital converter 16, it is possible to reduce the size of the correction value generation circuit compared to the wireless communication device 10 of the first embodiment. [Explanation of symbols]

[0050] 10, 10A, 10X wireless communication device 11 Antenna 12 Low-noise amplifier 13 Mixer 14 Local Oscillator 15 IF amplifier 16 Analog-to-Digital Converter 17 Filters 18 Logic Circuits 19 Capacitor 20A, 20B differential detection circuit 21A, 21B Correction value generation circuit 22 Memory 23 Correction value generation circuit 23, 23A, 23B Control voltage generation circuit 24A, 24B compensation circuit 25 Positive phase switching circuit 26 Negative phase side switching circuit 27A, 27B, 28A, 28B switches

Claims

1. a mixer that mixes a radio frequency signal with a local oscillation signal and outputs an intermediate frequency signal; The level of the DC component included in the intermediate frequency signal is corrected based on a DC voltage output from the mixer when the radio frequency signal is not input to the mixer and the local oscillation signal is input to the mixer. Wireless communication device.

2. a correction value generating circuit that generates a correction value according to a DC voltage output from the mixer when the radio frequency signal is not input to the mixer and the local oscillation signal is input to the mixer; a memory that stores the correction value; a control voltage generating circuit that generates a control voltage based on the correction value stored in the memory; a correction circuit that corrects the DC level of the intermediate frequency signal based on the control voltage; 10. The wireless communication device of claim 1, comprising:

3. a difference detection circuit that outputs a voltage corresponding to the difference between a DC voltage output from the mixer when the radio frequency signal is not input to the mixer and the local oscillation signal is input to the mixer and a predetermined reference voltage; The correction value generation circuit generates the correction value based on the output of the difference detection circuit. The wireless communication device according to claim 2 .

4. an analog-to-digital converter that converts a DC voltage output from the mixer into a digital value when the radio frequency signal is not input to the mixer and the local oscillation signal is input to the mixer, The correction value generation circuit generates the correction value based on the digital value output from the analog-to-digital converter. The wireless communication device according to claim 2 .

5. the intermediate frequency signal is a differential signal including a positive phase signal and a negative phase signal, a positive phase side switching circuit that switches a signal input to one input terminal of the analog-to-digital converter between the positive phase signal and a reference voltage; a negative phase side switching circuit that switches the signal input to the other input terminal of the analog-to-digital converter between the negative phase signal and a reference voltage; have 5. The wireless communication device according to claim 4.

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