Semiconductor device

Abstract

To suppress the number of pads to be used to transmit and receive signals between a plurality of semiconductor chips in a semiconductor device having the plurality of semiconductor chips.SOLUTION: A semiconductor device includes: a first semiconductor chip having a plurality of first pads; and a second semiconductor chip having a plurality of second pads connected to each of the plurality of first pads. The first semiconductor chip includes a first multiplexer that allocates a signal corresponding to a selected function among the plurality of functions to a part of the plurality of first pads. The second semiconductor chip includes: a plurality of third pads to which a signal from an outside is input or to which a signal from the outside is output; and a second multiplexer that allocates a selected part of the signals input and output through the plurality of second pads to the plurality of third pads.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The disclosed technology relates to a semiconductor device. [Background technology]

[0002] The following technologies are known as technologies related to semiconductor devices with a multi-chip configuration having multiple semiconductor chips. For example, Patent Document 1 describes a multi-chip package semiconductor device including: a first semiconductor chip having multiple input / output pins and multiple first pads for connecting chips and configured to be able to supply test signals to each of the multiple first pads; a second semiconductor chip having multiple second pads for connecting chips, a third pad electrically connected to a test pin that is one of the multiple input / output pins, and a first selector that receives multiple signals generated at the multiple second pads, selects one of the signals, and outputs it to the third pad; and multiple inter-chip wirings, each connecting a corresponding one of the multiple first pads of the first semiconductor chip to a corresponding one of the multiple second pads of the second semiconductor chip.

[0003] Patent Document 2 describes an I / O semiconductor chip provided in a multi-chip module having multiple semiconductor chips and multiple external terminals. The I / O semiconductor chip has an input / output function unit consisting of multiple input / output circuits provided between the multiple semiconductor chips and the multiple external terminals. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-26463 [Patent Document 2] Japanese Patent Application Laid-Open No. 2002-270759 Summary of the Invention [Problem to be solved by the invention]

[0005] In a multi-chip semiconductor device having a first semiconductor chip and a second semiconductor chip, the total number of signals used in the multiple functions of the semiconductor device is assumed to be greater than the total number of external terminals of the semiconductor device. In this case, it is conceivable that selected functions of the multiple functions of the semiconductor device are assigned to the external terminals, and the remaining functions are left unused. In order to increase the versatility of the semiconductor device, all functions may be selectively made available.

[0006] In a configuration in which external terminals are provided only on the second semiconductor chip and access to the first semiconductor chip is possible only via the second semiconductor chip, it is necessary to enable transmission and reception of all signals used in the multiple functions between the first semiconductor chip and the second semiconductor chip 2 in order to selectively enable all functions. To achieve this, a configuration is conceivable in which the first semiconductor chip and the second semiconductor chip each have pads equal in number to the total number of signals used in the multiple functions and the corresponding pads are connected to each other. However, this would require an enormous number of pads, and the number of signal processing circuits, such as level shifters, associated with each pad would also be enormous. As a result, the area of ​​the first semiconductor chip and the second semiconductor chip would increase, leading to increased costs.

[0007] The disclosed technology has been made in consideration of the above points, and aims to reduce the number of pads used for transmitting and receiving signals between multiple semiconductor chips in a semiconductor device having multiple semiconductor chips. [Means for solving the problem]

[0008] The semiconductor device according to the disclosed technology includes a first semiconductor chip having a plurality of first pads and a second semiconductor chip having a plurality of second pads connected to each of the plurality of first pads. The first semiconductor chip has a first multiplexer that assigns signals corresponding to a selected function from among a plurality of functions to some of the plurality of first pads. The second semiconductor chip has a plurality of third pads to which external signals are input or output, and a second multiplexer that assigns a selected portion of the signals input / output via the plurality of second pads to the plurality of third pads. [Effects of the Invention]

[0009] According to the present invention, in a semiconductor device having a plurality of semiconductor chips, it is possible to reduce the number of pads used for transmitting and receiving signals between the plurality of semiconductor chips. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a perspective view illustrating an example of a configuration of a semiconductor device according to an embodiment of the disclosed technique; [Figure 2] 1 is a circuit block diagram showing an example of the configuration of a first semiconductor chip and a second semiconductor chip according to an embodiment of the disclosed technique. [Figure 3] FIG. 2 is a circuit block diagram showing an example of the configuration of a first semiconductor chip and a second semiconductor chip according to a comparative example. [Figure 4] FIG. 10 is a diagram showing an example of the total number of inner pads provided on each of a first semiconductor chip and a second semiconductor chip according to a comparative example. [Figure 5] 10 is a diagram showing an example of the total number of inner pads provided on each of a first semiconductor chip and a second semiconductor chip according to the embodiment of the disclosed technique. FIG. [Figure 6] FIG. 10 is a circuit block diagram showing an example of the configuration of a first semiconductor chip and a second semiconductor chip according to another embodiment of the disclosed technique. [Figure 7]FIG. 10 is a circuit block diagram showing an example of the configuration of a first semiconductor chip and a second semiconductor chip according to another embodiment of the disclosed technique. [Figure 8] FIG. 10 is a circuit block diagram showing an example of the configuration of a first semiconductor chip and a second semiconductor chip according to another embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals.

[0012] [First embodiment] FIG. 1 is a perspective view showing an example of the configuration of a semiconductor device 100 according to an embodiment of the disclosed technology. The semiconductor device 100 has a multi-chip configuration including a first semiconductor chip 1 and a second semiconductor chip 2. The first semiconductor chip 1 is, for example, a general-purpose core chip and has general-purpose functional units such as a CPU and memory. The second semiconductor chip 2 is, for example, a custom chip and has functional units for realizing specific functions according to the application. The applications and functions of the first semiconductor chip 1 and the second semiconductor chip 2 are not particularly limited.

[0013] The first semiconductor chip 1 and the second semiconductor chip 2 each have a plurality of pads arranged in a grid pattern on the surface of a semiconductor substrate. The first semiconductor chip 1 and the second semiconductor chip 2 are electrically and mechanically connected to each other by joining the pads together using a conductive bonding material such as solder. The area of ​​the second semiconductor chip 2 is larger than the area of ​​the first semiconductor chip 1, and the first semiconductor chip 1 is stacked on top of the second semiconductor chip 2. After the first semiconductor chip 1 and the second semiconductor chip 2 are connected, the first semiconductor chip 1 can only be accessed via the second semiconductor chip 2.

[0014] FIG. 2 is a circuit block diagram showing an example of the configuration of a first semiconductor chip 1 and a second semiconductor chip 2. The first semiconductor chip 1 has multiple functions. FIG. 2 shows a first function f1, a second function f2, a third function f3, and an n-th function fn. The first semiconductor chip 1 has a processing circuit (not shown) for realizing each of these multiple functions. In this embodiment, the first function f1 and the second function f2 are selectively used. That is, one of the first function f1 and the second function f2 is used, and the other is unused. The first semiconductor chip 1 has a multiplexer (MUX) 10 and multiple inner pads 11 (11A, 11B, 11C, 11Z).

[0015] The multiplexer 10 assigns a signal corresponding to a selected function from the first function f1 and the second function f2 to some of the inner pads 11A among the multiple inner pads 11. For example, when the first function f1 is selected, one or more signals corresponding to the first function f1 are input / output via one or more inner pads 11A. In this case, the second function f2 is unused. On the other hand, when the second function f2 is selected, one or more signals corresponding to the second function f2 are input / output via one or more inner pads 11A. In this case, the first function f1 is unused. The multiplexer 10 selects one of the first function f1 and the second function f2 based on a selection signal S1 supplied via the bus 30. The selection signal S1 can be set by, for example, a user and is supplied to the first semiconductor chip 1 via the second semiconductor chip 2 from outside the semiconductor device 100. The multiplexer 10 is an example of a “first multiplexer” in the disclosed technology.

[0016] One or more signals corresponding to the third function f3 are input / output via one or more inner pads 11B. One or more signals corresponding to the n-th function fn are input / output via one or more inner pads 11C. The bus 30 is connected to the inner pad 11Z. The inner pad 11 is an example of a "first pad" in the disclosed technology.

[0017] The second semiconductor chip 2 has a multiplexer (MUX) 20, multiple inner pads 21 (21A, 21B, 21C, 21Z), and multiple IO pads 22. The inner pads 21A, 21B, 21C, and 21Z of the second semiconductor chip 2 correspond to the inner pads 11A, 11B, 11C, and 11Z of the first semiconductor chip 1, respectively, and the corresponding inner pads are connected to each other. Signals are transmitted and received between the first semiconductor chip 1 and the second semiconductor chip 2 via these inner pads. Therefore, one or more signals corresponding to the first function f1 or the second function f2 are input / output via one or more inner pads 21A. One or more signals corresponding to the third function f3 are input / output via one or more inner pads 21B. One or more signals corresponding to the n-th function fn are input / output via one or more inner pads 21C. The bus 30 is connected to the inner pad 21Z. The inner pad 21 is an example of a "second pad" in the technology disclosed herein.

[0018] The multiple IO pads 22 function as external terminals, and transmission and reception of signals to and from an external system are performed via the multiple IO pads 22. The first semiconductor chip 1 does not have an IO pad, and access to the first semiconductor chip 1 can only be performed via the second semiconductor chip 2. The IO pads 22 are an example of a "third pad" in the disclosed technology.

[0019] The multiplexer 20 assigns a selected portion of the signals input / output via the multiple inner pads 21 (21A, 21B, 21C) to the multiple IO pads 22. The multiplexer 20 selects the signals to be assigned to the IO pads 22 based on a selection signal S2 supplied via a bus 30. The selection signal S2 can be set by, for example, a user and is supplied from outside the semiconductor device 100. The multiplexer 20 is an example of a "second multiplexer" in the disclosed technology.

[0020] The total number of the multiple IO pads 22 is set to be less than the total number of signals used in the first to n-th functions f1 to fn of the first semiconductor chip 1. Therefore, in the semiconductor device 100, it is not possible to use all of the first to n-th functions f1 to fn simultaneously. Only some of the first to n-th functions f1 to fn are enabled, and the other functions are not used. Selection of the enabled functions from the first to n-th functions f1 to fn is performed by multiplexers 10 and 20 selecting signals to be assigned to the inner pads 11 and IO pads 22.

[0021] 3 is a circuit block diagram showing an example of the configuration of a first semiconductor chip 1X and a second semiconductor chip 2X included in a semiconductor device 100X according to a comparative example. The semiconductor device 100X according to the comparative example differs from the semiconductor device 100 according to the embodiment of the disclosed technique described above in that the first semiconductor chip 1X does not have a multiplexer.

[0022] The total number of the IO pads 22 included in the second semiconductor chip 2X is set to be smaller than the total number of signals used in the first to n-th functions f1 to fn included in the first semiconductor chip 1X. Therefore, in the semiconductor device 100X, it is not possible to use all of the first to n-th functions f1 to fn simultaneously. Only some of the first to n-th functions f1 to fn are enabled, and the other functions are not used. Selection of the enabled functions from the first to n-th functions f1 to fn is performed by the multiplexer 20 included in the second semiconductor chip 2X.

[0023] In order to enable selective use of all of the first to n-th functions f1 to fn, it is necessary to enable transmission and reception of all signals used in the first to n-th functions f1 to fn between the first semiconductor chip 1X and the second semiconductor chip 2X. Therefore, in the semiconductor device 100X according to the comparative example, inner pads 11 and 21 are assigned to each of the first to n-th functions f1 to fn. In the semiconductor device 100X according to the comparative example, the same number of inner pads 11 and 21 as the total number of signals used in the first to n-th functions f1 to fn are provided.

[0024] FIG. 4 is a diagram illustrating an example of the total number of inner pads 11, 21 provided on a first semiconductor chip 1X and a second semiconductor chip 2X, respectively, in a semiconductor device 100X according to a comparative example. In the example illustrated in FIG. 4, the first semiconductor chip 1 has a first function f1, a second function f2, a third function f3, a fourth function f2, and a fifth function f5. The number of signals used in the first function f1 is 50. The number of signals used in the first function f2 is 40. The number of signals used in the third function f3 is 30. The number of signals used in the fourth function f4 is 20. The number of signals used in the fifth function f5 is 20. In the semiconductor device 100X according to the comparative example, the total number of signals used in the first to fifth functions f1 to f5 is 160, and the number of inner pads 11, 21 required in each of the first semiconductor chip 1X and the second semiconductor chip 2 is the same as the total number of signals, 160. In the example illustrated in FIG. 4, the number of IO pads 22 is 100, which is less than the total number of signals, 160. FIG. 4 illustrates an example in which 100 signals corresponding to the first function f1, the third function f3, and the fourth function f4, among the first to fifth functions f1 to f5, are assigned to the IO pad 22 by the multiplexer 20.

[0025] FIG. 5 is a diagram illustrating an example of the total number of inner pads 11, 21 provided on the first semiconductor chip 1 and the second semiconductor chip 2, respectively, in a semiconductor device 100 according to an embodiment of the disclosed technology. In the example illustrated in FIG. 5, the first semiconductor chip 1 has a first function f1, a second function f2, a third function f3, a fourth function f2, and a fifth function f5, similar to the semiconductor device 100X according to the comparative example. The number of signals used in each of these functions is the same as that of the semiconductor device 100X according to the comparative example. The first semiconductor chip 1 has a multiplexer 10 that assigns signals corresponding to a selected function from the first function f1 and the second function f2 to some of the inner pads 11. According to the semiconductor device 100 according to the embodiment of the disclosed technology, the number of inner pads 11, 21 required in each of the first semiconductor chip 1 and the second semiconductor chip 2 is 120, which is fewer than the number of inner pads 11, 21 (160) required in the semiconductor device 100X according to the comparative example.

[0026] As described above, according to the semiconductor device 100 relating to the embodiment of the disclosed technology, it is possible to reduce the number of inner pads 11, 21 used for transmitting and receiving signals between the first semiconductor chip 1 and the second semiconductor chip 2.

[0027] In the above description, the functions selected by the multiplexer 10 are the first function f1 and the second function f2, but the disclosed technology is not limited to this. The number and combination of functions to be selected by the multiplexer 10 can be changed as appropriate. In the above description, the first semiconductor chip 1 includes one multiplexer 10, but the disclosed technology is not limited to this. For example, the first semiconductor chip 1 may include a multiplexer that assigns a signal corresponding to a function selected from the first and second functions to a portion of the inner pads 11, and another multiplexer that assigns a signal corresponding to a function selected from the third and fourth functions to another portion of the inner pads 11.

[0028] [Second embodiment] The semiconductor device 100 according to the first embodiment described above has a restriction that multiple functions (in the example shown in FIG. 2, the first function f1 and the second function f2) that are to be selected by the multiplexer 10 cannot be used simultaneously, which poses a problem in the versatility of the semiconductor device. The semiconductor device according to the second embodiment described below relaxes the restriction on the functions that can be used simultaneously.

[0029] FIG. 6 is a circuit block diagram showing an example of the configuration of a first semiconductor chip 1A and a second semiconductor chip 2A included in a semiconductor device 100A according to a second embodiment of the disclosed technology. The first semiconductor chip 1A includes multiplexers 10A and 10B. The multiplexer 10A assigns a signal corresponding to a selected function of the first function f1 and the second function f2 to an inner pad 11A. The multiplexer 10B assigns a signal corresponding to a selected function of the second function f2 and the third function f3 to an inner pad 11B. In other words, the second function f2 is selected by the multiplexer 10A and is also selected by the multiplexer 10B. The multiplexer 10A is an example of a "first multiplexer" in the disclosed technology, and the multiplexer 10B is an example of a "third multiplexer" in the disclosed technology.

[0030] According to the semiconductor device 100A of the second embodiment, the multiplexer 10A selects the first function f1 and the multiplexer 10B selects the second function f2, thereby enabling simultaneous use of the first function f1 and the second function f2. Furthermore, the multiplexer 10A selects the first function f1 and the multiplexer 10B selects the third function f3, thereby enabling simultaneous use of the first function f1 and the third function f3. The multiplexer 10A selects the second function f2 and the multiplexer 10B selects the third function f3, thereby enabling simultaneous use of the second function f2 and the third function f3. Thus, according to the semiconductor device 100A of the second embodiment, it is possible to relax restrictions on the functions that can be used simultaneously.

[0031] [Third embodiment] In the semiconductor devices 100, 100A according to the first and second embodiments described above, the functions selected in the multiplexers 10, 10A, and 10B provided in the first semiconductor chips 1 and 1A are set by the user. However, because the inner pads 11 and 21 are internal components that are not visible to the user, it is considered undesirable from the standpoint of convenience to have the user set the functions selected in the multiplexers 10, 10A, and 10B. The semiconductor device according to the third embodiment described below improves convenience with regard to setting the functions selected in the multiplexers provided in the first semiconductor chip.

[0032] 7 is a circuit block diagram showing an example of the configuration of a first semiconductor chip 1B and a second semiconductor chip 2B included in a semiconductor device 100B according to a third embodiment of the disclosed technique. The second semiconductor chip 2B according to the third embodiment includes a detection circuit 23.

[0033] The detection circuit 23 detects the allocation status of signals to the IO pads 22 in the multiplexer 20 based on the selection signal S2. In other words, the detection circuit 23 detects which inner pad 21 is associated with which IO pad 22. The detection circuit 23 generates information I a This information I is then supplied to the first semiconductor chip 1B. a By this, it is possible to specify which functions are to be used and which functions are to be unused among the first to n-th functions f1 to fn. a A function is selected based on the above, and a signal corresponding to the selected function is assigned to a part of the inner pad 11.

[0034] For example, if the information Ia indicating the allocation status of signals to the IO pads 22 in the multiplexer 20 indicates that the first function f1 and the second function f2 are in use and the third function f3 is unused, the multiplexer 10A assigns the signal corresponding to the first function f1 to the inner pad 11A, and the multiplexer 20B assigns the signal corresponding to the second function f2 to the inner pad 11B.

[0035] According to the semiconductor device 100B of the third embodiment, the user does not need to set the functions to be selected in the multiplexers 10A and 10B provided in the first semiconductor chip 1B, thereby improving convenience.

[0036] [Fourth embodiment] The semiconductor device according to the fourth embodiment described below, like the semiconductor device 100B according to the third embodiment described above, improves convenience in setting the functions selected in the multiplexer provided in the first semiconductor chip.

[0037] 8 is a circuit block diagram showing an example of the configuration of a first semiconductor chip 1C and a second semiconductor chip 2C included in a semiconductor device 100C according to a fourth embodiment of the disclosed technique. The first semiconductor chip 1C according to the fourth embodiment includes a storage unit 15. The storage unit 15 stores information I, which indicates the function to be selected in each of the multiplexers 10A and 10B included in the first semiconductor chip 1C. b The multiplexers 10A and 10B are non-volatile storage media such as flash memory that store information I b A function is selected based on the above, and a signal corresponding to the selected function is assigned to a part of the inner pad 11.

[0038] The semiconductor device 100C according to the fourth embodiment does not require the user to set the functions to be selected in the multiplexers 10A and 10B provided in the first semiconductor chip 1C, thereby improving convenience. The semiconductor device 100C according to the fourth embodiment has a configuration that can be adopted, for example, when unused functions are determined by the specifications of the second semiconductor chip 2C. [Explanation of symbols]

[0039] 1, 1A, 1B, 1C, 1X First semiconductor chip 2, 2A, 2B, 2C, 2X Second semiconductor chip 10, 10A, 10B Multiplexer 11, 11A, 11B, 11C, 11Z inner pad 20 Multiplexer 21, 21A, 21B, 21C, 21Z inner pad 22 IO Pad 100, 100A, 100B, 100C, 100X Semiconductor Devices

Claims

1. A semiconductor device including a first semiconductor chip having a plurality of first pads and a second semiconductor chip having a plurality of second pads connected to each of the plurality of first pads, the first semiconductor chip has a first multiplexer that assigns a signal corresponding to a selected function from among a plurality of functions to a part of the plurality of first pads; The second semiconductor chip includes: a plurality of third pads to which external signals are input or output; a second multiplexer that assigns a selected portion of a plurality of signals input / output via the plurality of second pads to the plurality of third pads; have Semiconductor device.

2. The first semiconductor chip has a third multiplexer that assigns a signal corresponding to a selected function from among a plurality of functions including at least some of the functions to be selected by the first multiplexer to another part of the plurality of first pads. The semiconductor device according to claim 1 .

3. the second semiconductor chip outputs information indicating a signal assignment status to the plurality of third pads in the second multiplexer; The first multiplexer assigns a signal corresponding to a function selected based on the information to a portion of the first pads. The semiconductor device according to claim 1 .

4. the second semiconductor chip outputs information indicating a signal assignment status to the plurality of third pads in the second multiplexer; Each of the first multiplexer and the third multiplexer assigns a signal corresponding to a function selected based on the information to a part of the plurality of first pads. The semiconductor device according to claim 2 .

5. the first semiconductor chip has a storage unit that stores information indicating a function to be selected by the first multiplexer; The first multiplexer assigns a signal corresponding to a function selected based on the information to a portion of the first pads. The semiconductor device according to claim 1 .

6. the first semiconductor chip has a storage unit that stores information indicating a function to be selected in each of the first multiplexer and the third multiplexer; Each of the first multiplexer and the third multiplexer assigns a signal corresponding to a function selected based on the information to a part of the plurality of first pads. The semiconductor device according to claim 2 .

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