Light-emitting element

Abstract

To provide a light-emitting element capable of reducing a forward voltage.SOLUTION: A light-emitting element includes: a conductive member disposed on a substrate; a first insulating layer disposed on the conductive member; a semiconductor structure including a first light-emitting part and a second light-emitting part disposed on the first insulating layer and spaced apart from each other, in which each of the first and second light-emitting parts includes a first semiconductor layer of a first conductivity type, a light-emitting layer, and a second semiconductor layer of a second conductivity type; first wiring electrically connected to the first semiconductor layer of the first light-emitting part; second wiring electrically connected to the second semiconductor layer of the first light-emitting part and the first semiconductor layer of the second light-emitting part; third wiring electrically connected to the second semiconductor layer of the second light-emitting part; and a first pad electrode electrically connected to the first wiring and a second pad electrode electrically connected to the third wiring, which are separated from the semiconductor structure in plan view. The first wiring is in contact with the conductive member through one or two or more first openings of the first insulating layer, and the second wiring and the third wiring are not in contact with the conductive member.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to light-emitting devices. [Background technology]

[0002] A light emitting device has been proposed in which two active regions connected in series to each other are provided on one substrate (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2015-533022 [Patent Document 2] Patent Publication No. 2021-34652 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional light emitting elements, it is required to reduce the forward voltage.

[0005] An object of the present disclosure is to provide a light-emitting element capable of reducing the forward voltage. [Means for solving the problem]

[0006] According to one aspect of the technique of the present disclosure, a light-emitting element is a semiconductor structure including a substrate, a conductive member disposed on the substrate, a first insulating layer disposed on the conductive member, and a first light-emitting portion and a second light-emitting portion disposed apart from each other on the first insulating layer, wherein each of the first light-emitting portion and the second light-emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light-emitting portion; and the second semiconductor layer of the first light-emitting portion. the first insulating layer has one or more first openings, the first wiring is in contact with the conductive member through the one or more first openings, and the second wiring and the third wiring are not in contact with the conductive member. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a light-emitting element capable of reducing the forward voltage. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a top view showing some of the components of the light-emitting device according to the first embodiment. [Figure 2] 1 is an exploded top view showing some of the components of the light-emitting device according to the first embodiment. [Figure 3] 1 is a cross-sectional view showing a light-emitting element according to a first embodiment. [Figure 4] FIG. 10 is a top view showing some of the components of the light-emitting device according to the second embodiment. [Figure 5] FIG. 10 is an exploded top view showing some of the components of the light-emitting device according to the second embodiment. [Figure 6]FIG. 4 is a cross-sectional view showing a light-emitting element according to a second embodiment. [Figure 7] FIG. 10 is a top view showing some of the components of the light-emitting device according to the third embodiment. [Figure 8] FIG. 10 is a top view showing some of the components of the light-emitting device according to the fourth embodiment. [Figure 9] FIG. 10 is an exploded top view showing some of the components of the light-emitting device according to the fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a light-emitting element according to a fourth embodiment. [Figure 11] FIG. 10 is a top view showing some of the components of the light-emitting device according to the fifth embodiment. [Figure 12] 10A and 10B are top views showing modified examples of the arrangement of n-type semiconductor layers and pad electrodes. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments for carrying out the present disclosure will be described with reference to the drawings. The following description is intended to embody the technical idea of ​​the present disclosure, and unless otherwise specified, the present disclosure is not limited to the following description.

[0010] In each drawing, components having the same function may be designated by the same reference numeral. For convenience, the following embodiments may be shown separately to facilitate easy explanation or understanding. However, partial substitution or combination of the configurations shown in different embodiments or examples is possible. In the following embodiments, differences from the previously shown embodiments will be mainly described, and overlapping descriptions of common features may be omitted. The size and positional relationships of components shown in each drawing may be exaggerated for clarity. To avoid overly complex drawings, some elements may be omitted, or end views showing only the cut surface may be used as cross-sectional views. The following description uses an XYZ Cartesian coordinate system, but this coordinate system is defined for explanatory purposes and does not limit the orientation of the substrate, etc. From an arbitrary point, the +Z side may be referred to as the upper side, top, or top, and the -Z side may be referred to as the lower side, bottom, or bottom. A view along the Z direction is referred to as a "planar view."

[0011] (First embodiment) First, the light-emitting device according to the first embodiment will be described. Fig. 1 is a top view showing some of the components of the light-emitting device according to the first embodiment. Fig. 2 is an exploded top view showing some of the components of the light-emitting device according to the first embodiment. Fig. 3 is a cross-sectional view showing the light-emitting device according to the first embodiment. Fig. 3 corresponds to the cross-sectional view taken along line III-III in Fig. 1.

[0012] The light-emitting element 1 of the first embodiment has a substrate 10, a conductive member 20, a first insulating layer 30, a second insulating layer 40, a third insulating layer 50, a first pad electrode 61, a second pad electrode 62, light-reflective conductive layers 71 and 72, a semiconductor structure 100, a first wiring 210, a second wiring 220, and a third wiring 230.

[0013] The substrate 10 is, for example, an insulating substrate. The substrate 10 may be a semiconductor substrate or a conductive substrate. The substrate 10 has a square shape in a planar view. When the substrate 10 has a square shape in a planar view, the length of one side of the substrate 10 is, for example, 500 μm or more and 3000 μm or less. In a planar view, the substrate 10 has vertices 11, 12, 13, and 14. The vertex 11 is a vertex on the −X side and −Y side of the center of the substrate 10. The vertex 12 is a vertex on the +X side and −Y side of the center of the substrate 10. The vertex 13 is a vertex on the +X side and +Y side of the center of the substrate 10. The vertex 14 is a vertex on the −X side and +Y side of the center of the substrate 10. The substrate 10 may be, for example, a silicon substrate. The thickness of the substrate 10 is, for example, 100 μm or more and 1000 μm or less.

[0014] Layer 2A in FIG. 2 shows the arrangement of the first wiring 210, the second wiring 220, and the third wiring 230 relative to the substrate 10. Layer 2B in FIG. 2 shows the arrangement of the opening 31 in the first insulating layer 30, the arrangement of the openings 41, 42, 43, and 44 in the second insulating layer 40, and the arrangement of the regions 216, 226, 227, and 236 within the openings 41, 42, 43, and 44 of the first wiring 210, the second wiring 220, and the third wiring 230 relative to the substrate 10. Layer 2C in FIG. 2 shows the arrangement of the n-type semiconductor layers 112 and 122 included in the semiconductor structure 100 relative to the substrate 10. In addition, the two vertices 11 and 13 of the substrate 10 are connected by dashed double-dashed lines between layers 2A, 2B, and 2C.

[0015] As shown in FIG. 3, the conductive member 20 is disposed on the substrate 10. The conductive member 20 includes a metal layer such as solder. The conductive member 20 has a thickness of, for example, 3 μm or more and 10 μm or less. The first insulating layer 30 is disposed on the conductive member 20. The first insulating layer 30 is, for example, a layer including at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first wiring 210, the second wiring 220, and the third wiring 230 are disposed on the first insulating layer 30. The first insulating layer 30 has a thickness of, for example, 0.1 μm or more and 2 μm or less.

[0016] As shown in FIGS. 1 and 2 , in a plan view, the first wiring 210 is arranged inside a triangle whose three vertices are vertices 11, 12, and 14. The first wiring 210 has a connection portion 450 and an extension portion 460. The connection portion 450 is arranged near vertex 11. The extension portion 460 is connected to the connection portion 450 and extends from the connection portion 450. A first pad electrode 61 is connected to the connection portion 450. The outline of the extension portion 460 in a plan view has a portion parallel to the side connecting vertices 11 and 12, a portion parallel to the diagonal line 92 connecting vertices 12 and 14, and a portion parallel to the side connecting vertices 14 and 11. In a plan view, the extension portion 460 has multiple portions extending in a direction parallel to the diagonal line 91 connecting vertices 11 and 13. In a plan view, a portion of the second wiring 220 is located between the multiple portions of the extension portion 460. In the direction parallel to the diagonal line 92, parts of the first wiring 210 and extensions 221 of the second wiring 220 described later are arranged alternately.

[0017] 1 and 2, the third wiring 230 has connection portions 412, 413, and 414 and an extension portion 420. The connection portion 412 is arranged near the vertex 12, the connection portion 413 is arranged near the vertex 13, and the connection portion 414 is arranged near the vertex 14. The extension portion 420 is connected to the connection portions 412, 413, and 414 and extends from the connection portions 412, 413, and 414. A second pad electrode 62 is connected to each of the connection portions 412, 413, and 414. The extension portion 420 has a first extension portion 421 and a plurality of second extension portions 422. In a plan view, the first extension portion 421 extends from the connection portions 412 and 413 in a direction parallel to the outer edge of the semiconductor structure 100. A portion of the first extending portion 421 extends in a direction parallel to the outer edge of the semiconductor structure 100 between the connecting portion 412 and the connecting portion 413, and another portion of the first extending portion 421 extends in a direction parallel to the outer edge of the semiconductor structure 100 between the connecting portion 413 and the connecting portion 414. The second extending portion 422 extends from the first extending portion 421 in a direction parallel to the diagonal line 91. In the direction parallel to the diagonal line 92, the second extending portion 422 and extending portions 222 of the second wiring 220 described later are alternately arranged. For example, the width of the second extending portion 422 is larger than the width of the first extending portion 421. The width of the second extending portion 422 is the length of the second extending portion 422 in a direction perpendicular to the direction in which the second extending portion 422 extends. In FIG. 1, the width of the second extending portion 422 is the width in a direction parallel to the diagonal line 92. The width of the first extending portion 421 in plan view is, for example, 5 μm or more and 100 μm or less, and the width of the second extending portion 422 in plan view is, for example, 10 μm or more and 300 μm or less.

[0018] 1 and 2, the second wiring 220 is disposed between the first wiring 210 and the third wiring 230 in a direction parallel to the diagonal line 91. The second wiring 220 has a plurality of extending portions 221 located in the recesses of the first wiring 210 and a plurality of extending portions 222 located between the second extending portions 422 of the third wiring 230.

[0019] The first wiring 210, the second wiring 220, and the third wiring 230 are made of metal. Examples of suitable materials for the first wiring 210, the second wiring 220, and the third wiring 230 include simple metals such as Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, W, and Ru, as well as alloys containing these metals as their main components. The first wiring 210, the second wiring 220, and the third wiring 230 are made of, for example, an Al alloy. The first wiring 210, the second wiring 220, and the third wiring 230 may have a single-layer structure consisting of one of these metal layers, or may have a multilayer structure consisting of multiple layers stacked together. The thickness of the first wiring 210, the second wiring 220, and the third wiring 230 is, for example, 0.3 μm or more and 3 μm or less.

[0020] As shown in FIG. 3 , the second insulating layer 40 is disposed on the first insulating layer 30 so as to cover the first wiring 210, the second wiring 220, and the third wiring 230. The second insulating layer 40 is, for example, a layer containing at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The second insulating layer 40 has one opening 41 as a second opening, multiple openings 42, one opening 43, and multiple openings 44. The openings 41, 42, 43, and 44 penetrate the second insulating layer 40. The thickness of the second insulating layer 40 is, for example, not less than 0.1 μm and not more than 2 μm.

[0021] As shown in FIGS. 1 and 2 , the outer shape of the opening 41 is smaller than the outer shape of the first wiring 210 in a plan view. The opening 41 is arranged inside the outer edge of the first wiring 210 in a plan view. The opening 42 has a circular shape in a plan view. When the opening 42 has a circular shape in a plan view, the diameter of the opening 42 is 2 μm or more and 20 μm or less. The opening 42 is arranged inside the outer edge of the extension 221 of the second wiring 220 in a plan view. The outer shape of the opening 43 is smaller than the outer shape of the second wiring 220 in a plan view. The opening 43 is arranged inside the outer edge of the second wiring 220 in a plan view. The opening 44 has a circular shape in a plan view. When the opening 44 has a circular shape in a plan view, the diameter of the opening 44 is 2 μm or more and 20 μm or less. In plan view, the opening 44 is disposed inside the outer edge of the second extending portion 422 of the third wiring 230. The second insulating layer 40 may have a plurality of openings 41, a plurality of openings 43, or the number of openings 44 may be one.

[0022] The first wiring 210 has a region 216 arranged inside the opening 41 in a plan view. The second wiring 220 has a region 226 arranged inside the opening 42 and a region 227 arranged inside the opening 43 in a plan view. The third wiring 230 has a region 236 arranged inside the opening 44 in a plan view.

[0023] As shown in FIGS. 1 and 3 , the light-reflective conductive layer 71 is disposed on the second insulating layer 40 away from the opening 42 in a cross-sectional view, overlapping with the extension 460 of the first wiring 210 and the extension 221 of the second wiring 220. The light-reflective conductive layer 71 is electrically connected to the first wiring 210 through the opening 41. The light-reflective conductive layer 71 has a plurality of openings 73 in a plan view. The openings 73 of the light-reflective conductive layer 71 have a circular shape in a plan view. In a plan view, the openings 42 are disposed inside the openings 73 of the light-reflective conductive layer 71. The light-reflective conductive layer 72 is disposed on the second insulating layer 40 away from the opening 44 in a plan view, overlapping with the portion of the second wiring 220 on the vertex 13 side of the diagonal line 92 (including the extension 222) and the extension 420 of the third wiring 230. The light-reflective conductive layer 72 is electrically connected to the second wiring 220 through the openings 43. The light-reflective conductive layer 72 has a plurality of openings 74 in a planar view. The openings 74 in the light-reflective conductive layer 72 are circular in a planar view. In a planar view, the openings 44 are disposed inside the openings 74 in the light-reflective conductive layer 72. The light-reflective conductive layers 71 and 72 are made of metal. For the light-reflective conductive layers 71 and 72, simple metals such as Ag, Al, Ni, Ti, Pt, Ta, Ru, Rh, and Au, or alloys containing these metals as main components, can be suitably used. The light-reflective conductive layers 71 and 72 may have a single-layer structure consisting of one of these metal layers, or a multilayer structure consisting of multiple layers. The light-reflective conductive layer 71 has a thickness of, for example, 0.05 μm to 1 μm.

[0024] As shown in Fig. 3, the semiconductor structure 100 is disposed on the second insulating layer 40 and the light-reflective conductive layers 71 and 72. The semiconductor structure 100 includes a first light-emitting section 110 and a second light-emitting section 120. As shown in Figs. 1 and 2, the first light-emitting section 110 and the second light-emitting section 120 have a substantially triangular shape in plan view. The first light-emitting section 110 is disposed on the vertex 11 side of the diagonal line 92, and the second light-emitting section 120 is disposed on the vertex 13 side of the diagonal line 92. The thickness of the semiconductor structure 100 is, for example, not less than 1 µm and not more than 10 µm.

[0025] The first light-emitting section 110 has a p-type semiconductor layer 111 as a first semiconductor layer, an n-type semiconductor layer 112 as a second semiconductor layer, and a light-emitting layer 113. The light-emitting layer 113 is disposed between the p-type semiconductor layer 111 and the n-type semiconductor layer 112. The p-type semiconductor layer 111 is disposed on the light-reflective conductive layer 71 and the second insulating layer 40, away from the opening 42 in a planar view, and the light-emitting layer 113 is disposed on the p-type semiconductor layer 111. The light-reflective conductive layer 71 and the p-type semiconductor layer 111 are electrically connected. The n-type semiconductor layer 112 is disposed on a region 226 of the second wiring 220, the light-emitting layer 113, and the second insulating layer 40. As shown in FIGS. 1 and 2 , the shape of the n-type semiconductor layer 112 in a planar view is approximately triangular. The upper surface of the n-type semiconductor layer 112, which is located on the opposite side to the light-emitting layer 113, has multiple protrusions. The convex portion of n-type semiconductor layer 112 is disposed in a portion that overlaps light emitting layer 113 in plan view. The convex portion of n-type semiconductor layer 112 has a shape such as a cone, a polygonal pyramid, or a truncated cone, for example.

[0026] The second light-emitting section 120 has a p-type semiconductor layer 121 as a first semiconductor layer, an n-type semiconductor layer 122 as a second semiconductor layer, and a light-emitting layer 123. The light-emitting layer 123 is disposed between the p-type semiconductor layer 121 and the n-type semiconductor layer 122. The p-type semiconductor layer 121 is disposed on the light-reflective conductive layer 72 and the second insulating layer 40, away from the opening 44 in a planar view, and the light-emitting layer 123 is disposed on the p-type semiconductor layer 121. The light-reflective conductive layer 72 and the p-type semiconductor layer 121 are electrically connected. The n-type semiconductor layer 122 is disposed on a region 236 of the third wiring 230, the light-emitting layer 123, and the second insulating layer 40. As shown in FIGS. 1 and 2 , the shape of the n-type semiconductor layer 122 in a planar view is approximately triangular. The upper surface of the n-type semiconductor layer 122, which is located on the opposite side to the light-emitting layer 123, has multiple protrusions. The convex portion of n-type semiconductor layer 122 is disposed in a portion that overlaps with light emitting layer 123 in a plan view. The convex portion of n-type semiconductor layer 122 has a cross-sectional shape that is, for example, a cone shape, a polygonal pyramid shape, or a truncated cone shape.

[0027] The first light-emitting section 110 and the second light-emitting section 120 are arranged apart from each other. The first light-emitting section 110 and the second light-emitting section 120 are electrically connected by conductive members such as a first wiring 210, a second wiring 220, and a third wiring 230.

[0028] The material of the p-type semiconductor layers 111 and 121, the material of the n-type semiconductor layers 112 and 122, and the material of the light emitting layers 113 and 123 can be, for example, a nitride semiconductor. X Al Y Ga 1-X-Y The term "nitride semiconductor" includes all semiconductors with compositions in which the composition ratios x and y in the chemical formula represented by N (0≦X, 0≦Y, X+Y<1) are varied within their respective ranges. Furthermore, the term "nitride semiconductor" also includes semiconductors with the above chemical formula that further contain a Group V element other than N (nitrogen), and semiconductors that further contain various elements added to control various physical properties such as conductivity type. The p-type semiconductor layers 111 and 121, the n-type semiconductor layers 112 and 122, and the light-emitting layers 113 and 123 may each have a single-layer structure or a stacked structure having multiple semiconductor layers with different semiconductor compositions and film thicknesses. In particular, the light-emitting layers 113 and 123 preferably have a single quantum well or multiple quantum well structure in which thin semiconductor layers that generate quantum effects are stacked. The n-type semiconductor layers 112 and 122 have a semiconductor layer containing n-type impurities. Examples of the n-type impurities include Si and Ge, and the p-type semiconductor layers 111 and 121 have a semiconductor layer containing p-type impurities. Examples of the p-type impurities include Mg and Zn. The peak wavelength of the light emitted by light-emitting layer 113 is the same as the peak wavelength of the light emitted by light-emitting layer 123. The peak wavelength of the light emitted by light-emitting layers 113 and 123 is, for example, 210 nm or more and 580 nm or less. Note that the peak wavelength of the light emitted by light-emitting layer 113 may be different from the peak wavelength of the light emitted by light-emitting layer 123.

[0029] The first wiring 210 is electrically connected to the p-type semiconductor layer 111 of the first light emitting section 110 through the opening 41. The second wiring 220 is electrically connected to the n-type semiconductor layer 112 of the first light emitting section 110 through the opening 42, and is electrically connected to the p-type semiconductor layer 121 of the second light emitting section 120 through the opening 43. The third wiring 230 is electrically connected to the n-type semiconductor layer 122 of the second light emitting section 120 through the opening 44.

[0030] As shown in FIG. 3 , the third insulating layer 50 is disposed to cover the semiconductor structure 100 and the second insulating layer 40. The third insulating layer 50 is, for example, a layer containing at least one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride. The upper surfaces of the third insulating layer 50 that overlap the n-type semiconductor layers 112 and 122 have shapes that reflect the shapes of the convex portions on the upper surfaces of the n-type semiconductor layers 112 and 122 in a cross-sectional view. The stack of the second insulating layer 40 and the third insulating layer 50 has openings 51 and 52. The openings 51 and 52 penetrate the stack of the second insulating layer 40 and the third insulating layer 50. The opening 51 reaches the connection portion 450 of the first wiring 210, and the opening 52 reaches the connection portions 412, 413, and 414 of the third wiring 230. The thickness of the third insulating layer 50 is, for example, 0.01 μm or more and 2 μm or less.

[0031] The first pad electrode 61 is disposed on the connection portion 450 inside the opening 51. The first pad electrode 61 is electrically connected to the connection portion 450. That is, the first pad electrode 61 is separated from the semiconductor structure 100 in a plan view and electrically connected to the first wiring 210. The second pad electrode 62 is disposed on the connection portions 412, 413, and 414 inside the opening 52. The second pad electrode 62 is electrically connected to the connection portions 412, 413, and 414. That is, the second pad electrode 62 is separated from the semiconductor structure 100 in a plan view and electrically connected to the third wiring 230. As shown in FIG. 3 , the first insulating layer 30 is disposed between the connection portion 450 and the conductive member 20, and is also disposed between the connection portion 413 and the conductive member 20. That is, the first insulating layer 30 is disposed between the first pad electrode 61 and the conductive member 20 and between the second pad electrode 62 and the conductive member 20. Although not shown, the first insulating layer 30 is also disposed between the connecting portions 412 and 414 and the conductive member 20.

[0032] As shown in FIGS. 1 to 3 , the first insulating layer 30 has an opening 31 as a first opening. The opening 31 penetrates the first insulating layer 30. The opening 31 is disposed inside the opening 41 in a plan view, and overlaps with at least the opening 41 in a plan view. A portion of the conductive member 20 is disposed inside the opening 31, and the first wiring 210 is in contact with the conductive member 20. That is, the first wiring 210 is electrically connected to the conductive member 20 through the opening 31. On the other hand, the second wiring 220 and the third wiring 230 are not in contact with the conductive member 20. The first insulating layer 30 may have a plurality of openings 31.

[0033] In the first embodiment, the first wiring 210 is electrically connected to the conductive member 20 through the opening 31. This reduces the sheet resistance between the first pad electrode 61 and the p-type semiconductor layer 111, and reduces the forward voltage compared to when the first wiring 210 is not electrically connected to the conductive member 20 through the opening 31. Furthermore, compared to when the first insulating layer 30 does not have the opening 31, heat generated in the semiconductor structure 100 is more easily transferred to the conductive member 20, improving heat dissipation.

[0034] In particular, since the opening 31 overlaps with the opening 41 in a plan view, the sheet resistance in the vicinity of the region 216 that functions as a contact region of the first wiring 210 with the p-type semiconductor layer 111 can be easily reduced.

[0035] In a plan view, the area of ​​the opening 31 is preferably 10% or more and 50% or less of the area of ​​the first light-emitting section 110. When the area of ​​the opening 31 is 10% or more of the area of ​​the first light-emitting section 110, the sheet resistance of the first wiring 210 can be easily reduced. On the other hand, when the area of ​​the opening 31 is 50% or less of the area of ​​the first light-emitting section 110, the area in which the second wiring 220 can be arranged can be easily increased.

[0036] (Second embodiment) Next, a light-emitting device according to a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the first insulating layer 30. FIG. 4 is a top view showing some of the components of the light-emitting device according to the second embodiment. FIG. 5 is an exploded top view showing some of the components of the light-emitting device according to the second embodiment. FIG. 6 is a cross-sectional view showing the light-emitting device according to the second embodiment. FIG. 6 corresponds to the cross-sectional view taken along line VI-VI in FIG. 4.

[0037] Layer 5A in FIG. 5 shows the arrangement of first wiring 210, second wiring 220, and third wiring 230 relative to substrate 10. Layer 5B in FIG. 5 shows the arrangement of opening 32 in first insulating layer 30, the arrangement of openings 41, 42, 43, and 44 in second insulating layer 40, and the arrangement of regions 216, 226, 227, and 236 within openings 41, 42, 43, and 44 of first wiring 210, second wiring 220, and third wiring 230 relative to substrate 10. Layer 5C in FIG. 5 shows the arrangement of n-type semiconductor layers 112 and 122 relative to substrate 10. In addition, two vertices 11 and 13 of substrate 10 are connected by dashed double-dashed lines between layers 5A, 5B, and 5C.

[0038] In the light-emitting element 2 according to the second embodiment, the second insulating layer 40 has an opening 44 as a second opening instead of the opening 41. Furthermore, as shown in FIGS. 4 to 6, the first insulating layer 30 has a plurality of openings 32 as first openings instead of the opening 31. The openings 32 penetrate the first insulating layer 30. The openings 32 are arranged inside the second extending portion 422 of the third wiring 230 in a planar view. The openings 32 overlap with the region 236 as a second region in a planar view. The number of openings 32 may be one.

[0039] 4 and 5, the extending portion 420 of the third wiring 230 has a region 232 as a first region that overlaps with the n-type semiconductor layer 122 in a plan view. The opening 32 overlaps with the region 232 in a plan view. The third wiring 230 may have multiple regions 232.

[0040] A portion of the conductive member 20 is disposed inside the opening 32, and the third wiring 230 is in contact with the conductive member 20. That is, the third wiring 230 is electrically connected to the conductive member 20 through the opening 32. On the other hand, the first wiring 210 and the second wiring 220 are not in contact with the conductive member 20.

[0041] Other configurations of the second embodiment are basically the same as those of the first embodiment.

[0042] In the second embodiment, the third wiring 230 is electrically connected to the conductive member 20 through the opening 32. This reduces the sheet resistance between the second pad electrode 62 and the n-type semiconductor layer 122, thereby reducing the forward voltage. Furthermore, heat generated in the semiconductor structure 100 is easily transferred to the conductive member 20, improving heat dissipation.

[0043] In particular, since the opening 32 overlaps with the opening 44 in a plan view, it is easy to reduce the sheet resistance in the vicinity of the region 236 of the third wiring 230 that functions as a contact region for the n-type semiconductor layer 122. Furthermore, since the opening 32 overlaps with the region 232 of the third wiring 230 that overlaps with the n-type semiconductor layer 122 in a plan view, it is easy to increase the area of ​​the opening 32 and the contact area between the third wiring 230 and the conductive member 20. Furthermore, since the extension 420 of the third wiring 230 has both the region 232 and the region 236 disposed inside the opening 44, it is easy to increase the size of the opening 32 and the contact area between the third wiring 230 and the conductive member 20.

[0044] In a plan view, the area of ​​the opening 32 is preferably 10% or more and 50% or less of the area of ​​the second light-emitting section 120. When the area of ​​the opening 32 is 10% or more of the area of ​​the second light-emitting section 120, it is easy to reduce the sheet resistance of the third wiring 230. When the area of ​​the opening 32 is 50% or less of the area of ​​the second light-emitting section 120, it is easy to increase the area in which the second wiring 220 can be arranged.

[0045] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the second embodiment mainly in the configuration of the opening 32. Fig. 7 is a top view showing some of the components of the light-emitting device according to the third embodiment.

[0046] In the light emitting element 3 according to the third embodiment, the opening 32 is arranged so as to overlap the first extending portion 421 and the second extending portion 422 in a plan view. The opening 32 may also overlap the connecting portion 413 in a plan view.

[0047] Other configurations of the third embodiment are basically the same as those of the second embodiment.

[0048] In the third embodiment, the openings 32 are arranged over a wider range than in the second embodiment. Therefore, the sheet resistance between the second pad electrode 62 and the n-type semiconductor layer 122 can be reduced more than in the second embodiment, and the forward voltage can be further reduced. In addition, the heat dissipation performance can be further improved.

[0049] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the first embodiment mainly in the configuration of the first insulating layer 30. FIG. 8 is a top view showing some of the components of the light-emitting device according to the fourth embodiment. FIG. 9 is an exploded top view showing some of the components of the light-emitting device according to the fourth embodiment. FIG. 10 is a cross-sectional view showing the light-emitting device according to the fourth embodiment. FIG. 10 corresponds to the cross-sectional view taken along line XX in FIG. 8.

[0050] Layer 9A in FIG. 9 shows the arrangement of the first wiring 210, the second wiring 220, and the third wiring 230 relative to the substrate 10. Layer 9B in FIG. 9 shows the arrangement of the openings 33 and 34 in the first insulating layer 30, the arrangement of the openings 41, 42, 43, and 44 in the second insulating layer 40, and the arrangement of the regions 216, 226, 227, and 236 within the openings 41, 42, 43, and 44 of the first wiring 210, the second wiring 220, and the third wiring 230 relative to the substrate 10. Layer 9C in FIG. 9 shows the arrangement of the n-type semiconductor layers 112 and 122 relative to the substrate 10. In addition, the two vertices 11 and 13 of the substrate 10 are connected by dashed double-dashed lines between layers 9A, 9B, and 9C.

[0051] In the light-emitting element 4 according to the fourth embodiment, the second insulating layer 40 has an opening 42 as a second opening instead of the opening 41, and an opening 43 as a fourth opening. Furthermore, the first insulating layer 30 has an opening 33 as a first opening and an opening 34 as a first or third opening instead of the opening 31. The openings 33 and 34 penetrate the first insulating layer 30. The opening 33 is disposed inside the extension 221 of the second wiring 220 in a planar view and overlaps with at least the opening 42 in a planar view. The opening 34 is disposed inside the opening 43 in a planar view and overlaps with at least the opening 43 in a planar view. The second wiring 220 has a region 223 that overlaps with the n-type semiconductor layer 112 in a planar view. The opening 33 overlaps with the region 223 as a first region in a planar view. The first insulating layer 30 may have a plurality of openings 33 or a plurality of openings 34. The second insulating layer 40 may have a plurality of openings 42. The opening 33 may have a plurality of regions 223 .

[0052] A part of the conductive member 20 is disposed inside the opening 33, and another part is disposed inside the opening 34, and the second wiring 220 is in contact with the conductive member 20. In other words, the second wiring 220 is electrically connected to the conductive member 20 through the openings 33 and 34. On the other hand, the first wiring 210 and the third wiring 230 are not in contact with the conductive member 20.

[0053] Other configurations of the fourth embodiment are basically the same as those of the first embodiment.

[0054] In the fourth embodiment, the second wiring 220 is electrically connected to the conductive member 20 through the openings 33 and 34. This reduces the sheet resistance between the n-type semiconductor layer 112 and the p-type semiconductor layer 121, thereby reducing the forward voltage. Furthermore, heat generated in the semiconductor structure 100 is easily transferred to the conductive member 20, improving heat dissipation.

[0055] In particular, since opening 33 overlaps with opening 42 in a plan view, it is easy to reduce the sheet resistance in the vicinity of region 226 that functions as a contact region of second wiring 220 with n-type semiconductor layer 112. Similarly, since opening 34 overlaps with opening 43 in a plan view, it is easy to reduce the sheet resistance in the vicinity of region 227 that functions as a contact region of second wiring 220 with p-type semiconductor layer 121. Furthermore, since opening 33 overlaps with region 223 that overlaps with n-type semiconductor layer 112 of first wiring 210 in a plan view, it is easy to form opening 33 large, and it is easy to obtain a large area for the portion where first wiring 210 and conductive member 20 contact each other.

[0056] In plan view, the area of ​​the opening 33 is preferably 10% or more and 50% or less of the area of ​​the first light-emitting section 110. When the area of ​​the opening 33 is 10% or more of the area of ​​the first light-emitting section 110, the sheet resistance of the first wiring 210 can be easily reduced. When the area of ​​the opening 33 is 50% or less of the area of ​​the first light-emitting section 110, the area in which the second wiring 220 can be arranged can be easily increased. Furthermore, the area of ​​the opening 34 is preferably 10% or more and 50% or less of the area of ​​the second light-emitting section 120. When the area of ​​the opening 34 is 10% or more of the area of ​​the second light-emitting section 120, the sheet resistance of the second wiring 220 can be easily reduced. When the area of ​​the opening 34 is 50% or less of the area of ​​the second light-emitting section 120, the area in which the third wiring 230 can be arranged can be easily increased.

[0057] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment differs from the first embodiment mainly in the configurations of the first wiring 210, the second wiring 220, and the third wiring 230. Fig. 11 is a top view showing some of the components of the light-emitting device according to the fourth embodiment.

[0058] In the light-emitting element 5 according to the fifth embodiment, the outer shape of the extending portion 460 of the first wiring 210 in a planar view has a portion parallel to the side connecting the vertices 11 and 12 and a portion parallel to the side connecting the vertices 14 and 11. Unlike the first embodiment, the extending portion 460 does not have a plurality of portions extending in a direction parallel to the diagonal line 91 connecting the vertices 11 and 13 in a planar view. The extending portion 460 has a shape having a recess recessed from the diagonal line 92 connecting the vertices 12 and 14 toward the vertex 11 in a planar view.

[0059] The outline of the extending portion 420 of the third wiring 230 in a plan view has a portion parallel to the side connecting the vertices 12 and 13, a portion parallel to the diagonal line 92 connecting the vertices 12 and 14, and a portion parallel to the side connecting the vertices 13 and 14. Unlike the first embodiment, the extending portion 420 does not have multiple second extending portions 422 in a plan view. The extending portion 420 extends in a direction parallel to the diagonal line 92 and is electrically connected to the n-type semiconductor layer 122 of the second light-emitting section 120 through multiple openings 44.

[0060] Unlike the first embodiment, the second wiring 220 does not have a plurality of extensions 221 in plan view. The outer shape of the second wiring 220 has a portion extending parallel to the diagonal line 92 in plan view, and is electrically connected to the n-type semiconductor layer 112 of the first light emitting section 110 through a plurality of openings 42.

[0061] Other configurations of the fifth embodiment are basically the same as those of the first embodiment, and the fifth embodiment can also achieve the same effects as the first embodiment.

[0062] In any of the second, third and fourth embodiments, the first wiring 210, the second wiring 220 and the third wiring 230 having the same configuration as in the fifth embodiment can be used.

[0063] The arrangement of the n-type semiconductor layer and pad electrodes is not limited to that of the above-described embodiment. Fig. 12 is a top view showing a modified example of the arrangement of the n-type semiconductor layer and pad electrodes.

[0064] 12 , the n-type semiconductor layers 112 and 122 have a substantially rectangular shape in a plan view. In a plan view, the n-type semiconductor layer 112 is disposed closer to the vertices 11 and 14 than a center line 93 connecting the midpoint of the side connecting the vertices 11 and 12 and the midpoint of the side connecting the vertices 13 and 14, and the n-type semiconductor layer 122 is disposed closer to the vertices 12 and 13 than the center line 93. In addition, in a plan view, the first pad electrode 61 is disposed near the midpoint of the side connecting the vertices 11 and 14, and the second pad electrode 62 is disposed near the midpoint of the side connecting the vertices 12 and 13.

[0065] Although not shown in the drawings, the first wiring 210, the second wiring 220, the third wiring 230, the opening 31 in the first insulating layer 30, and the openings 41, 42, 43, and 44 in the second insulating layer 40 are arranged in the same manner as in the first embodiment, in accordance with the arrangement of the first pad electrode 61, the second pad electrode 62, and the n-type semiconductor layers 112 and 122. The components included in the semiconductor structure 100 other than the n-type semiconductor layers 112 and 122 are also arranged in the same manner as in the first embodiment, in accordance with the arrangement of the first pad electrode 61, the second pad electrode 62, and the n-type semiconductor layers 112 and 122.

[0066] Even with this modification, the same effects as those of the first embodiment can be obtained.

[0067] (Experimental example) Next, a test on the characteristics of the light-emitting element conducted by the inventors of the present invention will be described.

[0068] In this test, three samples were fabricated following the first, second, and fourth embodiments. The substrate 10 in each sample had a square shape in plan view, with the length of one side of the substrate 10 being 1000 μm. A current of 500 mA was then passed between the first pad electrode 61 and the second pad electrode 62 of each sample, and the forward voltage and output were measured. The results are shown in Table 1.

[0069] [Table 1]

[0070] As shown in Table 1, the sample fabricated according to the second embodiment had a particularly low forward voltage and a high output.

[0071] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0072] The present specification includes the following embodiments. 1. A substrate; a conductive member disposed on the substrate; a first insulating layer disposed on the conductive member; a semiconductor structure including a first light emitting portion and a second light emitting portion spaced apart from each other on the first insulating layer, wherein each of the first light emitting portion and the second light emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light emitting portion; a second wiring electrically connected to the second semiconductor layer of the first light emitting portion and the first semiconductor layer of the second light emitting portion; a third wiring electrically connected to the second semiconductor layer of the second light emitting portion; a first pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the first wiring; a second pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the third wiring; and the first insulating layer has one or more first openings; the first wiring is in contact with the conductive member through the one or more first openings, The light-emitting element, wherein the second wiring and the third wiring are not in contact with the conductive member. 2. a second insulating layer disposed between the first wiring and the first semiconductor layer of the first light emitting portion; the second insulating layer has one or more second openings; the first wiring is electrically connected to the first semiconductor layer of the first light-emitting portion through the one or more second openings; 2. The light-emitting device according to 1, wherein each of the one or more first openings overlaps with each of the one or more second openings at least in plan view. 3. 3. The light emitting device according to 1 or 2 above, wherein an area of ​​the one or more first openings is 10% to 50% of an area of ​​the first light emitting portion in a plan view. 4. A substrate; a conductive member disposed on the substrate; a first insulating layer disposed on the conductive member; a semiconductor structure including a first light emitting portion and a second light emitting portion spaced apart from each other on the first insulating layer, wherein each of the first light emitting portion and the second light emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light emitting portion; a second wiring electrically connected to the second semiconductor layer of the first light emitting portion and the first semiconductor layer of the second light emitting portion; a third wiring electrically connected to the second semiconductor layer of the second light emitting portion; a first pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the first wiring; a second pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the third wiring; and the first insulating layer has one or more first openings; the third wiring is in contact with the conductive member through the one or more first openings, The light-emitting element, wherein the first wiring and the second wiring are not in contact with the conductive member. 5. a second insulating layer disposed between the third wiring and the second semiconductor layer of the second light emitting portion; the second insulating layer has one or more second openings; the third wiring is electrically connected to the second semiconductor layer of the second light-emitting portion through the one or more second openings, 5. The light-emitting device according to 4 above, wherein each of the one or more first openings overlaps each of the one or more second openings at least in plan view. 6. the third wiring has one or more first regions that overlap with the second semiconductor layer of the second light-emitting portion in a plan view, 6. The light-emitting device according to item 5, wherein each of the one or more first openings overlaps each of the one or more first regions in plan view. 7. The third wiring is a connection portion in contact with the second pad electrode; one or more extension portions extending from the connection portion in a plan view and electrically connected to the first semiconductor layer of the second light emitting portion; and Each of the one or more extension portions is the first region; a second region disposed inside the second opening; 7. The light-emitting device according to claim 6, wherein 8. Each of the one or more extension portions is a first extension portion extending in a direction parallel to an outer edge of the semiconductor structure in a plan view; a second extension portion extending from the first extension portion toward the inside of the semiconductor structure in a plan view; and 8. The light-emitting element according to claim 7, wherein the first opening overlaps with the first extension portion and the second extension portion in a plan view. 9. 9. The light-emitting element according to item 8, wherein the width of the second extending portion is greater than the width of the first extending portion. 10. 10. The light-emitting device according to any one of 4 to 9 above, wherein an area of ​​the one or more first openings is 10% to 50% of an area of ​​the second light-emitting portion in a plan view. 11. A substrate; a conductive member disposed on the substrate; a first insulating layer disposed on the conductive member; a semiconductor structure including a first light emitting portion and a second light emitting portion spaced apart from each other on the first insulating layer, wherein each of the first light emitting portion and the second light emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light emitting portion; a second wiring electrically connected to the second semiconductor layer of the first light emitting portion and the first semiconductor layer of the second light emitting portion; a third wiring electrically connected to the second semiconductor layer of the second light emitting portion; a first pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the first wiring; a second pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the third wiring; and the first insulating layer has one or more first openings; the second wiring is in contact with the conductive member through the one or more first openings, The light-emitting element, wherein the first wiring and the third wiring are not in contact with the conductive member. 12. a second insulating layer disposed between the second wiring and the second semiconductor layer of the first light emitting portion; the second insulating layer has one or more second openings; the second wiring is electrically connected to the second semiconductor layer of the first light emitting portion through the one or more second openings, 12. The light-emitting device according to item 11, wherein each of the one or more first openings overlaps each of the one or more second openings at least in plan view. 13. the second wiring has one or more first regions that overlap with the second semiconductor layer of the first light emitting portion in a plan view, 13. The light-emitting device according to item 12, wherein each of the one or more first openings overlaps each of the one or more first regions in plan view. 14. the first insulating layer has one or more third openings; the second insulating layer is also disposed between the second wiring and the first semiconductor layer of the second light-emitting portion, the second insulating layer has one or more fourth openings; each of the one or more third openings overlaps with each of the one or more fourth openings at least in a plan view; the second wiring is electrically connected to the first semiconductor layer of the second light-emitting portion through the one or more fourth openings, 14. The light-emitting element according to 12 or 13 above, wherein the second wiring is electrically connected to the conductive member through the one or more third openings. 15. 15. The light-emitting device according to item 14, wherein the area of ​​the one or more third openings is 10% to 50% of the area of ​​the second light-emitting portion in plan view. 16. 16. The light-emitting device according to any one of 11 to 15 above, wherein an area of ​​the one or more first openings is 10% to 50% of an area of ​​the first light-emitting portion in a plan view. 17. a second insulating layer disposed between the second wiring and the first semiconductor layer of the second light emitting portion; the second insulating layer has one or more fourth openings; the second wiring is electrically connected to the first semiconductor layer of the second light-emitting portion through the one or more fourth openings, 12. The light-emitting device according to item 11, wherein each of the one or more first openings overlaps each of the one or more fourth openings at least in plan view. 18. 18. The light-emitting device according to item 17, wherein the area of ​​the one or more first openings is 10% to 50% of the area of ​​the second light-emitting portion in plan view. 19. 19. The light-emitting element according to any one of 1 to 18, wherein the first insulating layer is disposed between the first pad electrode and the conductive member. 20. 20. The light-emitting element according to any one of 1 to 19, wherein the first insulating layer is disposed between the second pad electrode and the conductive member. [Explanation of symbols]

[0073] 1, 2, 3, 4, 5: Light-emitting elements 10: Circuit board 20: Conductive material 30: First insulating layer 31, 32, 33, 34: Openings 40: Second insulating layer 41, 42, 43, 44: Openings 50: Third insulating layer 61: First pad electrode 62: Second pad electrode 71, 72: Light-reflective conductive layer 100: Semiconductor structure 110: First light-emitting part 120: Second light-emitting part 111, 121: p-type semiconductor layer 112, 122: n-type semiconductor layer 113, 123: Light-emitting layer 210: 1st wiring 220: 2nd wiring 221, 222: Stretching part 230: 3rd wiring 412, 413, 414, 450: Connection parts 420, 460: Stretching part 421: 1st extension part 422:Second extension part

Claims

1. A substrate; a conductive member disposed on the substrate; a first insulating layer disposed on the conductive member; a semiconductor structure including a first light emitting portion and a second light emitting portion spaced apart from each other on the first insulating layer, wherein each of the first light emitting portion and the second light emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light emitting portion; a second wiring electrically connected to the second semiconductor layer of the first light emitting portion and the first semiconductor layer of the second light emitting portion; a third wiring electrically connected to the second semiconductor layer of the second light emitting portion; a first pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the first wiring; a second pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the third wiring; and the first insulating layer has one or more first openings; the first wiring is in contact with the conductive member through the one or more first openings, The light-emitting element, wherein the second wiring and the third wiring are not in contact with the conductive member.

2. a second insulating layer disposed between the first wiring and the first semiconductor layer of the first light emitting portion; the second insulating layer has one or more second openings; the first wiring is electrically connected to the first semiconductor layer of the first light emitting portion through the one or more second openings, The light-emitting element according to claim 1 , wherein each of the one or more first openings overlaps each of the one or more second openings at least in plan view.

3. The light-emitting element according to claim 1 , wherein an area of ​​the one or more first openings is 10% to 50% of an area of ​​the first light-emitting portion in a plan view.

4. A substrate; a conductive member disposed on the substrate; a first insulating layer disposed on the conductive member; a semiconductor structure including a first light emitting portion and a second light emitting portion spaced apart from each other on the first insulating layer, wherein each of the first light emitting portion and the second light emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light emitting portion; a second wiring electrically connected to the second semiconductor layer of the first light emitting portion and the first semiconductor layer of the second light emitting portion; a third wiring electrically connected to the second semiconductor layer of the second light emitting portion; a first pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the first wiring; a second pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the third wiring; and the first insulating layer has one or more first openings; the third wiring is in contact with the conductive member through the one or more first openings, The light-emitting element, wherein the first wiring and the second wiring are not in contact with the conductive member.

5. a second insulating layer disposed between the third wiring and the second semiconductor layer of the second light emitting portion; the second insulating layer has one or more second openings; the third wiring is electrically connected to the second semiconductor layer of the second light emitting portion through the one or more second openings, The light-emitting element according to claim 4 , wherein each of the one or more first openings overlaps each of the one or more second openings at least in plan view.

6. the third wiring has one or more first regions that overlap with the second semiconductor layer of the second light emitting portion in a plan view, The light-emitting element according to claim 5 , wherein each of the one or more first openings overlaps each of the one or more first regions in a plan view.

7. The third wiring is a connection portion in contact with the second pad electrode; one or more extension portions extending from the connection portion in a plan view and electrically connected to the first semiconductor layer of the second light emitting portion; and Each of the one or more extension portions is the first region; a second region disposed inside the second opening; The light-emitting device according to claim 6 , having

8. Each of the one or more extension portions is a first extension portion extending in a direction parallel to an outer edge of the semiconductor structure in a plan view; a second extension portion extending from the first extension portion toward an inside of the semiconductor structure in a plan view; and The light-emitting element according to claim 7 , wherein the first opening overlaps with the first extension portion and the second extension portion in a plan view.

9. The light-emitting element according to claim 8 , wherein the width of the second extending portion is greater than the width of the first extending portion.

10. 10. The light-emitting element according to claim 4, wherein an area of ​​the one or more first openings is 10% to 50% of an area of ​​the second light-emitting portion in a plan view.

11. A substrate; a conductive member disposed on the substrate; a first insulating layer disposed on the conductive member; a semiconductor structure including a first light emitting portion and a second light emitting portion spaced apart from each other on the first insulating layer, wherein each of the first light emitting portion and the second light emitting portion has a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a first wiring electrically connected to the first semiconductor layer of the first light emitting portion; a second wiring electrically connected to the second semiconductor layer of the first light emitting portion and the first semiconductor layer of the second light emitting portion; a third wiring electrically connected to the second semiconductor layer of the second light emitting portion; a first pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the first wiring; a second pad electrode that is spaced from the semiconductor structure in a plan view and electrically connected to the third wiring; and the first insulating layer has one or more first openings; the second wiring is in contact with the conductive member through the one or more first openings, The light-emitting element, wherein the first wiring and the third wiring are not in contact with the conductive member.

12. a second insulating layer disposed between the second wiring and the second semiconductor layer of the first light emitting portion; the second insulating layer has one or more second openings; the second wiring is electrically connected to the second semiconductor layer of the first light emitting portion through the one or more second openings, The light-emitting element according to claim 11 , wherein each of the one or more first openings overlaps each of the one or more second openings at least in plan view.

13. the second wiring has one or more first regions that overlap with the second semiconductor layer of the first light emitting portion in a plan view, The light-emitting element according to claim 12 , wherein each of the one or more first openings overlaps each of the one or more first regions in a plan view.

14. the first insulating layer has one or more third openings; the second insulating layer is also disposed between the second wiring and the first semiconductor layer of the second light-emitting portion, the second insulating layer has one or more fourth openings; each of the one or more third openings overlaps with each of the one or more fourth openings at least in a plan view; the second wiring is electrically connected to the first semiconductor layer of the second light emitting portion through the one or more fourth openings, The light-emitting element according to claim 12 , wherein the second wiring is electrically connected to the conductive member through the one or more third openings.

15. The light-emitting element according to claim 14 , wherein an area of ​​the one or more third openings is 10% to 50% of an area of ​​the second light-emitting portion in a plan view.

16. 14. The light-emitting element according to claim 11, wherein an area of ​​the one or more first openings is 10% to 50% of an area of ​​the first light-emitting portion in a plan view.

17. a second insulating layer disposed between the second wiring and the first semiconductor layer of the second light emitting portion; the second insulating layer has one or more fourth openings; the second wiring is electrically connected to the first semiconductor layer of the second light emitting portion through the one or more fourth openings, The light-emitting element according to claim 11 , wherein each of the one or more first openings overlaps each of the one or more fourth openings at least in plan view.

18. The light-emitting element according to claim 17 , wherein an area of ​​the one or more first openings is 10% to 50% of an area of ​​the second light-emitting portion in a plan view.

19. The light-emitting element according to claim 1 , wherein the first insulating layer is disposed between the first pad electrode and the conductive member.

20. The light-emitting element according to claim 1 , wherein the first insulating layer is disposed between the second pad electrode and the conductive member.

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