amplifier

Abstract

To provide an amplifier in which an effective chopper amplifier gain is stably obtained with respect to a closed-loop gain setting, and the convenience of correction is good.SOLUTION: An amplifier 1 includes: an operational amplifier 11 having input terminals INP and INN, chopper circuits 21 and 22 capable of switching between a straight connection state and a cross connection state, resistors 31 and 33, a variable resistor 32, an input terminal 11a connected to an output terminal 21c, a control terminal 11b receiving a supplied control signal, and an input terminal 11c connected to one end of the resistor 31 and one end (node N2) of the variable resistor 32; an operational amplifier 12 having an input terminal 12a connected to an output terminal 21d, a control terminal 12b for receiving a supplied control signal, and an input terminal 12c connected to one end of the resistor 33 and the other end (node N3) of the variable resistor 32; and output terminals OUTP and OUTN. The operational amplifiers 11 and 12 are configured to be capable of switching the gain bandwidth based on the control signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an amplifier. [Background technology]

[0002] For example, chopper amplifiers are used to amplify minute input voltages, such as the output signal of a magnetic sensor element, without generating an offset voltage and pass them on to a downstream signal processing circuit. Chopper amplifiers consist of an amplifier stage made up of a modulator and an operational amplifier, and a demodulator. The offset voltage is frequency-converted to a high-frequency range by the modulator, the signal components are amplified by the amplifier stage, the offset voltage modulated to the high-frequency range is removed by applying band limiting, and the signal components are frequency-converted back to their original frequency by the demodulator.

[0003] Modulators and demodulators are generally configured with chopper switch circuits, and are driven to output differential output signals by alternately switching between straight and cross connections of differential input signals using a clock signal of a predetermined frequency. This predetermined frequency must be sufficiently higher than the frequency bandwidth of the input signal to be amplified in order to output the signal correctly. The closed-loop gain of the amplifier stage is set using the ratio of feedback resistors, etc. This closed-loop gain is set in advance during an inspection process at the time of shipment, taking into account the dynamic range of the upstream sensor, etc., or is dynamically switched and set automatically controlled. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-054766 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the amplifiers of the prior art, the bandwidth BW of the operational amplifier that constitutes the chopper amplifier changes depending on the closed-loop gain setting of the entire chopper amplifier, and the rate of decrease in the effective gain of the chopper amplifier due to insufficient settling time changes depending on the closed-loop gain setting, making the effective chopper amplifier gain unstable relative to the gain setting and reducing convenience.

[0006] The reason for this is explained below. An operational amplifier has a gain-bandwidth product (GBW) that is determined by the drive current and the compensation capacitance value. The gain-bandwidth product (GBW) is calculated using the closed-loop gain G and bandwidth BW as follows: GBW=G·BW ---(1) The time constant τ, which determines the settling time for the final value of the output signal from the amplifier stage that amplifies the output signal from the chopper switch driven at a predetermined clock frequency, is limited by the bandwidth BW, and is expressed as follows: τ≒0.35 / BW[μs] ---(2) It is expressed as:

[0007] If the half-clock time corresponding to the predetermined clock frequency is not sufficiently long for the time constant τ, a static determination error occurs, and the effective gain of the chopper amplifier decreases. On the other hand, as mentioned above, the predetermined clock frequency is set higher when attempting to achieve high-speed response in response to a wide frequency bandwidth of the input signal. Here, the gain-bandwidth product GBW of a general operational amplifier is calculated using the transconductance Gm of the operational amplifier, the current value IDD of the drive current, and the capacitance value Cc of the phase compensation capacitance, as follows: GBW∝Gm / Cc=√IDD / Cc ---(3) That is, the gain bandwidth product GBW is proportional to the square root (1 / 2 power) of the current value IDD of the drive current, and inversely proportional to the capacitance value Cc of the phase compensation capacitance.

[0008] As can be seen from equation (3), to increase the gain-bandwidth product GBW of an operational amplifier, the current value IDD of the drive current or the capacitance value Cc of the phase compensation capacitance can be increased, or alternatively, the current value IDD of the drive current and the capacitance value Cc of the phase compensation capacitance can be increased and decreased. However, increasing the current value IDD of the drive current hinders efforts to reduce the amplifier's power consumption. Furthermore, reducing or eliminating the phase compensation capacitance can result in insufficient phase margin in the negative feedback system. Insufficient phase margin in the negative feedback system can cause ringing in the output voltage waveform, which can cause errors in the gain of the equivalent chopper amplifier.

[0009] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide an amplifier in which an effective chopper amplifier gain can be stably obtained for the closed-loop gain setting of the amplification stage. [Means for solving the problem]

[0010] An amplifier according to an embodiment of the present invention has a first input terminal and a second input terminal, a first input end connected to the first input terminal, a second input end connected to the second input terminal, a control end that receives a clock signal as a switching signal, a first output end, and a second output end, and is configured to switch between a first connection state in which the first input end and the first output end are connected and the second input end and the second output end are connected based on the switching signal, and a second connection state in which the first input end and the second output end are connected and the second input end and the first output end are connected a first chopper circuit capable of switching between a first and a second connection state; a first resistor; a second resistor having at least one control terminal and capable of switching a resistance value based on a control signal given to the control terminal; a third resistor; a first operational amplifier having a first input terminal connected to the first output terminal of the first chopper circuit, a second input terminal connected to one end of the first resistor and one end of the second resistor, an output terminal connected to the other end of the first resistor, and a control terminal for receiving the control signal; a second operational amplifier having an output terminal connected to one end of the third resistor and the other end of the second resistor, a second input terminal connected to the other end of the third resistor, and a control terminal for receiving the control signal; a first input terminal connected to the output terminal of the first operational amplifier, a second input terminal connected to the output terminal of the second operational amplifier, a control terminal for receiving the clock signal as the switching signal, a first output terminal, and a second output terminal; and a second chopper circuit switchable between a first connection state in which the first input terminal and the second output terminal are connected and a second connection state in which the first input terminal and the second output terminal are connected and the second input terminal and the first output terminal are connected; a first output terminal connected to the first output terminal of the second chopper circuit and a second output terminal connected to the second output terminal of the second chopper circuit, wherein the first operational amplifier and the second operational amplifier are configured to be able to switch the gain bandwidths of the first and second operational amplifiers based on the control signal. [Effects of the Invention]

[0011] According to the present invention, an effective chopper amplifier gain can be stably obtained for the closed loop gain setting of the amplifier stage. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a circuit diagram schematically illustrating the configuration of an amplifier according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a chopper circuit in the amplifier according to the present embodiment. [Figure 3] FIG. 2 is a circuit diagram showing an example of the configuration of a variable resistor in the amplifier according to the present embodiment. [Figure 4] 1 is a circuit diagram showing an example of the configuration of an operational amplifier in an amplifier according to a first embodiment. [Figure 5] 2 is a circuit diagram showing a configuration example of a capacitance bank circuit in the amplifier according to the first embodiment. FIG. [Figure 6] 1 is a timing diagram showing the time variations of a clock signal and an input signal supplied to the amplifier according to the present embodiment and a conventional amplifier (comparison example), and a modulator output signal (modulated input signal). [Figure 7] 4 is a timing diagram illustrating the operation of the amplifier according to the present embodiment and a conventional amplifier (comparison example). FIG. [Figure 8] (a) and (b) are the frequency characteristics of the closed-loop gain for the closed-loop gain designs of a conventional amplifier and the amplifier according to this embodiment, respectively. (c) and (d) are the effective gain versus the set gain and the normalized effective gain (=effective gain / set gain) based on the ideal straight line of the chopper amplifier, respectively. [Figure 9] FIG. 5 is a circuit diagram schematically illustrating the configuration of an amplifier according to a second embodiment of the present invention. [Figure 10] FIG. 10 is a circuit diagram illustrating a configuration example of an operational amplifier in the amplifier according to the second embodiment. [Figure 11] FIG. 10 is a circuit diagram showing an example of the configuration of a variable current source circuit in an amplifier according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, an amplifier according to an embodiment of the present invention will be described with reference to the drawings. For the sake of convenience, some components may be omitted or the scale may be changed.

[0014] [First embodiment] FIG. 1 is a circuit diagram schematically illustrating the configuration of an amplifier 1, which is an example of an amplifier according to a first embodiment of the present invention.

[0015] The amplifier 1 includes input terminals INP and INN, a chopper circuit 21, operational amplifiers 11 and 12, resistors 31 and 33, a variable resistor 32, a chopper circuit 22, a clock terminal CLK that receives a clock signal, a control terminal CNT that receives a 3-bit (3b) control signal, and output terminals OUTP and OUTN.

[0016] The chopper circuit 21 has an input terminal 21a connected to the input terminal INP, an input terminal 21b connected to the input terminal INN, output terminals 21c and 21d, and a control terminal 21e connected to the clock terminal CLK.

[0017] Operational amplifier 11 has an input terminal 11a connected to output terminal 21c, a control terminal 11b connected to node N1 to which a control signal is supplied, an input terminal 11c connected to node N2 which is a connection point between resistor 31 and variable resistor 32, and an output terminal 11d connected to input terminal 11c via resistor 31. Operational amplifier 12 includes an input terminal 12a connected to output terminal 21d, a control terminal 12b connected to node N1, an input terminal 12c connected to node N3 which is a connection point between variable resistor 32 and resistor 33, and an output terminal 12d connected to input terminal 12c via resistor 33. Variable resistor 32 has a first terminal connected to node N2, a second terminal connected to node N3, and a control terminal that receives a control signal, and is configured to be able to adjust the resistance value between the first terminal and the second terminal based on the control signal.

[0018] The chopper circuit 22 has an input terminal 22a connected to the operational amplifier 11 (specifically, the output terminal 11d), an input terminal 22b connected to the operational amplifier 12 (specifically, the output terminal 12d), an output terminal 22c connected to the output terminal OUTP, an output terminal 22d connected to the output terminal OUTN, and a control terminal 22e connected to the clock terminal CLK.

[0019] FIG. 2 is a circuit diagram showing an example of the configuration of the chopper circuit 21. In addition to having input terminals 21a and 21b, output terminals 21c and 21d, and control terminal 21e, chopper circuit 21 also has switches 211 to 214 including the control terminal, an inverter 216 including an input terminal and an output terminal connected to control terminal 21e, and an inverter 217 including an input terminal and an output terminal connected to the output terminal of inverter 216.

[0020] The switch 211 is connected between the input terminal 21a and the output terminal 21c so as to be able to open and close between the input terminal 21a and the output terminal 21c. The switch 212 is connected between the input terminal 21a and the output terminal 21d so as to be able to open and close between the input terminal 21a and the output terminal 21d. The switch 213 is connected between the input terminal 21b and the output terminal 21d so as to be able to open and close between the input terminal 21b and the output terminal 21d. The switch 214 is connected between the input terminal 21b and the output terminal 21c so as to be able to open and close between the input terminal 21b and the output terminal 21c. The control terminals of the switches 211 and 214 are connected to, for example, the output terminal of the inverter 217. The control terminals of the switches 212 and 213 are connected to the output terminal of the inverter 216.

[0021] Therefore, when switches 212 and 214 are in a closed state (on state) where both ends are short-circuited, switches 211 and 213 are in an open state (off state) where both ends are open, whereas switches 212 and 214 are in an open state (off state) where switches 211 and 213 are in a closed state (on state). In other words, switches 211 and 213 and switches 212 and 214 are configured so that the open and closed states are exclusive.

[0022] The configuration of the chopper circuit 22 is substantially the same as that of the chopper circuit 21, and therefore the description of the chopper circuit 22 can be replaced by the description of the chopper circuit 21 by substituting the reference numerals.

[0023] FIG. 3 is a circuit diagram showing an example of the configuration of the variable resistor 32. The variable resistor 32 has a first terminal 32a, a second terminal 32b, and a control terminal 32c, as well as a decoder circuit 320, resistive elements 321, 323, 325, and 327, and switch circuits 324, 326, and 328 including the control terminal. The decoder circuit 320 has an input terminal connected to the control terminal 32c, and an output terminal that outputs a signal after decoding a control signal received from the input terminal.

[0024] The resistance element 321, the resistance element 323 and the switch circuit 324 connected in series, the resistance element 325 and the switch circuit 326 connected in series, and the resistance element 327 and the switch circuit 328 connected in series are connected in parallel between the first terminal 32a and the second terminal 32b. The control terminals of the switch circuits 324, 326, and 328 are connected to the output terminals of the decoder circuit 320, respectively. The variable resistor 32 is configured so that the resistance value between the first terminal 32a and the second terminal 32b can be adjusted in stages within a predetermined range by controlling the open / closed states of the switch circuits 324, 326, and 328.

[0025] FIG. 4 is a circuit diagram showing a first configuration example of the operational amplifier 11. As shown in FIG. The operational amplifier 11 has input terminals 11a and 11c, a control terminal 11b, and an output terminal 11d, as well as a current source 111, a current source 112, a PMOS transistor 113, a PMOS transistor 114, an NMOS transistor 115, an NMOS transistor 116, an NMOS transistor 117, a capacitance bank circuit 118, and a decoder circuit 120.

[0026] The current source 111 includes a first terminal connected to a power supply line VDD (power supply terminal not shown) that supplies a power supply voltage Vdd, and a second terminal. The current source 112 includes a first terminal connected to the power supply line VDD that supplies the power supply voltage Vdd, and a second terminal connected to the output terminal 11d. The sources of the PMOS transistors 113 and 114 are each connected to the second terminal of the current source 111. The gate of the PMOS transistor 113 is connected to the input terminal 11a. The gate of the PMOS transistor 114 is connected to the input terminal 11c.

[0027] The drain of the PMOS transistor 113 is connected to the drain and gate of the NMOS transistor 115 and the gate of the NMOS transistor 116. The source of the NMOS transistor 115 and the source of the NMOS transistor 116 are each connected to a power supply line VSS (power supply terminal not shown) that supplies a power supply voltage Vss (≠Vdd). The drain of the NMOS transistor 116 is connected to the drain of the PMOS transistor 114. The NMOS transistor 117 includes a gate connected to the drain of the PMOS transistor 114 and the drain of the NMOS transistor 116, a drain connected to the second end of the current source 112, and a source connected to the power supply line VSS.

[0028] The capacitance bank circuit 118 has a first terminal 118a connected to the drain of the PMOS transistor 114, the drain of the NMOS transistor 116, and the gate of the NMOS transistor 117, a second terminal 118b connected to the drain of the NMOS transistor 117, the output terminal 11d, and the second terminal of the current source 112, and three control terminals 118c, 118d, and 118e connected to the three output terminals of the decoder circuit 120. The decoder circuit 120 includes an input terminal connected to the control terminal 11b, and three output terminals that respectively output signals after decoding the control signals received from the input terminal.

[0029] The configuration of the operational amplifier 12 is substantially the same as that of the operational amplifier 11, and therefore the description of the operational amplifier 12 can be replaced by the description of the operational amplifier 11 with the symbols replaced.

[0030] FIG. 5 is a circuit diagram showing an example of the configuration of the capacitive bank circuit 118. As shown in FIG. The capacitive bank circuit 118 has a first terminal 118a, a second terminal 118b, three control terminals 118c, 118d, and 118e, as well as capacitive elements 185A, 185C, 185D, and 185E, and switches 186C, 186D, and 186E. The capacitive element 185A, the series-connected capacitive element 185C and switch 186C, the series-connected capacitive element 185D and switch 186D, and the series-connected capacitive element 185E and switch 186E are connected in parallel between the first terminal 118a and the second terminal 118b, respectively.

[0031] The control terminals of the switches 186C, 186D, and 186E are connected to the control terminals 118c, 118d, and 118e, respectively. The capacitance bank circuit 118 is configured so that the capacitance value between the first terminal 118a and the second terminal 118b can be adjusted in stages within a predetermined range by controlling the open / close states of the switches 186C, 186D, and 186E.

[0032] Next, the operation of an amplifier according to an embodiment of the present invention will be described using amplifier 1 as an example. The amplifier stage, which is composed of operational amplifier 11, operational amplifier 12, resistor 31, variable resistor 32, and resistor 33, has the configuration of a so-called instrumentation amplifier, and therefore the closed-loop gain can be changed by switching the resistance value of variable resistor 32. Here, the control signal supplied from control terminal CNT is assumed to be, for example, 3 bits, with 0b000 setting the minimum closed-loop gain G8 and 0b111 setting the maximum closed-loop gain G1.

[0033] If the resistance values ​​of resistor 31, resistor 33, and resistance element 321, resistance element 323, resistance element 325, and resistance element 327 of variable resistor 32 are respectively R1, R3, R21, R22, R23, and R24, when the on-resistance values ​​of switch circuits 324, 326, and 328 are sufficiently small, the maximum closed-loop gain G1 and the minimum closed-loop gain G8 are respectively G(G1)=(R1+R3)·(1 / R21) =(R1+R3)·G21 ---(4) G(G8)=(R1+R3)·(1 / R21+1 / R22+1 / R23+1 / R24) =(R1+R3)·ΣG2x ---(5) Here, G2x is the inverse of R2x (=1 / R2x), where x represents an arbitrary subscript (in this example, x = 1, 2, 3, or 4). The ratio of each resistor value is selected so that the required gain range can be comprehensively set according to the dynamic range of the input signal required for amplifier 1.

[0034] The capacitance bank circuit 118 is a so-called Miller compensation capacitance, and therefore, by switching its capacitance value, it is possible to switch the gain bandwidth of the operational amplifiers 11 and 12. Here, it is assumed that the control signal supplied from the control terminal CNT is, for example, 3 bits, and when it is 0b000, i.e., when the closed-loop gain is the minimum, G8, the capacitance value is set to (C0+C1+C2+C3), and when it is 0b111, i.e., when the closed-loop gain is the maximum, G1, the capacitance value is set to C0.

[0035] When the transconductance of the operational amplifiers 11 and 12 is Gm, the gain bandwidth product GBW(G1) corresponding to the maximum closed-loop gain G1 and the gain bandwidth product GBW(G8) corresponding to the minimum closed-loop gain G8 are respectively given by GBW(G1)=G(G1)·BW(G1) =Gm / C0 ---(6) GBW(G8)=G(G8)·BW(G8) =Gm / (C0+C1+C2+C3) ---(7) It is expressed as:

[0036] Here, from the relationships of equations (4) to (7), in order to obtain an equal bandwidth BW between the maximum closed-loop gain G1 and the minimum closed-loop gain G8, it is sufficient to satisfy the relationship BW(G1)=BW(G8). That is, the following equation (8) G21 / ΣG2x=C0 / ΣCx ---(8) The constants may be determined so as to satisfy the following relationship: The constants may also be determined so as to satisfy the same relationship for the intermediate closed-loop gain settings.

[0037] Next, the operation and effects of the amplifier according to this embodiment will be described in comparison with the operation of a conventional amplifier (comparison example).

[0038] 6 is a timing diagram showing the time variations of the clock signal and input signal supplied to amplifier 1 and a conventional amplifier (comparison example), and the modulator output signal (modulated input signal). Fig. 6 includes three different timing diagrams, which, from top to bottom, show the clock signal (CLK), the input differential signal ΔVin, and the modulator output signal ΔMOD.

[0039] The clock signal supplied from the clock terminal CLK is a binary clock signal that periodically repeats a first state "L" and a second state "H," transitioning from "L" to "H" at time t1 and from "H" to "L" at time t4. For example, when CLK="L," the chopper circuit 21 functioning as a modulator and the chopper circuit 22 functioning as a demodulator are switched to a direct connection state and a cross connection state, respectively. When CLK="H," the chopper circuits 21 and 22 are switched to the other connection state, i.e., the cross connection state and the direct connection state, respectively, compared to the connection state when CLK="L." Here, for simplicity of explanation, the input differential signal ΔVin, which is the differential voltage input to the input terminals INP and INN, is set to a positive constant value "Vin," and the offset voltage is assumed to be zero.

[0040] The modulator output signal ΔMOD, which is an output signal from the chopper circuit 21, is a modulated signal obtained by modulating the input differential signal ΔVin in synchronization with the clock signal by the chopper circuit 21. The responsiveness of the modulator output signal ΔMOD is predominantly determined by the on-resistance of the chopper circuit 21 in the conductive state and the time constant determined by the input capacitances of the operational amplifiers 11 and 12, and is generally sufficiently fast, so is shown as a square wave in FIG.

[0041] FIG. 7 is a timing diagram of the operation of amplifier 1 and a conventional amplifier (comparison example). FIG. 7 includes six timing charts, which, from top to bottom, show the response waveforms over time of the amplifier stage output signal ΔAOUT of this embodiment, the amplifier stage output signal ΔAOUT' of the conventional technology, the demodulator output signal ΔDEMOD of this embodiment, the demodulator output signal ΔDEMOD' of the conventional technology, the integral value ∫ΔDEMOD obtained by smoothing the demodulator output signal ΔDEMOD of this embodiment, and the integral value ∫ΔDEMOD' obtained by smoothing the demodulator output signal ΔDEMOD' of the conventional technology. The maximum closed-loop gain G1 is indicated by a solid line, and the minimum closed-loop gain G8 is indicated by a dashed line. After time t7, the sequence repeats from times t1 to t6, so a description thereof will be omitted.

[0042] The amplifier stage output signal ΔAOUT, which is the output signal of the amplifier stage in amplifier 1, is a differential signal between output terminal 11d of operational amplifier 11 and output terminal 12d of operational amplifier 12. Because the amplifier stage output signal ΔAOUT has a finite response, if any closed-loop gain from the maximum closed-loop gain G1 to the minimum closed-loop gain G8 is Gn (here, n is a natural number from 1 to 8), then from time t1 to t3, it will settle from an initial value -Vin·Gn to a final value +Vin·Gn, and from time t4 to t6, it will settle from the initial value +Vin·Gn to a final value -Vin·Gn. Here, the response waveforms when the maximum closed-loop gain G1 or the minimum closed-loop gain G8 is set are similar because they have the same bandwidth BW.

[0043] On the other hand, since the amplification stage output signal ΔAOUT′ in the conventional technology has a finite responsiveness, the closed-loop gain Gn is statically settled from the initial value −Vin·Gn to the final value +Vin·Gn from time t1 to t3, and from the initial value +Vin·Gn to the final value −Vin·Gn from time t4 to t6, which is the same. However, the response waveforms when the maximum closed-loop gain G1 or the minimum closed-loop gain G8 is set, respectively, are not similar because the bandwidths BW are not the same.

[0044] As described above, the demodulator output signal ΔDEMOD, which is the output signal from the chopper circuit 22 that functions as a demodulator in the amplifier 1, has a similar waveform when the amplification stage output signal ΔAOUT is set to the maximum closed-loop gain G1 or the minimum closed-loop gain G8, and therefore the demodulated waveforms also have a similar relationship.

[0045] On the other hand, in the prior art, the demodulator output signal ΔDEMOD′ does not have a similar waveform when the amplifier stage output signal ΔAOUT′ is set to the maximum closed-loop gain G1 or the minimum closed-loop gain G8, and therefore the demodulated waveforms do not have a similar relationship either.

[0046] As mentioned above, the integral value ∫ΔDEMOD in amplifier 1 has a similar waveform when the demodulator output signal ΔDEMOD is set to the maximum closed-loop gain G1 or the minimum closed-loop gain G8, so the integral values ​​are also similar and the attenuation rates relative to the ideal values ​​(= Vin·G1, Vin·G8) are equal. This makes it easy to obtain a stable chopper amplifier gain for the set closed-loop gain.

[0047] On the other hand, as mentioned above, the integral value ∫ΔDEMOD' in the conventional technology does not have a similar waveform when the demodulator output signal ΔDEMOD' is set to the maximum closed-loop gain G1 or the minimum closed-loop gain G8, so the integral values ​​are not similar either, and the attenuation rates relative to the ideal values ​​(= Vin·G1, Vin·G8) are different. For this reason, it is difficult to obtain a stable chopper amplifier gain for the set closed-loop gain.

[0048] Thus, the amplifier according to this embodiment can obtain a stable and effective chopper amplifier gain for the closed loop gain setting of the amplifier stage, compared to the prior art.

[0049] Figures 8(a) to 8(d) respectively show the frequency characteristics of the closed-loop gain for the closed-loop gain designs G1 to G8 in a conventional amplifier, the frequency characteristics of the closed-loop gain for the closed-loop gain designs of amplifier 1 (from the highest closed-loop gain G1 to the lowest closed-loop gain G8), a relationship diagram showing the effective gain versus the set gain, and a relationship diagram showing the normalized effective gain (= effective gain / set gain) based on an ideal straight line of the chopper amplifier versus the set gain.

[0050] First, let us consider FIG. 8(a). Here, G0 in FIG. 8(a) represents the open-loop gain curve of the operational amplifier, G1 to G8 represent the DC closed-loop gains from the maximum set gain to the minimum set gain, fc represents the cutoff frequency of the operational amplifier, fGBW represents the gain bandwidth of the operational amplifier, and fBW1 to fBW8 represent the bandwidths from the maximum set gain to the minimum set gain. According to FIG. 8(a), the bandwidths fBW1 to fBW8 at each set gain are determined by the intersections of the open-loop gain curve G0 of the operational amplifier, each set gain G1 to G8, and the DC closed-loop gain. Therefore, the higher the set gain, the lower the bandwidths fBW1 to fBW8 at each set gain. Therefore, when the set gain is high, the responsiveness of the amplifier stage is poor, and when the set gain is low, the responsiveness of the amplifier stage is good. This changes the responsiveness of the amplifier stage depending on the set gain, which leads to changes in the deviation of the equivalent gain of the chopper amplifier from its design value.

[0051] Next, we will explain Figure 8(b). Here, fc1 to fc8, corresponding to the maximum to minimum set gains, are the cutoff frequencies of the operational amplifiers, and fBW(const) is the bandwidth common to all set gains. Note that G0 to G8 and fGBW are the same as in Figure 8(a). In amplifier 1, the bandwidth fBW(const) is determined to be a constant value at the intersection with the DC closed-loop gain at each set gain G1 to G8 because the open-loop gain curve G0 of operational amplifiers 11 and 12 varies depending on the set gain. Therefore, the bandwidth fBW at each set gain is equal to the constant bandwidth fBW(const) and remains stable whether the set gain is high or low. Therefore, amplifier 1 provides stable responsiveness of the amplification stage regardless of the set gain, and the deviation of the equivalent gain of the chopper amplifier from its design value is also constant.

[0052] Next, we will explain Figure 8(c). In Figure 8(c), the horizontal axis is the set closed-loop gain of the amplification stage, and the vertical axis is the effective gain of the chopper amplifier. An ideal straight line (dotted line), the characteristic curve of this embodiment (solid line), and the characteristic curve of the conventional technology (dashed line) are shown. The ideal straight line is a line with a slope of 1. With the conventional technology, when the set gain is low, the curve asymptotically approaches the ideal straight line, but the higher the set gain, the greater the deviation from the ideal straight line. On the other hand, with the amplifier of this embodiment, there is a small deviation from the ideal straight line at any gain, but the ratio to the ideal straight line is always constant.

[0053] Next, we will explain Figure 8(d). Figure 8(d) is a graph in which each curve in Figure 8(c) is normalized by an ideal line. Similar to Figure 8(c), Figure 8(d) shows the ideal line (dotted line), the characteristic curve of this embodiment (solid line), and the characteristic curve of the conventional technology (dashed line). In Figure 8(d), the horizontal axis represents the set closed-loop gain of the amplifier stage, and the vertical axis represents the normalized effective gain of the chopper amplifier based on the ideal line. It is obvious that the ideal line is always 1. As mentioned above, in the conventional technology (see Figure 8(c)), the deviation from the ideal line increases as the set gain increases. In contrast, in the amplifier of this embodiment, the deviation from the ideal line is small by a ratio α at any gain, but the ratio to the ideal line is always constant. By setting the set gain while taking this deviation ratio α into account, it is easy to obtain the desired effective gain at any gain setting.

[0054] As described above, according to the amplifier 1, the capacitor bank circuit 118 is controlled so that the bandwidth BW is constant in accordance with the closed-loop gain G, for which the gain-bandwidth product GBW of the operational amplifiers 11 and 12 is set, and the Miller compensation capacitance value is optimized, so that the effective chopper amplifier gain that occurs due to a gain error caused by insufficient settling time can be stably obtained.

[0055] [Second embodiment] FIG. 9 is a circuit diagram schematically showing the configuration of an amplifier 2, which is an example of an amplifier according to the second embodiment of the present invention.

[0056] Amplifier 2 differs from amplifier 1 in that it includes operational amplifiers 11A and 12A instead of operational amplifiers 11 and 12, respectively, but is essentially the same in other respects. Therefore, in the description of this embodiment, components that are essentially the same as those in amplifier 1 will be assigned the same reference numerals and descriptions thereof will be omitted.

[0057] The amplifier 2 includes input terminals INP and INN, a chopper circuit 21, operational amplifiers 11A and 12A, resistors 31 and 33, a variable resistor 32, a chopper circuit 22, a clock terminal CLK, a control terminal CNT, and output terminals OUTP and OUTN. Next, the operational amplifiers 11A and 12A will be described. Because the operational amplifier 12A has a configuration that is substantially the same as that of the operational amplifier 11A, the description of the operational amplifier 12A can be replaced by the description of the operational amplifier 11A, with the symbols being replaced.

[0058] FIG. 10 is a circuit diagram showing an example of the configuration of the operational amplifier 11A in the amplifier 2. As shown in FIG. The operational amplifier 11A differs from the operational amplifier 11 (see FIG. 4) in that it has a capacitive element 138 with a predetermined fixed capacitance value instead of a capacitive bank circuit 118 with a variable capacitance value between the terminals of a first terminal 118a and a second terminal 118b, and in that it has current source circuits 131 and 132 with a variable current value based on a control signal instead of current sources 111 and 112 with a predetermined fixed current value, but is essentially the same in other respects. Therefore, in the description of the operational amplifier 11A, components corresponding to those of the operational amplifier 11 are designated by the same reference numerals, and redundant description will be omitted.

[0059] FIG. 11 is a circuit diagram showing an example of the configuration of the current source circuit 131. The current source circuit 131 has a first terminal 131a, a second terminal 131b, three control terminals 131c, 131d, and 131e, PMOS transistors 135A to 135E, switch circuits 136C, 136D, and 136E, and a current source 137 including a first terminal connected to the drain of the PMOS transistor 135A and a second terminal connected to a power supply line VSS. The first terminal 131a and the second terminal 131b of the current source circuit 131 are connected in the same manner as the first terminal and the second terminal of the current source 111. That is, the first terminal 131a is connected to the power supply line VDD, and the second terminal 131b is connected to the sources of the PMOS transistors 113 and 114.

[0060] The PMOS transistors 135A to 135E form a current mirror circuit, in which the current sunk from the current source 137, i.e., the drain current of the PMOS transistor 135A, is copied and passed to the drains of the PMOS transistors 135B to 135E. The PMOS transistors 135C, 135D, and 135E are connected in series with the switch circuits 136C, 136D, and 136E, respectively. The PMOS transistor 135B, the series-connected PMOS transistor 135C and switch circuit 136C, the series-connected PMOS transistor 135D and switch circuit 136D, and the series-connected PMOS transistor 135E and switch circuit 136E are connected in parallel between the first terminal 131a and the second terminal 131b.

[0061] The control terminals of the switch circuits 136C, 136D, and 136E are connected to the control terminals 131c, 131d, and 131e, respectively, and are controlled to switch between an open state (off state) in which both ends of the switch circuits 136C, 136D, and 136E are open and a closed state (on state) in which both ends are short-circuited, depending on the signals supplied from the control terminals 131c, 131d, and 131e.

[0062] It should be noted that the current source circuit 132 has a configuration that is substantially the same as that of the current source circuit 131, and therefore the description of the current source circuit 132 can be replaced by the description of the current source circuit 131 by substituting the reference numerals.

[0063] Next, the operation of the amplifier according to this embodiment will be described using the amplifier 2 as an example. The amplifier 2 can switch the current values ​​of the current source circuits 131 and 132 to switch the gain bandwidths of the operational amplifiers 11A and 12A.

[0064] For example, the control signal is 3 bits, and here, when the control signal corresponding to the minimum closed-loop gain G8 is 0b000, the current value is set to I0, and when the control signal corresponding to the maximum closed-loop gain G1 is 0b111, the current value is set to I0+I1+I2+I3. When the Miller compensation capacitance value of the capacitive element 138 of the operational amplifiers 11A and 12A is C0, the gain-bandwidth products GBW corresponding to the maximum closed-loop gain G1 and the minimum closed-loop gain G8, respectively, are expressed as follows, with K being a proportionality constant: GBW(G1)'=K√(I0+I1+I2+I3) / C0 ---(9) GBW(G8)'=K√(I0) / C0 ---(10) It is expressed as:

[0065] Here, from the relationships of equations (4) to (5) and equations (9) to (10), in order to obtain an equal bandwidth BW for the maximum closed-loop gain G1 and the minimum closed-loop gain G8, it is sufficient to satisfy the relationship BW(G1)=BW(G8), G21 / ΣG2x=√(ΣIx / I0) ---(11) The constants can be determined so as to satisfy the following relationship: For the intermediate closed-loop gain settings, the constants can be determined so as to satisfy the following similar relationship:

[0066] As described above, according to the amplifier 2, the current source circuits 131, 132 of the operational amplifiers 11A, 12A are controlled so that the gain-bandwidth product GBW of the operational amplifiers 11A, 12A has a constant bandwidth BW in accordance with the set closed-loop gain G, and the transconductance Gm of the operational amplifiers 11A, 12A is optimized, so that the effective chopper amplifier gain that occurs due to a gain error caused by insufficient settling time can be stably obtained.

[0067] According to the present invention, the effective gain reduction rate due to insufficient settling time does not change depending on the closed-loop gain setting of the amplifier stage, so the effective chopper amplifier gain can be obtained stably for the closed-loop gain setting, thereby improving the usability of the amplifier.

[0068] The present invention is not limited to the above-described embodiments. Various other embodiments are possible, and various omissions, additions, substitutions, or modifications may be made without departing from the spirit of the invention. For example, the switching-controlled capacitance bank circuit 118 may be a so-called lead compensation capacitance connected in parallel to the feedback resistors 31 and 33, rather than a so-called Miller compensation capacitance. The switching-controlled capacitance element may be connected in series with a resistive element for frequency zero placement compensation. Various capacitance elements may be used, such as MOS (Metal-Oxide-Semiconductor) capacitance, MIM (Metal-Insulator-Metal) capacitance, and MOM (Metal-Oxide-Metal) capacitance.

[0069] Although the operational amplifier configuration is exemplified as a two-stage amplifier with an N-channel input and a single-ended type, it may be a complementary P-channel input type instead of an N-channel input type, or a fully differential type instead of a single-ended type.Furthermore, the operational amplifier is not limited to two amplification stages, but may be a multi-stage amplifier consisting of three or more amplification stages, or any of the amplification stages may include a cascode amplifier configuration.

[0070] In the above-described embodiment, a configuration example in which the resistance value of the variable resistor 32 can be switched to set the closed-loop gain has been described, but a configuration in which the resistance value of the resistor 31 or the resistor 33 can be switched may also be used. The variable resistor 32 is a configuration example in which the resistance value between two terminals can be switched and controlled, but a midpoint terminal for setting the common-mode potential may also be provided.

[0071] The amplifier according to this embodiment may include another amplifier stage between either chopper circuit 21 or 22 and the amplifier stage, or may further include a DC cut filter such as a high-pass filter that can block DC components contained in the signal. The control signal supplied from the control terminal CNT may be preset in an inspection process before shipping, or may be automatically controlled dynamically. Furthermore, a delay element or delay circuit may be provided between chopper circuits 21 and 22 and clock terminal CLK to set an appropriate delay time.

[0072] These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0073] 1,2 Amplifier INP, INN Input terminal (first input terminal, second input terminal) OUTP, OUTN Output terminals (first output terminal, second output terminal) 11,11A operational amplifier (first operational amplifier) 12,12A operational amplifier (second operational amplifier) 21, 22 Chopper circuit (first chopper circuit, second chopper circuit) 31 Resistor (first resistor) 32 Variable resistor (second resistor) 33 Resistor (third resistor) 118 Capacitor bank circuit 131,132 current source

Claims

1. a first input terminal and a second input terminal; a first chopper circuit having a first input end connected to the first input terminal, a second input end connected to the second input terminal, a control end that receives a clock signal as a switching signal, a first output end, and a second output end, and capable of switching, based on the switching signal, between a first connection state in which the first input end and the first output end are connected and the second input end and the second output end are connected, and a second connection state in which the first input end and the second output end are connected and the second input end and the first output end are connected; a first resistor; a second resistor having at least one control end and capable of switching a resistance value based on a control signal applied to the control end; a third resistor; and a first operational amplifier having a first input terminal connected to the first output terminal of the first chopper circuit, a second input terminal connected to one end of the first resistor and one end of the second resistor, an output terminal connected to the other end of the first resistor, and a control terminal for receiving the control signal; a second operational amplifier having a first input terminal connected to the second output terminal of the first chopper circuit, a second input terminal connected to one end of the third resistor and the other end of the second resistor, an output terminal connected to the other end of the third resistor, and a control terminal receiving the control signal; a second chopper circuit having a first input terminal connected to the output terminal of the first operational amplifier, a second input terminal connected to the output terminal of the second operational amplifier, a control terminal that receives the clock signal as the switching signal, a first output terminal, and a second output terminal, and is capable of switching, based on the switching signal, between a first connection state in which the first input terminal and the first output terminal are connected and the second input terminal and the second output terminal are connected, and a second connection state in which the first input terminal and the second output terminal are connected and the second input terminal and the first output terminal are connected; a first output terminal connected to the first output end of the second chopper circuit and a second output terminal connected to the second output end of the second chopper circuit, The amplifier is characterized in that the first operational amplifier and the second operational amplifier are configured so that the gain bandwidths of the first and second operational amplifiers can be switched based on the control signal.

2. 2. The amplifier according to claim 1, wherein at least one of the first and second operational amplifiers has a capacitance bank circuit capable of switching a capacitance value based on the control signal received from the control terminal.

3. 2. The amplifier according to claim 1, wherein at least one of the first and second operational amplifiers has a current source capable of switching the drive current value of the first and second operational amplifiers based on the control signal received from the control terminal.

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