Laminated ceramic capacitor and method for manufacturing laminated ceramic capacitor

Abstract

To provide a laminated ceramic capacitor having excellent adhesion between a dielectric layer and an internal electrode layer and capable of suppressing delamination.SOLUTION: A laminated ceramic capacitor includes a laminated body having a laminated structure in which a plurality of dielectric layers containing ceramic as a main component and a plurality of internal electrode layers are alternately laminated. The laminated body has first and second side surfaces facing each other and first and second end surfaces facing each other. The internal electrode layers include first and second internal electrode layers. A length of the first internal electrode layer in a first direction in which the first and second side surfaces face each other is longer than a length of the second internal electrode layer in the first direction. At least one internal electrode layer has at least one protrusion on one surface facing the second internal electrode layer. The protrusion is in a region where the first and second internal electrode layers do not overlap in a lamination direction in the first internal electrode layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor. [Background technology]

[0002] Large, high-capacity, and highly reliable multilayer ceramic capacitors are required for in-vehicle computers, etc. Patent Document 1 describes a multilayer ceramic capacitor in which the areas of internal electrodes arranged opposite each other with a ceramic sheet interposed therebetween are changed, thereby dispersing the tensile stress that occurs in the margins when a voltage is applied to the internal electrodes and suppressing the occurrence of cracks. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-124057 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when the areas of the internal electrodes are made different as in the configuration of Patent Document 1, there is a risk that the amount of metal elements diffused from each internal electrode will vary in the areas where they do not overlap in the stacking direction, near the ends of the internal electrode layers with larger areas and near the ends of the internal electrode layers with smaller areas, resulting in differences in composition in the dielectric layers and becoming the starting points for delamination.

[0005] An object of one aspect of the present invention is to provide a multilayer ceramic capacitor that has excellent adhesion between dielectric layers and internal electrode layers and can suppress delamination. [Means for solving the problem]

[0006] In order to solve the above problem, one aspect of the present invention is to The laminate has a laminate structure in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are alternately stacked, the laminate has a first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other, the internal electrode layers include a first internal electrode layer and a second internal electrode layer, the first internal electrode layer has a length in a first direction, in which the first side surface and the second side surface face each other, that is longer than a length in the first direction of the second internal electrode layer; At least one of the first internal electrode layers has at least one protrusion on one surface facing the second internal electrode layer, The present invention provides a multilayer ceramic capacitor in which the protrusion is present in an area of ​​the first internal electrode layer where the first internal electrode layer and the second internal electrode layer do not overlap in the lamination direction. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the adhesion between the dielectric layers and the internal electrode layers is excellent and delamination can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a partial cross-sectional perspective view of an example of a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 2] 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line AA in FIG. 1. [Figure 3] 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line BB in FIG. 1. [Figure 4] FIG. 4(A) is a partial cross-sectional perspective view of a multilayer ceramic capacitor having no protrusions, FIG. 4(B) is a cross-sectional view taken along line AA in FIG. 4(A), and FIG. 4(C) is a cross-sectional view taken along line BB in FIG. 4(A). [Figure 5] FIG. 4B is an enlarged schematic diagram of a region M1 in FIG. 4C. [Figure 6]FIG. 4 is an enlarged schematic diagram of a region M1 in FIG. 3. [Figure 7] FIG. 1 is a partial cross-sectional perspective view of an example of a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a cross-sectional view of the multilayer ceramic capacitor taken along line AA in FIG. [Figure 9] 8 is a cross-sectional view of the multilayer ceramic capacitor taken along line BB in FIG. 7. [Figure 10] 1 is a flowchart illustrating an example of a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 11] 3A to 3C are diagrams illustrating an example of a lamination step in a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 12] 3A to 3C are diagrams illustrating an example of a lamination step in a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 13] 3A to 3C are diagrams illustrating an example of a lamination step in a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 14] 1 is a diagram showing a schematic diagram of a first internal electrode layer on which a convex portion is formed in a multilayer ceramic capacitor according to an embodiment of the present disclosure, and a result of a surface shape analysis of the first internal electrode layer in a first direction. [Figure 15] 1 is a diagram showing a schematic diagram of a first internal electrode layer on which a convex portion is formed in a multilayer ceramic capacitor according to an embodiment of the present disclosure, and a result of a surface shape analysis of the first internal electrode layer in a first direction. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following describes in detail aspects of the present disclosure, but the present disclosure is not limited thereto. In this specification and the drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description. In this specification, "orthogonal" means "orthogonal" or "substantially orthogonal." The multilayer ceramic capacitor will be described below with reference to the drawings.

[0010] (multilayer ceramic capacitors) FIG. 1 is a partial cross-sectional perspective view of an example of a multilayer ceramic capacitor according to one embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, a multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. One of the two end faces of the laminated chip 10 is referred to as a first end face, and the other is referred to as a second end face. As long as the first end face and the second end face are one of the end faces of the laminated chip 10, either the first end face 18a or the second end face 18b may be one of the end faces. Of the four faces other than the first end face 18a and the second end face 18b, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces, one of which is referred to as a first side face, and the other is referred to as a second side face. As long as the first side surface and the second side surface are side surfaces of the laminated chip 10, either of them may be the first side surface 19a or the second side surface 19b. Note that because the end surface in the stacking direction is defined as the top surface or the bottom surface, the top surface of the laminated chip 10 is not limited to the top side, and either of the end surfaces in the stacking direction may be the top surface or the bottom surface. The external electrodes 20a, 20b extend to the top surface, bottom surface, first side surface 19a, and second side surface 19b of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

[0011] The laminated chip 10 has a laminated structure in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed to the first end face 18a, on which the external electrodes 20a of the laminated chip 10 are provided, and the second end face 18b, on which the external electrodes 20b are provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrodes 20a and 20b. Furthermore, in the laminated chip 10, the top and bottom surfaces of the dielectric layers 11 and internal electrode layers 12 in the stacking direction (hereinafter referred to as the stacking direction) are formed by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the primary component of the cover layers 13 is the same as the primary component of the dielectric layers 11. In this specification, the term "primary component" refers to the component that is contained in the largest amount of material among the components.

[0012] 2 and 3, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance portion 14. In other words, the capacitance portion 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0013] As shown in FIG. 2, the regions where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed are referred to as the first end margin 15a and the second end margin 15b. The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed is the first end margin 15a, and the region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed is the first end margin 15b. In other words, the first end margin 15a and the second end margin 15b are regions where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode being interposed. The first end margin 15a and the second end margin 15b are regions where no capacitance is generated.

[0014] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the first internal electrode layer 12a are referred to as the first side margin portion 16a and the second side margin portion 16b. That is, the side margin portions 16a and 16b are regions provided so as to cover the ends of the multiple first internal electrode layers 12a stacked in the laminated chip 10 that extend toward the two side surfaces. The first side margin portion 16a and the second side margin portion 16b are also regions that do not generate electrical capacitance.

[0015] 3, the portion surrounded by the cover layer 13, the first side margin portion 16a or the second side margin portion 16b, and the capacitance portion 14 is referred to as a margin portion 17. The margin portion 17 is also a region that does not generate capacitance.

[0016] As shown in FIG. 3, in the multilayer ceramic capacitor 100, the width of the internal electrode layer 12 varies in two stages in a direction in which the first side margin portion 16a and the second side margin portion 16b face each other, i.e., in a first direction (hereinafter referred to as the first direction) in which the first side surface 19a and the second side surface 19b face each other. More specifically, as shown in FIG. 3, the internal electrode layer 12 includes a first internal electrode layer 12a and a second internal electrode layer 12b, and the width W2, which is the length in the first direction of the second internal electrode layer 12b, is smaller than the width W1, which is the length in the first direction of the first internal electrode layer 12a. That is, the length in the first direction of the first internal electrode layer is longer than the length in the first direction of the second internal electrode layer. The stacking direction and the first direction are perpendicular to each other. Furthermore, at least one first internal electrode layer 12a has at least one protrusion 30 on one surface facing the second internal electrode layer 12b, and the protrusion 30 is present in a region M1 of the first internal electrode layer 12a where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the stacking direction. Note that the margin portion 17 may be one of the regions M1. The presence of the protrusion 30 in this region improves the adhesion between the dielectric layer and the internal electrode layer, making it possible to suppress delamination. This point will be explained in detail.

[0017] First, a multilayer ceramic capacitor 200 will be described, which differs from the multilayer ceramic capacitor 100 according to this embodiment in that the first internal electrode layers 12a do not have any protrusions. FIG. 4(A) is a partial cross-sectional perspective view of the multilayer ceramic capacitor 200 having no protrusions on the internal electrode layers 12a, FIG. 4(B) is a cross-sectional view taken along line AA in FIG. 4(A), and FIG. 4(C) is a cross-sectional view taken along line BB in FIG. 4(A). As shown in FIG. 4(C), the multilayer ceramic capacitor 200 has the same configuration as the multilayer ceramic capacitor 100, except that it does not have any protrusions. FIG. 5 is an enlarged schematic view of region M1 in FIG. 4(C). 5, in a region M1 where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the stacking direction, the dielectric layer 11 overlapping with the first internal electrode layer 12a in the stacking direction has a region M2 where there are many metal elements 21 diffused from the first internal electrode layer 12a and the second internal electrode layer 12b, and a region M3 where there are few metal elements 21. In the region M1 where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the stacking direction, the first internal electrode layer 12a diffuses the metal elements 21 into the dielectric layer 11 in the first direction from the entire surface facing the second internal electrode layer 12b, so that the region M2 is a region where there are many metal elements 21. On the other hand, in the region M1 where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the stacking direction, the metal elements 21 from the first internal electrode layer 12a do not reach the region M3, and the metal elements 21 diffused from the end of the second internal electrode layer 12b also do not reach the region M3, so the region M3 is a region with few metal elements 21. In this way, in the region M1 where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the stacking direction, the density of the metal elements 21 diffused from the internal electrode layer 12 varies, which may cause differences in composition in the dielectric layer 11 and lead to delamination.

[0018] 6 is a schematic diagram of an enlarged region M1 in FIG. 3. As shown in FIGS. 3 and 6, if a convex portion 30 is present in a region M1 in the first internal electrode layer 12a where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the stacking direction, the metal element 21 is also diffused from the convex portion 30, and the metal element 21 is also diffused to a region M3 in the region M1 where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the stacking direction. This makes it difficult for the density of the metal element 21 to vary in the region M1 where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the stacking direction, and therefore makes it difficult for composition differences to occur in the region M1 of the dielectric layer 11. In addition, the convex portion 30 itself serves as a wedge to the dielectric layer 11, and its anchor effect improves the adhesion between the dielectric layer and the internal electrode layer, thereby suppressing delamination.

[0019] Furthermore, the first internal electrode layer 12a has a convex portion 30 on one of the surfaces facing the second internal electrode layer 12b. By having the convex portion 30 on one of the surfaces facing the second internal electrode layer 12b, the convex portions do not come close to each other, thereby preventing short circuits from occurring. Furthermore, when the first internal electrode layer 12a has two surfaces facing the second internal electrode layer 12b, that is, when both the upper and lower surfaces of the first internal electrode layer 12a face the second internal electrode layer 12b, it is preferable to have a convex portion 30 on the upper surface side of the multilayer ceramic capacitor 100 from the viewpoint of ease of manufacturing the multilayer ceramic capacitor 100. When the multilayer ceramic capacitor 100 is divided into three parts, an upper part, a central part, and a lower part, in the stacking direction, the closer to the bottom in the stacking direction of the multilayer ceramic capacitor 100, the more likely it is that sufficient adhesion between the dielectric layers 11 and the internal electrode layers 12 will be ensured by compression bonding when manufacturing the multilayer capacitor 100. Therefore, the multilayer ceramic capacitor 100 preferably has the protrusions 30 at the upper part in the stacking direction, more preferably has the protrusions 30 at the upper and central parts in the stacking direction, and even more preferably has the protrusions 30 at the upper, central, and lower parts in the stacking direction.

[0020] Furthermore, the protrusion 30 can be present in any region where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the stacking direction, and there may be one or more protrusions 30. When there are multiple protrusions 30, multiple protrusions 30 exist in the region M1. If there are multiple protrusions 30, the amount of metal element 21 diffused into the region M3 increases, making it easier to resolve the state where the metal element 21 is low in the region M3, and delamination can be further suppressed. Furthermore, the protrusions 30 may extend continuously in a second direction (hereinafter referred to as the second direction) that is a direction perpendicular to the stacking direction and the first direction, and such protrusions 30 may be included as the protrusions 30. When the protrusions 30 extend continuously in the second direction, the metal elements 21 are more likely to diffuse over a wide range in the region M3, which makes it easier to eliminate the state in which the metal elements 21 are scarce in the region M3, and thus makes it possible to further suppress delamination. The multilayer ceramic capacitor 100 may further include a protruding portion 30 extending continuously in the first direction. In this case, the protruding portion 30 extending continuously in the first direction is present in the first end margin portion 15a and the second end margin portion 15b.

[0021] The first internal electrode layer 12a is included in a first laminate structure in which the first internal electrode layers 12a and the dielectric layers 11 are alternately laminated, and the second internal electrode layer 12b is included in a second laminate structure in which the second internal electrode layers 12b and the dielectric layers 11 are alternately laminated. Therefore, in the multilayer ceramic capacitor 100, the laminate structure in which the dielectric layers 11 and the internal electrode layers 12 are alternately laminated preferably has a configuration in which the second laminate structure, the first laminate structure, and the second laminate structure are laminated in this order from bottom to top in the lamination direction. In other words, the second laminate structure is preferably provided on the outside of the first laminate structure in the lamination direction.

[0022] Furthermore, among the internal electrode layers 12 in the laminate structure of the multilayer ceramic capacitor 100, the internal electrode layer 12 located at the end of the laminate structure in the lamination direction is preferably the second internal electrode layer 12b. That is, in the multilayer ceramic capacitor 100, it is preferable that the second laminate structure is located at the end of the laminate direction. In this case, by using the internal electrode layer 12 located next to the second internal electrode layer 12b located at the end of the internal electrode layers 12 in the laminate structure in the lamination direction of the multilayer ceramic capacitor 100 as the first internal electrode layer 12a, it is possible to form a region M1 where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the lamination direction, and therefore a convex portion 30 can be provided in the region M1. This makes it possible to suppress delamination of the multilayer ceramic capacitor 100.

[0023] Furthermore, in the multilayer ceramic capacitor 100, it is preferable that the first internal electrode layers 12a are periodically arranged in the stacking direction of the laminate. "Periodic arrangement" means that they are arranged at regular intervals in the laminate. By periodically arranging the first internal electrode layers 12a in the stacking direction of the laminate, it is possible to equalize the stress differences that occur in the laminate during sintering while maintaining high adhesion between the layers of the laminate, and to suppress cracks and uneven sintering in the first side margin portion 16a and the second side margin portion 16b.

[0024] An example of a laminate in which the first internal electrode layers 12a are arranged periodically in the stacking direction is a laminate in which the first internal electrode layers 12a and the second internal electrode layers 12b are arranged alternately, i.e., a laminate having a stacking structure in which the first stacking structure and the second stacking structure are stacked alternately in the stacking direction. Furthermore, examples of laminates in which the first internal electrode layers 12a are positioned periodically in the stacking direction include laminates in which a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b are arranged alternately, i.e., laminates having a stacking structure in which a plurality of first stacking structures and a plurality of second stacking structures are alternately stacked in the stacking direction. Furthermore, examples of laminates in which the first internal electrode layers 12a are positioned periodically in the stacking direction include laminates in which a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b are arranged at regular intervals with different numbers of layers, i.e., laminates having a stacking structure in which a plurality of first stacking structures and a plurality of second stacking structures are stacked at regular intervals in the stacking direction with different numbers of layers.

[0025] The multilayer ceramic capacitor of the present disclosure may have embodiments exemplified in Figures 7 to 9. Figure 7 is a partial cross-sectional perspective view of an example of a multilayer ceramic capacitor according to one embodiment of the present disclosure. Figure 8 is a cross-sectional view taken along line AA in Figure 7. Figure 9 is a cross-sectional view taken along line BB in Figure 7. 7 to 9, in the multilayer ceramic capacitor 100, a plurality of protrusions 30 are present in the first internal electrode layer in a region where the first internal electrode layer and the second internal electrode layer do not overlap in the stacking direction, and the protrusions 30 include protrusions 30 that extend continuously in the second direction. Furthermore, since there are locations where the first internal electrode layers 12a and the second internal electrode layers 12b are alternately arranged, in the multilayer ceramic capacitor 100 shown in FIGS. 7 to 9, the first internal electrode layers 12a are periodically arranged in the stacking direction. Furthermore, in the multilayer ceramic capacitor 100 shown in FIGS. 7 to 9, the internal electrode layer at the endmost position of the internal electrode layers 12 in the stacking direction is the second internal electrode layer 12b.

[0026] The protrusions 30 contain the same metal as the metal contained in the first internal electrode layers 12a. In addition, from the viewpoint of adhesion to the first internal electrode layers 12a, the protrusions 30 preferably have the same composition as the first internal electrode layers 12a. The length of the protrusions 30 in the stacking direction is preferably 1.02 times or more, more preferably 1.03 times, and even more preferably 1.05 times, the thickness of the first internal electrode layers 12a. When the length of the protrusions 30 in the stacking direction is 1.02 times or more the thickness of the first internal electrode layers 12a, the anchor effect in which the protrusions 30 act as wedges is easily obtained. Furthermore, the length of the protrusions 30 in the stacking direction is preferably 3.0 times or less, and more preferably 2.5 times or less. When the length of the protrusions 30 in the stacking direction is 3.0 times or less, cracks due to the difference in shrinkage between the dielectric layers 11 and the protrusions 30 during sintering are less likely to occur.

[0027] The thickness of the internal electrode layer 12 is not particularly limited, but from the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase the capacitance, it is preferably 0.65 μm or less, and more preferably 0.6 μm or less.

[0028] The lower limit of the thickness of the internal electrode layer 12 is not particularly limited, but it is preferable to set it to, for example, 0.3 μm or more.

[0029] To evaluate the thickness of the first internal electrode layer 12a, as illustrated in Figures 1 and 7, the multilayer ceramic capacitor 100 is polished in a first direction up to the center along the first direction to prepare a sample in which a cross section where the dielectric layers 11 and the internal electrode layers 12 are laminated is exposed. Of the exposed cross sections, a cross section corresponding to the first internal electrode layer 12a is selected. At this time, the selected internal electrode layer 12 is selected from within the capacitive section 14.

[0030] Then, for the cross section corresponding to the selected first internal electrode layer 12a, the thickness is measured at the center position along the second direction, and this thickness is taken as the thickness of the first internal electrode layer 12a.

[0031] Furthermore, the length of the protrusions 30 in the stacking direction is preferably 1.03 μm or more and 2.0 μm or less. When the length of the protrusions 30 in the stacking direction is 1.03 μm or more, the protrusions 30 tend to have an anchor effect by acting as wedges. When the length of the protrusions 30 in the stacking direction is 2.0 μm or less, cracks are less likely to occur due to the difference in shrinkage between the dielectric layer 11 and the protrusions 30 during sintering.

[0032] The length of the protrusion 30 in the first direction is preferably 6% to 30% of the length of the first internal electrode layer in the first direction. When the length of the protrusion 30 in the first direction is 6% or more of the length of the first internal electrode layer 12a in the first direction, a decrease in capacitance due to a decrease in the continuity ratio of the internal electrode layer is unlikely to occur, and when it is 30% or less, the dielectric layer is unlikely to become locally thin where the protrusion 30 is present, and the shape of the protrusion 30 is unlikely to remain in the multilayer ceramic capacitor. Furthermore, it is preferable that the shortest length of the protrusion 30 in the first direction and the length in the second direction is 6% to 30% of the length in the first direction of the first internal electrode layer 12a. "The shortest length of the length of the protrusion in the first direction and the length in the second direction" refers to the length of the protrusion 30 in the first direction when the protrusion 30 extends continuously in the second direction, and refers to the length of the protrusion 30 in the second direction when the protrusion 30 extends continuously in the first direction. Note that when the protrusion 30 does not extend continuously in either the first direction or the second direction, the length of the protrusion 30 in the first direction is preferably 6% to 30% of the length of the first internal electrode layer in the first direction. When the shortest length of the protrusion 30 in the first direction and the length in the second direction is 6% or more of the length in the first direction of the first internal electrode layer 12a, a decrease in capacitance due to a decrease in the continuity ratio of the internal electrode layer is unlikely to occur, and when it is 30% or less, the dielectric layer is unlikely to become locally thin where the protrusion 30 is present, and the shape of the protrusion 30 is unlikely to remain in the multilayer ceramic capacitor.

[0033] Furthermore, the shortest length of the protrusions 30 in the first and second directions is preferably 0.05 μm or more, more preferably 0.1 μm or more. When the shortest length of the protrusions 30 in the first and second directions is 0.05 μm or more, a decrease in capacitance due to a decrease in the continuity ratio of the internal electrode layers is unlikely to occur. Furthermore, the shortest length of the protrusions 30 in the first and second directions is preferably 0.35 μm or less, more preferably 0.3 μm or less. When the shortest length of the protrusions 30 in the first and second directions is 0.35 μm or less, the dielectric layer is unlikely to become locally thin where the protrusions 30 are present, and the shape of the protrusions 30 is unlikely to remain in the multilayer ceramic capacitor.

[0034] Note that the smaller the width W2 of the second internal electrode layer 12b, the smaller the capacitance of the multilayer ceramic capacitor 100. Therefore, the ratio of the width W2, which is the length in the first direction of the second internal electrode layer 12b, to the width W1, which is the length in the first direction of the first internal electrode layer 12a, is preferably 0.5 or more, more preferably 0.55 or more, and even more preferably 0.60 or more. On the other hand, if the ratio of the width W2 of the second internal electrode layer 12b is increased, the region M1 where the first internal electrode layer 12a and the second internal electrode layer 12b do not overlap in the lamination direction becomes smaller, and after the first internal electrode layer 12a and the second internal electrode layer 12b are laminated, the convex portion 30 arranged in the region M1 comes into contact with the second internal electrode layer 12b, which may cause a short circuit when the multilayer ceramic capacitor 100 is used. Therefore, the ratio of the width W2 of the second internal electrode layer 12b to the width W1 of the first internal electrode layer 12a is preferably 0.75 or less, more preferably 0.7 or less, and even more preferably 0.65 or less.

[0035] The widths W1 of the first internal electrode layers 12a may differ from one another within a range of ±4%, and the widths W2 of the second internal electrode layers 12b may differ from one another within a range of ±4%. Therefore, the ratio of the width W2 of the second internal electrode layers 12b to the width W1 of the first internal electrode layers 12a may be the ratio of the average value of the widths W2 of the plurality of second internal electrode layers 12b to the average value of the widths W1 of the plurality of first internal electrode layers 12a. Furthermore, the length of the first internal electrode layer 12a in the first direction may be the average value of the widths W1 of the multiple first internal electrode layers 12a, and the length of the first internal electrode layer 12a in the second direction may be the average value of the lengths of the multiple first internal electrode layers 12a in the second direction.

[0036] The size of the multilayer ceramic capacitor 100 is, for example, 1.6 mm in length, 0.8 mm in width, and 0.8 mm in height, or 2.0 mm in length, 1.2 mm in width, and 1.2 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 3.2 mm in length, 2.5 mm in width, and 2.5 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0037] The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layers 12. The dielectric layers 11 are mainly composed of ceramic, and may be mainly composed of, for example, a ceramic material having a perovskite structure represented by the general formula ABO3. Note that the perovskite structure is formed by an ABO3 that deviates from the stoichiometric composition. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr zO3 (0≦x≦1, 0≦y≦1, 0≦z≦1) etc. can be used. Moreover, the protrusions 30 contain the same metal as the metal contained in the internal electrode layers 12. From the viewpoint of adhesion to the internal electrode layers 12, the protrusions 30 preferably have the same composition as the internal electrode layers 12.

[0038] The thickness of the dielectric layer 11 is, for example, preferably 1 μm or less, and more preferably 0.8 μm or less. To evaluate the thickness of the dielectric layers 11, as shown in Figures 1 and 7, the multilayer ceramic capacitor 100 is polished in a first direction up to the center in the first direction to prepare a sample with an exposed cross section where the dielectric layers 11 and internal electrode layers 12 are laminated. From the exposed cross section, three dielectric layers 11 are selected from the top edge, three from the bottom edge, and three located in the center along the lamination direction. In this case, the selected dielectric layers 11 are selected from within the capacitive section 14.

[0039] Then, for the selected dielectric layer 11, the thickness is measured at the center position in the second direction and is defined as the thickness of the dielectric layer 11. By measuring the thicknesses of all the selected dielectric layers 11 using the same procedure and evaluating the average value, the thickness of the dielectric layers 11 in the multilayer ceramic capacitor 100 can be determined.

[0040] In the multilayer ceramic capacitor 100 according to this embodiment, the number of stacked internal electrode layers 12 per mm of height in the stacking direction of the capacitance section 14 is preferably 10 to 600.

[0041] (Manufacturing method of multilayer ceramic capacitors) A method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure includes the steps of forming a first internal electrode layer on a first ceramic green sheet, forming at least one convex portion on the first internal electrode layer, forming a second internal electrode layer on a second ceramic green sheet, the second internal electrode layer having an area smaller than that of the first internal electrode layer, and stacking the second ceramic green sheet on the first ceramic green sheet on which the first internal electrode layer and the convex portion are formed. In addition, in the process of stacking a second ceramic green sheet having a second internal electrode layer formed thereon on a first ceramic green sheet having a first internal electrode layer and a convex portion formed thereon, the second ceramic green sheet having the second internal electrode layer formed thereon is stacked on the first ceramic green sheet having the first internal electrode layer and a convex portion formed thereon so that the first internal electrode layer is sandwiched between the first ceramic green sheet and the second ceramic green sheet. A method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention will now be described. Fig. 10 is a flowchart showing an example of a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure.

[0042] (1) Raw material powder preparation process (S1) First, a dielectric material for forming the dielectric layer 11 is prepared. The dielectric material includes a ceramic that is the main component of the dielectric layer 11. The A-site elements and B-site elements contained in the dielectric layer 11 are typically present in the form of a sintered compact of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the main component ceramic of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0043] Depending on the purpose, a predetermined additive compound may be added to the obtained ceramic powder, such as oxides of Zr (zirconium), Ca (calcium), Sr (strontium), Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), and rare earth elements, as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon).

[0044] Next, a margin material for forming the first end margin portion 15a and the second end margin portion 15b is prepared. The margin material contains the main component ceramic of the first end margin portion 15a and the second end margin portion 15b. BaTiO3 powder, for example, is prepared as the main component ceramic. BaTiO3 powder can be prepared using the same procedure as the dielectric material. A specific additive compound is added to the obtained BaTiO3 powder depending on the purpose. Examples of additive compounds include oxides of Zr, Ca, Sr, Mg, Mn, V, Cr, and rare earth elements, as well as oxides or glasses of Co, Ni, Li, B, Na, K, and Si.

[0045] Next, a cover material for forming the cover layer 13 is prepared. The cover material contains the main ceramic component of the cover layer 13. For example, BaTiO3 powder is prepared as the main ceramic component. The BaTiO3 powder can be prepared using the same procedure as for the dielectric material. A predetermined additive compound is added to the obtained BaTiO3 powder depending on the purpose. Examples of the additive compound include oxides of Zr, Ca, Sr, Mg, Mn, V, Cr, and rare earth elements, as well as oxides or glass of Co, Ni, Li, B, Na, K, and Si. The margin material described above may also be used as the cover material.

[0046] (2) Lamination process (S2) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the dielectric material obtained in the raw powder preparation process and wet mixed. The resulting slurry is used to coat a substrate with a ceramic green sheet 51, which will become a strip-shaped dielectric material, having a thickness of, for example, 0.8 μm or less, by, for example, a die coater method or a doctor blade method, and then dried.

[0047] Next, as illustrated in Fig. 11(A), a metal conductive paste for forming an internal electrode layer containing an organic binder is printed on the surface of the ceramic green sheet 51 by screen printing, gravure printing, or the like, to arrange a first pattern 52a for the first internal electrode layer. As a result, the first internal electrode layer is formed on the first ceramic green sheet 51. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11.

[0048] 11(B), a metal conductive paste containing an organic binder is printed on the surface of the first pattern 52a by screen printing, gravure printing, or the like, to arrange the convex pattern 31 on the first pattern 52a. At this time, the convex pattern 31 is arranged so that the convex portion 30 is formed on the outer side along the first direction than the edge on the first direction side of a third pattern 52b for a second internal electrode layer (described later) and on the inner side along the first direction than the edge on the first direction side of the first pattern 52a for the first internal electrode layer. As a result, the convex portion 30 is formed on the first internal electrode layer 12a.

[0049] Next, a binder such as an ethyl cellulose binder and an organic solvent such as a terpineol binder are added to the margin material obtained in the raw material powder preparation process, and the mixture is kneaded in a roll mill to obtain a margin paste for the reverse pattern layer. As illustrated in Figures 11(A) and 11(B), the margin paste may be printed in the peripheral area of ​​the ceramic green sheet 51 where the first pattern 52a is not printed, thereby arranging the second pattern 53a and filling in the step with the first pattern 52a.

[0050] 11(C), the ceramic green sheets 51, the first patterns 52a, and the second patterns 53a are stacked so that the first internal electrode layers 12a and the dielectric layers 11 alternate, and so that the edges of the first internal electrode layers 12a are alternately exposed at both longitudinal end faces of the dielectric layers 11 and alternately drawn out to a pair of external electrodes 20a, 20b of opposite polarity, to obtain a first laminated portion. For example, the number of stacked ceramic green sheets 51 is set to 20 to 250. Note that in the first laminated portion, the ceramic green sheets 51, the first patterns 52a, and the second patterns 53a without the convex patterns 31 are not stacked on the ceramic green sheets 51, the first patterns 52a, and the second patterns 53a with the convex patterns 31 formed thereon.

[0051] Next, the second laminated portion is obtained in the same manner as the process for obtaining the first laminated portion, except for arranging the convex pattern 31. For example, the number of laminated ceramic green sheets 51 is set to 20 to 250.

[0052] 11(D), a metal conductive paste for forming an internal electrode layer is printed on the surface of the ceramic green sheet 51 by screen printing, gravure printing, or the like to arrange the third pattern 52b for the second internal electrode layer. The width W4 of the third pattern 52b for the second internal electrode layer in the opposing direction of the two side surfaces is narrower than the width W3 of the first pattern 52a for the first internal electrode layer. As a result, a second internal electrode layer having an area smaller than that of the first internal electrode layer is formed on the second ceramic green sheet.

[0053] As illustrated in Figure 11(D), a margin paste may be printed on the ceramic green sheet 51 in the peripheral area where the third pattern 52b is not printed to place the fourth pattern 53b and fill in the step with the third pattern 52b.

[0054] 11(E), the ceramic green sheets 51, the third pattern 52b, and the fourth pattern 53b are laminated so that the second internal electrode layers 12b and the dielectric layers 11 alternate, and so that the edges of the second internal electrode layers 12b are alternately exposed at both end faces in the length direction of the dielectric layers 11 and are alternately drawn out to a pair of external electrodes 20a, 20b of opposite polarity, to obtain a third laminated portion. For example, the number of laminated ceramic green sheets 51 is set to 20 to 250.

[0055] Next, as shown in Figures 12(A) and 12(B), the third laminate portion, the second laminate portion, the first laminate portion, and the third laminate portion are laminated in this order to obtain a ceramic laminate. After the second laminate portion, the first laminate portion, and the third laminate portion are laminated in this order to obtain a laminate 40 including the protrusions 30 shown by dotted lines in Figures 12(A) and 12(B), the ceramic green sheets 51 on the undersides of the two laminates 40 can be aligned to bond the two laminates 40 together to obtain a single ceramic laminate. Figure 12(A) is a cross-sectional view corresponding to the AA cross section in Figure 1, and Figure 12(B) is a cross-sectional view corresponding to the BB cross section in Figure 1.

[0056] Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the cover material obtained in the raw material powder preparation process and wet-mixed. Using the resulting slurry, strip-shaped cover sheets 54, for example, 10 μm thick or less, are applied to a substrate by, for example, a die coater method or a doctor blade method, and then dried. As illustrated in Figures 12(A) and 12(B), a predetermined number of cover sheets 54 (e.g., 2 to 10 layers) are stacked on the top and bottom of a ceramic laminate, thermocompression-bonded, and then cut to predetermined chip dimensions (e.g., 1.6 mm x 0.8 mm). Alternatively, a predetermined number of cover sheets 54 may be stacked and compressed before being attached to the top and bottom of the ceramic laminate.

[0057] (3) Firing process (S3) The ceramic laminate thus obtained is fired for about 2 hours at a firing temperature of about 1100°C to 1400°C in a reducing atmosphere containing about 1.0% by volume of H2. In this way, a laminated chip 10 is obtained in which dielectric layers 11 and internal electrode layers 12 made of sintered bodies are alternately stacked inside, and cover layers 13 are formed on the outermost layers. Note that the firing temperature is preferably set to 1100°C to 1200°C to prevent deterioration of temperature characteristics due to over-sintering.

[0058] (4) Reoxidation treatment step (S4) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0059] (5) External electrode formation process (S5) Next, a conductive paste for forming external electrodes is applied to the two end faces of the fired laminated chip 10 where the internal electrode layer patterns are exposed. The conductive paste for forming external electrodes contains powder of the main component metal of the external electrodes 20a, 20b (Cu in this embodiment), a glass component, a binder, a solvent, and, if necessary, other auxiliary agents. The binder and solvent may be the same as those used for the ceramic paste described above.

[0060] Next, the laminated chip 10 to which the conductive paste for forming external electrodes has been applied is baked in a nitrogen atmosphere at a temperature of about 770° C. or less, thereby baking the external electrodes 20a, 20b.

[0061] Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, or Sn by plating.

[0062] The above steps are merely an example, and the method for manufacturing the multilayer ceramic capacitor of this embodiment is not limited to the above embodiment. For example, in the above-mentioned lamination process (S2), if no pattern is placed in the portion that will become the side margin portion in the multilayer ceramic capacitor, after laminating the dielectric layers 11 and the internal electrode layers 12, a laminate having only the capacitive portion 14a, the capacitive portion 14b, and the margin portion 17 may be cut out so that the cross sections of the dielectric layers 11 and the internal electrode layers 12 are exposed, and a sheet formed from a side margin paste may be attached to the side of the laminate where the cross section of the dielectric layers 11 and the cross section of the internal electrode layers 12 are exposed, or the side margin paste may be applied to form the side margin portion. Furthermore, part of the processing in step S5 above may be performed before step S3. For example, before step S3, a conductive paste for forming unsintered external electrodes may be applied to two end faces of the unsintered ceramic laminate, and in step S3, the unsintered ceramic laminate is fired and the conductive paste for forming unsintered external electrodes is baked at the same time to form base layers for the external electrodes 20a, 20b. Alternatively, the conductive paste for forming unsintered external electrodes may be applied to two end faces of the ceramic laminate that has been subjected to the binder removal process, and these may be fired simultaneously.

[0063] FIG. 14(a) shows the results of a surface shape analysis in the first direction of the first internal electrode layer 12a on which the protrusions 30 are formed, using a three-dimensional optical surface shape / roughness measuring device (Zygo Newview 9000). In FIG. 14(a), the darker colored parts are the protrusions 30. From FIG. 14(a), it can be confirmed that the protrusions 30 are formed, and that the protrusions 30 extend continuously in the second direction. It can also be confirmed that there are multiple protrusions 30. The graph in FIG. 14(b) shows the change in the length in the stacking direction when the surface shape of the first internal electrode layer 12a shown in FIG. 14(a) was analyzed multiple times along a line L1 in the first direction indicated by the arrow. In FIG. 14(b), the formation of the convex portions 30 can be confirmed by the presence of distinct peaks in each line analysis graph. The length of each convex portion 30 in the stacking direction was calculated by subtracting the average height of the surface of the first internal electrode layer 12a where no convex portion 30 was formed from each peak value (average height = the average value of the lengths in the stacking direction of the portions where no convex portion was formed among the portions where the length in the stacking direction was measured on the line L1). The results are shown in FIG. 14(c). The length in the stacking direction of each convex portion 30 formed by the convex portion pattern 31 can be calculated by averaging the lengths in the stacking direction of each convex portion 30 shown in each graph.

[0064] Similarly to the above, the first internal electrode layer 12a on which the convex portions 30 are formed was subjected to a surface shape analysis in the second direction using a three-dimensional optical surface shape / roughness measuring device (Zygo Newview 9000), and the results are shown in Figure 15(a). As in Figure 15(a), the darker colored parts in Figure 15(a) are the convex portions 30. From Figure 15(a), it can be confirmed that the convex portions 30 have been formed, and that the convex portions 30 extend continuously in the first direction. The graph in FIG. 15(b) shows the change in the length in the stacking direction when the surface shape of the first internal electrode layer 12a shown in FIG. 15(a) was analyzed multiple times along the line L2 in the second direction. In FIG. 15(b), the presence of a distinct peak in each line analysis graph confirms the formation of the convex portion 30. The length of each convex portion 30 in the stacking direction was calculated by subtracting the average height of the surface of the first internal electrode layer 12a where no convex portion 30 was formed from each peak value (average height = the average value of the lengths in the stacking direction of the portions where no convex portion was formed among the portions where the length in the stacking direction was measured on the line L2). The results are shown in FIG. 15(c). The length in the stacking direction of each convex portion 30 formed by the convex portion pattern 31 can be calculated by averaging the lengths in the stacking direction of each convex portion 30 shown in each graph.

[0065] The results of FIGS. 14 and 15 show that convex portions can be formed on the internal electrode layers.

[0066] Aspects of the present disclosure are, for example, as follows. <1> The laminate has a laminate structure in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are alternately stacked, the laminate has a first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other, the internal electrode layers include a first internal electrode layer and a second internal electrode layer, the first internal electrode layer has a length in a first direction, in which the first side surface and the second side surface face each other, that is longer than a length in the first direction of the second internal electrode layer; At least one of the first internal electrode layers has at least one protrusion on one surface facing the second internal electrode layer, The multilayer ceramic capacitor, wherein the convex portion is present in a region of the first internal electrode layer where the first internal electrode layer and the second internal electrode layer do not overlap in the lamination direction. <2> the protrusions extend continuously in a second direction that is a direction perpendicular to the stacking direction and the first direction. <1> The multilayer ceramic capacitor according to claim 1. <3> The above-mentioned further includes a protrusion extending continuously in the first direction. <1> or <2> The multilayer ceramic capacitor according to claim 1. <4> The internal electrode layer at the end of the internal electrode layers in the laminated structure in the lamination direction is the second internal electrode layer. <1> , <2> and <3> 10. The multilayer ceramic capacitor according to claim 9, wherein <5> The length of the protrusion in the stacking direction is 1.02 times or more and 3.0 times or less the average thickness of the first internal electrode layers. <1> , <2> , <3> and <4> 10. The multilayer ceramic capacitor according to claim 9, wherein <6> the length of the protrusion in the first direction is 6% to 30% of the length of the first internal electrode layer in the first direction; <1> , <2> , <3> , <4> and <5> 10. The multilayer ceramic capacitor according to claim 9, wherein <7> the shortest length of the length of the protrusion in the first direction and the length of the protrusion in the second direction is 6% to 30% of the length of the first internal electrode layer in the first direction; <1> , <2> , <3> , <4> , <5> and <6> 10. The multilayer ceramic capacitor according to claim 9, wherein <8> In the laminate, the first internal electrode layers are periodically arranged in the lamination direction. <1> , <2> , <3> , <4> , <5> , <6> and <7> 10. The multilayer ceramic capacitor according to claim 9, wherein <9> forming a first internal electrode layer on a first ceramic green sheet; forming at least one protrusion on the first internal electrode layer; forming second internal electrode layers having areas smaller than those of the first internal electrode layers on second ceramic green sheets; laminating the second ceramic green sheet on which the second internal electrode layer is formed, on the first ceramic green sheet on which the first internal electrode layer and the protrusions are formed; A method for manufacturing a multilayer ceramic capacitor, comprising:

[0067] the above <1> from <8> Any of the above multilayer ceramic capacitors <9> According to this method for manufacturing a multilayer ceramic capacitor, the conventional problems can be solved and the object of the present invention can be achieved. [Explanation of symbols]

[0068] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 12a First internal electrode layer 12b Second internal electrode layer 13 Cover Layer 14 Capacity part 15a First end margin 15b Second end margin 16a First side margin 16b Second side margin 17 Margin 18a first end face 18b Second end face 19a First Aspect 19b Second Aspect 20a,20b external electrode 21 Metal elements 30 Convex part 31 Convex pattern 40 laminate L1 line L2 line M1 area M2 area M3 area 100 Multilayer ceramic capacitors

Claims

1. The laminate has a laminate structure in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are alternately stacked, the laminate has a first side surface and a second side surface opposed to each other, and a first end surface and a second end surface opposed to each other; the internal electrode layers include a first internal electrode layer and a second internal electrode layer, the first internal electrode layer has a length in a first direction in which the first side surface and the second side surface face each other, which is longer than a length in the first direction of the second internal electrode layer; At least one of the first internal electrode layers has at least one protrusion on one surface facing the second internal electrode layer, The multilayer ceramic capacitor, wherein the convex portion is present in a region of the first internal electrode layer where the first internal electrode layer and the second internal electrode layer do not overlap in the lamination direction.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the protrusions extend continuously in a second direction that is a direction perpendicular to the stacking direction and the first direction.

3. The multilayer ceramic capacitor according to claim 2 , further comprising a protrusion extending continuously in the first direction.

4. 2. The multilayer ceramic capacitor according to claim 1, wherein the internal electrode layer at the end of the internal electrode layers in the laminated structure in the lamination direction is the second internal electrode layer.

5. 2. The multilayer ceramic capacitor according to claim 1, wherein the length of said protrusions in said lamination direction is 1.02 to 3.0 times the average thickness of said first internal electrode layers.

6. 2. The multilayer ceramic capacitor according to claim 1, wherein the length of said protrusion in said first direction is 6% to 30% of the length of said first internal electrode layer in said first direction.

7. 3. The multilayer ceramic capacitor according to claim 2, wherein the shortest length of the length of the protrusion in the first direction and the length in the second direction is 6% to 30% of the length of the first internal electrode layer in the first direction.

8. 8. The multilayer ceramic capacitor according to claim 1, wherein the first internal electrode layers are periodically arranged in the stacking direction in the laminate.

9. forming a first internal electrode layer on a first ceramic green sheet; forming at least one protrusion on the first internal electrode layer; forming second internal electrode layers having areas smaller than those of the first internal electrode layers on second ceramic green sheets; laminating the second ceramic green sheet on which the second internal electrode layer is formed, on the first ceramic green sheet on which the first internal electrode layer and the protrusions are formed; A method for manufacturing a multilayer ceramic capacitor, comprising:

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