Semiconductor device

Abstract

To provide a semiconductor device capable of recovering changes in transistor characteristics due to BTI.SOLUTION: A semiconductor device 11 includes: a control input 13 receiving a control signal SCNT; one or more signal inputs 15; a BTI avoidance circuit 19 including a plurality of inputs and one or more outputs and configured to receive signals from the signal inputs 15 and the control inputs 13; and a combination logic circuit 17 including an input connected to the signal inputs 15 via the BTI avoidance circuit 19 and at least one output. The BTI avoidance circuit 19 includes at least one exclusive OR gate 21. The exclusive OR gate 21 receives signals from the control input 13, and the excluding OR gate 21 receives signals from the signal inputs 15 and provides output signals to one of the outputs of the BTI avoidance circuit 19 in response to the received signals.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses that a semiconductor integrated circuit device and a semiconductor system are provided that have a function to deal with NBTI (Negative Bias Temperature Instability) with a simple configuration and that achieve high reliability. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-54499 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device integrates a large number of transistors. Specifically, the semiconductor device includes an integrated circuit including an insulated gate field effect transistor such as a metal-oxide semiconductor (MOS) field effect transistor, and such an integrated circuit is widely used. A change in transistor characteristics due to BTI (Bias Temperature Instability) appears as an increase in the transistor threshold voltage VT and a decrease in the drain current ID. Such a deterioration in transistor characteristics can, for example, reduce the operating speed of the transistor.

[0005] Furthermore, applying a specific bias to a transistor whose characteristics have changed can restore the characteristics of the transistor that have changed due to BTI.

[0006] Semiconductor devices provided to the market are used in their operating environments, and therefore, even if an operating mode that reduces the change in transistor characteristics due to BTI in a semiconductor device, specifically, a new mode that applies a bias to recover the changed characteristics, is implemented, it may not be used frequently or regularly.

[0007] What is needed is a method for recovering the changes in transistor characteristics caused by BTI, and it is desirable that this method be applicable to semiconductor devices provided on the market.

[0008] An object of the present disclosure is to provide a semiconductor device capable of recovering from changes in transistor characteristics due to BTI. [Means for solving the problem]

[0009] A semiconductor device according to a first aspect of the present disclosure comprises a control input for receiving a control signal, one or more signal inputs, and a BTI avoidance circuit having a plurality of inputs and one or more outputs configured to receive signals from the signal input and the control input, the BTI avoidance circuit including at least one exclusive-OR gate, the exclusive-OR gate receiving a signal from the control input, the exclusive-OR gate receiving a signal from the signal input and providing an output signal at one of the outputs of the BTI avoidance circuit in response to the received signal. [Effects of the Invention]

[0010] According to the above aspect, it is possible to provide a semiconductor device capable of recovering from changes in transistor characteristics due to BTI. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram schematically showing a semiconductor device according to this embodiment. [Figure 2] FIG. 2 is a diagram illustrating a semiconductor device including an exemplary BTI avoidance circuit according to this embodiment. [Figure 3]FIG. 3 is a diagram illustrating an exemplary BTI avoidance circuit according to an embodiment. [Figure 4] FIG. 4 is a diagram illustrating a semiconductor device that does not include a BTI avoidance circuit. [Figure 5] FIG. 5 is a diagram showing an exemplary combinational logic circuit in a semiconductor device according to this embodiment. [Figure 6] FIG. 6 is a diagram showing an exemplary combinational logic circuit in a semiconductor device according to this embodiment. [Figure 7] FIG. 7 is a diagram showing an exemplary combinational logic circuit in a semiconductor device according to this embodiment. [Figure 8] FIG. 8 is a diagram schematically showing the change in BTI characteristics between the semiconductor device shown in FIGS. 1 to 3 and the semiconductor device shown in FIG. [Figure 9] FIG. 9 is a diagram showing a schematic diagram of the change in the BTI characteristics in a CMOS NOT logic circuit. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same parts are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0013] FIG. 1 is a diagram schematically showing a semiconductor device according to this embodiment.

[0014] The semiconductor device 11 includes a control input 13 that receives a control signal SCNT, one or more signal inputs 15, a combinational logic circuit 17, and a BTI avoidance circuit 19. An exemplary control signal SCNT can be a signal that activates the BTI avoidance circuit 19, such as a sleep mode signal that indicates a sleep mode. The sleep mode signal stops most of the circuits in the semiconductor device 11. Specifically, clock signals are stopped. Therefore, the exemplary combinational logic circuit 17 shown in FIG. 1 does not operate in the sleep mode.

[0015] Combinatorial logic circuit 17 has input 17b connected to signal input 15 via BTI avoidance circuit 19, and at least one output 17c. Combinatorial logic circuit 17 does not include sequential circuits such as flip-flop circuits and latch circuits. Therefore, combinational logic circuit 17 can determine the logic values ​​of all nodes within combinational logic circuit 17 by the logic values ​​received at the inputs of combinational logic circuit 17 at a given time.

[0016] The BTI avoidance circuit 19 has a plurality of inputs 19b and one or more outputs 19c configured to receive signals from the control input 13 and the signal input 15,

[0017] BTI avoidance circuit 19 includes at least one exclusive-OR gate 21. Exclusive-OR gate 21 receives a control signal SCNT from control input 13 and an input signal from one of signal inputs 15. Exclusive-OR gate 21 generates an output signal in response to a signal received from one of signal inputs 15 and control input 13, and this output signal is provided to one of the outputs of BTI avoidance circuit 19.

[0018] The exemplary control signal SCNT changes from one of the logic value [H] and the logic value [L] to the other, thereby conveying the activation of the control signal SCNT to the BTI avoidance circuit 19 .

[0019] The truth table of the exclusive OR gate 21 having two inputs (In1 and In2) and an output (Out) is shown below.

[0020] In1, In2, Out 0, 0, 0. 0, 1, 1. 1, 0, 1. 1, 1, 0.

[0021] Specifically, the input (In1) is connected to the control input 13, and the input (In2) is connected to the signal input 15. When the input (In1) is a logical value [L], the exclusive OR gate 21 provides the logical value of the input (In2) as is to the output. Furthermore, when the input (In1) changes from a logical value [L] to a logical value [H], the exclusive OR gate 21 provides the inverted value of the logical value of the input (In2) to the output.

[0022] Whether the value of the signal input is a logical value [H] or a logical value [L], the exclusive OR gate 21 generates a value that is the inverse of the logical value of the signal input at the output of the exclusive OR gate 21 in response to a change in the input that activates the control signal SCNT.

[0023] Specifically, exclusive-OR gate 21 receives a control signal SCNT from control input 13 and an input signal from signal input 15. At this time, exclusive-OR gate 21 provides an output signal of a logic value different from the logic value received at signal input 15 to one output of BTI avoidance circuit 19 in response to a change in control signal SCNT. This causes the logic value of the signal at the input of combinational logic circuit 17 that receives the signal from the output of exclusive-OR gate 21 to be inverted when control signal SCNT is activated.

[0024] Although it is unknown how long the inputs of combinational logic circuit 17 were maintained at the same logic value prior to control input 13 changing, when control input 13 changes, that input is forced to receive an inverted signal by BTI avoidance circuit 19. This causes most of the outputs of the series of logic gates connected to that input to be inverted. This inversion is maintained for a period until the next change of control input 13, making it possible to prevent the logic gates in combinational logic circuit 17 from receiving the same logic value every time control input 13 changes.

[0025] Accordingly, the BTI characteristic change in the combinational logic circuit 17 is reduced.

[0026] An exemplary BTI avoidance circuit 19 may include one or more exclusive-OR gates 21 connected to all of the inputs 17 b of the combinational logic circuit 17 .

[0027] The semiconductor device 11 may further include one or more first sequential circuits 23 connected to the output 17c of the combinational logic circuit 17, and one or more signal outputs 25 connected to the output 23b of the first sequential circuit 23.

[0028] The semiconductor device 11, specifically an integrated circuit including a microcomputer, performs synchronous operations according to a clock, and therefore has a sequential circuit somewhere in the signal propagation path.

[0029] The first sequential circuit 23 defines the range or size of the combinational logic circuit 17 and indicates the boundary along which the output signal of the BTI avoidance circuit 19 propagates. The exemplary first sequential circuit 23 may include a D-type flip-flop circuit or a latch circuit. In the circuit symbol (D-type flip-flop circuit) of the exemplary first sequential circuit 23, "D" indicates a data input, "Q" indicates a data output, and "CK" indicates a clock input. The clock input receives a clock signal CLK.

[0030] The semiconductor device 11 may further include one or more second sequential circuits 27 connected to the input 17 b of the combinational logic circuit 17 .

[0031] The second sequential circuit 27 defines the starting point of the range or size of the combinational logic circuit 17 and indicates the boundary for providing the output signal of the BTI avoidance circuit 19 to the combinational logic circuit 17 .

[0032] When the exemplary control signal SCNT is activated, the clocks that control the first sequential circuit 23 and the second sequential circuit 27 are stopped.

[0033] The second sequential circuit 27 is located on the input side of the combinational logic circuit 17 and can fix the logic value from the signal input 15 that is input to the BTI avoidance circuit 19 .

[0034] An exemplary second sequential circuit 27 may include a D-type flip-flop circuit or a latch circuit.

[0035] FIG. 2 is a diagram illustrating a semiconductor device including an exemplary BTI avoidance circuit according to this embodiment.

[0036] The exclusive-OR gate 21 of the BTI avoidance circuit 19 can be connected between one of the inputs 19b of the BTI avoidance circuit 19 and one of the outputs 19c of the BTI avoidance circuit 19. An exemplary BTI avoidance circuit 19 can be provided with an exclusive-OR gate 21 connected to all of the inputs 17b of the combinational logic circuit 17.

[0037] FIG. 3 is a diagram illustrating an exemplary BTI avoidance circuit according to an embodiment.

[0038] The BTI avoidance circuit 19 includes at least one signal generating circuit 29, which is connected to the control input 13. Each of the signal generating circuits 29 is connected to one of the signal inputs 15. The signal generating circuits 29 can be connected to at least one of the inputs 17b of the combinational logic circuit 17. The signal generating circuit 29 is provided with an exclusive-OR gate 21.

[0039] (1st form) The exemplary signal generation circuit 29 may include a selector circuit 31. In addition to the selector circuit 31, the exemplary signal generation circuit 29 may include one or more gate circuits 33. The gate circuit 33 may include a first gate circuit 33b, and the exemplary first gate circuit 33b may include an exclusive-OR gate 21.

[0040] The selector circuit 31 can have multiple inputs, for example, a first input 31d and a second input 31c. The selector circuit 31 can receive a signal from the output of the exclusive OR gate 21 at the first input 31d. The selector circuit 31 can receive a signal directly from the signal input 15 at the second input 31c.

[0041] The selector circuit 31 receives at its input 31b a selection signal SSEL that is associated with the control signal SCNT from the control input 13. In response to the selection signal SSEL, the selector circuit 31 switches between its inputs, specifically, the first input 31d and the second input 31c, and provides the signal from the switched input to its output 31h.

[0042] The inputs of the exclusive OR gate 21 can be connected to the line of the control signal SCNT from the control input 13 and to the line of the direct signal from the signal input 15 .

[0043] The truth table of the exclusive OR gate 21 having two inputs (In1 and In2) and an output (Out) is shown below. In13, In15, Out 0, 0, 0. 0, 1, 1. 1, 0, 1. 1, 1, 0.

[0044] (2nd form) In the exemplary signal generating circuit 29, the plurality of gate circuits 33 may include a second gate circuit 33c in addition to the selector circuit 31 and the exclusive-OR gate 21. The second gate circuit 33c of the gate circuits 33 may be a logic gate circuit that is different from the exclusive-OR gate and does not include an exclusive-OR gate. The selector circuit 31 may be provided with a plurality of inputs, for example, a first input 31d and a third input 31f. The selector circuit 31 may receive a signal from the output of the exclusive-OR gate 21 at its first input 31c. The selector circuit 31 may receive a signal from the output of the second gate circuit 33c at its third input 31d. The exemplary second gate circuit 33c may be either an OR gate or an AND gate, for example, an AND gate.

[0045] The inputs of the AND gate (second gate circuit 33c) can be connected to the line of the control signal SCNT from the control input 13 and the line of the inverted signal from the signal input 15. The truth tables of the AND gate and the inverting gate as the second gate circuit 33c are shown below.

[0046] In13, In13_, In15, Out 0, 1, 0, 0. 0, 1, 1, 1. 1, 0, 1, 0. 1, 0, 0, 0. (In13_ indicates the inversion of In13)

[0047] The selector circuit 31 receives a select signal SSEL that is associated with the control signal SCNT from the control input 13. In response to the select signal SSEL, the selector circuit 31 switches between a first input 31d and a third input 31f of the selector circuit 31 to provide the switched signal to an output 31h of the selector circuit 31.

[0048] (3rd form) The exemplary signal generating circuit 29 may include a third gate circuit 33d in addition to the selector circuit 31 and the exclusive-OR gate 21. The third gate circuit 33d among the gate circuits 33 may be a logic gate circuit that is different from an exclusive-OR gate and does not include an exclusive-OR gate. The selector circuit 31 may be provided with multiple inputs, for example, a first input 31c and a fourth input 31g. The selector circuit 31 may receive a signal from the output of the exclusive-OR gate 21 at its first input 31d.

[0049] The selector circuit 31 can receive a signal from the output of the third gate circuit 33d at a fourth input 31g. The exemplary third gate circuit 33d can be either an OR gate or an AND gate, for example, an OR gate.

[0050] The truth table of the OR gate serving as the third gate circuit 33d is shown below. In13, In15, Out 0, 0, 0. 0, 1, 1. 1, 0, 1. 1, 1, 1.

[0051] The selector circuit 31 receives a select signal SSEL that is associated with the control signal SCNT from the control input 13. In response to the select signal SSEL, the selector circuit 31 switches a first input 31d and a fourth input 31g of the selector circuit 31 to provide the switched signal to an output 31h of the selector circuit 31.

[0052] (4th form) In the exemplary signal generating circuit 29, the selector circuit 31 may be provided with, for example, a first input 31d, a second input 31c, and a third input 31d. The selector circuit 31 may receive a signal from the output of the exclusive OR gate 21 at its first input 31d. The selector circuit 31 may receive a signal directly from the signal input 15 at its second input 31c. The selector circuit 31 may receive a signal from the output of the second gate circuit 33c at its third input 31d.

[0053] (5th form) In the exemplary signal generating circuit 29, the selector circuit 31 may have, for example, a first input 31d, a third input 31f, and a fourth input 31g. The selector circuit 31 may receive a signal from the output of the exclusive OR gate 21 at its first input 31d. The selector circuit 31 may receive a signal from the output of the second gate circuit 33c at its third input 31f. The exemplary second gate circuit 33c may be either an OR gate or an AND gate, for example, an AND gate. The selector circuit 31 may receive a signal from the output of the third gate circuit 33d at its fourth input 31g. The exemplary third gate circuit 33d may be either the other of an OR gate or an AND gate, for example, an OR gate.

[0054] (6th form) In the exemplary signal generating circuit 29, the selector circuit 31 may have, for example, a first input 31d, a second input 31c, and a fourth input 31f. The selector circuit 31 may receive a signal from the output of the exclusive OR gate 21 at the first input 31d. The selector circuit 31 may receive a signal directly from the signal input 15 at the second input 31c. The selector circuit 31 may receive a signal from the output of the third gate circuit 33d at the fourth input 31g. The exemplary third gate circuit 33d may be either an OR gate or an AND gate, for example, an OR gate.

[0055] (7th form) In the exemplary signal generating circuit 29, the selector circuit 31 may have, for example, a first input 31d, a second input 31c, a third input 31d, and a fourth input 31f. The selector circuit 31 may receive a signal from the output of the exclusive OR gate 21 at its first input 31d. The selector circuit 31 may receive a signal directly from the signal input 15 at its second input 31c. The selector circuit 31 may receive a signal from the output of the second gate circuit 33c at its third input 31f. The exemplary second gate circuit 33c may be either an OR gate or an AND gate, for example, an AND gate. The selector circuit 31 may receive a signal from the output of the third gate circuit 33d at its fourth input 31g. The exemplary third gate circuit 33d may be either an OR gate or an AND gate, for example, an OR gate.

[0056] Referring to FIG. 3, an exemplary selector circuit 31 may have, for example, a first input 31d, a second input 31c, a third input 31f, and a fourth input 31g.

[0057] The BTI avoidance circuit 19 may further include a selector control circuit 35. The selector control circuit 35 is connected to the selector circuit 31. The selector control circuit 35 is connected to an input 31b (selection input) of the selector circuit 31 and provides a selection signal SSEL to the selector circuit 31. The selector circuit 31 receives the selection signal SSEL at the input 31b (selection input) and provides one of the signals from inputs 31c, 31d, 31f, and 31g of the selector circuit 31 to an output 31h depending on the value of the selection signal SSEL.

[0058] The exemplary selector control circuit 35 may include an edge detection circuit 35b and a counter circuit 35c. The edge detection circuit 35b detects a transition of the control signal SCNT from one of its active value and inactive value to the other. The counter circuit 35c counts the transitions in the edge detection circuit 35b. The exemplary counter circuit 35c includes a 2-bit counter and can generate a signal that cycles through four states (

[00] →

[01] →

[10] →

[11] →

[00] ...).

[0059] The states of the selector control circuit 35 (for example, four states

[00] ,

[01] ,

[10] , and

[11] ) are assigned to the inputs 31c, 31d, 31f, and 31g of the selector circuit 31, respectively.

[0060] (8th form) All inputs 17 b of the combinational logic circuit 17 are connected to respective signal generating circuits 29 .

[0061] 4 is a diagram schematically illustrating a semiconductor device that does not include a BTI avoidance circuit. In FIG. 4, parts that are the same as those in FIG. 3 are assigned the same reference numerals. The output 17c of the combinational logic circuit 17 is connected to a first sequential circuit 23. The signal input 15 is connected to a second sequential circuit 27. The output of the second sequential circuit 27 is connected to the input of the combinational logic circuit 17.

[0062] FIG. 8 is a diagram schematically showing the change in BTI characteristics between the semiconductor device shown in FIGS. 1 to 3 and the semiconductor device shown in FIG.

[0063] 8, the dashed-dotted reference REF indicates an exemplary limit of the accumulated value (accumulation of characteristic changes). The arrow (SPN1) indicates the accumulated operating time in a semiconductor device that does not include a BTI avoidance circuit. The arrow (SPN2) indicates the accumulated operating time in a semiconductor device that includes a BTI avoidance circuit 19.

[0064] In FIG. 8, the vertical axis represents the cumulative change in BTI characteristics. The horizontal axis represents the cumulative value during the period when power is applied to the semiconductor device. The characteristic CMP represents the change in BTI characteristics in the semiconductor device shown in FIG. 4. The characteristic EMB represents the change in BTI characteristics in the semiconductor device shown in FIGS. 1 to 3.

[0065] In a semiconductor device that does not include a BTI avoidance circuit, the change in BTI characteristics increases monotonically during the period SPN1 in which normal operation continues.

[0066] In a semiconductor device including the BTI avoidance circuit 19, the BTI characteristic changes occurring during the normal operation period different from the sleep mode period TSLP can be recovered during the sleep mode period TSLP. Therefore, the BTI avoidance circuit 19 can prevent the BTI characteristic changes from increasing monotonically.

[0067] FIG. 5 is a diagram showing an exemplary combinational logic circuit in a semiconductor device according to this embodiment.

[0068] 5, a full adder 41 is shown as an example of the combinational logic circuit 17. The full adder 41 includes a first half adder 43b, a second half adder 43c, and an OR gate 49. Each of the first half adder 43b and the second half adder 43c includes an AND gate 45 and an exclusive OR gate 47.

[0069] The first half adder 43b receives two inputs (X, Y) to be added. Specifically, the AND gate 45 receives the two inputs (X, Y) and generates a signal indicating whether or not a carry is present. The exclusive OR gate 47 receives the two inputs (X, Y) and generates the sum of the two inputs (X, Y).

[0070] The second half adder 43c receives the addition result from the first half adder 43b and the carry result from the downstream full adder. Specifically, the logical AND gate 45 receives the addition result from the first half adder 43b and the carry result (CI) from the downstream full adder, and generates a signal indicating whether or not a carry has occurred in the second half adder 43c. The exclusive OR gate 47 receives the addition result from the first half adder 43b and the carry result (CI) from the downstream full adder, and generates a signal (S) indicating the addition result in the second half adder 43c.

[0071] OR gate 49 receives signals from AND gate 45 of first half adder 43b and AND gate 45 of second half adder 43c, and generates a signal (CO) indicating whether or not a carry occurs in full adder 41.

[0072] The carry input from the downstream full adder in the 2-bit full adder is zero. The 2-bit full adder is a combinational logic circuit with two inputs.

[0073] The truth table is shown below. X, Y, CI, CO, S 0, 0, 0, 0, 0. 0, 0, 1, 0, 1. 0, 1, 0, 0, 1. 0, 1, 1, 1, 0. 1, 0, 0, 0, 1. 1, 0, 1, 1, 0. 1, 1, 0, 1, 0. 1, 1, 1, 1, 1.

[0074] 6 is a diagram showing an exemplary combinational logic circuit in a semiconductor device according to this embodiment. Referring to FIG. 6, a carry propagate adder 51 is shown as an example of the combinational logic circuit 17.

[0075] The carry propagate adder 51 includes a full adder 41b (FA0), a full adder 41c (FA1), ..., a full adder 41f (FA n-1 The carry propagate adder 51 receives an n-bit X input 53 and an n-bit Y input 55 .

[0076] Specifically, these full adders (41b, 41c, ..., 41f) are configured to receive 1-bit X input 53 and 1-bit Y input 55 in order from the least significant bit of the X input 53 and Y input 55, and perform n-bit addition as a whole. The operation of the full adders (41b, 41c, ..., 41f) has already been described.

[0077] The carry propagate adder 51 receives a carry signal (CI0). The carry signals of the full adders (41b, 41c, . . . , 41f) are propagated serially from the lower to the higher full adders (41b, 41c, . . . , 41f). The carry signal of the carry propagate adder 51 is propagated in series from the lower full adder (41b) to the higher full adder (41f) in the carry propagate adder 51. n-1 )

[0078] The addition results of each of the full adders (41b, 41c, . . . , 41f) are provided to an n-bit addition output 57.

[0079] FIG. 7 is a diagram showing an exemplary combinational logic circuit in a semiconductor device according to this embodiment.

[0080] 7, exemplary two-stage full adders (41d, 41u) are shown as an example of the combinational logic circuit 17. In these full adders (41d, 41u), for example, the propagation of carry signals from the lower and upper full adders directly connected to the carry propagate adder 51 is shown. The dashed line CRTP indicates the propagation path of the carry signal in the two-stage full adders (41d, 41u).

[0081] When a carry occurs in the operation of the downstream full adder 41d, this carry causes a gate delay of three stages within the downstream full adder 41d. This carry is input to the upstream full adder 41u. The upstream full adder 41u causes a gate delay of two stages in generating the carry signal.

[0082] In the carry propagate adder 51, the carry signal of the least significant bit addition propagates from the least significant bit full adder to the most significant bit full adder, and the addition result of the carry propagate adder 51 may be determined. Each of the full adders (41d, 41u) has the circuit connections already described.

[0083] In FIG. 8, the arrow (SPN2) is longer than the arrow (SPN1), and therefore, a semiconductor device including the BTI avoidance circuit 19 can operate for a long period of time in the market.

[0084] 9 is a diagram showing a schematic diagram of the change in BTI characteristics in a CMOS NOT logic circuit, with reference to parts (a) and (b) of FIG. 9, a CMOS type inverter gate is shown.

[0085] Referring to part (a) of Figure 9, a CMOS inverter gate receives a logic value [L] at its input and outputs a logic value [H] in response to this. In this CMOS inverter gate, the p-type MOS transistor (PMOS) is turned on and receives a bias that causes BTI. The continuation of this bias condition can change the characteristics of the p-type MOS transistor (PMOS).

[0086] Referring to part (b) of Figure 9, a CMOS inverter gate receives a logic value [H] at its input and outputs a logic value [L] in response to this. In this CMOS inverter gate, the n-type MOS transistor (NMOS) is turned on and receives a bias that causes BTI. The persistence of this bias condition can change the characteristics of the n-type MOS transistor.

[0087] However, when CMOS logic gates operate periodically, intermittently, or at pseudo-random times, the sustained bias conditions are disrupted.

[0088] According to this embodiment, it is possible to provide a semiconductor device 11 that can recover from changes in transistor characteristics caused by BTI.

[0089] As described above, this embodiment has various aspects as follows.

[0090] A first aspect of the semiconductor device according to this embodiment comprises a control input for receiving a control signal, one or more signal inputs, and a BTI avoidance circuit having a plurality of inputs and one or more outputs configured to receive signals from the signal input and the control input, the BTI avoidance circuit including at least one exclusive-OR gate, the exclusive-OR gate receiving a signal from the control input, the exclusive-OR gate receiving a signal from the signal input and providing an output signal at one of the outputs of the BTI avoidance circuit in response to the received signal.

[0091] The semiconductor device of the second aspect according to the first aspect of this embodiment may further include a combinational logic circuit having an input connected to the signal input via the BTI avoidance circuit, and at least one output.

[0092] The semiconductor device of a third aspect according to the second aspect of this embodiment may further include a first sequential circuit connected to the output of the combinational logic circuit, and one or more signal outputs connected to the output of the first sequential circuit.

[0093] In the semiconductor device of the fourth aspect according to the third aspect of this embodiment, the first sequential circuit can include a D-type flip-flop.

[0094] In the semiconductor device of the fifth aspect according to the first aspect, the second aspect, the third aspect, or the fourth aspect of this embodiment, the semiconductor device further comprises one or more second sequential circuits connected to the signal input, and the input of the BTI avoidance circuit can be connected to the output of the second sequential circuit.

[0095] In the semiconductor device of the sixth aspect according to the fifth aspect of this embodiment, the second sequential circuit can include a D-type flip-flop.

[0096] In a semiconductor device of a seventh aspect according to any one of the second to sixth aspects of this embodiment, the exclusive OR gate of the BTI avoidance circuit can be connected between one of the inputs of the BTI avoidance circuit and one of the outputs of the BTI avoidance circuit.

[0097] In a semiconductor device of an eighth aspect according to any one of the second to fifth aspects of this embodiment, the BTI avoidance circuit includes one or more signal generation circuits connected to the control input, each of the signal generation circuits being connected to any one of the signal inputs, and each of the signal generation circuits can be provided with the exclusive OR gate.

[0098] In a semiconductor device of a ninth aspect according to an eighth aspect of this embodiment, a first signal generation circuit of the signal generation circuits is connected to a first signal input of the signal inputs, at least one of the signal generation circuits includes a selector circuit and a plurality of gate circuits, a first gate circuit of the gate circuits is provided with the exclusive-OR gate, a second gate circuit of the gate circuits generates either a logical value "1" or a logical value "0" in response to receiving an active value of the control signal, the selector circuit has at least a first signal input and a second signal input, and the first signal input and the second signal input of the selector circuit can be connected to an output of the first gate circuit and an output of the second gate circuit, respectively.

[0099] In a semiconductor device of a tenth aspect according to the ninth aspect of this embodiment, a third gate circuit among the gate circuits generates either the logical value "1" or the logical value "0" in response to receiving the active value of the control signal, and the selector circuit has at least a third signal input in addition to the first signal input and the second signal input, and the third signal input of the selector circuit can be connected to the output of the third gate circuit.

[0100] In a semiconductor device of an eleventh aspect according to the tenth aspect of this embodiment, the selector circuit has at least a fourth signal input in addition to the first signal input, the second signal input, and the third signal input, and the first gate circuit, the second gate circuit, the third gate circuit, and the fourth signal input of the selector circuit can be connected to the first signal input.

[0101] In a semiconductor device of a twelfth aspect according to the ninth, tenth or eleventh aspect of this embodiment, the BTI avoidance circuit further includes a selector control circuit, which includes an edge detection circuit that detects a transition from one of the active value and the inactive value of the control signal to the other, and a counter circuit that counts the transition in the edge detection circuit, and the selector circuit can have a select input connected to an output of the counter circuit.

[0102] In a semiconductor device according to a thirteenth aspect of the present embodiment, the control signal may be a sleep mode signal.

[0103] In the semiconductor device of the fourteenth aspect according to the second, third or fourth aspect of this embodiment, the combinational logic circuit may include one or more full adders.

[0104] In the semiconductor device of the fifteenth aspect according to the fourteenth aspect of the present embodiment, the full adder can be configured to perform two n-bit additions.

[0105] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0106] 11. Semiconductor device, 13. Control input, 15 Signal Input 17. Logic circuits, 17b···input, 17c···output, 19...BTI avoidance circuit, 19b···input, 19c···output, 21... Exclusive OR gate, 23...first sequential circuit, 25···signal output, 27...second sequential circuit, 29...signal generation circuit, 31...Selector circuit, 31b···Selection input, 31c, 31d, 31f... input, 31h... output, 33, 33b, 33c, 33d... Gate circuit, 35···Selector control circuit, 35b Edge detection circuit, 35c···Counter circuit, 41, 41b, 41c, 41d, 41f, 41u... Full adder, 43b, 43c... Half adder, 45···Logical AND gate, 47···Exclusive OR gate, 49... OR gate, 51···Carry propagate adder, 53···input, 55···input, 57···bit sum output, CLK: Clock signal, CMP...Characteristics, CRTP···dashed line, EMB...Characteristics, IN1 Input REF...standard, SCNT control signal, SPN1...Normal operation, SPN1··· period, SSEL: Selection signal, TSLP Sleep mode period.

Claims

1. a control input for receiving a control signal; one or more signal inputs; a BTI avoidance circuit having a plurality of inputs and one or more outputs configured to receive signals from the signal input and the control input; Equipped with the BTI avoidance circuit includes at least one exclusive-OR gate; the exclusive-OR gate receives a signal from the control input; the exclusive-OR gate receives a signal from the signal input and provides an output signal at one of the outputs of the BTI avoidance circuit in response to the received signal; Semiconductor device.

2. a combinational logic circuit having an input connected to said signal input via said BTI avoidance circuit, and at least one output; 2. The semiconductor device according to claim 1.

3. a first sequential circuit connected to the output of the combinational logic circuit; one or more signal outputs connected to the output of the first sequential circuit; Further comprising:

3. The semiconductor device according to claim 2.

4. the first sequential circuit includes a D-type flip-flop; 4. The semiconductor device according to claim 3.

5. further comprising one or more second sequential circuits connected to the signal input; the input of the BTI avoidance circuit is connected to the output of the second sequential circuit; 2. The semiconductor device according to claim 1.

6. the second sequential circuit includes a D-type flip-flop; 6. The semiconductor device according to claim 5.

7. the exclusive-OR gate of the BTI avoidance circuit is connected between one of the inputs of the BTI avoidance circuit and one of the outputs of the BTI avoidance circuit; 2. The semiconductor device according to claim 1.

8. the BTI avoidance circuit includes one or more signal generating circuits coupled to the control input; each of the signal generating circuits is connected to one of the signal inputs; Each of the signal generating circuits is provided with the exclusive OR gate.

2. The semiconductor device according to claim 1.

9. a first one of the signal generating circuits connected to a first one of the signal inputs; At least one of the signal generating circuits includes a selector circuit and a plurality of gate circuits; a first gate circuit of the gate circuits is provided with the exclusive OR gate; a second one of the gate circuits generating one of a logic value "1" and a logic value "0" in response to receiving an active value of the control signal; the selector circuit has at least a first signal input and a second signal input, the first signal input and the second signal input of the selector circuit being connected to the output of the first gate circuit and the output of the second gate circuit, respectively; 9. The semiconductor device according to claim 8.

10. a third gate circuit among the gate circuits generates the other of the logic value "1" and the logic value "0" in response to receiving the active value of the control signal; the selector circuit has at least a third signal input in addition to the first and second signal inputs; the third signal input of the selector circuit is connected to the output of the third gate circuit; 10. The semiconductor device according to claim 9.

11. the selector circuit has at least a fourth signal input in addition to the first signal input, the second signal input, and the third signal input; the fourth signal inputs of the first gate circuit, the second gate circuit, the third gate circuit, and the selector circuit are connected to the first signal input; 11. The semiconductor device according to claim 10.

12. the BTI avoidance circuit further includes a selector control circuit; The selector control circuit an edge detection circuit for detecting a transition from one of the active value and the inactive value of the control signal to the other; a counter circuit for counting the transitions in the edge detection circuit; Including, the selector circuit has a select input connected to the output of the counter circuit; 10. The semiconductor device according to claim 9.

13. the control signal is a sleep mode signal; 2. The semiconductor device according to claim 1.

14. the combinational logic circuit includes one or more full adders; 5. The semiconductor device according to claim 2, claim 3, or claim 4.

15. the full adder is configured to perform two n-bit additions; 15. The semiconductor device according to claim 14.

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