Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of improving the reliability thereof.SOLUTION: A semiconductor device (DEV1, DEV2) includes: a semiconductor substrate (SUB); a first interlayer dielectric film (ILD3) formed over the semiconductor substrate; first wiring (WL3a, WL3b) formed on the first interlayer dielectric film; a second interlayer dielectric film (ILD4) formed on the first interlayer dielectric film and having a first layer (ILD4a) covering the first wiring and a second layer (ILD4b) formed on the first layer; a first resistive film (RF1) formed on the first layer and covered by the second layer; a first via plug (VP4aa,VP4ab) formed in the first layer and electrically connecting the first wiring and the first resistive film; and a second via plug (VP4ba,VP4bb) formed in the second interlayer dielectric film and electrically connected to the first wiring. The first resistive film contains silicon.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] The semiconductor device disclosed in Japanese Patent Laid-Open No. 2023-160003 (Patent Document 1) has a semiconductor substrate, a first interlayer insulating film, wiring, a second interlayer insulating film, a via plug, and a resistive film. The first interlayer insulating film is formed above the semiconductor substrate. The second interlayer insulating film has a first layer and a second layer. The first layer of the second interlayer insulating film is formed on the first interlayer insulating film so as to cover the wiring. A via hole is formed in the first layer of the second interlayer insulating film. The resistive film is formed on the first layer of the second interlayer insulating film. The via plug is formed in the via hole and electrically connects the wiring and the resistive film. The second layer of the second interlayer insulating film is formed on the first layer of the second interlayer insulating film so as to cover the resistive film. The resistive film contains silicon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-160003 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, washing with water may be performed after the resistive film is formed but before the second layer of the second interlayer insulating film is formed. During this process, silicon in the resistive film may dissolve, reducing the width of the resistive film and causing fluctuations in the electrical resistance value of the resistive film. Other issues and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate, a first interlayer insulating film formed above the semiconductor substrate, a first wiring formed on the first interlayer insulating film, a second interlayer insulating film formed on the first interlayer insulating film, the second interlayer insulating film having a first layer covering the first wiring and a second layer formed on the first layer, a first resistive film formed on the first layer and covered by the second layer, a first via plug formed in the first layer and electrically connecting the first wiring to the first resistive film, and a second via plug formed in the second interlayer insulating film and electrically connecting the first wiring. The first resistive film contains silicon. The first resistive film is electrically connected to the semiconductor substrate via the first wiring, the first via plug, and the second via plug.

[0006] The method for manufacturing a semiconductor device according to the present disclosure includes the steps of: forming a first interlayer insulating film on a semiconductor substrate; The method includes the steps of forming a first wiring on a first interlayer insulating film, forming a first layer of a second interlayer insulating film on the first interlayer insulating film so as to cover the first wiring, forming a first via plug in the first layer so as to be electrically connected to the first wiring, forming a first resistive film containing silicon on the first layer so as to be electrically connected to the first via plug, forming a second layer of a second interlayer insulating film on the first layer so as to cover the first resistive film, and cleaning the top surface of the first layer after the step of forming the first resistive film. In the step of cleaning the top surface of the first layer, the top surface of the first layer is cleaned while the first resistive film is not electrically connected to the semiconductor substrate. [Effects of the Invention]

[0007] According to the present disclosure, the reliability of a semiconductor device can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a cross-sectional view of the semiconductor device DEV1. [Figure 2] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV1. [Figure 3] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S2. [Figure 4]FIG. 10 is a cross-sectional view illustrating a contact plug forming step S3. [Figure 5] FIG. 10 is a cross-sectional view illustrating a wiring layer forming step S4. [Figure 6] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S5. [Figure 7] FIG. 10 is a cross-sectional view illustrating a via plug forming step S6. [Figure 8] FIG. 10 is a cross-sectional view illustrating a wiring layer forming step S7. [Figure 9] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S8. [Figure 10] FIG. 10 is a cross-sectional view illustrating a via plug forming step S9. [Figure 11] FIG. 10 is a cross-sectional view illustrating a resistive film forming step S10. [Figure 12] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S12. [Figure 13] FIG. 10 is a cross-sectional view illustrating a via plug forming step S13. [Figure 14] FIG. 10 is a cross-sectional view of a semiconductor device DEV1 according to a modified example. [Figure 15] FIG. 10 is a first cross-sectional view of the semiconductor device DEV2. [Figure 16] FIG. 2 is a second cross-sectional view of the semiconductor device DEV2. [Figure 17] 10 is a cross-sectional view illustrating a resistive film forming step S10 in the manufacturing method of the semiconductor device DEV2. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0010] (First embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0011] <Configuration of semiconductor device DEV1> The configuration of the semiconductor device DEV1 will be described below.

[0012] 1, the semiconductor device DEV1 has a semiconductor substrate SUB. The semiconductor substrate SUB has an upper surface F1 and a lower surface F2. The lower surface F2 is located on the opposite side of the upper surface F1. The semiconductor substrate SUB is made of, for example, single-crystal silicon.

[0013] Although not shown, a source region, a drain region, and a well region are formed in the semiconductor substrate SUB. The source region and the drain region are formed on the upper surface F1. The source region and the drain region are spaced apart from each other. The well region is formed on the upper surface F1 so as to surround the source region and the drain region. The portion of the well region located between the source region and the drain region is defined as a channel region. Although not shown, a gate insulating film is formed on the channel region, and a gate electrode is formed on the gate insulating film. The source region, the drain region, the well region, the gate insulating film, and the gate electrode constitute a transistor.

[0014] The semiconductor device DEV1 further includes interlayer insulating films ILD1, ILD2, ILD3, and ILD4, and wiring layers WL1, WL2, WL3, and WL4.

[0015] An interlayer insulating film ILD1 is formed on the semiconductor substrate SUB (upper surface F1) so as to cover the above-mentioned transistors. A wiring layer WL1 is formed on the interlayer insulating film ILD1. An interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1 so as to cover the wiring layer WL1. A wiring layer WL2 is formed on the interlayer insulating film ILD2. An interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2 so as to cover the wiring layer WL2. A wiring layer WL3 is formed on the interlayer insulating film ILD3. An interlayer insulating film ILD4 is formed on the interlayer insulating film ILD3 so as to cover the wiring layer WL3. A wiring layer WL4 is formed on the interlayer insulating film ILD4.

[0016] The interlayer insulating films ILD1 to ILD4 are made of, for example, silicon oxide. The wiring layers WL1 to WL4 are made of, for example, aluminum or an aluminum alloy. Each of the wiring layers WL1 to WL4 may be formed on a barrier metal BM1. Furthermore, a barrier metal BM2 may be formed on the upper surface of each of the wiring layers WL1 to WL4. The barrier metal BM1 and the barrier metal BM2 are, for example, a stacked film of a titanium nitride film and a titanium film.

[0017] 1, the semiconductor device DEV1 further includes a resistive film RF1. The wiring layer WL3 includes a wiring WL3a and a wiring WL3b. The interlayer insulating film ILD4 includes a first layer ILD4a and a second layer ILD4b. The first layer ILD4a is formed on the interlayer insulating film ILD3 so as to cover the wiring layer WL3.

[0018] The resistive film RF1 is formed on the first layer ILD4a. An insulating film IF1 is formed on the resistive film RF1. The side surfaces of the resistive film RF1 are exposed between the insulating film IF1 and the first layer ILD4a. The second layer ILD4b is formed on the first layer ILD4a so as to cover the resistive film RF1 and the insulating film IF1. The resistive film RF1 contains silicon. The resistive film RF1 is made of, for example, SiCr or SiCrC. The insulating film IF1 is made of, for example, silicon oxide or silicon oxynitride.

[0019] Via holes VH4a and VH4b are formed in the first layer ILD4a. The via holes VH4a and VH4b penetrate the first layer ILD4a. The via holes VH4a overlap the resistive film RF1 and the wiring WL3a in a plan view. The via holes VH4b overlap the resistive film RF1 and the wiring WL3b in a plan view.

[0020] The semiconductor device DEV1 further has via plugs VP4aa and VP4ab. The via plugs VP4aa and VP4ab may be collectively referred to as via plugs VP4a. The via plug VP4aa is formed in a via hole VH4a. The via plug VP4ab is formed in a via hole VH4b. The via plug VP4aa electrically connects the resistive film RF1 and the wiring WL3a. The via plug VP4ab electrically connects the resistive film RF1 and the wiring WL3b. The via plug VP4a is made of, for example, tungsten.

[0021] The wiring layer WL3 further includes wiring WL3c and wiring WL3d, and the wiring layer WL4 includes wiring WL4a and wiring WL4b. Via holes VH4c, VH4d, VH4e, and VH4f are formed in the interlayer insulating film ILD4. The via holes VH4c, VH4d, VH4e, and VH4f penetrate the interlayer insulating film ILD4. The via hole VH4c overlaps the wiring WL4a and wiring WL3a in a planar view, and the via hole VH4d overlaps the wiring WL4b and wiring WL3b in a planar view. The via hole VH4e overlaps the wiring WL4a and wiring WL3c in a planar view, and the via hole VH4f overlaps the wiring WL4b and wiring WL3d in a planar view.

[0022] The semiconductor device DEV1 further has via plugs VP4ba, VP4bb, VP4bc, and VP4bd. The via plugs VP4ba, VP4bb, VP4bc, and VP4bd may be collectively referred to as via plug VP4b. The via plug VP4ba is formed in the via hole VH4c. The via plug VP4bb is formed in the via hole VH4d. The via plug VP4bc is formed in the via hole VH4e. The via plug VP4bd is formed in the via hole VH4f. The via plug VP4ba electrically connects the wiring WL4a and the wiring WL3a. The via plug VP4bb electrically connects the wiring WL4b and the wiring WL3b. The via plug VP4bc electrically connects the wiring WL4a and the wiring WL3c. The via plug VP4bd electrically connects the wiring WL4b and the wiring WL3d. The via plug VP4b is made of, for example, tungsten.

[0023] The wiring layer WL2 has wiring WL2a and wiring WL2b, and the wiring layer WL1 has wiring WL1a and wiring WL1b. The semiconductor device DEV1 further has via plugs VP3a and VP3b, via plugs VP2a and VP2b, and contact plugs CPa and CPb. The via plugs VP3a and VP3b may be collectively referred to as via plugs VP3, and the via plugs VP2a and VP2b may be collectively referred to as via plugs VP2. The contact plugs CPa and CPb may be collectively referred to as contact plugs CP.

[0024] In the interlayer insulating film ILD3, a via hole VH3a is formed so as to overlap the wiring WL3c and wiring WL2a in a plan view, and a via hole VH3b is formed so as to overlap the wiring WL3d and wiring WL2b in a plan view. The via holes VH3a and VH3b penetrate the interlayer insulating film ILD3. In the interlayer insulating film ILD2, a via hole VH2a is formed so as to overlap the wiring WL2a and wiring WL1a in a plan view, and a via hole VH2b is formed so as to overlap the wiring WL2b and wiring WL1b in a plan view. The via holes VH2a and VH2b penetrate the interlayer insulating film ILD2.

[0025] In the interlayer insulating film ILD1, a contact hole CHa is formed so as to overlap the wiring WL1a in a plan view, and a contact hole CHb is formed so as to overlap the wiring WL1b in a plan view. The contact holes CHa and CHb penetrate the interlayer insulating film ILD1.

[0026] The via plug VP3a is formed in the via hole VH3a. The via plug VP3b is formed in the via hole VH3b. The via plug VP3a electrically connects the wiring WL3c and the wiring WL2a. The via plug VP3b electrically connects the wiring WL3d and the wiring WL2b. The via plug VP2a is formed in the via hole VH2a. The via plug VP2b is formed in the via hole VH2b. The via plug VP2a electrically connects the wiring WL2a and the wiring WL1a. The via plug VP2b electrically connects the wiring WL2b and the wiring WL1b. The contact plug CPa is formed in the contact hole CHa. The contact plug CPb is formed in the contact hole CH3b. The contact plug CPa electrically connects the wiring WL1a and the semiconductor substrate SUB (the source region or drain region of the transistor), and the contact plug CPb electrically connects the wiring WL1b and the semiconductor substrate SUB. The via plugs VP3, VP2 and contact plugs CP are made of, for example, tungsten.

[0027] In this way, the resistive film RF1 is electrically connected to the semiconductor substrate SUB via the wiring WL3a, the via plug VP4aa, and the via plug VP4ba. The resistive film RF1 is also electrically connected to the semiconductor substrate SUB via the wiring WL3b, the via plug VP4ab, and the via plug VP4bb. As shown in Fig. 1, the resistive film RF1 is electrically connected to the semiconductor substrate SUB via the wiring WL4a and also electrically connected to the semiconductor substrate SUB via the wiring WL4b. However, the resistive film RF1 may be connected to the semiconductor substrate SUB via the wiring WL4a and electrically connected to a structure different from the semiconductor substrate SUB via the wiring WL4b.

[0028] <Method of Manufacturing Semiconductor Device DEV1> A method for manufacturing the semiconductor device DEV1 will be described below.

[0029] As shown in FIG. 2, the manufacturing method of the semiconductor device DEV1 includes a preparation step S1, an interlayer insulating film forming step S2, a contact plug forming step S3, a wiring layer forming step S4, an interlayer insulating film forming step S5, and a via plug forming step S6.

[0030] In the preparation step S1, a semiconductor substrate SUB is prepared. A source region, a drain region, and a well region are formed in the semiconductor substrate SUB prepared in the preparation step S1, and a gate insulating film and a gate electrode are formed on the semiconductor substrate SUB.

[0031] 3, in the interlayer insulating film formation step S2, an interlayer insulating film ILD1 is formed on the semiconductor substrate SUB. The interlayer insulating film ILD1 is formed by depositing a constituent material of the interlayer insulating film ILD1 on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method, and then planarizing the deposited constituent material of the interlayer insulating film ILD1 by, for example, a CMP (Chemical Mechanical Polishing) method.

[0032] 4, in the contact plug formation step S3, contact holes CHa and CHb are formed in the interlayer insulating film ILD1, and then contact plugs CP are formed in the contact holes CHa and CHb. In the contact plug formation step S3, first, a resist pattern is formed on the interlayer insulating film ILD1 by photolithography. Second, the interlayer insulating film ILD1 is etched using the resist pattern as a mask, thereby forming the contact holes CHa and CHb. Third, the contact plugs CP are formed in the contact holes CHa and CHb by, for example, a CVD method. Fourth, the constituent material of the contact plugs CP formed outside the contact holes CHa and CHb is removed by, for example, a CMP method.

[0033] 5, in the wiring layer formation process S4, a wiring layer WL1 is formed on an interlayer insulating film ILD1. In the wiring layer formation process S4, first, a constituent material of the barrier metal BM1, a constituent material of the wiring layer WL1, and a constituent material of the barrier metal BM2 are sequentially deposited by, for example, sputtering. Second, a resist pattern is formed by photolithography on the deposited constituent material of the barrier metal BM2. Third, using the resist pattern as a mask, the constituent material of the barrier metal BM1, the constituent material of the wiring layer WL1, and the constituent material of the barrier metal BM2 are etched.

[0034] 6, in the interlayer insulating film formation step S5, an interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1 so as to cover the wiring layer WL1. In the interlayer insulating film formation step S5, first, a constituent material of the interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1 by, for example, a CVD method. Second, the constituent material of the interlayer insulating film ILD2 thus formed is planarized by, for example, a CMP method.

[0035] 7, in the via plug formation step S6, via holes VH2a and VH2b are formed in the interlayer insulating film ILD2, and then via plugs VP2 are formed in the via holes VH2a and VH2b. In the via plug formation step S6, first, a resist pattern is formed on the interlayer insulating film ILD2 by photolithography. Second, the interlayer insulating film ILD2 is etched using the resist pattern as a mask to form the via holes VH2a and VH2b. Third, via plugs VP2 are formed in the via holes VH2a and VH2b by, for example, CVD. Fourth, the constituent material of the via plugs VP2 formed outside the via holes VH2a and VH2b is removed by, for example, CMP.

[0036] Thereafter, steps similar to the wiring layer forming step S4, the interlayer insulating film forming step S5, and the via plug forming step S6 are repeated to form the wiring layer WL2, the interlayer insulating film ILD3, the via holes VH3a and VH3b, and the via plugs VP3.

[0037] As shown in FIG. 2, the manufacturing method of the semiconductor device DEV1 further includes a wiring layer forming step S7, an interlayer insulating film forming step S8, a via plug forming step S9, a resistive film forming step S10, a cleaning step S11, an interlayer insulating film forming step S12, a via plug forming step S13, and a wiring layer forming step S14.

[0038] As shown in Fig. 8, in the wiring layer formation process S7, a wiring layer WL3 is formed on the interlayer insulating film ILD3 using a method similar to that used in the wiring layer formation process S4. Specifically, wirings WL3c and WL3d are formed so as to be electrically connected to the semiconductor substrate SUB, and wirings WL3a and WL3b are formed so as not to be electrically connected to the semiconductor substrate SUB. As shown in Fig. 9, in the interlayer insulating film formation process S8, a first layer ILD4a is formed on the interlayer insulating film ILD3 so as to cover the wiring layer WL3 using a method similar to that used in the interlayer insulating film formation process S5. As shown in Fig. 10, in the via plug formation process S9, via holes VH4a and VH4b are formed in the first layer ILD4a using a method similar to that used in the via plug formation process S6, and then via plugs VP4a are formed in the via holes VH4a and VH4b.

[0039] As shown in FIG. 11 , in the resistive film formation step S10, a resistive film RF1 is formed on the first layer ILD4a. In the resistive film formation step S10, first, a constituent material of the resistive film RF1 and a constituent material of the insulating film IF1 are sequentially deposited on the first layer ILD4a by, for example, a CVD method. Second, a resist pattern is formed by photolithography on the deposited constituent material of the insulating film IF1. Third, the deposited constituent material of the insulating film IF1 is etched using the resist pattern as a mask, thereby forming the insulating film IF1. Third, the deposited constituent material of the resistive film RF1 is etched using the insulating film IF1 as a mask, thereby forming the resistive film RF1. At this time, the resistive film RF1 is formed so as not to be electrically connected to the semiconductor substrate SUB.

[0040] In the cleaning step S11, the semiconductor wafer that has undergone the resistive film forming step S10 is cleaned. Specifically, the upper surface of the first layer ILD4a is cleaned. In this cleaning, residues generated during etching in the resistive film forming step S10 are removed using a solvent, and the solvent is then removed by rinsing with water. In the cleaning step S11, the upper surface of the first layer ILD4a is cleaned while the resistive film RF1 is not electrically connected to the semiconductor substrate SUB.

[0041] As shown in FIG. 12, in the interlayer insulating film forming step S12, a second layer ILD4b is formed on the first layer ILD4a to cover the resistive film RF1 and the insulating film IF1, using a method similar to that used in the interlayer insulating film forming step S5. As shown in FIG. 13, in the via plug forming step S13, via holes VH4c, VH4d, VH4e, and VH4f are formed in the interlayer insulating film ILD4 using a method similar to that used in the via plug forming step S6, and then via plugs VP4b are formed in the via holes VH4c, VH4d, VH4e, and VH4f. In the wiring layer forming step S14, a wiring layer WL4 is formed on the interlayer insulating film ILD4 using a method similar to that used in the wiring layer forming step S4. By forming the wiring layer WL4, the resistive film RF1 and the semiconductor substrate SUB are electrically connected via the wiring layer WL4. As a result, the structure of the semiconductor device DEV1 shown in FIG. 1 is formed.

[0042] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below.

[0043] As described above, in the manufacturing process of the semiconductor device DEV1, water rinsing is performed after the resistive film RF1 is formed but before the second layer ILD4b is formed. That is, in the manufacturing process of the semiconductor device DEV1, water rinsing is performed with the side surfaces of the resistive film RF1 exposed from the first layer ILD4a and the insulating film IF1. At this time, the resistive film RF1 becomes charged when it comes into contact with water. Therefore, if the resistive film RF1 is electrically connected to the semiconductor substrate SUB, a current flows between the resistive film RF1 and the semiconductor substrate SUB, and the silicon contained in the resistive film RF1 is likely to dissolve. As a result, the width of the resistive film RF1 becomes smaller, and the electrical resistance value of the resistive film RF1 fluctuates.

[0044] On the other hand, in the semiconductor device DEV1, the resistive film RF1 is electrically connected to the semiconductor substrate SUB via the via plug VP4aa, the wiring WL3a, and the via plug VP4ba, and is also electrically connected to the semiconductor substrate SUB via the via plug VP4ab, the wiring WL3b, and the via plug VP4ba. That is, the resistive film RF1 is not electrically connected to the semiconductor substrate SUB when the resistive film RF1 is washed with water. Therefore, in the semiconductor device DEV1, it is possible to suppress fluctuations in the electrical resistance value of the resistive film RF1 due to dissolution of silicon in the resistive film RF1 caused by washing with water.

[0045] <Modification> 14, in the semiconductor device DEV1, resistive films RF2 and RF3 may be formed instead of the wirings WL4a and WL4b. That is, in the semiconductor device DEV1, as long as the resistive film RF1 is connected to the semiconductor substrate SUB via the via plug VP4aa, the wiring WL3a, and the via plug VP4ba, and the resistive film RF1 is connected to the semiconductor substrate SUB via the via plug VP4ab, the wiring WL3b, and the via plug VP4bb, the connection method between the via plug VP4ba and the semiconductor substrate SUB and the connection method between the via plug VP4bb and the semiconductor substrate SUB are not particularly limited. The resistive films RF2 and RF3 contain silicon. The resistive films RF2 and RF3 are formed of, for example, SiCr or SiCrC.

[0046] (Second embodiment) A semiconductor device DEV2 according to the second embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0047] <Configuration of semiconductor device DEV2> The configuration of the semiconductor device DEV2 will be described below.

[0048] As shown in FIG. 15, the semiconductor device DEV2 includes a semiconductor substrate SUB, interlayer insulating films ILD1, ILD2, ILD3, and ILD4, wiring layers WL1, WL2, WL3, and WL4, a resistive film RF1, and an insulating film IF1. As shown in FIG. 16, the semiconductor device DEV2 further includes a resistive film RF4 and an insulating film IF2. The resistive film RF4 contains silicon. The resistive film RF4 is made of, for example, SiCr or SiCrC. The insulating film IF2 is made of, for example, silicon oxide.

[0049] In the semiconductor device DEV2, contact holes CHc and CHd are further formed in the interlayer insulating film ILD1. In the semiconductor device DEV2, via holes VH2c and VH2d are further formed in the interlayer insulating film ILD2. In the semiconductor device DEV2, via holes VH3c and VH3d are further formed in the interlayer insulating film ILD3. In the semiconductor device DEV2, via holes VH4g and VH4h are further formed in the first layer ILD4a.

[0050] In the semiconductor device DEV2, the wiring layer WL1 further includes a wiring WL1c and a wiring WL1d, the wiring layer WL2 further includes a wiring WL2c and a wiring WL2d, and the wiring layer WL3 further includes a wiring WL3e and a wiring WL3f.

[0051] The contact holes CHc and CHd overlap with the wiring WL1c and wiring WL1d, respectively, in plan view. A contact plug CPc is formed in the contact hole CHc, and a contact plug CPd is formed in the contact hole CHd. The contact plug CPc electrically connects the wiring WL1c to the semiconductor substrate SUB, and the contact plug CPd electrically connects the wiring WL1d to the semiconductor substrate SUB.

[0052] The via hole VH2c overlaps with the wiring WL1c and wiring WL2c in plan view. The via hole VH2d overlaps with the wiring WL1d and wiring WL2d in plan view. The via plug VP2c is formed in the via hole VH2c, and the via plug VP2d is formed in the via hole VH2d. The via plug VP2c electrically connects the wiring WL1c and wiring WL2c, and the via plug VP2d electrically connects the wiring WL1d and wiring WL2d.

[0053] The via hole VH3c overlaps with the wiring WL2c and wiring WL3e in plan view. The via hole VH3d overlaps with the wiring WL2d and wiring WL3f in plan view. The via plug VP3c is formed in the via hole VH3c, and the via plug VP3d is formed in the via hole VH3d. The via plug VP3c electrically connects the wiring WL2c and wiring WL3c, and the via plug VP3d electrically connects the wiring WL2d and wiring WL3d.

[0054] The via hole VH4g overlaps the resistive film RF4 and the wiring WL3e in a planar view. The via hole VH4h overlaps the resistive film RF4 and the wiring WL3f in a planar view. The via plug VP4ac is formed in the via hole VH4g, and the via plug VP4ad is formed in the via hole VH4h. The via plug VP4ac electrically connects the wiring WL3e and the resistive film RF4, and the via plug VP4d electrically connects the wiring WL3f and the resistive film RF4. Therefore, the resistive film RF4 is electrically connected to the semiconductor substrate SUB via the wiring WL3e, the via plug VP4ac, and the via plug VP3c, and is also electrically connected to the semiconductor substrate SUB via the wiring WL3f, the via plug VP4ad, and the via plug VP3d.

[0055] The width of the resistive film RF4 is, for example, smaller than the width of the resistive film RF1. The width of the resistive film RF1 is measured in a direction perpendicular to the direction in which the via plugs VP4a connected to the resistive film RF1 are arranged in a plan view. The width of the resistive film RF4 is measured in a direction perpendicular to the direction in which the via plugs VP4a connected to the resistive film RF4 are arranged in a plan view. The electrical resistance value of the resistive film RF4 is, for example, larger than the electrical resistance value of the resistive film RF1.

[0056] In the semiconductor device DEV2, for example, the resistive film RF1 is electrically connected to a transistor constituting a first circuit, and the resistive film RF4 is electrically connected to a transistor constituting a second circuit, and the precision of the electrical resistance value required for the second circuit may be lower than the precision of the electrical resistance value required for the first circuit.

[0057] <Method of manufacturing semiconductor device DEV2> The method for manufacturing the semiconductor device DEV2 includes a preparation step S1, an interlayer insulating film forming step S2, a contact plug forming step S3, a wiring layer forming step S4, an interlayer insulating film forming step S5, and a via plug forming step S6. The method for manufacturing the semiconductor device DEV2 further includes a wiring layer forming step S7, an interlayer insulating film forming step S8, a via plug forming step S9, a resistance film forming step S10, a cleaning step S11, an interlayer insulating film forming step S12, a via plug forming step S13, and a wiring layer forming step S14.

[0058] In the manufacturing method of the semiconductor device DEV2, in a contact plug forming step S3, contact holes CHc and CHd are further formed in the interlayer insulating film ILD1, and then contact plugs CPc and CPd are further formed in the contact holes CHc and CHd. In the manufacturing method of the semiconductor device DEV2, in a wiring layer forming step S4, wirings WL1c, WL1d, WL2c, and WL2d are further formed.

[0059] In the manufacturing method of the semiconductor device DEV2, in the via plug forming step S6, after via holes VH2c and VH2d are further formed in the interlayer insulating film ILD2, via plugs VP2c and VP2d are formed in the via holes VH2c and VH2d. Also, in the manufacturing method of the semiconductor device DEV2, in the via plug forming step S6, after via holes VH3c and VH3d are further formed in the interlayer insulating film ILD3, via plugs VP3c and VP3d are further formed in the via holes VH3c and VH3d.

[0060] In the manufacturing method of the semiconductor device DEV2, in the wiring layer forming step S7, wirings WL3c and WL3d are further formed. In the manufacturing method of the semiconductor device DEV2, in the via plug forming step S9, via holes VH4g and VH4h are further formed in the first layer ILD4, and then via plugs VP4ac and VP4ad are further formed in the via holes VH4g and VH4h.

[0061] 17, in the manufacturing method of the semiconductor device DEV2, a resistive film RF4 and an insulating film IF2 are further formed in a resistive film forming step S10. In the manufacturing method of the semiconductor device DEV2, at the stage when the resistive film forming step S10 is completed, the side surface of the resistive film RF4 is exposed between the insulating film IF2 and the first layer ILD4a, and the resistive film RF4 is electrically connected to the semiconductor substrate SUB. In the cleaning step S11, the upper surface of the first layer ILD4a is cleaned while the resistive film RF4 is electrically connected to the semiconductor substrate SUB. Therefore, in the manufacturing method of the semiconductor device DEV2, in the cleaning step S11, silicon in the resistive film RF4 dissolves, and the width of the resistive film RF4 becomes smaller.

[0062] <Effects of semiconductor device DEV3> The effects of the semiconductor device DEV3 will be described below.

[0063] In the semiconductor device DEV3, since the resistive film RF4 is electrically connected to the semiconductor substrate SUB during the cleaning step S11, the width of the resistive film RF4 decreases as silicon in the resistive film RF4 dissolves. As a result, in the semiconductor device DEV3, by actively utilizing the dissolution of silicon in the resistive film RF4, it becomes possible to form the resistive film RF4 having a width smaller than the resolution limit of photolithography.

[0064] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0065] BM1 barrier metal, BM2 barrier metal, CHa, CHb, CHc, CHd contact holes, CP, CPa, CPb, CPc, CPd contact plugs, DEV1 semiconductor device, DEV2 semiconductor device, F1 upper surface, F2 lower surface, IF1, IF2 insulating film, ILD1, ILD2, ILD3, ILD4 interlayer insulating film, ILD4a first layer, ILD4b second layer, RF1 resistive film, RF2, RF3, RF4 resistive film, S1 preparation step, S2 interlayer insulating film formation step, S3 contact plug formation step, S4 wiring layer formation step, S5 interlayer insulating film formation step, S6 via plug formation step, S7 wiring layer formation step, S8 interlayer insulating film formation step, S9 via plug formation step, S10 resistive film formation step, S11 cleaning step, S12 interlayer insulating film formation step, S13 via plug formation step, S14 Wiring layer formation process, SUB semiconductor substrate, VH2a, VH2b, VH2c, VH2d, VH3a, VH3b, VH3c, VH3d, VH4a, VH4b, VH4c, VH4d, VH4e, VH4f, VH4g, VH4h via holes, VP2, VP2a, VP2b, VP2c, VP2d, VP3, VP3a, VP3b, VP3c, VP3d, VP4a, VP4aa, VP4ab, VP4ac, VP4ad, VP4b, VP4ba, VP4bb via plugs, WL1a, WL1b, WL1c, WL1d, WL2a, WL2b, WL2c, WL2d, WL3a, WL3b, WL3c, WL3d, WL3e, WL3f, WL4a, WL4b wiring, WL1, WL2, WL3, WL4 wiring layer.

Claims

1. a semiconductor substrate; a first interlayer insulating film formed above the semiconductor substrate; a first wiring formed on the first interlayer insulating film; a second interlayer insulating film formed on the first interlayer insulating film, the second interlayer insulating film having a first layer covering the first wiring and a second layer formed on the first layer; a first resistive film formed on the first layer and covered with the second layer; a first via plug formed in the first layer and electrically connecting the first wiring and the first resistive film; a second via plug formed in the second interlayer insulating film and electrically connected to the first wiring; the first resistive film contains silicon; The semiconductor device, wherein the first resistive film is electrically connected to the semiconductor substrate via the first wiring, the first via plug, and the second via plug.

2. Further comprising a first insulating film; the first insulating film is formed on the first resistive film, a side surface of the first resistive film is exposed between the first layer and the first insulating film; The semiconductor device according to claim 1 , wherein said second layer further covers said first insulating film.

3. The semiconductor device according to claim 1 , wherein said first resistive film is made of SiCr or SiCrC.

4. Further provided with a second wiring, the second wiring is formed on the second interlayer insulating film, The semiconductor device according to claim 1 , wherein said second wiring is electrically connected to said second via plug.

5. Further comprising a second resistive film; the second resistive film is formed on the second interlayer insulating film, the second resistive film contains silicon; The semiconductor device according to claim 1 , wherein said second resistive film is electrically connected to said second via plug.

6. The semiconductor device according to claim 5 , wherein the second resistive film is made of SiCr or SiCrC.

7. a third wiring formed on the first interlayer insulating film and covered with the first layer; a third resistive film formed on the first layer and covered with the second layer; a third via plug formed in the first layer and electrically connecting the third wiring and the third resistive film; a fourth via plug formed in the first interlayer insulating film and electrically connected to the third wiring; The semiconductor device according to claim 1 , wherein said third resistive film contains silicon.

8. Further comprising a second insulating film; the second insulating film is formed on the third resistive film, a side surface of the third resistive film is exposed between the first layer and the second insulating film; The semiconductor device according to claim 7 , wherein said second layer further covers said second insulating film.

9. 8. The semiconductor device according to claim 7, wherein said third resistive film is electrically connected to said semiconductor substrate via said third wiring, said third via plug, and said fourth via plug.

10. 8. The semiconductor device according to claim 7, wherein said third resistive film is made of SiCr or SiCrC.

11. The semiconductor device according to claim 7 , wherein a width of said third resistive film is smaller than a width of said first resistive film.

12. forming a first interlayer insulating film on a semiconductor substrate; forming a first wiring on the first interlayer insulating film; forming a first layer of a second interlayer insulating film on the first interlayer insulating film so as to cover the first wiring; forming a first via plug in the first layer so as to be electrically connected to the first wiring; forming a first resistive film containing silicon on the first layer so as to be electrically connected to the first via plug; forming a second layer of the second interlayer insulating film on the first layer so as to cover the first resistive film; and cleaning the upper surface of the first layer after the step of forming the first resistive film. A method for manufacturing a semiconductor device, wherein in the step of cleaning the upper surface of the first layer, the upper surface of the first layer is cleaned in a state where the first resistive film is not electrically connected to the semiconductor substrate.

13. After the step of cleaning the upper surface of the first layer, forming a second layer of the second interlayer insulating film on the first layer so as to cover the first resistive film; 13. The method for manufacturing a semiconductor device according to claim 12, further comprising the step of forming a second via plug in said second interlayer insulating film so as to be electrically connected to said first wiring.

14. after the step of forming the second via plug, a step of forming a second wiring on the second interlayer insulating film so as to be electrically connected to the second via plug; 14. The method for manufacturing a semiconductor device according to claim 13, wherein the first resistive film is electrically connected to the semiconductor substrate via the first wiring, the second wiring, the first via plug, and the second via plug.

15. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the first resistive film is made of SiCr or SiCrC.

16. after the step of forming the second via plug, forming a second resistance film on the second interlayer insulating film so as to be electrically connected to the second via plug; the second resistive film contains silicon; 14. The method for manufacturing a semiconductor device according to claim 13, wherein the first resistive film is electrically connected to the semiconductor substrate via the first wiring, the second resistive film, the first via plug, and the second via plug.

17. forming a fourth via plug in the first interlayer insulating film; forming a third wiring on the first interlayer insulating film so as to be connected to the fourth via plug; forming a third via plug in the first layer so as to be electrically connected to the third wiring; forming a third resistive film on the first layer; the third resistive film contains silicon; 13 . The method for manufacturing a semiconductor device according to claim 12 , wherein in the step of cleaning the upper surface of the first layer, the upper surface of the first layer is cleaned in a state where the third resistive film is electrically connected to the semiconductor substrate.

18. 18. The method for manufacturing a semiconductor device according to claim 17, wherein after the step of cleaning the top surface of the first layer, a width of the third resistive film is smaller than a width of the first resistive film.

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