Digital filter circuit with fault detection function and method for fault detection in digital filter circuit

Abstract

To detect faults in digital filters used for analog signals in railway track circuit devices while ensuring the integrity of components such as A / D converters.SOLUTION: A digital filter circuit 10 with fault detection function includes A / D converters 14 and 16 that convert analog signals into digital data, subtracters 20 and 22 that extract differences between pieces of the digital data, error range determination circuits 26 and 28 that determine whether the output results of the subtracters 20 and 22 fall within preset error ranges, digital filters 32 and 34 that perform filtering on the digital data, and an abnormality determination circuit 38 that determines the presence or absence of anomalies. By confirming that the outputs of the two subtracters 20 and 22 fall within the error range in this manner, a comparison mismatch caused by quantization errors or carry-over / carry-under in the A / D converters 14 and 16 can be avoided, allowing faults to be detected while ensuring the integrity of the output data of the A / D converters 14 and 16.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a digital filter circuit with a fault detection function used for analog signals in railway track circuit devices, and a fault detection method for such a digital filter circuit. [Background technology]

[0002] Railway track circuit devices include a transmitter that outputs a signal to detect trains on the rails and a receiver that receives the signal from the transmitter. The presence or absence of a train on the track is detected by the level of the signal received by the receiver. Because the receiver is affected by noise from sources other than the signal from the transmitter, such as train current, a bandpass filter (BPF) is used to extract the transmitted analog signal, and LC filters are widely used for this BPF. LC filters have a simple structure, so if a fault occurs within the circuit, the output is greatly attenuated, causing the final-stage output relay to recover (trip), making fault detection easy. However, LC filters are experiencing delivery delays and rising prices due to factors such as the discontinuation of production of inductance ferrite core components.

[0003] Therefore, the inventors decided to develop an inexpensive, readily available filter to replace conventional LC filters, and considered using digital filters to achieve this. In other words, digital filters can achieve the same characteristics as high-order LC filters using an AD converter and an integrated circuit (IC) such as an FPGA or CPU. These components are readily available, and cost reductions are expected. However, because safety must be maintained as required for track circuit receivers in the railway field, simply digitizing analog signals is not enough to replace conventional LC filters. This is because there is no guarantee that the reception level will necessarily decrease if the AD converter or digital filter fails.

[0004] In order to solve the above problems, the inventors conceived of using a dual-system AD converter and digital filter and a conventional bus collation circuit (see, for example, Patent Documents 1 and 2) to detect abnormalities in them. A bus collation circuit is a circuit that compares digital data, such as memory data and calculation results, of two CPUs, for example, an A-system CPU and a B-system CPU, and outputs an alternating signal if the comparison results are a perfect match. Therefore, when a bus collation circuit is used in a dual-system AD converter or digital filter, if an alternating signal is output from the bus collation circuit, it can be determined that the results of the AD converter or digital filter are correct. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-174648 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-197754 Summary of the Invention [Problem to be solved by the invention]

[0006] To ensure the validity of an AD converter using a bus matching circuit as described above, two AD converters must be used, each generating digital data from an analog signal, and the results compared using a bus matching circuit. However, AD converters are subject to certain output errors (quantization errors) and carryovers or borrowings that are stipulated in their specifications, which can manifest as differences in the results between the two AD converters. For this reason, using a bus matching circuit, which requires perfect matching of digital data, could result in the two AD converters being judged as abnormal even when they are operating normally, and therefore the bus matching circuit cannot be applied directly to the two AD converters.

[0007] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to detect faults in digital filters used for analog signals in railway track circuit devices while ensuring the validity of AD converters and the like. [Means for solving the problem]

[0008] (Aspects of the invention) The following embodiments of the present invention are examples of the configuration of the present invention, and are described in terms to facilitate understanding of the various configurations of the present invention. Each term does not limit the technical scope of the present invention, and while taking into consideration the best mode for carrying out the invention, some of the components of each term may be replaced or deleted, or other components may be added, and these may also be included in the technical scope of the present invention.

[0009] (1) A digital filter circuit used for an analog signal in a railway track circuit device, the digital filter circuit comprising: a first AD converter that converts the analog signal into first digital data; a second AD converter that converts the analog signal into second digital data; a first subtractor that subtracts the second digital data from the first digital data; a second subtractor that subtracts the first digital data from the second digital data; a first error range determination circuit that determines whether an output result of the first subtractor is within a preset error range taking into account specifications of the first AD converter and the second AD converter; a second error range determination circuit that determines whether an output result of a digital filter is within the error range; a first digital filter that removes noise components from either the first digital data or the second digital data and outputs the resulting digital data; a second digital filter that removes noise components from the one digital data and outputs the resulting digital data; and an abnormality determination circuit that determines whether an abnormality has occurred based on a determination result of the first error range determination circuit, a determination result of the second error range determination circuit, an output result of the first digital filter, and an output result of the second digital filter.

[0010] The digital filter circuit with fault detection function described in this section includes a first AD converter, a second AD converter, a first subtractor, a second subtractor, a first error range determination circuit, a second error range determination circuit, a first digital filter, a second digital filter, and an abnormality determination circuit. The first AD converter and the second AD converter convert analog signals used in railway track circuit devices into digital data, and form a dual AD converter system for converting the same analog signal. Here, the data converted from the analog signal by the first AD converter is referred to as first digital data, and the data converted from the analog signal by the second AD converter is referred to as second digital data.

[0011] The first subtractor subtracts the second digital data from the first digital data, while the second subtractor subtracts the first digital data from the second digital data. That is, the first and second subtractors extract the difference between the first and second digital data. The first error range determination circuit determines whether the output result of the first subtractor is within a preset error range, and similarly, the second error range determination circuit determines whether the output result of the second subtractor is within a preset error range. The error ranges set in both the first and second error range determination circuits are determined taking into account the specifications (error, carry, borrow) of the components used in the first and second AD converters.

[0012] The first digital filter and the second digital filter constitute a dual system of digital filters and operate on the same digital data. That is, both the first digital filter and the second digital filter remove noise components from either the first digital data or the second digital data and output the resulting digital data. These first digital filter and the second digital filter are configured to perform an appropriate filter function, such as a band-pass filter, depending on where the digital filter circuit with fault detection function described in this section is applied. Then, either the output result of the first digital filter or the output result of the second digital filter is used as the output result from the digital filter circuit with fault detection function described in this section.

[0013] The anomaly determination circuit determines whether an anomaly has occurred based on the determination results of the first error range determination circuit, the determination results of the second error range determination circuit, the output result of the first digital filter, and the output result of the second digital filter. For example, the anomaly determination circuit determines whether the difference between the first digital data and the second digital data is within the error range based on the determination results of the first error range determination circuit and the second error range determination circuit, and determines that an anomaly has occurred if the difference is not within the error range. This determination is made when an anomaly has occurred in the first AD converter, the second AD converter, the first subtractor, or the second subtractor. The anomaly determination circuit also determines that an anomaly has occurred when the output result of the first digital filter and the output result of the second digital filter are not equal. This determination is made when an anomaly has occurred in the first digital filter or the second digital filter.

[0014] With the above configuration, the digital filter circuit with fault detection function described in this section ensures the validity of the output data of the AD converter by verifying that the outputs of the two subtractors are within an error range, avoiding comparison discrepancies due to quantization errors, carryovers, and borrowings of the AD converter. Furthermore, by comparing the output results of two digital filters to which the output data of such AD converters is input, the validity of those digital filters is also ensured. Furthermore, even though input data, i.e., the output data from the two AD converters, do not perfectly match, a circuit similar to a bus matching circuit, which requires perfect match, can ultimately be used. Furthermore, since the anomaly detection circuit determines whether an anomaly has occurred in various components as described above, a failure of those components can be detected. Safety is ensured by processing, such as outputting the output result of the first or second digital filter only when the anomaly detection circuit determines that no anomaly has occurred. This will enable the realization of a digital filter circuit that is easy to obtain and can replace conventional LC filters, while targeting analog signals used in various parts of railway track circuit equipment and avoiding the problems specific to track circuit equipment and ensuring the validity of AD converters, etc.

[0015] (2) A digital filter circuit used for analog signals in a railway track circuit device, comprising: a first AD converter that converts the analog signal into first digital data; a second AD converter that converts the analog signal into second digital data; a first subtractor that subtracts lower-order bits of the second digital data in which a quantization error occurs in the second AD converter from lower-order bits of the first digital data in which a quantization error occurs in the first AD converter; a second subtractor that subtracts the lower-order bits of the first digital data from the lower-order bits of the second digital data; a first error range determination circuit that determines whether an output result of the first subtractor is within a predetermined error range taking into account specifications of the first AD converter and the second AD converter; a second error range determination circuit that determines whether or not the data is within an error range; a most significant bit comparison circuit that compares most significant bits of the first digital data, excluding the most significant bits, with most significant bits of the second digital data, excluding the most significant bits; a first digital filter that removes noise components from one of the first digital data and the second digital data and outputs the resulting digital data; a second digital filter that removes noise components from the one of the first digital data and the second digital data and outputs the resulting digital data; and an abnormality determination circuit that determines whether or not an abnormality has occurred, based on a determination result of the first error range determination circuit, a determination result of the second error range determination circuit, an output result of the most significant bit comparison circuit, an output result of the first digital filter, and an output result of the second digital filter.

[0016] The digital filter circuit with fault detection function described in this section includes, similarly to the digital filter circuit with fault detection function described in section (1) above, a first AD converter, a second AD converter, a first subtractor, a second subtractor, a first error range determination circuit, a second error range determination circuit, a first digital filter, a second digital filter, and an abnormality determination circuit. Of these, the first AD converter, the second AD converter, the first error range determination circuit, the second error range determination circuit, the first digital filter, and the second digital filter perform substantially the same operations as those of the digital filter circuit with fault detection function described in section (1) above. In contrast, the first subtractor and the second subtractor perform operations on only a portion of the first digital data output from the first AD converter or the second digital data output from the second AD converter, rather than on all bits of the first digital data or all bits of the second digital data.

[0017] That is, the first subtractor subtracts the least significant bits of the second digital data where a quantization error occurs in the second AD converter from the least significant bits of the first digital data where a quantization error occurs in the first AD converter. Conversely, the second subtractor subtracts the least significant bits of the first digital data where a quantization error occurs in the first AD converter from the least significant bits of the second digital data where a quantization error occurs in the second AD converter. The least significant bits where a quantization error occurs in the first and second AD converters are one or more bits including the LSB, as determined from the specifications of the components used in those AD converters. This allows a difference between the first digital data and the second digital data with respect to the least significant bits where a quantization error occurs in the first and second AD converters.

[0018] Furthermore, the digital filter circuit with fault detection function described in this section includes a most significant bit comparison circuit. This most significant bit comparison circuit compares the most significant bits of the first digital data, excluding the least significant bits where quantization error occurs as described above, with the most significant bits of the second digital data, excluding the least significant bits where quantization error occurs as described above. That is, the most significant bit comparison circuit compares the most significant bits of the first digital data, including the MSB, where a carry or borrow occurs, with the most significant bits of the second digital data, including the MSB, where a carry or borrow occurs. The most significant bit comparison circuit then outputs the comparison result to the abnormality determination circuit.

[0019] The anomaly determination circuit, like the digital filter circuit with fault detection function described in (1) above, determines whether an anomaly has occurred based on the determination result of the first error range determination circuit, the determination result of the second error range determination circuit, the output result of the first digital filter, and the output result of the second digital filter. Furthermore, the anomaly determination circuit also determines whether an anomaly has occurred based on the output result of the upper bit comparison circuit. Specifically, the anomaly determination circuit determines that an anomaly has occurred when a comparison result indicating a difference between the upper bits of the first digital data and the upper bits of the second digital data other than a difference due to carry-over or carry-down in the first and second AD converters is input. Such a determination is made when an anomaly has occurred in the output of the upper bits of the first AD converter or the output of the upper bits of the second AD converter.

[0020] Here, in the digital filter circuit with a fault detection function of the above paragraph (1), the first and second subtractors extract the difference between all bits of the first digital data and all bits of the second digital data, and the difference between the higher-order bits, excluding the lower-order bits where errors occur in the first and second AD converters, is always zero even under normal conditions. Therefore, even if an abnormality occurs in the first subtractor or the second subtractor such that the higher-order bit output is fixed to zero, this abnormality will not be detected, and naturally, a fault in the higher-order bits of the first AD converter or the second AD converter will not be detected either.

[0021] In contrast, in the digital filter circuit with fault detection function described in this section, the first and second subtractors do not extract the difference between the most significant bits of the first digital data and the most significant bits of the second digital data, but rather the most significant bits are compared by the most significant bit comparison circuit. As described above, the abnormality determination circuit detects the occurrence of an abnormality in the output of the most significant bits of the first AD converter or the output of the most significant bits of the second AD converter. Therefore, the digital filter circuit with fault detection function described in this section not only achieves the same functions as the digital filter circuit with fault detection function described in section (1) above, but also detects abnormalities in the abnormality determination circuit that may be overlooked by the digital filter circuit with fault detection function described in section (1) above. This allows for the detection of a wider variety of fault patterns.

[0022] (3) In the above paragraphs (1) and (2), when the upper limit of the error range is expressed by a positive integer n, the first error range determination circuit compares the output result of the first subtractor with each of the values ​​0 to n or 1 to n that increase by 1, and outputs a determination result that the output result of the first subtractor is within the error range when the comparison result is equal to only one of the values, and the second error range determination circuit compares the output result of the second subtractor with each of the values ​​0 to n or 1 to n, and outputs a determination result that the output result of the second subtractor is equal to only one of the values. a digital filter circuit with a fault detection function that outputs a determination result that the output result of the second subtractor is within the error range when the output result of the first error range determination circuit or the second error range determination circuit is equal to only the value of n; one of the first error range determination circuit and the second error range determination circuit uses 0 to n as a comparison target, and the other uses 1 to n as a comparison target; and the abnormality determination circuit outputs a determination result that an abnormality has occurred, except when only one of the determination result of the first error range determination circuit and the determination result of the second error range determination circuit is within the error range.

[0023] The digital filter circuit with fault detection function described in this section specifically specifies a determination method by the first and second error range determination circuits when the upper limit of the error range set in the first and second error range determination circuits is a positive integer n. That is, the first error range determination circuit compares the output result of the first subtractor with each of the values ​​0 to n or 1 to n, which increase by 1. For example, when n=5, the output result of the first subtractor is compared with each of the values ​​0, 1, 2, 3, 4, and 5, or with each of the values ​​1, 2, 3, 4, and 5. Then, as a result of this comparison, if the output result of the first subtractor is equal to only one of the above-mentioned values, a determination result is output that the output result of the first subtractor is within the error range. That is, if the output result of the first subtractor is a positive value as described below and falls within the error range whose upper limit is a positive integer n, the output result should be equal to one of the values ​​0 to n or 1 to n, and this is used to make the determination.

[0024] Similarly, the second error range determination circuit compares the output result of the second subtractor with each of the values ​​0 to n or 1 to n, which increase by one, and outputs a determination result that the output result of the second subtractor is within the error range if the comparison result is equal to only one of the values ​​0 to n or 1 to n. Here, the first subtractor and the second subtractor extract the difference between the first digital data and the second digital data (or the difference between their least significant bits). If the difference is not zero, the output result of one subtractor is a positive difference, and the output result of the other subtractor is a negative difference. Therefore, if the difference between the first digital data and the second digital data (or the difference between their least significant bits) is not zero, the first error range determination circuit and the second error range determination circuit make the following determination depending on the output result of the subtractor being determined. That is, if the output result is a positive difference, it is determined to be within the error range. If the output result is a negative difference, it is determined to be outside the error range because a bit inversion due to the minus has occurred in the digital data.

[0025] Furthermore, the first error range determination circuit and the second error range determination circuit compare the output result of the first subtractor or the second subtractor with a comparison target of 0 to n, while the other compares with a comparison target of 1 to n. That is, only one of the comparison targets of the first error range determination circuit and the second error range determination circuit includes zero. Assuming that the first and second AD converters and the first and second subtractors are operating normally, three possible cases are possible: a case where the output result of the first subtractor is a positive difference and the output result of the second subtractor is a negative difference; a case where the output result of the first subtractor is a negative difference and the output result of the second subtractor is a positive difference; and a case where both the output results of the first subtractor and the second subtractor are zero. In any of these three cases, with the above-described configuration, only one of the first and second error range determination circuits determines that the output result of the target subtractor is within the error range. For this reason, the abnormality determination circuit outputs a determination result that an abnormality has occurred unless only one of the determination results of the first error range determination circuit and the second error range determination circuit is within the error range, thereby enabling the abnormality determination circuit to more accurately detect the occurrence of an abnormality in the first and second AD converters or the first and second subtractors.

[0026] (4) In the digital filter circuit with a fault detection function in the above paragraph (2), the upper bit comparison circuit outputs three comparison results: a comparison result of whether or not one of the upper bits of the first digital data and the upper bits of the second digital data, with 1 added to it, is equal to the other; a comparison result of whether or not one of the upper bits is equal to the other; and a comparison result of whether or not one of the upper bits is equal to the other, with 1 subtracted from it; and the abnormality determination circuit outputs a determination result that an abnormality has occurred, except when only one of the three comparison results from the upper bit comparison circuit is equal.

[0027] The digital filter circuit with fault detection function described in this section specifically specifies a comparison method by a higher-order bit comparison circuit. Here, the higher-order bits of the first digital data, which cause a carry or borrow in the first AD converter, and the higher-order bits of the second digital data, which cause a carry or borrow in the second AD converter, are assumed to have the following patterns regarding carry or borrow: That is, a carry occurs in either one of the higher-order bits of the first digital data or the higher-order bits of the second digital data, a borrow occurs in either one, a carry occurs in both, a borrow occurs in both, or neither a carry nor a borrow occurs in either.

[0028] Taking this into consideration, the upper bit comparison circuit outputs three comparison results: a comparison result of whether or not adding 1 to one of the upper bits of the first digital data and the upper bits of the second digital data is equal to the other; a comparison result of whether or not one of the upper bits is equal to the other; and a comparison result of whether or not subtracting 1 from one of the upper bits is equal to the other. As a result, regardless of the pattern described above, only one of the three comparison results will result in an equality. Therefore, the abnormality determination circuit outputs a determination result indicating an abnormality has occurred in any case other than when only one of the three comparison results from the upper bit comparison circuit is equal. In this way, by intentionally generating and comparing carry or borrow data in the upper bit comparison circuit, an abnormality in the output of the upper bits of the first AD converter or an abnormality in the output of the upper bits of the second AD converter can be detected with greater accuracy.

[0029] (5) In the above (1) and (2), the digital filter circuit with a fault detection function further includes a threshold determination circuit that receives an output result of the first digital filter or an output result of the second digital filter and determines whether the input exceeds a preset threshold value, and an output control circuit that controls the threshold determination circuit to operate only when the abnormality determination circuit outputs a determination result that no abnormality has occurred. The digital filter circuit with fault detection function described in this section further includes a threshold value determination circuit and an output control circuit. The threshold value determination circuit receives the output result of the first digital filter or the output result of the second digital filter and determines whether or not this input data exceeds a preset threshold value. In other words, the threshold value determination circuit determines whether or not data obtained by digitizing an analog signal used in a railway track circuit device using a first or second AD converter and then removing noise components using a first or second digital filter exceeds a threshold value set depending on the use of the analog signal, etc.

[0030] The output control circuit controls the output from the threshold value judgment circuit, and controls the threshold value judgment circuit to operate only when the abnormality judgment circuit outputs a judgment result indicating that no abnormality has occurred. As a result, if no abnormality is detected by the abnormality judgment circuit, the data input to the threshold value judgment circuit is considered to be normal, and the judgment result by the threshold value judgment circuit is output as is. On the other hand, if an abnormality is detected by the abnormality judgment circuit, the data input to the threshold value judgment circuit is also considered to be abnormal, and the operation of the threshold value judgment circuit is stopped, and the output level is fixed to a LOW (lowered) side, for example. Therefore, it is possible to appropriately determine whether the analog signal used in railway track circuit equipment exceeds a threshold value appropriate for the application, and when an abnormality occurs, the output is fixed to a safe side.

[0031] (6) In the above items (1) and (2), the first AD converter and the second AD converter are configured with the same components having the same specifications, and the error range is twice the error range specified by the specifications of the same components. In the digital filter circuit with fault detection function described in this section, the first AD converter and the second AD converter are configured with the same components having the same specifications, and the error ranges set in the first and second error range determination circuits are twice the error ranges defined by the specifications of the components that make up the first and second AD converters.

[0032] That is, the first and second error range determination circuits determine the output result of a first subtractor that subtracts second digital data (or their least significant bits) from first digital data and the output result of a second subtractor that subtracts first digital data (or their least significant bits) from second digital data. Therefore, if the first and second AD converters and the first and second subtractors are operating normally, the output results of the first and second subtractors will be within twice the error range defined by the specifications of the components that make up the first and second AD converters. As a result, even if a quantization error, carry-over, or borrow error occurs in the output of the first AD converter or the output of the second AD converter, the first error range determination circuit and the second error range determination circuit will properly determine that the error is within the error range, thereby avoiding erroneous determination of an abnormality by the abnormality determination circuit.

[0033] (7) In the above items (1) and (2), at least the first subtractor, the second subtractor, the first error range determination circuit, the second error range determination circuit, the first digital filter, the second digital filter, and the abnormality determination circuit are implemented in a single component. The digital filter circuit with fault detection function described in this section is implemented in a single component, including at least a first subtractor, a second subtractor, a first error range determination circuit, a second error range determination circuit, a first digital filter, a second digital filter, and an abnormality determination circuit. Depending on the situation, the single component may also include a threshold determination circuit, a high-order bit comparison circuit, and the like. The single component may be a hardware-based component such as an FPGA or CPLD, or a software-based component such as a CPU. This reduces the overall circuit size and costs. Furthermore, while the same component is used, simply by rewriting data, the circuit can easily accommodate a wide range of components used as the first and second AD converters, multiple frequency lineups, and the like.

[0034] (8) A fault detection method for a digital filter circuit used for analog signals of a railway track circuit device, comprising: converting the analog signal into first digital data by a first AD converter; converting the analog signal into second digital data by a second AD converter; subtracting the second digital data from the first digital data by a first subtractor; subtracting the first digital data from the second digital data by a second subtractor; and determining whether an output result of the first subtractor is within a predetermined error range taking into account specifications of the first AD converter and the second AD converter. a second error range determination circuit determines whether or not an output result of the second subtractor is within the error range; a first digital filter removes noise components from either the first digital data or the second digital data and outputs the resulting digital data; and a second digital filter removes noise components from the one digital data and outputs the resulting digital data; and an abnormality determination circuit determines whether or not an abnormality has occurred based on the determination result of the first error range determination circuit, the determination result of the second error range determination circuit, the output result of the first digital filter, and the output result of the second digital filter.

[0035] (9) A fault detection method for a digital filter circuit used for analog signals of a railway track circuit device, comprising: converting the analog signal into first digital data by a first AD converter; converting the analog signal into second digital data by a second AD converter; subtracting, by a first subtractor, lower-order bits of the second digital data in which a quantization error occurs in the second AD converter from lower-order bits of the first digital data in which a quantization error occurs in the first AD converter; subtracting, by a second subtractor, lower-order bits of the first digital data from lower-order bits of the second digital data; determining, by a first error range determination circuit, whether or not an output result of the first subtractor is within a preset error range taking into account specifications of the first AD converter and the second AD converter; a first digital filter that removes noise components from one of the first digital data and the second digital data and outputs the resulting digital data, and a second digital filter that removes noise components from the other digital data and outputs the resulting digital data; and an abnormality detection circuit that determines whether or not an abnormality has occurred based on the determination result of the first error range determination circuit, the determination result of the second error range determination circuit, the output result of the upper bit comparison circuit, the output result of the first digital filter, and the output result of the second digital filter.

[0036] The fault detection methods in the digital filter circuit described in (8) and (9) are executed using the digital filter circuits with fault detection function described in (1) and (2) above, respectively, and thereby achieve the same effects as those of the digital filter circuits with fault detection function described in (1) and (2) above. [Effects of the Invention]

[0037] With the above-described configuration, the present invention makes it possible to detect failures in digital filters used for analog signals in railway track circuit devices while ensuring the validity of AD converters and the like. [Brief explanation of the drawings]

[0038] [Figure 1] 1 is a block diagram schematically illustrating an example of the configuration of a digital filter circuit with a failure detection function according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic block diagram showing an example of details of first and second error range determination circuits. [Figure 3] FIG. 3 is a block diagram schematically illustrating an example of details of an abnormality determination circuit. [Figure 4] FIG. 2 is a block diagram schematically illustrating an example of details of an output control circuit. [Figure 5] FIG. 10 is a block diagram schematically illustrating an example of the configuration of a digital filter circuit with a failure detection function according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a block diagram schematically illustrating an example of details of a high-order bit comparison circuit. [Figure 7] FIG. 3 is a block diagram schematically illustrating an example of details of an abnormality determination circuit. DETAILED DESCRIPTION OF THE INVENTION

[0039] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Here, detailed descriptions of parts that are the same as or corresponding to those in the prior art will be omitted, and the same reference numerals will be used throughout the drawings to indicate the same or corresponding parts. 1 shows a schematic diagram of an example of the configuration of a digital filter circuit 10 with fault detection function according to a first embodiment of the present invention, which processes analog signals used in railway track circuit equipment. As shown in FIG. 1, the digital filter circuit 10 with fault detection function according to the first embodiment of the present invention includes a first AD converter 14, a second AD converter 16, a first subtractor 20, a second subtractor 22, a first error range determination circuit 26, a second error range determination circuit 28, a first digital filter 32, a second digital filter 34, an abnormality determination circuit 38, a threshold determination circuit 44, and an output control circuit 46.

[0040] The first AD converter 14 and the second AD converter 16 are used to convert the analog signal to be processed, which is input to the digital filter circuit 10, into digital data. For ease of explanation, the digital data converted from the analog signal to be processed by the first AD converter 14 will be referred to as the first digital data, and the digital data converted from the analog signal to be processed by the second AD converter 16 will be referred to as the second digital data. Any AD converters having the required resolution may be used for the first AD converter 14 and the second AD converter 16, depending on the analog signal to be processed and its application. In this embodiment, the same AD converter having the same specifications, including quantization error, carry-over, and borrow-over, is used for both the first AD converter 14 and the second AD converter 16.

[0041] The first subtractor 20 and the second subtractor 22 extract the difference between the first digital data and the second digital data, performing subtraction with the opposite operations. That is, the first subtractor 20 subtracts the second digital data from the first digital data, and the second subtractor 22 subtracts the first digital data from the second digital data. The first error range determination circuit 26 and the second error range determination circuit 28 determine whether the output results of the first subtractor 20 and the second subtractor 22 are within predetermined error ranges. The error ranges set in the first error range determination circuit 26 and the second error range determination circuit 28 are set taking into account the specifications of the AD converters used as the first AD converter 14 and the second AD converter 16. In this embodiment, the first AD converter 14 and the second AD converter 16 are configured using the same AD converter with the same specifications, and therefore a range twice the error range specified in the specifications of the AD converter is set in the first error range determination circuit 26 and the second error range determination circuit 28.

[0042] 2 illustrates the detailed configuration of the first error range determination circuit 26 and the second error range determination circuit 28 when the upper limit of the error range set in the first error range determination circuit 26 and the second error range determination circuit 28 is a positive integer n. First, the first error range determination circuit 26 shown in FIG. 2(a) is configured to compare the output result from the first subtractor 20 with each of the values ​​0 to n, which increase by 1. To this end, the first error range determination circuit 26 includes a two-wire inspection circuit 50a for comparing the output result of the first subtractor 20 with ±0, a two-wire inspection circuit 50b for comparing it with +1, a two-wire inspection circuit 50c for comparing it with +2, and a two-wire inspection circuit 50d for comparing it with . . . and +n. Although only four two-wire inspection circuits 50a to 50d are shown in FIG. 2(a), the first error range determination circuit 26 has a plurality of two-wire inspection circuits 50 (n+1 in this embodiment) required for comparison with each of the values ​​0 to n, which increase by one.

[0043] Here, a brief description of the two-rail test circuit 50 will be given. Each two-rail test circuit 50 is a tree-like arrangement of basic narrowing-down circuits, each of which aggregates two input code words into a single code word and outputs the aggregated code word. When this aggregation is performed, the basic narrowing-down circuit outputs a single regular code word if both input code words are regular code words, and outputs a single non-regular code word otherwise. In the two-rail code used in the two-rail test, the bit pair (0,1) corresponds to the normal bit value (0), and the bit pair (1,0) corresponds to the normal bit value (1). Only these bit pairs are considered regular code words. Any other bit pairs, such as (0,0) or (1,1), are considered non-regular code words. For details of the two-wire inspection circuit 50, please refer to Patent Document 1 (JP 2014-174648 A) and Patent Document 2 (JP 2014-197754 A), which are cited as prior art documents, as they describe the two-wire inspection circuit 50 as part of a bus verification circuit.

[0044] Due to the above configuration, for example, two-rail inspection circuit 50a has basic narrowing-down circuits connected in multiple rows and multiple stages in a tree shape so as to compare the output result of first subtractor 20, which is expressed as multiple bits, with multiple bits corresponding to ±0. Two-rail inspection circuit 50a outputs a regular code word when the output result of first subtractor 20 is equal to ±0, and outputs an irregular code word otherwise. Similarly, each of two-rail inspection circuits 50b, 50c, ... 50d outputs a regular code word when the output result of first subtractor 20 is equal to the comparison target (1, 2, ... n) of each two-rail inspection circuit 50, and outputs an irregular code word otherwise.

[0045] Furthermore, first error range determination circuit 26 includes a plurality of logic-modified two-wire test circuits 60. Each logic-modified two-wire test circuit 60 is configured by arranging basic narrowing-down circuits in multiple rows and multiple stages in a tree configuration. The basic narrowing-down circuits aggregate two input code words into one code word and output the resulting code word, and so far this is similar to two-wire test circuit 50. However, unlike the narrowing-down circuit of two-wire test circuit 50, the narrowing-down circuit of logic-modified two-wire test circuit 60 is configured such that, when aggregating two code words into one code word, if one of the two input code words is a regular code word and the other is a non-regular code word, it outputs one regular code word, and otherwise outputs one non-regular code word. In the dual-rail code used in the logic-modified dual-rail checking circuit 60, the normal bit value (0,1) corresponds to the bit pair (0,1), and the normal bit value (1,0) corresponds to the bit pair (1,0), and only these bit pairs are considered to be regular code words. Other bit pairs, such as (0,0) or (1,1), are considered to be non-regular code words.

[0046] In first error range determination circuit 26, multiple logic-altered two-wire test circuits 60 are connected in multiple rows and columns in a tree structure so that the code words output by multiple two-wire test circuits 50a-50d are ultimately combined into a single code word; FIG. 2(a) illustrates only three of these logic-altered two-wire test circuits 60. With this configuration, first error range determination circuit 26 outputs a normal code word from the final-stage logic-altered two-wire test circuit 60 when the output result of first subtractor 20 is equal to only one value from 0 to n. The output from first error range determination circuit 26 is input to abnormality determination circuit 38, which, as will be described in detail later, determines that the output result of first subtractor 20 is within the error range when the input from first error range determination circuit 26 is a normal code word.

[0047] In contrast, the second error range determination circuit 28 shown in Fig. 2(b) is configured to compare the output result from the second subtractor 22 with each of the values ​​1 to n that increase by 1. To this end, the second error range determination circuit 28 includes a two-wire test circuit 50e for comparing the output result from the second subtractor 22 with +1, a two-wire test circuit 50f for comparing it with +2, a two-wire test circuit 50g for comparing it with +3, and a two-wire test circuit 50h for comparing it with ... and +n. Note that while Fig. 2(b) shows only four two-wire test circuits 50e to 50h, the second error range determination circuit 28 includes a plurality (n in this embodiment) of two-wire test circuits 50 required for comparing it with each of the values ​​1 to n that increase by 1.

[0048] The basic configuration of the two-wire inspection circuits 50e to 50h is the same as that of the two-wire inspection circuits 50a to 50d described above. For example, the two-wire inspection circuit 50e has basic narrowing-down circuits connected in multiple rows and multiple stages in a tree configuration so as to compare the output result of the second subtractor 22, which is expressed as multiple bits, with multiple bits corresponding to +1. The two-wire inspection circuit 50e outputs a regular code word when the output result of the second subtractor 22 is equal to +1, and outputs an irregular code word otherwise. Similarly, each of the two-wire inspection circuits 50f, 50g, ... 50h outputs a regular code word when the output result of the second subtractor 22 is equal to the comparison target (2, 3, ... n) of the respective two-wire inspection circuit 50, and outputs an irregular code word otherwise.

[0049] Furthermore, like the first error range determination circuit 26, the second error range determination circuit 28 includes multiple logic-altered two-wire test circuits 60. The multiple logic-altered two-wire test circuits 60 are connected in multiple rows and columns in a tree structure so that the code words output by the multiple two-wire test circuits 50e-50h are ultimately combined into a single code word. FIG. 2(b) illustrates only three of these logic-altered two-wire test circuits 60. With this configuration, the second error range determination circuit 28 outputs a normal code word from the final-stage logic-altered two-wire test circuit 60 when the output result of the second subtractor 22 is equal to only one of the values ​​1 to n. The output from the second error range determination circuit 28 is input to the abnormality determination circuit 38. As will be described in detail later, the abnormality determination circuit 38 determines that the output result of the second subtractor 22 is within the error range when the input from the second error range determination circuit 28 is a normal code word.

[0050] In the above-described embodiment, the first error range determination circuit 26 compares the output result of the first subtractor 20 with 0 to n, and the second error range determination circuit 28 compares the output result of the second subtractor 22 with 1 to n. However, a configuration in which the first error range determination circuit 26 compares the output result of the first subtractor 20 with 1 to n, and the second error range determination circuit 28 compares the output result of the second subtractor 22 with 0 to n, may also be used. That is, it is sufficient that either the first error range determination circuit 26 or the second error range determination circuit 28 uses 0 to n as a comparison target, and the other uses 1 to n as a comparison target, so that only one of them includes 0 as a comparison target.

[0051] Returning to FIG. 1 , in this embodiment, the first digital filter 32 and the second digital filter 34 each remove noise components from the first digital data converted by the first AD converter 14 and output the data, and both have the same circuit configuration. The first digital filter 32 and the second digital filter 34 are configured to exhibit appropriate filter performance (e.g., a band-pass filter corresponding to a predetermined frequency band) depending on the application of the digital filter circuit 10 with fault detection function according to the first embodiment of the present invention. Note that the first digital filter 32 and the second digital filter 34 may also be configured to remove noise components from the second digital data converted by the second AD converter 16 and output the data. In other words, the first digital filter 32 and the second digital filter 34 may be configured to remove noise components from either the first digital data or the second digital data and output the data.

[0052] The abnormality determination circuit 38 determines whether an abnormality (failure) has occurred in each component of the digital filter circuit with fault detection function 10 described above. Specifically, the abnormality determination circuit 38 determines whether an abnormality has occurred based on the determination results of the first error range determination circuit 26, the determination results of the second error range determination circuit 28, the output result of the first digital filter 32, and the output result of the second digital filter 34. FIG. 3 illustrates a detailed configuration of the abnormality determination circuit 38. In this embodiment, the abnormality determination circuit 38 includes two two-wire inspection circuits 70 and one logic-modified two-wire inspection circuit 60 arranged in two stages in a tree structure. The basic configuration of the two-wire inspection circuit 70 is similar to that of the two-wire inspection circuit 50 described above. However, whereas the two-wire inspection circuit 50 is configured to compare one input with a fixed value, the two-wire inspection circuit 70 is configured to compare two inputs. The basic configuration of the logic-modified two-wire inspection circuit 60 is also similar to that of the logic-modified two-wire inspection circuit 60 described above.

[0053] The two-wire inspection circuit 70 shown in the upper left of Fig. 3 receives the output results from the first digital filter 32 and the second digital filter 34, and is configured to compare these output results. Therefore, the abnormality determination circuit 38 outputs a normal code word indicating normality when the output results of the first digital filter 32 and the second digital filter 34 match, and outputs an abnormal code word indicating the occurrence of an abnormality when they do not match. In other words, the abnormality determination circuit 38 determines that an abnormality has occurred in one of the digital filters when the output results of the first digital filter 32 and the second digital filter 34, which have the same performance and are input with the same digital data, are not equal.

[0054] 3 receives as input the determination results from the first error range determination circuit 26 and the second error range determination circuit 28. Therefore, the abnormality determination circuit 38 outputs a normal code word if only one of the determination results from the first error range determination circuit 26 and the second error range determination circuit 28 is a normal code word, and outputs a non-normal code word otherwise. That is, the abnormality determination circuit 38 outputs a normal code word indicating normality if only one of the determination results from the first error range determination circuit 26 and the determination result from the second error range determination circuit 28 is a normal code word indicating that the result is determined to be within the error range. In response to this, the abnormality determination circuit 38 outputs an abnormal code word indicating that an abnormality has occurred when the determination result of the first error range determination circuit 26 and the determination result of the second error range determination circuit 28 are both abnormal code words indicating that they are determined not to be within the error range, or when the determination result of the second error range determination circuit 28 are normal code words indicating that they are determined to be within the error range. Such a determination is made when an abnormality has occurred in the first AD converter 14, the second AD converter 16, the first subtractor 20, the second subtractor 22, etc.

[0055] Furthermore, the anomaly determination circuit 38 aggregates the output results of the two-wire test circuit 70 and the logic-altered two-wire test circuit 60 in the two-wire test circuit 70 on the right side of FIG. 3 . That is, the two-wire test circuit 70 on the right side of FIG. 3 outputs a regular code word indicating normality when both the output result from the two-wire test circuit 70 on the upper left side of FIG. 3 and the output result from the logic-altered two-wire test circuit 60 below it are regular code words; otherwise, it outputs an irregular code word. Therefore, the anomaly determination circuit 38 outputs an irregular code word indicating an abnormality if an abnormality is detected in either the two-wire test circuit 70 on the lower left side of FIG. 3 , which detects an abnormality in the first digital filter 32 and the second digital filter 34, or the logic-altered two-wire test circuit 60, which detects an abnormality in the first AD converter 14, the second AD converter 16, the first subtractor 20, and the second subtractor 22. The result of such a determination by the abnormality determination circuit 38 is input to the output control circuit 46.

[0056] Referring to FIG. 1, the threshold determination circuit 44 determines whether the output result of the first digital filter 32 or the output result of the second digital filter 34 exceeds a predetermined threshold. In the embodiment of FIG. 1, the output result of the first digital filter 32 is input to the threshold determination circuit 44, so the threshold determination circuit 44 determines whether the output result of the first digital filter 32 exceeds the threshold. However, the output result of the second digital filter 34 may also be input to the threshold determination circuit 44 to determine whether the output result of the second digital filter 34 exceeds the threshold. In either case, the threshold set in the threshold determination circuit 44 is set to an appropriate value depending on the application of the analog signal input to the digital filter circuit 10. For example, the threshold determination circuit 44 outputs a HIGH level when the output result of the first digital filter 32 exceeds the threshold, and outputs a LOW level when the output result of the first digital filter 32 does not exceed the threshold. The output of the threshold value determination circuit 44 is the output from the digital filter circuit 10, and the output from the threshold value determination circuit 44 is controlled by an output control circuit 46 as described below.

[0057] The output control circuit 46 controls the threshold value determination circuit 44 to operate only when the abnormality determination circuit 38 outputs a determination result that no abnormality has occurred, and in this embodiment has a configuration as shown in Fig. 4. The output control circuit 46 in Fig. 4 includes a pendulum circuit 80 and a power supply generation circuit 82, and the pendulum circuit 80 generates an alternating signal based on the determination result of the abnormality determination circuit 38. That is, the pendulum circuit 80 outputs an alternating signal when the determination result from the abnormality determination circuit 38 is a regular code word indicating that no abnormality has occurred and that the system is normal, and stops outputting the alternating signal when the determination result is an irregular code word indicating that some kind of abnormality has occurred.

[0058] When an alternating signal is input from the pendulum circuit 80, the power supply generation circuit 82 generates power for operating the threshold determination circuit 44 and supplies it to the threshold determination circuit 44. In this case, the threshold determination circuit 44 operates without any problems, and the determination result by the threshold determination circuit 44 is output as is. On the other hand, when the input of the alternating signal from the pendulum circuit 80 is stopped, the power supply generation circuit 82 stops generating power for operating the threshold determination circuit 44. In this case, since the power supply for operating the threshold determination circuit 44 is no longer supplied, the output of the determination result from the threshold determination circuit 44 is stopped and, for example, an output fixed to the LOW level is produced.

[0059] In this embodiment, the first subtractor 20, the second subtractor 22, the first error range determination circuit 26, the second error range determination circuit 28, the first digital filter 32, the second digital filter 34, and the abnormality determination circuit 38 are implemented in a single component such as an FPGA or a CPLD. Furthermore, to the extent possible, at least a portion of the threshold value determination circuit 44 and the output control circuit 46 may also be implemented in the above-mentioned component. Furthermore, the functions of these components may be realized by software using a CPU.

[0060] Next, an example of the operation of the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention shown in FIGS. 1 to 4 will be described. First, a case will be described in which all components of the digital filter circuit with fault detection function 10 are operating normally. An analog signal input to the digital filter circuit with fault detection function 10 is converted into first digital data by the first AD converter 14 and into second digital data by the second AD converter 16. Then, the first subtractor 20 subtracts the second digital data from the first digital data, and simultaneously, the second subtractor 22 subtracts the first digital data from the second digital data. At this time, if the difference between the first digital data and the second digital data is not zero, the output result of either the first subtractor 20 or the second subtractor 22 will be a positive difference, and the output result of the other will be a negative difference.

[0061] Next, the first error range determination circuit 26 determines whether the output result of the first subtractor 20 is within a preset error range, and simultaneously the second error range determination circuit 28 determines whether the output result of the second subtractor 22 is within a preset error range. At this time, if the difference between the first digital data and the second digital data is not zero, the positive difference is input to one of the first error range determination circuit 26 and the second error range determination circuit 28, and the negative difference is input to the other. Then, the error range determination circuit that received the positive difference finally outputs a normal codeword because the input value is equal to one of the values ​​1 to n that are the preset error ranges as shown in FIG. 2.

[0062] In contrast, when a negative difference is input to an error range determination circuit, because a bit inversion due to the minus occurs in the input value, the input value does not match any of the values ​​of 1 to n as the preset error range as shown in Fig. 2, and ultimately outputs a non-regular codeword. Furthermore, when the difference between the first digital data and the second digital data is zero, either first error range determination circuit 26 or second error range determination circuit 28, whichever circuit includes 0 as the comparison target (first error range determination circuit 26 in the example of Fig. 2), determines that the difference is within the error range and outputs a regular codeword, and the other outputs a non-regular codeword.

[0063] Both the first digital filter 32 and the second digital filter 34 filter the first digital data and output digital data with noise components removed from the first digital data. The anomaly determination circuit 38 determines that no anomaly has occurred anywhere and outputs a normal code word because the output result of the first digital filter 32 and the output result of the second digital filter 34 match and only one of the output results of the first error range determination circuit 26 and the second error range determination circuit 28 is a normal code word. The pendulum circuit 80 of the output control circuit 46 receives the normal code word from the anomaly determination circuit 38 and generates an alternating signal. The power generation circuit 82 receives this alternating signal and generates and supplies power to the threshold determination circuit 44. The threshold determination circuit 44, which receives power from the output control circuit 46, compares the output result of the first digital filter 32 with a preset threshold and outputs a signal indicating whether the threshold value is exceeded or not.

[0064] Next, the operation of the digital filter circuit 10 with fault detection function when an abnormality (failure) occurs in one of its components will be described using examples in which abnormalities occur in several components. For example, if an abnormality occurs in the first AD converter 14 or the second AD converter 16, both the first error range determination circuit 26, which determines the output result of the first subtractor 20, and the second error range determination circuit 28, which determines the output result of the second subtractor 22, determine that the error is not within the error range. As a result, both the first error range determination circuit 26 and the second error range determination circuit 28 output non-regular code words, which are then detected by the abnormality determination circuit 38. The abnormality determination circuit 38 then outputs a non-regular code word, causing the pendulum circuit 80 to stop generating an alternating signal and the power generation circuit 82 to stop generating power. This stops power from the output control circuit 46, and the output from the threshold value determination circuit 44 is fixed to the LOW side.

[0065] Furthermore, if an abnormality occurs in the first subtractor 20 or the second subtractor 22, both the first error range determination circuit 26 and the second error range determination circuit 28 determine that the error is not within the error range. As a result, non-regular code words are output from both of them, and the abnormality determination circuit 38, upon receiving this, detects the occurrence of an abnormality and stops the power supply from the output control circuit 46, so that the output from the threshold value determination circuit 44 is fixed to the LOW side. Furthermore, if an abnormality occurs in the first error range determination circuit 26 or the second error range determination circuit 28, non-regular code words are output from both of them, and the same operation as above occurs.

[0066] On the other hand, if an abnormality occurs in the first digital filter 32 or the second digital filter 34, the output result of the first digital filter 32 and the output result of the second digital filter 34 will no longer match, and this will be detected as an abnormality by the abnormality determination circuit 38. In this case, an irregular code word will be output from the abnormality determination circuit 38, and the power supply from the output control circuit 46 will be stopped, so the output from the threshold value determination circuit 44 will be fixed to the LOW side. On the other hand, if an abnormality occurs in the two-wire inspection circuit 70 or the like that constitutes the abnormality determination circuit 38, abnormal data will be output from the abnormality determination circuit 38, and the power supply from the output control circuit 46 will be stopped, so the output from the threshold value determination circuit 44 will be fixed to the LOW side.

[0067] The above-described embodiment of the present invention can achieve the following advantageous effects. Specifically, as shown in FIG. 1 , a digital filter circuit 10 with a fault detection function according to a first embodiment of the present invention includes a first AD converter 14, a second AD converter 16, a first subtractor 20, a second subtractor 22, a first error range determination circuit 26, a second error range determination circuit 28, a first digital filter 32, a second digital filter 34, and an abnormality determination circuit 38. The first AD converter 14 and the second AD converter 16 convert analog signals used in railway track circuit devices into digital data, and form a dual AD converter system for converting the same analog signal. Here, the signal converted from the analog signal by the first AD converter 14 is referred to as first digital data, and the signal converted from the analog signal by the second AD converter 16 is referred to as second digital data.

[0068] The first subtractor 20 subtracts the second digital data from the first digital data, while the second subtractor 22 subtracts the first digital data from the second digital data. That is, the first subtractor 20 and the second subtractor 22 extract the difference between the first digital data and the second digital data. The first error range determination circuit 26 determines whether the output result of the first subtractor 20 is within a preset error range. Similarly, the second error range determination circuit 28 determines whether the output result of the second subtractor 22 is within a preset error range. The error ranges set in both the first error range determination circuit 26 and the second error range determination circuit 28 are set in consideration of the specifications (error, carry, borrow) of the components used in the first AD converter 14 and the second AD converter 16.

[0069] The first digital filter 32 and the second digital filter 34 constitute a dual system of digital filters and operate on the same digital data. That is, both the first digital filter 32 and the second digital filter 34 remove noise components from either the first digital data or the second digital data and output the resulting digital data. The first digital filter 32 and the second digital filter 34 are configured to perform an appropriate filter function, such as a band-pass filter, depending on where the digital filter circuit 10 with fault detection function is applied.

[0070] The abnormality determination circuit 38 determines whether an abnormality has occurred based on the determination results of the first error range determination circuit 26, the determination results of the second error range determination circuit 28, the output result of the first digital filter 32, and the output result of the second digital filter 34. For example, the abnormality determination circuit 38 determines whether the difference between the first digital data and the second digital data is within the error range based on the determination results of the first error range determination circuit 26 and the second error range determination circuit 28, and determines that an abnormality has occurred if the difference is not within the error range. Such a determination is made when an abnormality has occurred in the first AD converter 14, the second AD converter 16, the first subtractor 20, the second subtractor 22, or the like. Furthermore, the abnormality determination circuit 38 determines that an abnormality has occurred if the output result of the first digital filter 32 and the output result of the second digital filter 34 are not equal (see, for example, FIG. 3). Such a determination is made when an abnormality occurs in the first digital filter 32 or the second digital filter 34.

[0071] With the above-described configuration, the digital filter circuit 10 with fault detection function according to the first embodiment of the present invention can ensure the validity of the output data of the AD converters 14 and 16 by verifying that the outputs of the two subtractors 20 and 22 are within the error range, while avoiding comparison discrepancies due to quantization errors, carry-over errors, and borrow-over errors of the AD converters 14 and 16. Furthermore, by comparing the output results of the two digital filters 32 and 34 to which the output data of such AD converters 14 and 16 are input, the validity of these digital filters 32 and 34 can also be ensured. Furthermore, even though the output data from the two AD converters 14 and 16, which do not perfectly match, are used as input data, it is possible to ultimately realize a state in which a circuit similar to a bus matching circuit, which requires perfect match, can be used.

[0072] In addition, since the abnormality determination circuit 38 can determine whether an abnormality has occurred in various components as described above, it is possible to detect failures in those components. Then, safety can be ensured by processing such as providing a normal output from the digital filter circuit 10 with a failure detection function only when the abnormality determination circuit 38 determines that no abnormality has occurred. As a result, it is possible to realize a digital filter circuit that is easy to obtain and can replace conventional LC filters, while avoiding problems specific to track circuit devices and ensuring the validity of AD converters 14, 16, etc., for analog signals used in various parts of railway track circuit devices.

[0073] Furthermore, the digital filter circuit 10 with fault detection function according to the first embodiment of the present invention performs the following judgment when the upper limit of the error range set in the first and second error range judgment circuits 26, 28 is a positive integer n. That is, as shown in FIG. 2(a), the first error range judgment circuit 26 compares the output result of the first subtractor 20 with each of the values ​​from 0 to n or 1 to n (0 to n in this embodiment) that increase by one. Then, as a result of this comparison, if the output result of the first subtractor 20 is equal to only one of the above-mentioned values, the circuit outputs a judgment result that the output result of the first subtractor 20 is within the error range. That is, if the output result of the first subtractor 20 is a positive value as described below and falls within the error range whose upper limit is a positive integer n, the output result should be equal to one of the values ​​from 0 to n or 1 to n, and this is used to make the judgment.

[0074] Similarly, as shown in FIG. 2( b), the second error range determination circuit 28 compares the output result of the second subtractor 22 with each of the values ​​0 to n or 1 to n (1 to n in this embodiment), which increase by one, and outputs a determination result that the output result of the second subtractor 22 is within the error range if the comparison result is equal to only one of the values ​​0 to n or 1 to n. Here, the first subtractor 20 and the second subtractor 22 extract the difference between the first digital data and the second digital data. If the difference is not zero, the output result of one subtractor is a positive difference and the output result of the other subtractor is a negative difference. Therefore, if the difference between the first digital data and the second digital data is not zero, the first error range determination circuit 26 and the second error range determination circuit 28 make the following determination depending on the output result of the subtractor being determined. That is, if the output result is a positive difference, it is determined to be within the error range, and if the output result is a negative difference, it is determined to be outside the error range because a bit inversion due to the negative value has occurred in the digital data.

[0075] Furthermore, the first error range determination circuit 26 and the second error range determination circuit 28 compare the output results of the first subtractor 20 or the second subtractor 22, with one comparing a value from 0 to n and the other comparing a value from 1 to n. That is, only one of the comparison targets of the first error range determination circuit 26 and the second error range determination circuit 28 includes zero. Assuming that the first and second AD converters 14, 16 and the first and second subtractors 20, 22 are operating normally, three patterns are possible: a case where the output result of the first subtractor 20 is a positive difference and the output result of the second subtractor 22 is a negative difference; a case where the output result of the first subtractor 20 is a negative difference and the output result of the second subtractor 22 is a positive difference; and a case where both the output results of the first subtractor 20 and the second subtractor 22 are zero.

[0076] In any of these three cases, with the configuration described above, only one of the first and second error range determination circuits 26, 28 determines that the output result of the target subtractor is within the error range. Therefore, the abnormality determination circuit 38 outputs a determination result that an abnormality has occurred in any case other than when only one of the determination results of the first error range determination circuit 26 and the second error range determination circuit 28 is within the error range (see, for example, FIG. 3). This enables the abnormality determination circuit 38 to more accurately detect the occurrence of an abnormality in the first and second AD converters 14, 16 or the first and second subtractors 20, 22.

[0077] 1, the digital filter circuit 10 with fault detection function according to the first embodiment of the present invention further includes a threshold value determination circuit 44 and an output control circuit 46. The threshold value determination circuit 44 receives the output result of the first digital filter 32 or the output result of the second digital filter 34 and determines whether or not this input data exceeds a preset threshold value. That is, the threshold value determination circuit 44 determines whether or not data obtained by digitizing an analog signal used in a railway track circuit device by the first or second AD converter 14, 16 and then removing noise components by the first or second digital filter 32, 34 exceeds a threshold value set depending on the application of the analog signal, etc.

[0078] The output control circuit 46 controls the output from the threshold value determination circuit 44, and controls the threshold value determination circuit 44 to operate only when the abnormality determination circuit 38 outputs a determination result indicating that no abnormality has occurred (see, for example, FIG. 4). As a result, if no abnormality is detected by the abnormality determination circuit 38, the data input to the threshold value determination circuit 44 is considered to be normal, and the determination result by the threshold value determination circuit 44 is output as is. On the other hand, if an abnormality is detected by the abnormality determination circuit 38, the data input to the threshold value determination circuit 44 is also considered to be abnormal, and the operation of the threshold value determination circuit 44 is stopped, and the output level is fixed to a LOW (lowered) side, for example. Therefore, it is possible to appropriately determine whether or not an analog signal used in a railway track circuit device exceeds a threshold value appropriate for the application, and to fix the output to a safe side when an abnormality occurs.

[0079] Furthermore, in the digital filter circuit 10 with fault detection function according to the first embodiment of the present invention, the first AD converter 14 and the second AD converter 16 are configured using the same components (AD converters) with the same specifications. The error range set in the first and second error range determination circuits 26, 28 is twice the error range defined by the specifications of the components that make up the first and second AD converters 14, 16. That is, the first and second error range determination circuits 26, 28 determine the output result of the first subtractor 20, which subtracts second digital data from first digital data, and the output result of the second subtractor 22, which subtracts the first digital data from the second digital data.

[0080] Therefore, if the first and second AD converters 14, 16 and the first and second subtractors 20, 22 are operating normally, the output results of the first and second subtractors 20, 22 will be within twice the error range defined by the specifications of the components that make up the first and second AD converters 14, 16. As a result, even if a quantization error, carry-over, or borrow error occurs in the output of the first AD converter 14 or the output of the second AD converter 16, the first error range determination circuit 26 and the second error range determination circuit 28 can properly determine that this is within the error range, thereby making it possible to avoid the anomaly determination circuit 38 making an erroneous determination that an anomaly has occurred.

[0081] Furthermore, the digital filter circuit 10 with fault detection function according to the first embodiment of the present invention is implemented in a single component, including at least the first subtractor 20, the second subtractor 22, the first error range determination circuit 26, the second error range determination circuit 28, the first digital filter 32, the second digital filter 34, and the abnormality determination circuit 38. Depending on the circumstances, the same single component may also include a threshold determination circuit 44. Here, the single component may be a hardware-based component such as an FPGA or CPLD, or a software-based component such as a CPU. This allows for the overall circuit to be miniaturized and costs to be reduced. Furthermore, while using the same component, simply by rewriting data, it is possible to easily accommodate a wide range of components used as the first and second AD converters 14 and 16, and a lineup of multiple frequencies.

[0082] Next, a digital filter circuit with fault detection function 10' according to a second embodiment of the present invention will be described with reference to Figures 5 to 7. In Figures 5 to 7, the same components as or corresponding components to those in the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention shown in Figures 1 to 4 are designated by the same reference numerals. Note that, with regard to the digital filter circuit with fault detection function 10' according to the second embodiment of the present invention, only the components that differ from the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention will be described in detail, and the description of the configuration of the components that are the same as those in the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention will be simplified or omitted.

[0083] In describing the digital filter circuit with fault detection function 10′ according to the second embodiment of the present invention, we first consider the following case of an abnormality occurring in the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention shown in FIG. 1 . That is, in the subtractor that extracts a positive difference, either the first subtractor 20 or the second subtractor 22, the output of the bits higher than the lower bits where quantization error occurs as defined by the specifications of the first AD converter 14 or the second AD converter 16 is always 0 when the subtractor is operating normally. If an abnormality occurs in such a subtractor that causes the output of the higher bits to be fixed at 0, this abnormality may remain hidden. In this state, even if an abnormality occurs in the first AD converter 14 or the second AD converter 16, the abnormality may be overlooked. To address this concern, the digital filter circuit with fault detection function 10′ according to the second embodiment of the present invention has been devised.

[0084] 5, a digital filter circuit with fault detection function 10′ according to the second embodiment of the present invention includes a first AD converter 14, a second AD converter 16, a first subtractor 20′, a second subtractor 22′, a first error range determination circuit 26, a second error range determination circuit 28, a first digital filter 32, a second digital filter 34, an abnormality determination circuit 38′, a high-order bit comparison circuit 40, a threshold value determination circuit 44, and an output control circuit 46. Of these components, the components other than the first subtractor 20′, the second subtractor 22′, the abnormality determination circuit 38′, and the high-order bit comparison circuit 40 are the same as those of the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention, and therefore, please refer to the description thereof.

[0085] The first subtractor 20' and the second subtractor 22' extract the difference between the lower-order bits of the first digital data and the lower-order bits of the second digital data, and perform subtraction by reversing the operations. That is, the first subtractor 20' subtracts the lower-order bits of the second digital data, in which a quantization error occurs in the second AD converter 16, from the lower-order bits of the first digital data, in which a quantization error occurs in the first AD converter 14. In contrast, the second subtractor 22' subtracts the lower-order bits of the first digital data, as described above, from the lower-order bits of the second digital data, as described above. The lower-order bits of the first digital data and the second digital data are one or more bits on the LSB side. Therefore, the first error range determination circuit 26 and the second error range determination circuit 28 determine whether or not the output results of the first subtractor 20' and the second subtractor 22' described above are within a preset error range (see FIG. 2). At this time, the error ranges set in the first error range determination circuit 26 and the second error range determination circuit 28 may be the same as those in the digital filter circuit with a fault detection function 10 according to the first embodiment of the present invention.

[0086] The upper bit comparison circuit 40 compares the upper bits of the first digital data excluding the above-mentioned lower bits with the upper bits of the second digital data excluding the above-mentioned lower bits. That is, these upper bits are a plurality of bits on the MSB side of the first digital data or the second digital data, including bits that cause carry-over or borrow-over in the first AD converter 14 or the second AD converter 16, excluding the lower bits that cause quantization errors in the first AD converter 14 or the second AD converter 16. Therefore, in a configuration that includes only the upper bits of the first digital data or a configuration that includes only the upper bits of the second digital data, the LSBs correspond to bits that cause carry-over or borrow-over in the first AD converter 14 or the second AD converter 16.

[0087] The upper bit comparison circuit 40 of this embodiment has a configuration as shown in FIG. 6 and includes a virtual carry unit 86, a virtual borrow unit 88, and three two-rail inspection circuits 70. The virtual carry unit 86 virtually generates a carry that may occur in the first AD converter 14 or the second AD converter 16, and the virtual borrow unit 88 virtually generates a carry that may occur in the first AD converter 14 or the second AD converter 16. In this embodiment, a carry or borrow is generated in the upper bits of the first digital data. As a result, the upper two-rail inspection circuit 70 in FIG. 6 compares the first digital data obtained by adding 1 to the upper bit (causing a carry) with the upper bit of the second digital data, and outputs the comparison result to the abnormality determination circuit 38'. This comparison assumes that the two digital data are equal when no carry occurs in the first AD converter 14 but a carry occurs in the second AD converter 16.

[0088] 6, the upper-order bits of the first digital data are directly compared with the upper-order bits of the second digital data, and the comparison result is output to the abnormality determination circuit 38'. This comparison assumes that the first and second AD converters 14 and 16 are equal when a carry-over occurs, a borrow-over occurs, or neither a carry-over nor a borrow-over occurs. Furthermore, the lower two-rail inspection circuit 70 in FIG. 6 compares the first digital data obtained by subtracting 1 from the upper-order bits (a borrow-over occurs) with the upper-order bits of the second digital data, and the comparison result is output to the abnormality determination circuit 38'. This comparison assumes that the first and second AD converters 14 and 16 are equal when a borrow-over does not occur in the first AD converter 14 and a borrow-over occurs in the second AD converter 16.

[0089] In any of the three comparisons described above, if the two comparison targets are equal, a regular code word is output, and if the two comparison targets are not equal, a non-regular code word is output. When the first AD converter 14 and the second AD converter 16 are operating normally, a regular code word indicating that the two comparison targets are equal is output in only one of the three comparisons described above. Note that the upper bit comparison circuit 40 may be configured to generate a carry or borrow in the upper bits of the second digital data instead of the upper bits of the first digital data.

[0090] 5, the abnormality determination circuit 38' determines whether an abnormality (fault) has occurred based on the determination results of the first error range determination circuit 26, the determination results of the second error range determination circuit 28, the output results of the first digital filter 32, the output results of the second digital filter 34, and the output results of the higher-order bit comparison circuit 40. Specifically, the abnormality determination circuit 38' of this embodiment has a configuration as shown in FIG. 7, in which three two-wire inspection circuits 70 and three logic-altered two-wire inspection circuits 60 are arranged in three stages in a tree shape. Of these, the determination made by the two-wire inspection circuit 70 on the upper left side of the figure using the output results of the first digital filter 32 and the second digital filter 34, and the determination made by the logic-altered two-wire inspection circuit 60 below it using the determination results of the first error range determination circuit 26 and the second error range determination circuit 28 are similar to those of the abnormality determination circuit 38 shown in FIG. 3, and therefore will not be described here.

[0091] The first-stage logic-modified two-rail test circuit 60 on the lower left side of FIG. 7 and the second-stage logic-modified two-rail test circuit 60 on the right side thereof are configured to aggregate three comparison results from the most significant bit comparison circuits 40. That is, these two logic-modified two-rail test circuits 60 determine that no abnormality has occurred if only one of the three comparison results from the most significant bit comparison circuits 40 is equal, and output a normal code word from the second-stage logic-modified two-rail test circuit 60. Furthermore, the two logic-modified two-rail test circuits 60 determine that an abnormality has occurred if only one of the three comparison results from the most significant bit comparison circuits 40 is equal, and output an abnormal code word from the second-stage logic-modified two-rail test circuit 60. Such a determination is made when an abnormality has occurred in the most significant bit output of the first AD converter 14, the most significant bit output of the second AD converter 16, or any of the components of the most significant bit comparison circuit 40. The combination of the three comparison results from the most significant bit comparison circuit 40 that are input to the two logic-modified two-rail testing circuits 60 is arbitrary.

[0092] The anomaly determination circuit 38' uses the two-wire inspection circuit 70 near the center in FIG. 7 and the two-wire inspection circuit 70 to the right of it to aggregate the determination results using the output results of the first and second digital filters 32, 34, the determination results using the determination results of the first and second error range determination circuits 26, 28, and the determination results using the three comparison results from the upper bit comparison circuit 40. As a result, if none of the determination results indicate that an abnormality has occurred, the anomaly determination circuit 38' outputs a normal code word indicating that an abnormality has occurred from the two-wire inspection circuit 70 in the final stage on the right in the figure to the output control circuit 46. On the other hand, if any of the determination results indicate that an abnormality has occurred, the anomaly determination circuit 38' outputs a non-normal code word indicating that an abnormality has occurred from the two-wire inspection circuit 70 in the final stage to the output control circuit 46.

[0093] In this embodiment, the above-described first subtractor 20′, second subtractor 22′, first error range determination circuit 26, second error range determination circuit 28, first digital filter 32, second digital filter 34, abnormality determination circuit 38′, and upper bit comparison circuit 40 are implemented in a single component, such as an FPGA or CPLD. Furthermore, to the extent possible, at least a portion of the threshold determination circuit 44 and output control circuit 46 may also be implemented in the above-described component. Furthermore, the functions of these components may be realized by software using a CPU.

[0094] Next, an example of the operation of the digital filter circuit 10′ with a fault detection function according to the second embodiment of the present invention, shown in FIGS. 5 to 7, will be described. First, a case will be described in which all components of the digital filter circuit 10′ are operating normally. An analog signal input to the digital filter circuit 10′ is converted into first digital data by the first AD converter 14 and into second digital data by the second AD converter 16. Then, the first subtractor 20′ subtracts the lower-order bits of the second digital data from the lower-order bits of the first digital data, and simultaneously, the second subtractor 22′ subtracts the lower-order bits of the first digital data from the lower-order bits of the second digital data. At this time, if the difference between the lower-order bits of the first digital data and the lower-order bits of the second digital data is not zero, the output result of one of the first subtractor 20′ and the second subtractor 22′ will be a positive difference, and the output result of the other will be a negative difference.

[0095] Next, the first error range determination circuit 26 determines whether the output result of the first subtractor 20' is within a preset error range, and simultaneously, the second error range determination circuit 28 determines whether the output result of the second subtractor 22' is within a preset error range. At this time, if the difference between the least significant bits of the first digital data and the least significant bits of the second digital data is not zero, the positive difference is input to one of the first error range determination circuit 26 and the second error range determination circuit 28, and the negative difference is input to the other. Then, the error range determination circuit that received the positive difference finally outputs a normal codeword because the input value is equal to one of the values ​​1 to n that are the preset error ranges as shown in FIG. 2.

[0096] In contrast, when a negative difference is input to an error range determination circuit, because bit inversion due to the minus occurs in the input value, the input value does not match any of the values ​​of 1 to n as the preset error range as shown in Fig. 2, and ultimately outputs a non-regular codeword. Furthermore, when the difference between the lower-order bit of the first digital data and the lower-order bit of the second digital data is zero, either first error range determination circuit 26 or second error range determination circuit 28, whichever circuit includes 0 as the comparison target (first error range determination circuit 26 in the example of Fig. 2), determines that the difference is within the error range and outputs a regular codeword, and the other outputs a non-regular codeword.

[0097] The upper bit comparison circuit 40 compares the upper bits of the first digital data with the upper bits of the second digital data using the configuration shown in Fig. 6. For only one of the three comparison results, it outputs a regular code word indicating that the two comparison targets are equal, and for the remaining two, it outputs a non-regular code word indicating that the two comparison targets are unequal. Both the first digital filter 32 and the second digital filter 34 perform filtering on the first digital data and output digital data in which noise components have been removed from the first digital data.

[0098] The anomaly determination circuit 38' determines that no anomaly has occurred anywhere and outputs a normal code word because the output result of the first digital filter 32 and the output result of the second digital filter 34 match, only one of the output results of the first error range determination circuit 26 and the second error range determination circuit 28 is a normal code word, and only one of the three comparison results from the upper bit comparison circuit 40 is a normal code word. The pendulum circuit 80 of the output control circuit 46 receives the normal code word from the anomaly determination circuit 38' and generates an alternating signal. The power supply generation circuit 82 receives this alternating signal and generates power to supply to the threshold determination circuit 44. The threshold determination circuit 44, which receives power from the output control circuit 46, compares the output result of the first digital filter 32 with a preset threshold and outputs a signal indicating whether the threshold value is exceeded or not.

[0099] Next, the operation of the digital filter circuit 10′ with fault detection function when an abnormality (failure) occurs in a component will be described using examples in which several components have abnormalities. For example, if an abnormality occurs in the lower-order bit output, which generates a quantization error, in the first AD converter 14 or the second AD converter 16, both the first error range determination circuit 26, which determines the output result of the first subtractor 20′, and the second error range determination circuit 28, which determines the output result of the second subtractor 22′, determine that the output is outside the error range. As a result, both the first error range determination circuit 26 and the second error range determination circuit 28 output non-regular code words, which are then detected by the abnormality determination circuit 38′. The abnormality determination circuit 38′ then outputs a non-regular code word, causing the pendulum circuit 80 to stop generating an alternating signal and the power generation circuit 82 to stop generating power. This stops power from the output control circuit 46, and the output from the threshold value determination circuit 44 is fixed to the LOW side.

[0100] Furthermore, if an abnormality occurs in the most significant bit output, which involves a carry or borrow, in the first AD converter 14 or the second AD converter 16, the most significant bit comparison circuit 40 outputs a non-regular code word indicating that all three comparison results are unequal. The abnormality determination circuit 38' then detects the abnormality and stops the power supply from the output control circuit 46, causing the output from the threshold value determination circuit 44 to be fixed to the LOW side. The above-described most significant bit output abnormality of the first AD converter 14 or the second AD converter 16 may include a state in which the output is fixed to the 0 side. On the other hand, if an abnormality occurs in a component of the most significant bit comparison circuit 40, the state in which only one of the three comparison results outputs a regular code word is disrupted. The abnormality determination circuit 38' then detects the abnormality and stops the power supply from the output control circuit 46, causing the output from the threshold value determination circuit 44 to be fixed to the LOW side.

[0101] The operation when an abnormality occurs in the first subtractor 20' or the second subtractor 22' is similar to the operation when an abnormality occurs in the first subtractor 20 or the second subtractor 22 in Fig. 1. The operation when an abnormality occurs in the first digital filter 32 or the second digital filter 34 is similar to the operation when an abnormality occurs in the first digital filter 32 or the second digital filter 34 in Fig. 1. Furthermore, the operation when an abnormality occurs in a component of the abnormality determination circuit 38' is similar to the operation when an abnormality occurs in a component of the abnormality determination circuit 38 in Fig. 1.

[0102] According to the embodiment of the present invention configured as described above, the following advantageous effects can be obtained. That is, as shown in FIG. 5 , a digital filter circuit with fault detection function 10′ according to the second embodiment of the present invention includes a first AD converter 14, a second AD converter 16, a first subtractor 20′, a second subtractor 22′, a first error range determination circuit 26, a second error range determination circuit 28, a first digital filter 32, a second digital filter 34, and an abnormality determination circuit 38′, similar to the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention. Of these, the first AD converter 14, the second AD converter 16, the first error range determination circuit 26, the second error range determination circuit 28, the first digital filter 32, and the second digital filter 34 perform substantially the same operations as those of the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention. In contrast, the first subtractor 20' and the second subtractor 22' perform operations on a portion of the first digital data output from the first AD converter 14 or the second digital data output from the second AD converter 16, rather than on all bits of the first digital data or all bits of the second digital data.

[0103] That is, the first subtractor 20' subtracts the lower-order bits of the second digital data in which a quantization error occurs in the second AD converter 16 from the lower-order bits of the first digital data in which a quantization error occurs in the first AD converter 14. Conversely, the second subtractor 22' subtracts the lower-order bits of the first digital data in which a quantization error occurs in the first AD converter 14 from the lower-order bits of the second digital data in which a quantization error occurs in the second AD converter 16. The lower-order bits in which a quantization error occurs in the first and second AD converters 14, 16 are one or more bits including the LSB, as understood from the specifications of the components (AD converters) used as those AD converters 14, 16. In this way, a difference between the first digital data and the second digital data in terms of the lower-order bits in which a quantization error occurs in the first and second AD converters 14, 16 is extracted.

[0104] Furthermore, the digital filter circuit 10′ with fault detection function according to the second embodiment of the present invention includes a most significant bit comparison circuit 40. This most significant bit comparison circuit 40 compares the most significant bits of the first digital data, excluding the least significant bits where quantization error occurs as described above, with the most significant bits of the second digital data, excluding the least significant bits where quantization error occurs as described above. That is, the most significant bit comparison circuit 40 compares the most significant bits of the first digital data, including the MSB, where a carry or borrow occurs, with the most significant bits of the second digital data, including the MSB, where a carry or borrow occurs. The most significant bit comparison circuit 40 then outputs the comparison result to the abnormality determination circuit 38′.

[0105] Like the anomaly determination circuit 38 of the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention, the anomaly determination circuit 38′ determines whether an anomaly has occurred based on the determination result of the first error range determination circuit 26, the determination result of the second error range determination circuit 28, the output result of the first digital filter 32, and the output result of the second digital filter 34. Furthermore, the anomaly determination circuit 38′ also determines whether an anomaly has occurred based on the output result of the upper bit comparison circuit 40. Specifically, the anomaly determination circuit 38′ determines whether an anomaly has occurred when a comparison result indicating a difference between the upper bits of the first digital data and the upper bits of the second digital data other than a difference due to carry-over or carry-down in the first and second AD converters 14 and 16 is input. Such a determination is made when an anomaly has occurred in the output of the upper bits of the first AD converter 14 or the output of the upper bits of the second AD converter 16.

[0106] In the digital filter circuit 10 with fault detection function according to the first embodiment of the present invention, the first and second subtractors 20 and 22 extract the difference between all bits of the first digital data and all bits of the second digital data, and the difference between the higher-order bits, excluding the lower-order bits where errors occur in the first and second AD converters 14 and 16, is always zero even under normal conditions. For this reason, even if an abnormality occurs in the first subtractor 20 or the second subtractor 22 such that the output of the higher-order bits is fixed to zero, this abnormality cannot be detected, and naturally, a fault in the higher-order bits of the first AD converter 14 or the second AD converter 16 cannot be detected either.

[0107] In contrast, in the digital filter circuit with fault detection function 10′ according to the second embodiment of the present invention, the first and second subtractors 20′, 22′ do not extract the difference between the most significant bits of the first digital data and the most significant bits of the second digital data. Instead, the most significant bits are compared by the most significant bit comparison circuit 40. As described above, the abnormality determination circuit 38′ detects the occurrence of an abnormality in the output of the most significant bits of the first AD converter 14 or the output of the most significant bits of the second AD converter 16. Therefore, the digital filter circuit with fault detection function 10′ according to the second embodiment of the present invention not only achieves the same effects as the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention, but also enables the abnormality determination circuit 38′ to detect an abnormality that would be overlooked by the digital filter circuit with fault detection function 10 according to the first embodiment of the present invention. This allows for the detection of a wider variety of fault patterns.

[0108] In addition, in a digital filter circuit 10' with a fault detection function according to a second embodiment of the present invention, the upper bit comparison circuit 40 has a configuration as shown in Fig. 6. Here, the following patterns are assumed regarding carries and borrows between the upper bits of the first digital data, where a carry or borrow occurs in the first AD converter 14, and the upper bits of the second digital data, where a carry or borrow occurs in the second AD converter 16. That is, there are cases where a carry occurs in either one of the upper bits of the first digital data or the upper bits of the second digital data, where a borrow occurs in either one, where a carry occurs in both, where a borrow occurs in both, and where neither a carry nor a borrow occurs in either.

[0109] Taking this into consideration, the upper bit comparison circuit 40 outputs three comparison results: a comparison result of whether or not adding 1 to one of the upper bits of the first digital data and the upper bits of the second digital data is equal to the other; a comparison result of whether or not one of the upper bits is equal to the other; and a comparison result of whether or not subtracting 1 from one of the upper bits is equal to the other. As a result, for any of the above-described patterns, only one of the three comparison results will result in an equality. Therefore, the abnormality determination circuit 38' outputs a determination result indicating an abnormality has occurred in any case other than when only one of the three comparison results from the upper bit comparison circuit 40 is equal. In this way, intentionally generating and comparing carry or borrow data in the upper bit comparison circuit 40 allows for more accurate detection of an abnormality in the output of the upper bits of the first AD converter 14 or the output of the upper bits of the second AD converter 16.

[0110] Furthermore, the digital filter circuit 10' with fault detection function according to the second embodiment of the present invention is configured by mounting at least the first subtractor 20', the second subtractor 22', the first error range determination circuit 26, the second error range determination circuit 28, the first digital filter 32, the second digital filter 34, the abnormality determination circuit 38', and the upper bit comparison circuit 40 in a single component. Furthermore, depending on the situation, the same single component may also be configured to further mount a threshold value determination circuit 44 and part of the output control circuit 46. Thus, even with the configuration that adds the upper bit comparison circuit 40, it is possible to achieve the same effects as the digital filter circuit 10 with fault detection function according to the first embodiment of the present invention in terms of circuit size, cost reduction, flexibility through data rewriting, and the like.

[0111] The digital filter circuits 10, 10' with fault detection function according to the first and second embodiments described above are not limited to the configurations shown in Figures 1 to 7, and may have various configurations depending on the situation, application, etc. For example, the error range determination circuits 26, 28, the abnormality determination circuits 38, 38', the upper bit comparison circuit 40, and the output control circuit 46 may have configurations other than those shown in Figures 2 to 4, 6, and 7, as long as they are configured to fulfill the functions required of them. Furthermore, in the digital filter circuits 10, 10' with fault detection function, the first subtractors 20, 20', the second subtractors 22, 22', the first error range determination circuit 26, the second error range determination circuit 28, the first digital filter 32, the second digital filter 34, the abnormality determination circuits 38, 38', and the upper bit comparison circuit 40 are implemented in a single component, but some of them may be implemented in separate components.

[0112] On the other hand, the fault detection method for the digital filter circuit according to the embodiment of the present invention is executed using the digital filter circuit with fault detection function according to the first and second embodiments of the present invention described above, and can thereby achieve the same advantageous effects as those of the digital filter circuit with fault detection function according to the first and second embodiments of the present invention. An example of an application of the digital filter circuits 10, 10' with fault detection function according to the first and second embodiments of the present invention and the fault detection method in the digital filter circuit according to the embodiments of the present invention is to extract an analog signal that is output from a transmitter to a rail and received by a receiver to detect the presence of a train on the track, and to determine whether or not a train is present on the track. However, the digital filter circuits 10, 10' with fault detection function and the fault detection method in the digital filter circuit according to the embodiments of the present invention are not limited to use in such receivers, and may process various analog signals used in railway track circuit devices. [Explanation of symbols]

[0113] 10, 10': digital filter circuit with fault detection function, 14: first AD converter, 16: second AD converter, 20, 20': first subtractor, 22, 22': second subtractor, 26: first error range determination circuit, 28: second error range determination circuit, 32: first digital filter, 34: second digital filter, 38, 38': abnormality determination circuit, 40: upper bit comparison circuit, 44: threshold value determination circuit, 46: output control circuit

Claims

1. A digital filter circuit used for analog signals in a railway track circuit device, a first AD converter that converts the analog signal into first digital data; a second AD converter that converts the analog signal into second digital data; a first subtractor that subtracts the second digital data from the first digital data; a second subtractor that subtracts the first digital data from the second digital data; a first error range determination circuit that determines whether or not an output result of the first subtractor is within a preset error range taking into account specifications of the first AD converter and the second AD converter; a second error range determination circuit that determines whether the output result of the second subtractor is within the error range; a first digital filter that removes noise components from either the first digital data or the second digital data and outputs the resulting digital data; a second digital filter that removes noise components from the one digital data and outputs the resultant digital data; an abnormality determination circuit that determines whether or not an abnormality has occurred based on a determination result of the first error range determination circuit, a determination result of the second error range determination circuit, an output result of the first digital filter, and an output result of the second digital filter.

2. A digital filter circuit used for analog signals in a railway track circuit device, a first AD converter that converts the analog signal into first digital data; a second AD converter that converts the analog signal into second digital data; a first subtractor configured to subtract a lower-order bit of the second digital data, in which a quantization error occurs in the second AD converter, from a lower-order bit of the first digital data, in which a quantization error occurs in the first AD converter; a second subtractor that subtracts the least significant bits of the first digital data from the least significant bits of the second digital data; a first error range determination circuit that determines whether or not an output result of the first subtractor is within a preset error range taking into account specifications of the first AD converter and the second AD converter; a second error range determination circuit that determines whether the output result of the second subtractor is within the error range; a most significant bit comparison circuit that compares most significant bits of the first digital data excluding the least significant bits with most significant bits of the second digital data excluding the least significant bits; a first digital filter that removes noise components from either the first digital data or the second digital data and outputs the resulting digital data; a second digital filter that removes noise components from the one digital data and outputs the resultant digital data; an abnormality determination circuit that determines whether or not an abnormality has occurred based on a determination result of the first error range determination circuit, a determination result of the second error range determination circuit, an output result of the higher-order bit comparison circuit, an output result of the first digital filter, and an output result of the second digital filter.

3. When the upper limit of the error range is expressed by a positive integer n, the first error range determination circuit compares the output result of the first subtractor with each of the values ​​0 to n or 1 to n that increase by one, and when the comparison result is equal to only one of the values, outputs a determination result that the output result of the first subtractor is within the error range; the second error range determination circuit compares the output result of the second subtractor with each of the values ​​0 to n or 1 to n, and when the comparison result is equal to only one of the values, outputs a determination result that the output result of the second subtractor is within the error range; one of the first error range determination circuit and the second error range determination circuit uses 0 to n as a comparison target, and the other uses 1 to n as a comparison target; 3. The digital filter circuit with a fault detection function according to claim 1, wherein the abnormality determination circuit outputs a determination result that an abnormality has occurred in a case other than a case where only one of the determination result of the first error range determination circuit and the determination result of the second error range determination circuit is within the error range.

4. the upper bit comparison circuit outputs three comparison results: a comparison result as to whether or not a result of adding 1 to one of the upper bits of the first digital data and the upper bits of the second digital data is equal to the other; a comparison result as to whether or not one of the upper bits of the first digital data and the upper bits of the second digital data is equal to the other; and a comparison result as to whether or not a result of subtracting 1 from one of the upper bits of the first digital data is equal to the other; 3. The digital filter circuit with a fault detection function according to claim 2, wherein the abnormality determination circuit outputs a determination result that an abnormality has occurred in a case other than when only one of the three comparison results from the higher-order bit comparison circuit is equal.

5. a threshold value determination circuit that receives an output result of the first digital filter or an output result of the second digital filter and determines whether the input exceeds a preset threshold value; 3. The digital filter circuit with a fault detection function according to claim 1, further comprising: an output control circuit that controls the threshold value determination circuit to operate only when the abnormality determination circuit outputs a determination result indicating that no abnormality has occurred.

6. the first AD converter and the second AD converter are configured with the same components having the same specifications; 3. The digital filter circuit with a failure detection function according to claim 1, wherein the error range is twice the error range defined by the specifications of the same component.

7. 3. The digital filter circuit with a fault detection function according to claim 1, wherein at least the first subtractor, the second subtractor, the first error range determination circuit, the second error range determination circuit, the first digital filter, the second digital filter, and the abnormality determination circuit are implemented in a single component.

8. A method for detecting a fault in a digital filter circuit used for an analog signal of a railway track circuit device, comprising: converting the analog signal into first digital data by a first AD converter and converting the analog signal into second digital data by a second AD converter; a first subtractor subtracting the second digital data from the first digital data, and a second subtractor subtracting the first digital data from the second digital data; a first error range determination circuit determines whether or not the output result of the first subtractor is within a preset error range taking into account specifications of the first AD converter and the second AD converter, and a second error range determination circuit determines whether or not the output result of the second subtractor is within the error range; a first digital filter is used to remove noise components from either the first digital data or the second digital data, and the resulting digital data is output; and a second digital filter is used to remove noise components from the one digital data, and the resulting digital data is output; a fault detection method for a digital filter circuit, characterized in that an abnormality determination circuit determines whether or not an abnormality has occurred based on the determination result of the first error range determination circuit, the determination result of the second error range determination circuit, the output result of the first digital filter, and the output result of the second digital filter.

9. A method for detecting a fault in a digital filter circuit used for an analog signal of a railway track circuit device, comprising: converting the analog signal into first digital data by a first AD converter and converting the analog signal into second digital data by a second AD converter; a first subtractor subtracts lower order bits of the second digital data, in which a quantization error occurs in the second AD converter, from lower order bits of the first digital data, in which a quantization error occurs in the first AD converter, and a second subtractor subtracts the lower order bits of the first digital data from the lower order bits of the second digital data; a first error range determination circuit determines whether or not the output result of the first subtractor is within a preset error range taking into account specifications of the first AD converter and the second AD converter, and a second error range determination circuit determines whether or not the output result of the second subtractor is within the error range; a higher-order bit comparison circuit compares the higher-order bits of the first digital data excluding the lower-order bits with the higher-order bits of the second digital data excluding the lower-order bits; a first digital filter is used to remove noise components from either the first digital data or the second digital data, and the resulting digital data is output; and a second digital filter is used to remove noise components from the one digital data, and the resulting digital data is output; a fault detection method for a digital filter circuit, characterized in that an abnormality determination circuit determines whether or not an abnormality has occurred based on the determination result of the first error range determination circuit, the determination result of the second error range determination circuit, the output result of the higher-order bit comparison circuit, the output result of the first digital filter, and the output result of the second digital filter.

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