Processor and information processing apparatus equipped with matrix scheduler

Abstract

To support a matrix scheduler, which is one of the high-efficiency implementation methods for an instruction scheduler, in heterogeneous latency execution units that have source operands with different latencies.SOLUTION: A matrix scheduler 10b is provided with a first latency switch 17a inserted on the input side of each column corresponding to producers of a matrix 13 and a second latency switch 17b inserted on the output side of each row corresponding to consumers of the matrix 13. Wakeup is performed with a latency that is the sum of the latency of the first latency switch 17a through which a wakeup signal passes and the latency of the second latency switch 17b through which the wakeup signal further passes.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present invention relates to a processor and an information processing device that include a matrix scheduler. [Background technology]

[0002] In a general-purpose processor core, the latency of the execution unit that executes instructions is 1τ (cycle) for the ALU (Arithmetic Logic Unit) that executes basic integer instructions, while the latency of the execution unit for the FMA (Fused Multiply-Add) processor that executes floating-point multiply-add instructions is as long as 5τ.

[0003] For instructions executed by execution units with long latency, i.e., instructions with long latency, an out-of-order (OoO) core can execute instructions that are not dependent on the execution unit to hide the latency and maintain throughput. However, this requires a large amount of computational resources proportional to the length of the latency. Therefore, reducing latency is still important.

[0004] In addition to circuit-related efforts, there are also architectural methods that can effectively shorten latency under certain conditions. For example, in an FMA processor that calculates rL1*rL2+rS1, the source operand C is first used in the addition after the multiplication rL1*rL2, so it can be input later than rL1 and rL2. By utilizing this, it is possible to effectively shorten the latency when performing the cumulative sum rS1+=rL1*rL2.

[0005] In this case, however, the latency from the input differs between the source operands rL1, rL2, and rS1. An execution unit with source operands of different latencies is called a "heterogeneous latency execution unit." [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Publication No. 2016 / 0179552 Summary of the Invention [Problem to be solved by the invention]

[0007] The circuitry in an OoO core that determines when instructions are issued to the execution units is called the instruction scheduler.

[0008] Conventional schedulers do not assume the existence of non-uniform latency execution units. In particular, it is not simple to support non-uniform latency execution units in a matrix scheduler, which is one of the highly efficient implementation methods.

[0009] In one aspect, the matrix scheduler aims to accommodate non-uniform latency execution units with source operands of different latencies. [Means for solving the problem]

[0010] In one aspect, the processor includes a matrix scheduler having a first latency switch inserted on the input side of each column corresponding to a producer of the matrix and a second latency switch inserted on the output side of each row corresponding to a consumer of the matrix, and performing wake-up with a latency equal to the sum of the latency of the first latency switch through which the wake-up signal passes and the latency of the second latency switch through which the wake-up signal further passes. [Effects of the Invention]

[0011] In one aspect, the matrix scheduler can accommodate non-uniform latency execution units with source operands that vary in latency. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 2 is a block diagram illustrating a schematic configuration of a processor core. [Figure 2] FIG. 10 is a block diagram illustrating a schematic configuration of a calculation circuit for the latency of the entire FMA instruction in a related example. [Figure 3] FIG. 1 is a block diagram illustrating non-uniform latency in FMA instructions of a related example. [Figure 4] 10A and 10B are diagrams illustrating configuration examples of an FMA with uniform latency and an FMA with non-uniform latency in a related example. [Figure 5] FIG. 1 illustrates a related example of a uniform latency execution unit and a non-uniform latency execution unit. [Figure 6] FIG. 10 illustrates a second example of instruction scheduling with non-uniform latency in a related example. [Figure 7] FIG. 10 is a diagram illustrating a first example of a matrix scheduler in a related example. [Figure 8] FIG. 10 is a diagram illustrating a second example of a matrix scheduler in a related example. [Figure 9] FIG. 10 is a diagram illustrating an example of a matrix scheduler in a related example having two or more types of arithmetic units with uniform latency but different latencies. [Figure 10] FIG. 1 illustrates the challenges of conventional matrix schedulers in dealing with non-uniform latency in a related example. [Figure 11] 1 is a table illustrating homogeneous and non-homogeneous latency in a related example. [Figure 12] FIG. 1 is a diagram illustrating an example of the configuration of a multi-column matrix scheduler according to an embodiment. [Figure 13] FIG. 2 is a diagram illustrating an example of the configuration of a multi-bank matrix scheduler according to an embodiment. [Figure 14] FIG. 2 is a diagram illustrating an example of the configuration of a single-column matrix scheduler according to an embodiment. [Figure 15] FIG. 10 illustrates a latency switcher. [Figure 16] FIG. 10 is a diagram illustrating a hazard in a p-WLT entry. [Figure 17] FIG. 1 illustrates a design of a state machine in a p-WLT entry. DETAILED DESCRIPTION OF THE INVENTION

[0013] [A] Related Examples FIG. 1 is a block diagram illustrating a schematic configuration of a processor core 60. As shown in FIG.

[0014] The processor core 60 is an out-of-order (OoO) core capable of executing multiple instructions simultaneously, and includes an instruction cache 61, an instruction decoder, a register renaming unit 62, an instruction scheduler 63, a uniform latency execution unit 64a, and a non-uniform latency execution unit 64b.

[0015] An instruction fetched from the instruction cache 61 is sent to an instruction decoder and a register renaming unit 62 .

[0016] The instructions that have been decoded and register renamed by the instruction decoder and register renaming unit 62 are dispatched to the instruction scheduler 63 .

[0017] The instruction scheduler 63 is, for example, a matrix scheduler, and issues instructions to the uniform latency execution unit 64a and the non-uniform latency execution unit 64b.

[0018] FIG. 2 is a block diagram illustrating a schematic circuit configuration of a floating-point FMA (Fused Multiply-Add) arithmetic unit in a related example.

[0019] The FMA calculator 600 shown in FIG. 2 performs the calculation rL1*rL2+rS1.

[0020] The FMA instruction by the FMA arithmetic unit 600 can double the floating-point operation performance (FLOPS) per instruction compared to separately executing a multiplication instruction by the multiplier 601 and an addition instruction by the adder 602. Recent general-purpose processors execute two to three (SIMD) FMA instructions per cycle.

[0021] FMA instructions have a long latency. (Total instruction latency) ≒ (multiplication latency) + (addition latency). In supercomputer processors, the latency can be as long as 9τ.

[0022] To achieve high throughput, many instructions must be executed in parallel to hide the long latency, which consumes computational resources proportional to the latency, such as the instruction scheduler and physical register entries.

[0023] Therefore, if the latency can be reduced, the same performance can be achieved with a smaller core with fewer computing resources.

[0024] FIG. 3 is a block diagram illustrating the non-uniformity of latency in a related example FMA instruction.

[0025] The cumulative sum in which the result of the preceding FMA is received as the addend rS1 (rather than the multiplicand rL1 and multiplier rL2) is frequently used in scientific and technical calculations, such as the inner product of matrices and vectors.

[0026] In the case of cumulative sums, the latency can be reduced by shortening the "wait time" of the addend rS1 as shown at A2, instead of simply connecting two floating-point FMA arithmetic units 600 shown at A1. The latency of one FMA instruction is typically reduced from (multiplication latency) + (addition latency) to (addition latency).

[0027] In this case, the latency of the source side of the FMA instruction is non-uniform, that is, the latency from rL1, rL2 is different from that from rS1. rL1, rL2 are called long-latency source operands, and rS1 is called short-latency source operand.

[0028] The following explanation will be based on two cases, long and short, but there may be three or more cases.

[0029] 4 is a diagram showing an example of the stage configuration of a uniform latency FMA and a non-uniform latency FMA in a related example, in which mul represents multiplication and add represents addition.

[0030] In the uniform latency FMA shown by symbol B1, the number of stages from the input of all source operands rL1, rL2, and rS1 is the same.

[0031] That is, the number of stages from all inputs to outputs is the same, and in the example shown by symbol B1, the latency is always constant at 5.

[0032] In the non-uniform latency FMA shown by symbol B2, the number of stages from the input of source operands rL1 and rL2 and rS1 differs.

[0033] That is, the configuration shown by symbol B2 is a computing unit with different latency for each source operand. Some source operands are input at delayed stages. In the example shown by symbol B2, the latency from rL1 and rL2 is 5, and the latency from rS1 is 2.

[0034] This means that, for example, FMA normally has a latency of 5, but in the case of cumulative sums, the latency can be reduced to 2.

[0035] In the FMA example shown in Figure 4, there are two types of latency, long and short, but generally there can be three or more types.

[0036] FIG. 5 is a diagram illustrating a processor core having execution units with uniform latency and execution units with non-uniform latency in a related example.

[0037] In the homogeneous latency core shown in C1, each execution unit has a unique latency, but a single core has multiple execution units with different latencies. For example, the ALU has a latency of 1τ as shown in C11, and the FMA has a latency of 5τ as shown in C12.

[0038] In a non-uniform latency core, shown in symbol C2, the latency varies for each operand in a single execution unit. As shown in symbol C21, the ALU has a latency of 1τ, just like a uniform latency core. As shown in symbol C22, in an FMA where the input side is delayed, rL1 and rL2 are 5τ, and rS1 is 2τ. As shown in symbol C23, for instructions with multiple output destinations, rD1 is 2τ, and rD2 is 5τ.

[0039] As an example of different latencies from the input side, as mentioned above, in the case of FMA, the addend may be delayed relative to the multiplicand and multiplier. Also, in the case of a store instruction, the store value may be delayed relative to the store address.

[0040] As an example of different latencies to the output side, in the case of a CMP instruction (compare instruction), the latency may differ between the predicate register and the flag register.

[0041] FIG. 6 is a diagram illustrating a first example of instruction scheduling with non-uniform latency in a related example.

[0042] Instruction scheduling consists of a loop of wakeup and select. Select selects the instruction that will be issued and executed from the instruction with all its source operands ready. Once a producer instruction has been selected, wakeup sets the source operands of its consumer instructions as ready after the appropriate wakeup latency. Select again selects the instruction that will be issued and executed from the instruction with all its source operands ready.

[0043] In the uniform latency instruction scheduling shown at E1, as shown at E11, the producer P C Although the execution result C is not needed until the addition stage A1, it is passed to the multiplication stage M1 at the same time as the start of the multiplication stage M1. This causes a waiting time until A1, as shown by the symbol E12.

[0044] On the other hand, in the case of instruction scheduling with non-uniform latency shown at E2, C is passed to A1 where it is actually needed, as shown at E21. C From C FMA This schedule reduces latency from 5 to 2.

[0045] However, for this purpose, C FMA In addition to C, there is a consumer C that receives C as a long latency source operand. MUL If there is, P C The two types of schedule latency, 2τ and 5τ, are shown in C. FMA / C MUL It becomes necessary to use them differently.

[0046] In traditional uniform latency instruction scheduling, producer P C Only one type, 5τ, was needed, which was determined by the latency of the execution unit itself.

[0047] FIG. 7 is a diagram showing a first example of a matrix scheduler 80 in the related example.

[0048] The matrix scheduler 80 includes a select logic 81, multiple FFs (Flip Flops) 82, a matrix 83, and multiple reverse-phase FFs 84. The loop consisting of these is one of the most timing-critical paths in the core. Note that the FFs 82 and 84 may be reverse-phase and the FFs 84 may be normal-phase.

[0049] In the matrix scheduler 80, a single stage of FF 82 is provided at the output of the select logic 81, and multiple stages of FF 82 (four stages in the example shown in FIG. 7) are further provided after this FF 82. The outputs of the multiple stages of FF 82 are input to a matrix 83, and the output from the matrix 83 is input to an inverted phase FF 84. The output from the inverted phase FF 84 is input to the select logic 81.

[0050] In the matrix scheduler 80, wakeup is performed on a matrix 83 that represents dependencies between instructions. In the matrix 83, the columns represent producers and the rows represent consumers. The IDs that identify producers and consumers can be numbers of instructions, assigned physical registers, source operands, etc., but in the example shown in Figure 7, both the columns and the rows are instructions.

[0051] When a consumer is dispatched to a row, the element in its producer's column is set to 1.

[0052] Once a producer is selected, the corresponding column is asserted after an appropriate latency, although multiple columns may be asserted simultaneously.

[0053] An instruction in a row where all columns with 1 are asserted becomes ready.

[0054] FIG. 8 is a diagram showing a second example of a matrix scheduler 80a in the related example.

[0055] 8, unlike the example shown in Fig. 7, the matrix scheduler 80a includes a converter 85 for converting an instruction number into a physical register number between the FF 82 at the subsequent stage of the select logic 81 and the FFs 82 at the multiple stages. The matrix scheduler 80a also includes an AND gate 86 between each of the reverse-phase FFs 84 and the select logic 81.

[0056] In the matrix scheduler 80a, wakeup is performed on a matrix 83 that represents dependencies between instructions via the physical registers assigned to them. In the example shown in Figure 8, the columns are physical registers assigned to the producer's destinations and the rows are the consumer's source operands.

[0057] When a consumer is dispatched to a row, the element in its producer's column is set to 1.

[0058] Once a producer is selected, the corresponding column is asserted after an appropriate latency (multiple may be asserted simultaneously).

[0059] An instruction becomes ready if all columns in the instruction's source operand row are asserted as 1.

[0060] 9 is a diagram showing an example of a matrix scheduler 80b in a related example having two or more types of arithmetic units with uniform latency but different latencies. Even with uniform latency, different producers may use different latencies. If a producer finishes using a column and then another producer reuses the same column, the columns will use different latencies (at different times).

[0061] 9, unlike the example shown in FIG. 7, a matrix scheduler 80b includes a plurality of stages of FFs 82 and a selector 88 at the subsequent stage as a latency switcher 87.

[0062] The schedule latency is achieved by adding a latency switch 87 on the input side of the queue (producer) to adjust the wakeup latency. The latency is specified by an entry in the Wakeup Latency Table 89.

[0063] Even in this case, the wake-up latency is unique to the producer, and one producer cannot use two schedule latencies at the same time.

[0064] FIG. 10 illustrates the challenges faced by conventional matrix schedulers in dealing with non-uniform latency in a related example.

[0065] With non-uniform latency, one instruction (P C ) with different wake-up latencies (W L / W S =5 / 2) for each consumer (C MUL / C FMA ) must be used appropriately.

[0066] However, column by column (P C ) latency switch 87, as shown in FIG. MUL (W L =5) and C FMA (W S =2) cannot be handled simultaneously.

[0067] FIG. 11 is a table illustrating homogeneous and non-homogeneous latency in a related example.

[0068] As shown by symbol F1, in the case of homogeneous latency, the wake-up latency is unique for each producer.

[0069] In the case of non-uniform latency, as shown by symbol F2, the wake-up latency may vary from consumer to consumer.

[0070] [B] Embodiment An embodiment will be described below with reference to the drawings. However, the embodiment described below is merely an example, and is not intended to exclude various modifications or application of techniques not explicitly stated in the embodiment. In other words, this embodiment can be implemented with various modifications within the scope of its purpose. Furthermore, each figure does not intend to include only the components shown in the figure, but may also include other functions, etc.

[0071] In the following drawings, the same reference numerals denote similar parts, and therefore the description thereof will be omitted.

[0072] [B-1] Configuration example FIG. 12 is a diagram showing an example of the configuration of a multi-column matrix scheduler 10 according to an embodiment.

[0073] The matrix scheduler 10 includes a select logic 11, a plurality of FFs (Flip Flops) 12, a matrix 13, and a plurality of reverse-phase FFs 14.

[0074] In the matrix scheduler 10, one FF 12 is provided in the subsequent stage of the select logic 11, and multiple stages (four stages in the example shown in FIG. 12) of FFs 12 are provided in the subsequent stage of this FF 12. The outputs of the multiple stages of FFs 12 are input to multiple columns of the matrix 13 (P A Two pairs from P C The output from the matrix 13 is input to the inverted phase FF 14, and the output from the inverted phase FF 14 is input to the select logic 11.

[0075] In the example shown in Figure 12, a column is prepared for each non-uniform latency. The right column of each pair receives a signal from a stage in the middle of the multiple stages of FF12 (one stage in the example shown in Figure 12). As a result, the latency can be completely specified. C From the perspective of C FMA To is the right side of the pair, C MULhas a 1 set on the left side of the pair, and can wake up with latencies 2 and 5, respectively. In this way, the latency can be fully specified, but the width of the matrix is ​​doubled (to be precise, multiplied by the number of different latency types).

[0076] FIG. 13 is a diagram showing an example of the configuration of a multi-bank matrix scheduler 10a according to an embodiment.

[0077] In the example shown in FIG. 13, unlike the example shown in FIG. 12, the matrix scheduler 10a includes multiple (two in the example shown in FIG. 13) matrices 13a, 13b and a multiple-input (two-input in the example shown in FIG. 13) AND gate 16.

[0078] The output of the FF 12 in the first stage is input to the matrix 13b, and the output of the FF 12 in the fourth stage is input to the matrix 13a. L = 5, and the input to matrix 13b is W S =2.

[0079] The outputs of the matrices 13a and 13b are input to an AND gate 16, and the output of the AND gate 16 is input to an inverted phase FF 14.

[0080] In the example shown in Figure 13, each non-uniform latency is "banked" into a separate matrix. This makes delay optimization easier. The delay increase of the more critical right-hand matrix 13b can be limited to the increased fanout on the input side and the AND gate 16 on the output side.

[0081] FIG. 14 is a diagram illustrating an example of the configuration of a single-column matrix scheduler according to an embodiment.

[0082] 14, unlike the example shown in Fig. 12, the matrix scheduler 10b includes, on the input side of the matrix 13, multiple stages (four stages in the example shown in Fig. 14) of FFs 12, decoders 18, and OR gates 15, as well as a producer wakeup latency table 21. Also, on the output side of the matrix 13, multiple stages (three stages in the example shown in Fig. 14) of FFs 12, decoders 18, and OR gates 15, as well as a consumer wakeup latency table 22. The multiple stages of FFs 12, decoders 18, and OR gates 15 on the input side function as a first latency switcher 17a, and the multiple stages of FFs 12, decoders 18, and OR gates 15 on the output side function as a second latency switcher 17b.

[0083] P C The wake-up by the input side is W S (=2). P C From C FMA When waking up to S +W0=W S On the other hand, P C From C MUL At wake-up, the output side is short of W X =W L -W S (=3), and together we get W S +W X =W L In this way, by compensating for the shortage on the input side on the output side, it is possible to wake up different consumers from the same producer with different latencies.

[0084] In this configuration, the order of the circuit area and energy consumption is O(Q 2 ) matrix itself remains the same, but O(Q 1 ) on the output side. In the multi-column matrix scheduler 10 and the multi-bank matrix scheduler 10a, the latency is O(Q 2 ) has doubled the size of the matrix itself. Q represents the instruction queue size.

[0085] On the other hand, the single-column method cannot fully specify latency and may incur a penalty for correct operation. C From C FMA The latency of W S To do this, P C Side W S (C FMA The P side must be set to W0. C From C MUL The latency to S +W X =W L To do this, C MUL The side is W X As a result, P A From C MUL The latency to L +W X And W L Even more W X However, the probability of this situation occurring is not considered high.

[0086] [B-2] How to set wake-up latency Below, we will explain how to set up the Producer Wakeup Latency Table (p-WLT) and Consumer Wakeup Latency Table (c-WLT) in the single-column method. When switching the wakeup latency, the p-WLT entry wP is set to W on the input side. L / W S The c-WLT entry wC is W0 / W X Each wP / wC is directly connected to a latency switch 17a / 17b on the input / output side.

[0087] The basic rule for setting the p / c-WLT is as follows: the p-WLT entry of the producer of the long latency source operand is W. S If there is at least one c-WLT entry, X To do so.

[0088] c-WLT guarantees correct operation, and as long as the basic rules above are followed, the execution results will be correct regardless of the p-WLT. On the other hand, p-WLT affects performance.

[0089] In the example shown in Figure 14, C MUL The producer of rL1 / rL2=A / C is P A / P C wP[P C ]=W S And, W S Since there is one such thing, wC[C MUL ]=W X On the other hand, C FMA The producer of rL1 / rL2=A / A is P A Only, wP[PA]=W L Therefore, the above rule does not hold. C ]=W S However, rS1=C is not a long latency, so it is not referenced by the rules. As a result, wC[C FMA ]=W X Instead, use W0.

[0090] In principle, the p-WLT entry of the producer of a consumer's short latency source operand is W S However, when the producer reaches the stage where it sets the p-WLT entry, the consumer may not even be in the core. Therefore, at the time of setting the p-WLT, it is not known whether the consumer will receive a short latency source operand, and the producer does not know whether it will receive a W L / W S cannot be determined.

[0091] Therefore, the following two-stage process may be performed: In the first stage, W L / W S As with branch prediction, the producer predicts L / W S In the second stage, the consumer makes the correction. Note that the second stage can be omitted, and the first stage alone will work correctly.

[0092] Producers should L / W S The system predicts the execution time and initializes the p-WLT at dispatch time.

[0093] The prediction may be performed by a predictor based on history, similar to branch prediction, etc. The predictor learns the more favorable outcome after the fact and refers to the learning result from the next time onwards.

[0094] The method of not using a predictor may be a method of always predicting in one direction (always prediction) or a method depending on the type of instruction.

[0095] In particular, in the case of always prediction, the prediction is L If it is fixed to , it is equivalent to disabling the non-uniform latency support function.

[0096] In the method based on the type of instruction, for example, in the ARM SVE instruction set, there is a method that uses the following two types of FMA instructions. The FMAD instruction executes rL1 = rL1*rL2 + rS1, so an accumulated product is assumed, and W L On the other hand, the FMLA instruction executes rS1 = rL1*rL2 + rS1, so a cumulative sum is assumed, and W S It can be predicted that:

[0097] As mentioned earlier, W0 / W X To get W, we follow the basic rule: give the producer of the long latency source operand W S If there is even one item with W X To do so.

[0098] W to the producer of the long latency source operand SThe information on whether there is a register that has a value may be obtained via one of the following tables: First, it is obtained on a register number basis via the Register Map Table (RMT) referenced in the register renaming unit 62. Second, it is obtained on an instruction number basis via the p-WLT itself.

[0099] Using RMT, the W of the producer of the long latency source operand L / W S If you get a value of 0, the RMT entry is expanded and the wP field is added. L / W S is obtained.

[0100] Producers can then determine their W based on the forecast. L / W S The consumer reads the wP field of the RMT source and writes it to the producer's W L / W S and obtains its own W0 / W X When writing and reading are performed simultaneously to the same register number, the bypass function that RMT originally has is activated.

[0101] When dispatching, W L / W S Writing to p-WLT and W0 / W X is written to the c-WLT.

[0102] [B-3] Consumer corrections FIG. 15 is a diagram illustrating a latency switch.

[0103] Reference numeral I1 denotes an exit selection type latency switcher, which switches the latency by selecting a path using a selector provided at the junction.

[0104] In the exit selection type latency switch shown in symbol I2, (1)S After the signal passes, (2) L When the power is switched to (3), the state changes to (4) and the device wakes up again.

[0105] In the exit selection type latency switch shown in symbol I3, (1) L After the signal passes through the branch, it goes to W at (2). S When this is switched to, the state becomes (3) and the signal disappears at (4).

[0106] Symbol I4 is an entrance selection type latency switch, and the situation shown by symbols I2 and I3 does not occur. An entrance selection type latency switch branches a signal to multiple paths using a decoder (inside the square frame in the figure) provided at the branching point, and the signals are merged by an OR gate. The latency switches 17a and 17b in Figure 14 are also of this entrance selection type.

[0107] In the basic rule mentioned above, if we consider the timing of writing and reading p-WLT, the wake-up signal is Wp=W S and the consumer passes through wP=W L (and consequently writing wC=W0) must not occur.

[0108] There is a hazard regarding the correction: wP=W S If there is a cycle where wP=W L The preceding command must not be modified to wP=W L If you modify it to, the subsequent command will be wP=W S It must not be re-modified.

[0109] FIG. 16 is a diagram illustrating hazards in p-WLT entries.

[0110] In the example shown by symbol J1, (1) S After the signal passes, (2) L When the mode is switched to (3), W0 is written and the device is immediately woken up.

[0111] In the example shown by symbol J2, the preceding instruction is W L After correcting it to (2), the subsequent instruction is W S (3) The preceding command is W S +W0 will wake you up.

[0112] To address such hazards, each entry in the p-WLT may be implemented as a state machine. Figure 17 illustrates the design of a state machine in a p-WLT entry.

[0113] As shown in Figure 17, W L From W S The transition to is only from the initial state, i.e., the transition to is only for the consumer at the first rL. S From W L There is no transition to

[0114] To summarize, producers can predict their own W before dispatching. L / W S At dispatch time, the p-WLT initialization initializes its own wP based on the prediction, and modifies the producer's wP. Then, the p-WLT readout reads the producer's wP, and the W0 / W calculated according to the basic rules is used. X is written to wC.

[0115] [C] Effect A first latency switch 17a is inserted on the input side of each column corresponding to a producer of the matrix. A second latency switch 17b is inserted on the output side of each row corresponding to a consumer of the matrix. The matrix scheduler 10b performs wakeup with a latency equal to the sum of the latency of the first latency switch 17a through which the wakeup signal passes and the latency of the second latency switch 17b through which the wakeup signal further passes.

[0116] A matrix scheduler, which is one of the highly efficient implementations of instruction schedulers, can support non-uniform latency execution units with source operands that have different latencies.

[0117] The matrix scheduler 10 provides wake-up for the same consumer with different latencies depending on the producer by providing multiple columns for each producer in the matrix.

[0118] The matrix scheduler 10a has a plurality of matrices, and by using a plurality of matrices depending on the producer, wake-up is performed for the same consumer with different latencies depending on the producer.

[0119] The matrix scheduler 10b performs wakeup with a latency that is the sum of the latency of the first latency switch 17a through which the wakeup signal passes and the latency of the second latency switch 17b through which the wakeup signal further passes, thereby minimizing increases in circuit area and energy consumption compared to the matrix schedulers 10 and 10a.

[0120] The matrix scheduler 10b allows the producer to set the wake-up latency without using information from the consumer. The matrix scheduler 10b sets the wake-up latency using a predictor. The matrix scheduler 10b sets the wake-up latency according to the type of producer command. The matrix scheduler 10b has a first table for setting the latency of a first latency switch and a second table for setting the latency of a second latency switch, and compensates for any latency that is insufficient with the setting value of the first table by using the setting value of the second table. To obtain the setting value of the second table, the matrix scheduler 10b saves the setting value of the first table in a register map table, thereby obtaining it simultaneously with register renaming. To obtain the setting value of the second table, the matrix scheduler 10b reads the setting value of the first table from the first table. The matrix scheduler 10b allows the consumer to modify the setting value of the first table. When a consumer modifies the setting values ​​in the first table, the matrix scheduler 10b does not modify the values ​​in a direction that increases the latency, thereby enabling the latency to be set appropriately.

[0121] [D] Other The disclosed technology is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment. The configurations and processes of the present embodiment can be selected or combined as needed.

[0122] If the performance degradation due to the extra wake-up latency is significant, it may be possible to switch to a mode that does not support non-uniform latency. For example, L may be set to

[0123] [E] Supplementary Note The following additional notes are provided regarding the above-described embodiments.

[0124] (Appendix 1) a first latency switch inserted at the input side of each column corresponding to a producer of the matrix; a second latency switch inserted at the output side of each row corresponding to a consumer of the matrix; Equipped with performing a wake-up with a latency equal to the sum of the latency of the first latency switch through which the wake-up signal passes and the latency of the second latency switch through which the wake-up signal further passes; A processor with a matrix scheduler.

[0125] (Appendix 2) By having multiple columns for each producer in the matrix, Different producers wake up the same consumer with different latencies. A processor with a matrix scheduler.

[0126] (Appendix 3) With multiple matrices, By using different matrices for different producers, Different producers wake up the same consumer with different latencies. A processor with a matrix scheduler.

[0127] (Appendix 4) The producer sets the wake-up latency without the consumer's knowledge. A processor comprising the matrix scheduler according to any one of Supplementary Notes 1 to 3.

[0128] (Appendix 5) Setting wake-up latency using a predictor; 5. A processor comprising the matrix scheduler of claim 4.

[0129] (Appendix 6) Set wakeup latency depending on producer command type, 5. A processor comprising the matrix scheduler of claim 4.

[0130] (Appendix 7) a first table for setting a latency of the first latency switch and a second table for setting a latency of the second latency switch; The latency that is insufficient with the setting value of the first table is compensated for with the setting value of the second table. 2. A processor comprising the matrix scheduler of claim 1.

[0131] (Appendix 8) to obtain the setting values ​​of the second table, the setting values ​​of the first table are stored in a register map table, thereby obtaining the setting values ​​of the second table simultaneously with register renaming; 8. A processor comprising the matrix scheduler of claim 7.

[0132] (Appendix 9) obtaining the setting values ​​of the first table by reading the first table to obtain the setting values ​​of the second table; 8. A processor comprising the matrix scheduler of claim 7.

[0133] (Appendix 10) The consumer modifies the settings in the first table; 8. A processor comprising the matrix scheduler of claim 7.

[0134] (Appendix 11) When a consumer modifies the setting value in the first table, the modification is not made in a direction that increases latency. 11. A processor comprising the matrix scheduler of claim 10.

[0135] (Appendix 12) Each path has zero or more flip-flops. a decoder is further provided at a branch point to the plurality of paths, and latency is switched by selecting one of the plurality of paths with the decoder; Equipped with a latency switch 2. A processor comprising the matrix scheduler of claim 1.

[0136] (Appendix 13) a first latency switch inserted at the input side of each column corresponding to a producer of the matrix; a second latency switch inserted at the output side of each row corresponding to a consumer of said matrix; Equipped with a matrix scheduler that adds a latency of the first latency switch through which a wake-up signal passes and a latency of the second latency switch through which the wake-up signal further passes, so that one instruction performs wake-up with two or more different latencies for each row of the matrix; An information processing device comprising:

[0137] (Appendix 14) By having multiple columns for each producer in the matrix, Different producers wake up the same consumer with different latencies. An information processing device equipped with a matrix scheduler.

[0138] (Appendix 15) With multiple matrices, By using different matrices for different producers, Different producers wake up the same consumer with different latencies. An information processing device equipped with a matrix scheduler.

[0139] (Appendix 16) The producer sets the wake-up latency without the consumer's knowledge. An information processing device comprising the matrix scheduler according to any one of Supplementary notes 13 to 15.

[0140] (Appendix 17) Setting wake-up latency using a predictor; 17. An information processing device comprising the matrix scheduler according to claim 16.

[0141] (Appendix 18) Set wakeup latency depending on producer command type, 17. An information processing device comprising the matrix scheduler according to claim 16.

[0142] (Appendix 19) a first table for setting a latency of the first latency switch and a second table for setting a latency of the second latency switch; The latency that is insufficient with the setting value of the first table is compensated for with the setting value of the second table. 14. An information processing device comprising the matrix scheduler according to claim 13.

[0143] (Appendix 20) to obtain the setting values ​​of the second table, the setting values ​​of the first table are stored in a register map table, thereby obtaining the setting values ​​of the second table simultaneously with register renaming; 20. An information processing device comprising the matrix scheduler according to claim 19.

[0144] (Appendix 21) obtaining the setting values ​​of the first table by reading the first table to obtain the setting values ​​of the second table; 20. An information processing device comprising the matrix scheduler according to claim 19.

[0145] (Appendix 22) The consumer modifies the settings in the first table; 20. An information processing device comprising the matrix scheduler according to claim 19.

[0146] (Appendix 23) When a consumer modifies the setting value in the first table, the modification is not made in a direction that increases latency. 23. An information processing device comprising the matrix scheduler according to claim 22.

[0147] (Appendix 24) Each path has zero or more flip-flops. a decoder is further provided at a branch point to the plurality of paths, and latency is switched by selecting one of the plurality of paths with the decoder; Equipped with a latency switch 14. An information processing device comprising the matrix scheduler according to claim 13. [Explanation of symbols]

[0148] 10, 10a, 10b, 10c, 10d, 80, 80a, 80b: Matrix scheduler 13, 13a, 13b: Matrix 15: OR gate 16: AND gate 17a, 17b: Latency switch 19: Selector 60: Processor cores 61: Instruction cache 62: Instruction decoder, register renaming unit 63: Instruction scheduler 64a: Uniform Latency Execution Unit 64b: Non-uniform latency execution unit 83: Matrix 85: Converter 86: AND gate 87: Latency switch 88: Selector 89: Wakeup Latency Table 600: Floating point FMA operator 601: Multiplier 602: Adder 11, 81: Select logic 12, 82:FF 13: Matrix 14, 84: Reverse phase FF 15: OR gate 16: AND gate 17a, 17b: Latency switch 18: Decoder 21 :Producer Wakeup Latency Table 22 :Consumer Wakeup Latency Table

Claims

1. a first latency switch inserted at the input side of each column corresponding to a producer of the matrix; a second latency switch inserted at the output side of each row corresponding to a consumer of the matrix; Equipped with performing a wake-up with a latency equal to the sum of the latency of the first latency switch through which the wake-up signal passes and the latency of the second latency switch through which the wake-up signal further passes; A processor with a matrix scheduler.

2. By having multiple columns for each producer in the matrix, Different producers wake up the same consumer with different latencies. A processor with a matrix scheduler.

3. With multiple matrices, By using different matrices for different producers, Different producers wake up the same consumer with different latencies. A processor with a matrix scheduler.

4. The producer sets the wake-up latency without the consumer's knowledge. A processor comprising the matrix scheduler according to any one of claims 1 to 3.

5. Setting wake-up latency using a predictor; A processor comprising the matrix scheduler of claim 4.

6. Set wakeup latency depending on producer command type, A processor comprising the matrix scheduler of claim 4.

7. a first table for setting a latency of the first latency switch and a second table for setting a latency of the second latency switch; The latency that is insufficient with the setting value of the first table is compensated for with the setting value of the second table. A processor comprising the matrix scheduler of claim 1.

8. to obtain the setting values ​​of the second table, the setting values ​​of the first table are stored in a register map table, thereby obtaining the setting values ​​of the second table simultaneously with register renaming; A processor comprising the matrix scheduler of claim 7.

9. obtaining the setting values ​​of the first table by reading the first table to obtain the setting values ​​of the second table; A processor comprising the matrix scheduler of claim 7.

10. The consumer modifies the settings in the first table; A processor comprising the matrix scheduler of claim 7.

11. When a consumer modifies the setting value in the first table, the modification is not made in a direction that increases latency. A processor comprising the matrix scheduler of claim 10.

12. each of which has a plurality of paths each consisting of zero or more flip-flops; a decoder is further provided at a branch point to the plurality of paths, and latency is switched by selecting one of the plurality of paths with the decoder; Equipped with a latency switch A processor comprising the matrix scheduler of claim 1.

13. a first latency switch inserted at the input side of each column corresponding to a producer of the matrix; a second latency switch inserted at the output side of each row corresponding to a consumer of said matrix; Equipped with a matrix scheduler that adds a latency of the first latency switch through which a wake-up signal passes and a latency of the second latency switch through which the wake-up signal further passes, so that one instruction performs wake-up with two or more different latencies for each row of the matrix; An information processing device comprising:

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