ram

Abstract

To provide RAM that can suppress interference between ports.SOLUTION: RAM (100) has a configuration in which a first bit line (bita) and a first inverted bit line (bitab) are arranged in parallel, a second bit line (bitb) and a second inverted bit line (bitbb) are arranged in parallel in a direction along which the first bit line (bita) and the first inverted bit line (bitab) are arranged in parallel, and a power supply line (VDD) or a ground line (VSS) is arranged in at least a part of the region between the first bit line (bita) and the first inverted bit line (bitab) and the region between the second bit line (bitb) and the second inverted bit line (bitbb).SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The invention disclosed herein relates to RAM (Random Access Memory), and more particularly to multi-port RAM, including dual-port RAM and two-port RAM. [Background technology]

[0002] The RAM disclosed in Patent Document 1 can read data from a first memory cell and write data to a second memory cell simultaneously or almost simultaneously. Such RAM can process data at high speed. It is known that such RAM can cause port-to-port interference (see Patent Document 1, for example). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2007 / 018043 [Summary]

[0004] In the RAM disclosed in Patent Document 1, there is an increasing demand for suppressing interference between ports.

[0005] The RAM disclosed in this specification includes a plurality of memory cells, a first bit line and a first inverted bit line connected to each of the plurality of memory cells and configured to be used for a write operation to write information to the memory cell or a read operation to read information from the memory cell based on a first clock signal, a second bit line and a second inverted bit line connected to each of the plurality of memory cells and configured to be used for the write operation or the read operation based on a second clock signal different from the first clock signal, a power supply line, and a ground line. The RAM is configured such that the first bit line and the first inverted bit line are arranged in parallel. The RAM is configured such that the second bit line and the second inverted bit line are arranged in parallel in a direction along which the first bit line and the first inverted bit line are arranged in parallel. The power supply line or the ground line is arranged in at least a part of a region between the first bit line and the first inverted bit line and a region between the second bit line and the second inverted bit line. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic block diagram of a dual port RAM according to this embodiment. [Figure 2] FIG. 2 is a circuit diagram showing the basic configuration of a memory cell. [Figure 3] FIG. 3 is a timing chart showing voltage waveforms at various points in the dual port RAM according to this embodiment. [Figure 4] FIG. 4 is a diagram showing a part of the dual port RAM according to this embodiment. [Figure 5] FIG. 5 is a diagram showing a part of the dual port RAM according to this embodiment. [Figure 6] FIG. 6 is a schematic diagram showing the wiring layout of a dual-port RAM.

[0007] [Detailed explanation] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a field effect transistor whose gate structure consists of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. An N-channel MOS field effect transistor is called an NMOS transistor, and a P-channel MOS field effect transistor is called a PMOS transistor.

[0008] <Dual-port RAM> FIG. 1 is a schematic block diagram of a dual port RAM 100 as an example of a RAM according to this embodiment.

[0009] The dual port RAM 100 includes an A port, which is a first input / output port, and a B port, which is a second input / output port, which are independent of each other.

[0010] The dual port RAM 100 includes a row decoder 11 dedicated to the A port, a column decoder 12 dedicated to the A port, and a row selector 13 dedicated to the A port.

[0011] The row decoder 11 supplies row information obtained by decoding the A port address ADRA supplied from the A port to the row selector 13 .

[0012] The column decoder 12 decodes the A port address ADRA supplied from the A port to obtain column information, which is then supplied to a column selector 33, which will be described later.

[0013] The row selector 13 selects a row of a memory array 35 (to be described later) based on row information supplied from the row decoder 11 .

[0014] The dual port RAM 100 includes a row decoder 21 dedicated to the B port, a column decoder 22 dedicated to the B port, and a row selector 23 dedicated to the B port.

[0015] The row decoder 21 supplies row information obtained by decoding the B port address ADRB supplied from the B port to the row selector 23 .

[0016] The column decoder 22 decodes the B port address ADRB supplied from the B port to obtain column information, which is then supplied to a column selector 33, which will be described later.

[0017] The row selector 23 selects a row of a memory array 35 (to be described later) based on row information supplied from the row decoder 21 .

[0018] The dual port RAM 100 includes a write driver 31, a sense amplifier 32, a column selector 33, and a precharge circuit .

[0019] When the write driver 31 receives a write command and input data IA from the A port, it writes the input data IA to a memory cell selected based on the A port address ADRA in the memory array 35 via the column selector 33 and precharge circuit 34. When the write driver 31 receives a write command and input data IB from the B port, it writes the input data IB to a memory cell selected based on the B port address ADRB in the memory array 35 via the column selector 33 and precharge circuit 34.

[0020] When the sense amplifier 32 receives a read command from the A port, it reads data from a memory cell selected based on the A port address ADRA in the memory array 35 via the column selector 33 and the precharge circuit 34, and outputs the read data as output data OA to the A port. When the sense amplifier 32 receives a read command from the B port, it reads data from a memory cell selected based on the B port address ADRB in the memory array 35 via the column selector 33 and the precharge circuit 34, and outputs the read data as output data OB to the B port.

[0021] The column selector 33 selects a column for the A port of the memory array 35 based on column information supplied from the column decoder 12. The column selector 33 also selects a column for the B port of the memory array 35 based on column information supplied from the column decoder 22.

[0022] The precharge circuit 34 precharges the columns (bit lines) of the memory array 35 in the standby state.

[0023] The memory array 35 includes a plurality of memory cells 50 arranged in a matrix. The memory cells 50 will now be described in detail.

[0024] <Memory cell 50> FIG. 2 is a circuit diagram showing the basic configuration of a memory cell 50. FIG. 2 shows the circuit configuration of the kth memory cell 50. In the following description, when it is necessary to distinguish between memory cells 50, the kth memory cell 50 will be referred to as memory cell 50[k]. The memory cell 50 shown in FIG. 2 has a 6T structure (a structure consisting of six transistors). The memory cell 50 has NMOS transistors M2 and M4, PMOS transistors M1 and M3, and NMOS transistors M5, M6, M7, and M8.

[0025] The sources of transistors M1 and M3 are both connected to the power supply line VDD (= the terminal where the power supply voltage is applied). The drains of transistors M1 and M2 and the gates of transistors M3 and M4 are both connected to the internal node Node0. The drains of transistors M3 and M4 and the gates of transistors M1 and M2 are both connected to the internal node Node1. The sources of transistors M2 and M4 are both connected to the ground line VSS (= the terminal where the ground voltage GND is applied).

[0026] The transistors M1 and M2 form an inverter whose input terminal is connected to the internal node Node1 and whose output terminal is connected to the internal node Node0. The transistors M3 and M4 form an inverter whose input terminal is connected to the internal node Node0 and whose output terminal is connected to the internal node Node1. That is, the transistors M1 to M4 function as an inverter loop connected between the internal nodes Node0 and Node1.

[0027] The transistor M5 is connected between the internal node Node0 and the second bit line bitb, and is turned on / off in response to the voltage applied to the word line WLB[k] connected to its gate. The transistor M6 is connected between the drains of the transistors M1 and M2 and the first bit line bita, and is turned on / off in response to the voltage applied to the word line WLA[k] connected to its gate.

[0028] The transistor M7 is connected between the drains of the transistors M3 and M4 and the second inverted bit line bitbb, and is turned on / off in response to the voltage applied to the word line WLB[k] connected to its gate. The transistor M8 is connected between the internal node Node1 and the first inverted bit line bitab, and is turned on / off in response to the voltage applied to the word line WLA[k] connected to its gate.

[0029] In the dual-port RAM 100, the write driver 31, sense amplifier 32, column selector 22, and precharge circuit 34 are configured to receive information and commands from both the A port and the B port and perform the corresponding operations, but this is not limiting. The dual-port RAM 100 may also include a write driver 31, sense amplifier 32, column selector 22, and precharge circuit 34 dedicated to both the A port and the B port.

[0030] The dual port RAM 100 includes a signal generator 41 dedicated to the A port and a signal generator 42 dedicated to the B port.

[0031] The signal generation unit 41 generates a one-shot pulse signal 1shotA synchronized with the clock signal CLKA supplied from port A. The signal generation unit 41 supplies the one-shot pulse signal 1shotA to the row decoder 11, the column decoder 12, the row selector 13, the write driver 31, the sense amplifier 32, the column selector 33, and the precharge circuit 34.

[0032] The signal generation unit 42 generates a one-shot pulse signal 1shotB synchronized with the clock signal CLKB supplied from the B port. The clock signals CLKA and CLKB are asynchronous. The signal generation unit 42 supplies the one-shot pulse signal 1shotB to the row decoder 21, the column decoder 22, the row selector 23, the write driver 31, the sense amplifier 32, the column selector 33, and the precharge circuit 34.

[0033] Next, the inter-port interference will be described.

[0034] FIG. 3 is a timing chart showing voltage waveforms at various parts of the dual-port RAM 100 when port A receives a write command and port B receives a read command, and writing and reading are performed on different memory cells in the same column.

[0035] 4 and 5 are diagrams showing relevant parts of a comparative dual-port RAM 100 when port A receives a write command and port B receives a read command to write and read different memory cells in the same column.

[0036] A write operation starts at a first timing T1 (see FIG. 2) when a rising edge of the clock signal CLKA appears.

[0037] Next, at a second timing T2 (see FIG. 3) when the precharge control signal PRCA switches from the LOW level to the HIGH level, the first bit line bita and the first inverted bit line bitab are brought into a floating state.

[0038] Next, at the third timing T3 (see FIG. 3), the voltage applied to the word line WLA[0] switches from a low level to a high level, and data corresponding to the input data IA is written to the memory cell 50[0] as shown in FIG. 5.

[0039] Next, at the fourth timing T4 (see FIG. 3) when the rising edge of the clock signal CLKB appears, the read operation starts.

[0040] Next, at a fifth timing T5 (see FIG. 3) when the precharge control signal PRCB switches from the LOW level to the HIGH level, the second bit line bitb and the second inverted bit line bitbb are brought into a floating state.

[0041] Next, at a sixth timing T6 (see FIG. 3), the voltage applied to the word line WLB[N-1] switches from a low level to a high level, and the second inverted bit line bitbb is discharged.

[0042] Thereafter, the write operation is completed, the precharge control signal PRCA is switched from HIGH level to LOW level, and at the seventh timing T7 (see FIG. 3), the first inverted bit line bitab is switched from LOW level to HIGH level.

[0043] Since the first inversion bit line bitab and the second inversion bit line bitbb are arranged in parallel, a parasitic capacitance is formed between the first inversion bit line bitab and the second inversion bit line bitbb (see Figures 4 and 5). Because the signal on the first inversion bit line bitab and the signal on the second inversion bit line bitbb are in opposite phase to each other, noise is carried on the second inversion bit line bitbb due to the influence of capacitive crosstalk of the parasitic capacitance.

[0044] 3, the ideal voltage of the second inversion bit line bitbb is shown by the dashed line, and the voltage of the second inversion bit line bitbb that is not sufficiently discharged due to the influence of port-to-port interference is shown by the solid line. As described above, when noise is introduced into the second inversion bit line bitbb due to capacitive crosstalk from parasitic capacitance, the discharge of the second inversion bit line bitbb is prevented, and the drop in the voltage applied to the second inversion bit line bitbb becomes insufficient.

[0045] Then, at the eighth timing T8 (see Figure 3), the sense amplifier enable signal SAE switches from LOW level to HIGH level, and the sense amplifier 32 determines the logic of the difference between the voltage applied to the second bit line bitb and the voltage applied to the second inverted bit line bitbb to determine the read data.

[0046] In Fig. 3, the correct output data OB is indicated by a dashed line, and the erroneous output data OB due to the influence of inter-port interference is indicated by a solid line. As shown in Fig. 3, if the voltage drop of the second inversion bit line bitbb is insufficient, the difference between the voltage applied to the second bit line bitb and the voltage applied to the second inversion bit line bitbb becomes small. If the difference between the voltage applied to the second bit line bitb and the voltage applied to the second inversion bit line bitbb is less than the voltage difference that allows the sense amplifier 32 to discriminate logic, the erroneous output data OB (solid line in Fig. 3) is read out.

[0047] In addition, there may be cases where data is written to memory cell 50[N-1] and read from memory cell 50[0], and in such cases, the same crosstalk occurs. Furthermore, a parasitic capacitance is also formed between the first bit line bita and the second bit line bitb. Capacitive crosstalk from this parasitic capacitance may also cause erroneous data to be read.

[0048] <Device configuration> The dual port RAM 100 according to this embodiment has a device configuration that suppresses the occurrence of parasitic capacitance, thereby reducing the effects of interference between ports. The device configuration of the dual port RAM 100 according to this embodiment will be described below with reference to the drawings.

[0049] 6 is a schematic diagram showing the wiring layout of a dual-port RAM, which shows the k-th memory cell 50[k] and the k-1-th memory cell 50[k-1] among a plurality of memory cells.

[0050] As shown in FIG. 6, in the dual-port RAM 100, the kth memory cell 50[k] and the k-1th memory cell 50[k-1] are arranged side by side in the row direction (X direction) to form a pair. In the dual-port RAM 100, a word line WLA[m] is arranged on one side of the pair of the kth memory cell 50[k] and the k-1th memory cell 50[k-1] in the column direction (Y direction). Furthermore, a word line WLB[m] is arranged on the other side of the pair of the kth memory cell 50[k] and the k-1th memory cell 50[k-1] in the column direction (Y direction). Note that m is a positive integer such that k=2m holds. Both the kth memory cells 50[k] and 50[k-1] are driven by the word lines WLA[m] and WLB[m].

[0051] 6, the dual port RAM 100 has active regions A1 to A8, metal wiring 61, gate wiring 62, and contacts 63. In Fig. 6, the metal wiring 61 is hatched in a grid pattern, and the contacts 63 are solid. The active regions A1 to A8 are enclosed in thick lines.

[0052] 6, the dual port RAM 100 has a metal wiring layer in which metal wiring 61 is arranged. The metal wiring 61 is configured to connect the transistors M1 to M8 configured in the active regions A1 to A8, respectively.

[0053] The contacts 63 are connected to any one of the first bit line bita, the first inverted bit line bitab, the second bit line bitb, the second inverted bit line bitbb, the power supply line VDD, and the ground line VSS. That is, the metal wiring 61 is connected via the contacts 63 to any one of the first bit line bita, the first inverted bit line bitab, the second bit line bitb, the second inverted bit line bitbb, the power supply line VDD, and the ground line VSS.

[0054] Signals from each bit line are input to metal wiring 61 connected to the first bit line bita, the first inverted bit line bitab, the second bit line bitb, and the second inverted bit line bitbb. A power supply voltage is applied to the metal wiring 61 connected to the power supply line VDD. The metal wiring 61 connected to the ground line VSS is grounded. The metal wiring 61 also includes those connected to word lines WLA[m] and WLB[m].

[0055] As shown in FIG. 6, the dual port RAM 100 includes a first active area A1, a second active area A2, a third active area A3, a fourth active area A4, an active area A5, an active area A6, an active area A7, and an active area A8.

[0056] The active regions A1 to A8 constitute transistors M1 to M8, respectively. The two ends of each of the active regions A1 to A8 are the source or drain of the transistors M1 to M8, and the center is the gate. The two ends of the active regions A1 to A8 overlap with metal wiring 61, and signals from each bit line, a power supply voltage, or a ground voltage are supplied via the metal wiring 61.

[0057] The gate wiring 62 is connected to either the metal wiring 61 connected to one of the bit lines or the word lines WLA[k], WLB[k]. Signals from each bit line or word line are input to the gate wiring 62. The gate wiring 62 is connected to the portions that form the gates of the transistors M1 to M8 configured in the active regions A1 to A8. The transistors M1 to M8 configured in the active regions A1 to A8 are driven by signals supplied from the gate wiring 62.

[0058] 6, the dual port RAM 100 has metal wirings 611 to 617, metal wirings 61a to 61d, and gate wirings 621 to 624. In the dual port RAM 100, a ground line VSS is arranged in the center of the row direction of the memory cells 50[k], and the ground line VSS is connected via a contact 63 to the metal wiring 611 arranged in the center.

[0059] The metal wiring 612 is a word line WLB[m] that is arranged on one side in the column direction with respect to the metal wiring 611 and extends in the row direction. The metal wiring 613 that is arranged on the other side in the column direction with respect to the metal wiring 611 and extends in the row direction is a word line WLA[m].

[0060] Furthermore, metal wiring 614 and metal wiring 615 are arranged between metal wiring 612 and metal wiring 613. Metal wiring 614 is arranged on the other side of metal wiring 612 in the column direction, and has a portion extending in the row direction and a portion extending in the column direction. Metal wiring 615 has the same shape as metal wiring 614, and is arranged in a position that is point-symmetrical with metal wiring 611 in between. Metal wiring 616 and metal wiring 617 are arranged in positions that face each other in the row direction with metal wiring 611 in between. A power supply line VDD is connected to metal wiring 616 and metal wiring 617 via contact 63.

[0061] Furthermore, metal wires 61a and 61b are arranged side by side in the row direction on the opposite side of the metal wire 611 with the metal wire 612 in between. A second bit line bitb is connected to the metal wire 61a via a contact 63. A second inverted bit line bitbb is connected to the metal wire 61b via a contact 63.

[0062] Furthermore, metal wires 61c and 61d are arranged side by side in the row direction on the opposite side of the metal wire 611 with the metal wire 613 in between. A first bit line bita is connected to the metal wire 61c via a contact 63. A second inverted bit line bitab is connected to the metal wire 61d via a contact 63.

[0063] The gate wiring 621 is connected to a metal wiring 612, which is a word line WLB[m], via a contact 63. The gate wiring 622 is connected to a metal wiring 613, which is a word line WLA[m], via a contact 63. The gate wiring 623 is disposed between the gate wiring 621 and the metal wiring 611 and extends in the row direction. The gate wiring 624 is disposed between the gate wiring 622 and the metal wiring 611 and extends in the row direction.

[0064] The active region A1 is a region extending in the column direction, with one end in the column direction joined to a metal wiring 616 via a contact 63, and the other end joined to a metal wiring 615 via a contact 63. A gate wiring 624 is arranged to intersect the middle part of the active region A1. This forms a transistor M1 in the active region A1.

[0065] The active region A2 is a region extending in the column direction, with one end in the column direction joined to a metal wiring 611 via a contact 63, and the other end joined to a metal wiring 615 via a contact 63. A gate wiring 624 is arranged to intersect the middle part of the active region A2. This forms a transistor M2 in the active region A2.

[0066] The active region A3 is a region extending in the column direction, with one end in the column direction joined to a metal wiring 614 via a contact 63, and the other end joined to a metal wiring 617 via a contact 63. A gate wiring 623 is arranged to intersect the middle part of the active region A3. This forms a transistor M3 in the active region A3.

[0067] The active region A4 is a region extending in the column direction, with one end in the column direction joined to a metal wiring 614 via a contact 63, and the other end joined to a metal wiring 611 via a contact 63. A gate wiring 623 is arranged to intersect the middle part of the active region A4. This forms a transistor M4 in the active region A4.

[0068] The active region A5 is a region extending in the column direction, with one end in the column direction joined to the metal wiring 61a via a contact 63, and the other end joined to the gate wiring 623 via the contact 63. The gate wiring 621 is arranged to intersect with the middle part of the active region A5. This forms a transistor M5 in the active region A5.

[0069] The active region A6 is a region extending in the column direction, with one end in the column direction joined to a metal wiring 615 via a contact 63, and the other end joined to a metal wiring 61c via a contact 63. A gate wiring 622 is arranged to intersect the middle part of the active region A6. This forms a transistor M6 in the active region A6.

[0070] The active region A7 is a region extending in the column direction, with one end in the column direction joined to metal wiring 61b via contact 63 and the other end joined to metal wiring 614 via contact 63. A gate wiring 621 is arranged to intersect the middle part of the active region A7. This forms a transistor M7 in the active region A7.

[0071] The active region A8 is a region extending in the column direction, with one end in the column direction joined to the gate wiring 624 via a contact 63, and the other end joined to the metal wiring 61d via a contact 63. A gate wiring 622 is arranged to intersect the middle part of the active region A8. This forms a transistor M8 in the active region A8.

[0072] As described above, by arranging the active regions A1 to A8, the first bit line bita and the first inverted bit line bitab are arranged in parallel, and the second bit line bitb and the second inverted bit line bitbb are arranged in parallel. A ground line VSS is arranged between the first inverted bit line bitab and the second bit line bitb. Similarly, a power supply line VDD is arranged between the second inverted bit line bitbb and the first bit line bita.

[0073] In the memory array 35 of the dual-port RAM 100, multiple memory cells 50 are arranged side by side in the row direction. Each bit line is a wiring that supplies signals to each memory cell 50, and is therefore formed to have a length approximately equal to the column length of the memory array 35. The power supply line VDD and ground line VSS are configured to be equal to or longer than the column length of each bit line. As a result, the ground line VSS arranged between the first inverted bit line bitab and the second bit line bitb acts as a shield, suppressing the formation of parasitic capacitance. Furthermore, the power supply line VDD arranged between the second inverted bit line bitbb and the first bit line bita acts as a shield, suppressing the formation of parasitic capacitance.

[0074] Parasitic capacitance is formed between the first bit line bita and the first inverted bit line bitab, and between the second bit line bitb and the second inverted bit line bitbb, which are arranged in parallel. However, the parasitic capacitance is formed between bit lines connected to the same port. In other words, the effect of capacitive noise due to parasitic capacitance is contained within the port. Therefore, inter-port interference due to capacitive noise is suppressed.

[0075] Furthermore, because the effects of capacitive noise caused by parasitic capacitance are contained within the same port, timing differences between different ports do not need to be taken into account in pre-shipment testing, which reduces the number of tests and makes it easier to detect defects through testing.

[0076] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0077] For example, the RAM in each of the above embodiments is a dual-port RAM having an A port, which is a first input / output port, and a B port, which is a second input / output port, which are independent of each other, but instead of the dual-port RAM, a two-port RAM having an input-only port and an output-only port may be used.

[0078] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0079] The RAM (100) of the present disclosure includes a plurality of memory cells (50), a first bit line (bita) and a first inverted bit line (bitab) connected to each of the plurality of memory cells (50) and configured to be used for a write operation to write information to the memory cells (50) or a read operation to read information from the memory cells (50) based on a first clock signal, a second bit line (bitb) and a second inverted bit line (bitbb) connected to each of the plurality of memory cells (50) and configured to be used for the write operation or the read operation based on a second clock signal different from the first clock signal, a power supply line (VDD), and a ground line (VSS). The first bit line (bita) and the first inverted bit line (bitab) are configured to run parallel to each other. The second bit line (bitb) and the second inverted bit line (bitbb) are configured to run parallel to each other in a direction along which the first bit line (bita) and the first inverted bit line (bitab) are configured to run parallel to each other. In this configuration (first configuration), a power supply line (VDD) or a ground line (VSS) is arranged in at least a part of the area between the first bit line (bita) and the first inverted bit line (bitab) and the area between the second bit line (bitb) and the second inverted bit line (bitbb).

[0080] In the RAM of the first configuration described above, a configuration (second configuration) may be adopted in which, when one of the write operation and the read operation is executed by the first bit line (bita) and the first inverted bit line (bitab), the other of the write operation and the read operation is executed by the second bit line (bitb) and the second inverted bit line (bitbb).

[0081] In the RAM of the first or second configuration, the power supply line (VDD) and ground line (VSS) may be continuous lines and may be configured (third configuration) to be longer than either the length in the parallel direction of the first bit line (bita) and the first inverted bit line (bitab) or the length in the parallel direction of the second bit line (bitb) and the second inverted bit line (bitbb).

[0082] In a RAM having any of the first to third configurations described above, the plurality of memory cells (50) may be arranged side by side along a parallel direction, and word lines (WLA, WLB) extending in a direction intersecting the parallel direction may be arranged between adjacent memory cells (50) in the parallel direction (fourth configuration).

[0083] In the RAM of the fourth configuration, two memory cells (50) may be arranged side by side in pairs in a direction intersecting the parallel running direction between the word lines (WLA, WLB) (fifth configuration). [Explanation of symbols]

[0084] 11, 21 row decoder 12, 22 column decoder 13, 23 Row Selector 31 Light Driver 32 Sense Amplifier 33 Column Selector 34 Precharge circuit 35 Memory Array 41, 42 Signal generation unit 50 memory cells M1~M8 transistors 61 Metal wiring 62 Gate wiring 63 Contacts 100 Dual Port RAM

Claims

1. a plurality of memory cells; a first bit line and a first inverted bit line connected to each of the plurality of memory cells and configured to be used for a write operation for writing information to the memory cells or a read operation for reading information from the memory cells based on a first clock signal; a second bit line and a second inverted bit line connected to each of the plurality of memory cells and configured to be used for the write operation or the read operation based on a second clock signal different from the first clock signal; The power line and a ground line; The first bit line and the first inverted bit line are arranged in parallel, the second bit line and the second inverted bit line are arranged in parallel in a direction along which the first bit line and the first inverted bit line are arranged in parallel, A RAM having a configuration in which the power supply line or the ground line is arranged in at least a part of the region between the first bit line and the first inverted bit line and the region between the second bit line and the second inverted bit line.

2. 2. The RAM of claim 1, wherein when one of the write operation and the read operation is performed by the first bit line and the first inverted bit line, the other of the write operation and the read operation is performed by the second bit line and the second inverted bit line.

3. 2. The RAM according to claim 1, wherein the power supply line and the ground line are continuous lines and have a length greater than or equal to the length of the first bit line and the first inverted bit line in the parallel running direction and the length of the second bit line and the second inverted bit line in the parallel running direction.

4. The plurality of memory cells are arranged side by side along the parallel running direction, 4. The RAM according to claim 1, wherein a word line extending in a direction intersecting the parallel arrangement direction is arranged between the memory cells adjacent to each other in the parallel arrangement direction.

5. 5. The RAM according to claim 4, wherein two of said memory cells are arranged side by side as a pair between said word lines in a direction intersecting said parallel running direction.

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