Manufacturing method of wiring board

Abstract

To suppress deterioration of a pad and a seed layer around the pad due to laser processing.SOLUTION: A manufacturing method of a wiring board includes steps of: laminating a seed layer made of a metal on an upper surface of a first insulating layer; forming a pad having, on the upper surface of the seed layer, a pad main body made of a metal and a surface treatment layer covering the upper surface and a side surface of the pad main body and including, at least in part, a metal layer made of a metal different from that of the pad main body; forming a protective film covering the surface of the pad and the upper surface of the seed layer around the pad; forming a second insulating layer covering the surface of the protective film on the upper surface of the first insulating layer; forming a cavity exposing the surface of the protective film in the second insulating layer by a laser processing; removing the protective film exposed in the cavity by etching; and removing a portion of the seed layer that does not overlap with the pad.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a wiring board. [Background technology]

[0002] In recent years, in order to realize high-density component mounting, attention has been focused on wiring boards that incorporate electronic components such as capacitors inside the board. Wiring boards that incorporate electronic components are manufactured, for example, by providing a cavity in an insulating layer of a substrate in which layers made of insulating layers and wiring layers are laminated, and filling a filling resin into the cavity in which the electronic component is placed.

[0003] The electronic component is bonded to the pads of the wiring layer exposed in the cavity using solder. Specifically, a seed layer made of a metal such as copper is formed on the surface of an insulating layer forming a wiring substrate, and a wiring layer including pads made of a metal such as copper is formed on the upper surface of the seed layer. An unnecessary portion of the seed layer is then removed so that the seed layer surrounding the pads disposed in the region where the cavity is to be formed remains. Another insulating layer is then formed on the surface of the insulating layer to cover the surfaces of the pads and the upper surface of the seed layer surrounding the pads. A cavity is then formed in the other insulating layer by laser processing, exposing the surfaces of the pads and the upper surface of the seed layer surrounding the pads. After that, the unnecessary portion not overlapping the pads is removed from the seed layer within the cavity, and the pads are bonded to the electrodes of the electronic component via solder. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2023-533233 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the process of forming a cavity by laser processing, the laser is directly irradiated onto the pad exposed in the cavity and the seed layer surrounding the pad, which poses a problem that the heat from the irradiated laser can deteriorate the pad and the seed layer surrounding the pad.

[0006] The disclosed technology has been made in consideration of the above, and aims to provide a method for manufacturing a wiring board that can suppress deterioration of the pads and the seed layer around the pads due to laser processing. [Means for solving the problem]

[0007] In one aspect, the method for manufacturing a wiring board disclosed in the present application includes the steps of: laminating a seed layer made of metal on the upper surface of a first insulating layer; forming a pad on the upper surface of the seed layer, the pad having a pad body made of metal and a surface treatment layer that covers the upper and side surfaces of the pad body and has a metal layer made of a metal different from the pad body on at least a portion of the pad; forming a protective film that covers the surface of the pad and the upper surface of the seed layer around the pad; forming a second insulating layer on the upper surface of the first insulating layer that covers the surface of the protective film; forming a cavity in the second insulating layer by laser processing to expose the surface of the protective film; removing the protective film exposed in the cavity by etching; and removing the portion of the seed layer that does not overlap with the pad. [Effects of the Invention]

[0008] According to one aspect of the method for manufacturing a wiring board disclosed in the present application, it is possible to suppress deterioration of the pads and the seed layer around the pads due to laser processing. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the configuration of a wiring board according to the first embodiment. [Figure 2] FIG. 2 is an enlarged view of the pad and its surroundings. [Figure 3]FIG. 3 is a flowchart showing a method for manufacturing a wiring board according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing a specific example of the build-up process. [Figure 5] FIG. 5 is a diagram showing a specific example of a via hole forming step. [Figure 6] FIG. 6 is a diagram showing a specific example of the seed layer forming step. [Figure 7] FIG. 7 is a diagram showing a specific example of the resist layer forming step. [Figure 8] FIG. 8 is a diagram showing a specific example of an electrolytic plating process. [Figure 9] FIG. 9 is a diagram showing a specific example of the resist layer removing step. [Figure 10] FIG. 10 is a diagram showing a specific example of the resist layer forming step. [Figure 11] FIG. 11 is a diagram showing a specific example of the surface treatment layer forming step. [Figure 12] FIG. 12 is a diagram showing a specific example of the resist layer removing step. [Figure 13] FIG. 13 is a diagram showing a specific example of the resist layer forming step. [Figure 14] FIG. 14 is a diagram showing a specific example of the protective film forming step. [Figure 15] FIG. 15 is a diagram showing a specific example of the resist layer removing step. [Figure 16] FIG. 16 is a diagram showing a specific example of the insulating layer forming step. [Figure 17] FIG. 17 is a diagram showing a specific example of the cavity forming step. [Figure 18] FIG. 18 is a diagram showing a specific example of the protective film removing step. [Figure 19] FIG. 19 is a diagram showing a specific example of an electronic component mounting process. [Figure 20] FIG. 20 is a diagram showing a specific example of the electronic component embedding step. [Figure 21] FIG. 21 is a diagram showing a specific example of a via hole forming step. [Figure 22]FIG. 22 is a diagram showing a specific example of a wiring formation step. [Figure 23] FIG. 23 is a diagram showing a specific example of the solder resist layer forming step. [Figure 24] FIG. 24 is a diagram illustrating the variation in thickness of the protective film. [Figure 25] FIG. 25 is a diagram illustrating how galvanic corrosion occurs in the surface treatment layer. [Figure 26] FIG. 26 is a flowchart showing a method for manufacturing a wiring board according to the second embodiment. [Figure 27] FIG. 27 is a diagram showing a specific example of the protective film forming step. [Figure 28] FIG. 28 is a diagram showing a specific example of the resist layer removing step. [Figure 29] FIG. 29 is a diagram showing a specific example of the insulating layer forming step. [Figure 30] FIG. 30 is a diagram showing a specific example of the cavity forming step. [Figure 31] FIG. 31 is a diagram showing a first modification of the protective film forming step. [Figure 32] FIG. 32 is a diagram showing a second modification of the protective film forming step. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of a method for manufacturing a wiring board disclosed in the present application will be described in detail with reference to the drawings. However, the disclosed technology is not limited to the embodiment.

[0011] (First embodiment) Fig. 1 is a diagram showing the configuration of a wiring board 100 according to a first embodiment. Fig. 1 shows a schematic cross section of the wiring board 100. In the following description, the solder resist layer 150 is assumed to be the uppermost layer as shown in Fig. 1, but the wiring board 100 may be manufactured and used, for example, upside down, or in any position.

[0012] The wiring board 100 has a layered structure and includes insulating layers 110, 120, and 130, a wiring layer 111, a filled resin layer 140, and a solder resist layer 150. An electronic component 170 is embedded in the insulating layer 130. Although not shown in FIG. 1, other insulating layers and wiring layers may be formed below the insulating layer 110, and a core layer made of, for example, glass may be formed.

[0013] The insulating layer 110 is formed using an insulating resin whose main component is, for example, an epoxy resin or a polyimide resin. The insulating resin may be, for example, a thermosetting insulating resin or a photosensitive insulating resin.

[0014] The wiring layer 111 is patterned into a predetermined planar shape on the upper surface of the insulating layer 110. The wiring layer 111 may be made of, for example, copper (Cu). The wiring layer 111 may be connected to a wiring layer (not shown) below the insulating layer 110 via a via wiring (not shown) that penetrates the insulating layer 110.

[0015] The insulating layer 120 is formed on the upper surface of the insulating layer 110 so as to cover the wiring layer 111. The material of the insulating layer 120 can be, for example, the same as that of the insulating layer 110. The insulating layer 120 is an example of a first insulating layer.

[0016] A via hole 120a is formed in the insulating layer 120, penetrating the insulating layer 120 and exposing the upper surface of the wiring layer 111 from the bottom. The via hole 120a may be a through-hole in the shape of an inverted truncated cone, with the diameter of the opening opening on the upper surface side of the insulating layer 120 being larger than the diameter of the opening at the bottom exposing the upper surface of the wiring layer 111. A pad 160, which is an electrode protruding from the upper surface of the insulating layer 120 and electrically connected to a lower electrode pad 171 of the electronic component 170, is formed at the position of the via hole 120a. The configuration of the pad 160 will be described later.

[0017] Although not shown in Figure 1, another wiring layer including a pad 160 is formed on the upper surface of the insulating layer 120, and this other wiring layer is connected to the wiring layer 111 on the upper surface of the insulating layer 110 by a via that penetrates the insulating layer 120.

[0018] The insulating layer 130 is formed on the upper surface of the insulating layer 120 so as to cover the other wiring layers including the pads 160. The material of the insulating layer 130 can be, for example, the same as that of the insulating layers 110 and 120. The insulating layer 130 is an example of a second insulating layer.

[0019] An electronic component 170 is embedded in the insulating layer 130. A cavity for accommodating the electronic component 170 is formed in the insulating layer 130. A pad 160 is located within the cavity.

[0020] Although not shown in Figure 1, another wiring layer is formed on the upper surface of insulating layer 130, and this other wiring layer is connected to another wiring layer on the upper surface of insulating layer 120 by a via that penetrates insulating layer 130.

[0021] The filled resin layer 140 is a layer formed continuously with the filled resin 141 that is filled into the cavities in the electronic component embedding step described below. Wiring 142 is formed on the upper surface of the filled resin layer 140, and these wiring 142 are covered with a solder resist layer 150. Vias are formed in the filled resin layer 140 as necessary after the electronic component embedding step, connecting the wiring 142 on the upper surface of the filled resin layer 140 to upper electrode pads 172 of the electronic component 170 or other wiring layers on the upper surface of the insulating layer 130. The resin that forms the filled resin layer 140 may be, for example, an insulating resin similar to that of the insulating layers 110 and 120.

[0022] The solder resist layer 150 is a layer that covers and protects the wiring arranged on the outermost surface of the wiring board 100 (here, the wiring 142 on the upper surface of the filling resin layer 140). The solder resist layer 150 is formed as a coating film by, for example, pattern printing. For example, in the portion where an external component such as a semiconductor chip is to be mounted, an opening is provided in the solder resist layer 150, and a bump 151 that connects to the wiring 142 on the upper surface of the filling resin layer 140 is formed.

[0023] Electronic component 170 is, for example, a capacitor or other such electronic component, and is embedded in insulating layer 130. That is, in a cavity formed in insulating layer 130, lower electrode pad 171 of electronic component 170 and pad 160 are joined with solder 175, and filling resin 141 is filled around electronic component 170 and pad 160. In this way, electronic component 170 is embedded in wiring substrate 100.

[0024] Next, the configuration of the pad 160 will be described in detail with reference to Fig. 2. Fig. 2 is an enlarged view of the periphery of the pad 160. The pad 160 is a protruding electrode formed so as to protrude from the upper surface of the insulating layer 120, and includes a pad main body 161 and a surface treatment layer 162.

[0025] The pad body 161 is an electrode that serves as the main body of the pad 160, and is formed by, for example, electrolytic plating of copper (Cu). Specifically, a seed layer 121 is formed on the upper surface of the insulating layer 120, and the pad body 161 is formed on the upper surface of the seed layer 121 by electrolytic plating. The seed layer 121 is made of, for example, copper (Cu) and is formed on the upper surface of the insulating layer 120 by sputtering or electroless plating.

[0026] The surface treatment layer 162 is a metal layer that covers the upper and side surfaces of the pad body 161 and is in contact with the upper surface of the seed layer 121, and is formed by, for example, electrolytic plating or electroless plating of gold (Au). Instead of a gold (Au) layer, the surface treatment layer 162 may be a multilayer film of nickel (Ni) layer / palladium (Pd) layer / gold (Au) layer or a multilayer film of palladium (Pd) layer / gold (Au) layer. That is, the surface treatment layer 162 at least partially includes a gold (Au) layer, which is a metal different from the seed layer 121 and the pad body 161. When the surface treatment layer 162 is a multilayer film of nickel (Ni) layer / palladium (Pd) layer / gold (Au) layer, the nickel (Ni) layer, the palladium (Pd) layer, and the gold (Au) layer are preferably formed by electrolytic plating or electroless plating, in this order from the side closest to the pad body 161. Furthermore, when the surface treatment layer 162 is a multilayer film of a palladium (Pd) layer / gold (Au) layer, the palladium (Pd) layer and the gold (Au) layer may be formed by electrolytic plating or electroless plating in that order from the side closer to the pad body 161.

[0027] Next, a method for manufacturing the wiring board 100 configured as described above will be specifically described with reference to Fig. 3. Fig. 3 is a flowchart showing the method for manufacturing the wiring board 100 according to the first embodiment.

[0028] First, an insulating layer 110, a wiring layer 111, and an insulating layer 120 are laminated by a build-up method (step S101). Specifically, as shown in FIG. 4, for example, the insulating layer 110 is formed on the upper surface of another wiring layer, insulating layer, or core layer (not shown), and the wiring layer 111 is formed on the upper surface of the insulating layer 110. The wiring layer 111 is formed by patterning, for example, copper (Cu) into a predetermined planar shape by, for example, a semi-additive method. Then, the insulating layer 120 is laminated on the upper surface of the insulating layer 110 so as to cover the wiring layer 111. FIG. 4 is a diagram showing a specific example of the build-up process.

[0029] After the insulating layer 110, the wiring layer 111, and the insulating layer 120 are laminated, a via hole 120a is formed in the insulating layer 120 (step S102). That is, as shown in FIG. 5, for example, a via hole 120a is formed that penetrates the insulating layer 120 and exposes the upper surface of the wiring layer 111 from the bottom. FIG. 5 is a diagram showing a specific example of the via hole formation step. The via hole 120a can be formed by, for example, a laser processing method using a CO2 laser. When the via hole 120a is formed by the laser processing method, a desmearing process is performed to remove resin residue adhering to the upper surface of the wiring layer 111 exposed from the bottom of the via hole 120a.

[0030] After the via holes 120a are formed, a seed layer 121 is formed on the upper surface of the insulating layer 120 (step S103). Specifically, as shown in Fig. 6, the seed layer 121 that continuously covers the upper surface of the insulating layer 120, the inner surface of the via holes 120a, and the upper surface of the wiring layer 111 exposed at the bottom of the via holes 120a is formed by, for example, sputtering or electroless plating. Fig. 6 is a diagram showing a specific example of the seed layer formation step. The seed layer 121 is made of, for example, copper (Cu).

[0031] After the seed layer 121 is formed, a resist layer for forming the pad body 161 is formed on the upper surface of the seed layer 121 (step S104). Specifically, as shown in Fig. 7, for example, a resist layer 210 having an opening at the portion where the pad body 161 is to be formed is formed on the seed layer 121 by patterning using exposure and development. Fig. 7 is a diagram showing a specific example of the resist layer formation step. In this case, the pad body 161 is formed at the position of the via hole 120a, and therefore the opening in the resist layer 210 is provided at the position of the via hole 120a.

[0032] After the resist layer 210 is formed, the pad body 161 is formed in the opening of the resist layer 210 by electrolytic plating using the seed layer 121 as a power supply layer (step S105). Specifically, as shown in Fig. 8, for example, copper (Cu) is deposited inside the via hole 120a and inside the opening of the resist layer 210 to form the pad body 161. Fig. 8 is a diagram showing a specific example of the electrolytic plating process.

[0033] After the pad body 161 is formed, the resist layer 210 is removed, for example, with an alkaline remover (step S106). As a result, a structure is obtained in which the pad body 161 protrudes upward from the seed layer 121 on the upper surface of the insulating layer 120, as shown in Fig. 9. Fig. 9 is a diagram showing a specific example of the resist layer removal step.

[0034] After removing the resist layer 210, a resist layer for forming the surface processing layer 162 is formed on the upper surface of the seed layer 121 (step S107). Specifically, as shown in Fig. 10, for example, a resist layer 220 having openings in areas where the surface processing layer 162 will be formed is formed on the seed layer 121 by patterning using exposure and development. Fig. 10 is a diagram showing a specific example of the resist layer forming step.

[0035] After the resist layer 220 is formed, a surface treatment layer 162 is formed in the openings of the resist layer 220 by electrolytic plating using the seed layer 121 as a power supply layer (step S108). Specifically, as shown in FIG. 11, the surface treatment layer 162 is formed so as to cover the upper and side surfaces of the pad body 161 and reach the upper surface of the seed layer 121. FIG. 11 is a diagram showing a specific example of the surface treatment layer formation step. As the surface treatment layer 162, a gold (Au) layer is laminated on the upper and side surfaces of the pad body 161. As the surface treatment layer 162, instead of a gold (Au) layer, a multilayer film of a nickel (Ni) layer / palladium (Pd) layer / gold (Au) layer or a multilayer film of a palladium (Pd) layer / gold (Au) layer may be formed. When a multilayer film is formed, the outermost layer of the surface treatment layer 162 is a gold (Au) layer.

[0036] After the surface treatment layer 162 is formed, the resist layer 220 is removed, for example, with an alkaline stripping liquid (step S109). As a result, a pad 160 having a pad body 161 and the surface treatment layer 162 is formed on the upper surface of the seed layer 121, as shown in FIG. 12, for example. At this stage, the seed layer 121 remains on the entire surface, and the pad 160 is short-circuited with other pads. FIG. 12 is a diagram showing a specific example of the resist layer removal step.

[0037] After removing the resist layer 220, a resist layer is formed on the upper surface of the seed layer 121 to form a protective film that protects the pads 160 and the seed layer 121 around the pads 160 (step S110). Specifically, as shown in Fig. 13, for example, a resist layer 230 having openings in areas where the protective film is to be formed is formed on the seed layer 121 by patterning using exposure and development. Fig. 13 is a diagram showing a specific example of the resist layer formation step.

[0038] After the resist layer 230 is formed, a protective film is formed in the openings of the resist layer 230 by electrolytic plating using the seed layer 121 as a power supply layer (step S111). Specifically, as shown in FIG. 14, a protective film 310 is formed to cover the surface of the pad 160 and the upper surface of the seed layer 121 around the pad 160. FIG. 14 illustrates a specific example of the protective film formation process. The thickness of the protective film 310 can be, for example, approximately 8 μm. The protective film 310 is made of a metal different from the surface treatment layer 162, i.e., the gold (Au) layer. In this example, the protective film 310 is made of copper (Cu), the same material as the seed layer 121 and the pad body 161, and a single-layer protective film 310 made of copper (Cu) is formed. The protective film 310 is formed by copper plating using a copper plating solution containing a brightener (accelerator), for example.

[0039] After the protective film 310 is formed, the resist layer 230 is removed, for example, with an alkaline stripping liquid (step S112). Furthermore, the seed layer 121 in the portion that was in contact with the resist layer 230 is removed by flash etching, and the insulating layer 120 is exposed in the region other than the portion that is in contact with the protective film 310, as shown in Fig. 15. Fig. 15 is a diagram showing a specific example of the resist layer removal step.

[0040] After the resist layer 230 is removed, an insulating layer 130 is formed on the upper surface of the insulating layer 120 to cover the surface of the protective film 310 (step S113), as shown in FIG. 16, for example. FIG. 16 is a diagram illustrating a specific example of the insulating layer formation step. Although not illustrated in FIG. 16, after the insulating layer 130 is formed, another wiring layer is formed on the upper surface of the insulating layer 130, and this other wiring layer is connected to another wiring layer on the upper surface of the insulating layer 120 by vias that penetrate the insulating layer 130. At this time, no other wiring layer or vias are arranged in the region of the insulating layer 130 where the electronic component 170 is to be accommodated. In the example of FIG. 16, the electronic component 170 is to be accommodated in the region of the insulating layer 130 located above the protective film 310, so no other wiring layer or vias are arranged in this region.

[0041] Then, a cavity is formed in the region of the insulating layer 130 where the electronic component 170 is to be accommodated (step S114). Specifically, as shown in FIG. 17, the insulating layer 130 is cut out toward the protective film 310 to form the cavity 180. FIG. 17 is a diagram showing a specific example of the cavity formation step. The cavity formation step can be achieved by laser processing using, for example, a CO2 laser. By cutting out the insulating layer 130 down to the surface of the protective film 310, the surface of the protective film 310 is exposed at the bottom of the cavity 180.

[0042] In the cavity formation process, laser processing using a CO2 laser is performed in a state in which the surface of the pad 160 and the upper surface of the seed layer 121 around the pad 160 are covered with the protective film 310. Therefore, the CO2 laser is not directly irradiated onto the pad 160 and the seed layer 121 around the pad 160. In other words, the protective film 310 can shield the pad 160 and the seed layer 121 around the pad 160 from heat that is received by the CO2 laser irradiation. As a result, deterioration of the pad 160 and the seed layer 121 around the pad 160 due to laser processing can be suppressed.

[0043] When the surface of the protective film 310 is exposed on the bottom surface of the cavity 180, the exposed protective film 310 is removed (step S115). That is, the protective film 310 exposed on the bottom surface of the cavity 180 is removed by wet etching using a copper (Cu) etchant. At this time, the pad 160 and the seed layer 121 around the pad 160 are exposed, and the copper (Cu) etchant comes into contact with and dissolves the seed layer 121 in the portion that does not overlap with the pad 160.

[0044] That is, for example, as shown in Fig. 18, the protective film 310 is removed from the bottom surface of the cavity 180, and the seed layer 121 is removed from the portion that does not overlap with the pad 160. This eliminates short circuits between the pad 160 and other pads, and the pad 160 having the pad body 161 and the surface treatment layer 162 is completed. Fig. 18 is a diagram showing a specific example of the protective film removal step.

[0045] In the protective film removal process, the seed layer 121 in the portion that does not overlap the pad 160 is removed together with the protective film 310, thereby improving the manufacturing efficiency of the wiring substrate 100 compared to when a separate process is performed to remove unnecessary portions of the seed layer 121.

[0046] After the protective film 310 is removed, the electronic component 170 is mounted on the pad 160 in the cavity 180 (step S116). Specifically, for example, as shown in Fig. 19, the electronic component 170 is accommodated in the cavity 180, and the lower electrode pad 171 of the electronic component 170 and the pad 160 are joined with solder 175. Fig. 19 is a diagram showing a specific example of the electronic component mounting step.

[0047] Once electronic component 170 is mounted on pad 160, filling resin 141 is filled into cavity 180, and electronic component 170 is embedded together with pad 160 (step S117). That is, as shown in FIG. 20 for example, filling resin 141 is filled into cavity 180, and a filling resin layer 140 extending above electronic component 170 is formed. As a result, electronic component 170 is embedded together with pad 160 in insulating layer 130, and electronic component 170 is built into wiring substrate 100. FIG. 20 is a diagram showing a specific example of the electronic component embedding step. Once filling resin 141 is filled into cavity 180 and filling resin layer 140 is formed, filling resin 141 is thermally cured.

[0048] Then, a via hole is formed in the filled resin layer 140 (step S118). Specifically, as shown in FIG. 21, for example, a via hole 140a is formed that penetrates the filled resin layer 140 and exposes the upper electrode pad 172 of the electronic component 170. FIG. 21 is a diagram showing a specific example of the via hole formation step. The via hole 140a can be formed by, for example, laser processing. Although not shown in FIG. 21, other via holes that penetrate the filled resin layer 140 and expose other wiring layers on the upper surface of the insulating layer 130 may also be formed by laser processing together with the via hole 140a.

[0049] At the positions where the via hole 140a and other via holes are formed, wiring 142 is formed on the upper surface of the filled resin layer 140 (step S119). That is, as shown in FIG. 22, for example, wiring 142 is formed at the positions of the via hole 140a and other via holes. FIG. 22 is a diagram showing a specific example of the wiring formation step. The wiring 142 is formed, for example, by SAP (Semi-Additive Process). In SAP, a via penetrating the filled resin layer 140 is formed together with the wiring 142, and the wiring 142 on the upper surface of the filled resin layer 140 is connected to the upper electrode pad 172 of the electronic component 170 or another wiring layer on the upper surface of the insulating layer 130.

[0050] The wiring 142 on the upper surface of the filling resin layer 140 is covered by forming a solder resist layer 150 (step S120). The solder resist layer 150 is formed by coating an insulating resin pattern by printing or the like. Then, openings 150a are formed in the solder resist layer 150 at positions corresponding to the wiring 142 on the upper surface of the filling resin layer 140, as shown in FIG. 23, for example. FIG. 23 is a diagram showing a specific example of the solder resist layer formation step. The openings 150a are formed using, for example, photolithography or a laser. External components, such as semiconductor chips, are placed at the positions of these openings 150a.

[0051] Therefore, bumps 151 are formed in the openings 150a by plating or solder balls (step S121). The bumps 151 serve as contact points between the wiring 142 on the top surface of the filling resin layer 140 and external components.

[0052] As described above, in the method for manufacturing the wiring board 100 according to the first embodiment, a protective film 310 is formed to cover the surfaces of the pads 160 formed on the upper surface of the seed layer 121 and the seed layer 121 around the pads 160. Then, with the surfaces of the pads 160 and the upper surface of the seed layer 121 around the pads 160 covered by the protective film 310, a cavity 180 exposing the protective film 310 is formed by laser processing using a CO2 laser. This allows the protective film 310 to shield the pads 160 and the seed layer 121 around the pads 160 from heat received by CO2 laser irradiation. As a result, deterioration of the pads 160 and the seed layer 121 around the pads 160 due to laser processing can be suppressed.

[0053] (Second embodiment) In the above-described first embodiment, a single-layer protective film 310 made of copper (Cu) is formed by copper plating on the surface of the pad 160 and on the upper surface of the seed layer 121 around the pad 160. When the single-layer protective film 310 is formed by copper plating, there is a possibility that the thickness of the protective film 310 will vary depending on the electrolytic copper plating conditions applied to the copper plating, etc.

[0054] The mechanism by which the thickness of the protective film 310 varies will be described with reference to FIG. 24. FIG. 24 is a diagram illustrating the variation in the thickness of the protective film 310. The single-layer protective film 310 made of copper (Cu) is formed by copper plating using, for example, a copper plating solution containing a brightener (accelerator). That is, by performing copper plating at a predetermined current density for a predetermined time using a copper plating solution containing a brightener, copper is deposited in the openings of the resist layer 230, and the protective film 310 is formed on the surface of the pad 160 and on the upper surface of the seed layer 121 around the pad 160. As shown in FIG. 24, the thickness of the protective film 310 is relatively thin on the upper surface of the pad 160 and relatively thick on the upper surface of the seed layer 121 around the pad 160. The reason why the thickness of the protective film 310 varies depending on the position is as follows.

[0055] That is, the flow of the copper plating solution containing brightener is more likely to stagnate on the side surfaces of the pad 160 and on the upper surface of the seed layer 121 around the pad 160 than on the upper surface of the pad 160. Therefore, the brightener, which promotes plating deposition, is less likely to be adsorbed to the side surfaces of the pad 160 and on the upper surface of the seed layer 121 around the pad 160 than on the upper surface of the pad 160. As a result, the amount of plating deposition is greater on the side surfaces of the pad 160 and on the upper surface of the seed layer 121 around the pad 160 than on the upper surface of the pad 160, and a thicker protective film 310 is formed on the side surfaces of the pad 160 and on the upper surface of the seed layer 121 around the pad 160 than on the upper surface of the pad 160.

[0056] If the protective film 310 is formed with thickness variations depending on the position, there is a possibility that galvanic corrosion will occur in the surface treatment layer 162 of the pad 160 when the protective film 310 is removed.

[0057] The mechanism by which galvanic corrosion occurs in the surface treatment layer 162 will be described with reference to FIG. 25 . FIG. 25 is a diagram illustrating the occurrence of galvanic corrosion in the surface treatment layer 162. The protective film 310 is removed by wet etching using a copper (Cu) etchant. Here, the thickness of the protective film 310 is thinner on the top surface of the pad 160 than on the side surface of the pad 160 and the top surface of the seed layer 121 around the pad 160. Therefore, by wet etching, the protective film 310 is removed more quickly on the top surface of the pad 160 than on the side surface of the pad 160 and the top surface of the seed layer 121 around the pad 160, and the top surface of the pad 160 (surface treatment layer 162) is exposed. In contrast, the protective film 310 remains on the side surface of the pad 160 and the top surface of the seed layer 121 around the pad 160. As a result, the remaining protective film 310 and the surface treatment layer 162 of the pad 160 come into contact with each other under the etching solution. The metal forming the protective film 310 is copper (Cu), while the metal forming the surface treatment layer 162 is gold (Au). As a result, a cell is formed by the surface treatment layer 162, the remaining protective film 310, and the etching solution, and as a result, bimetallic corrosion, i.e., galvanic corrosion, occurs in the surface treatment layer 162. The example in Fig. 25 shows how galvanic corrosion occurs near the contact point between the surface treatment layer 162 and the remaining protective film 310.

[0058] As explained above, when a single layer of protective film 310 is formed, the thickness of protective film 310 varies depending on the position, and therefore, when protective film 310 is removed by wet etching, galvanic corrosion may occur in surface treatment layer 162.

[0059] Therefore, in the second embodiment, a multi-layer protective film is formed by stacking multiple metal films, thereby making the thickness of the protective film uniform and suppressing the occurrence of galvanic corrosion in the surface treatment layer 162 when the protective film is removed by wet etching.

[0060] Fig. 26 is a flowchart showing a method for manufacturing wiring substrate 100 according to the second embodiment. In Fig. 26, the same parts as in Fig. 3 are denoted by the same reference numerals. In the method for manufacturing wiring substrate 100 shown in Fig. 26, after resist layer 230 is formed in step S110, a multilayer protective film is formed by stacking multiple metal films.

[0061] After the resist layer 230 is formed, a multilayer protective film is formed by stacking multiple metal films in the openings of the resist layer 230 using an electrolytic plating method that uses the seed layer 121 as a power supply layer (step S201). Specifically, as shown in FIG. 27, for example, a first metal film 411 and a second metal film 412 are stacked to form a protective film 410 that covers the surface of the pad 160 and the upper surface of the seed layer 121 around the pad 160. FIG. 27 is a diagram showing a specific example of the protective film formation step. The thickness of the protective film 410 can be, for example, about 8 μm. The thicknesses of the first metal film 411 and the second metal film 412 are preferably equal to or less than the thickness of the surface treatment layer 162, and can be, for example, about 4 μm.

[0062] The first metal film 411 is made of a material different from that of the surface treatment layer 162, i.e., the gold (Au) layer. Here, the first metal film 411 is made of copper (Cu), the same as the seed layer 121 and the pad body 161. The first metal film 411 is formed by copper plating using a copper plating solution containing a brightener (accelerator), for example. The first metal film 411 is disposed on the bottom layer of the protective film 410 in contact with the seed layer 121.

[0063] The second metal film 412 is made of a metal different from that of the surface treatment layer 162, i.e., the gold (Au) layer. Here, nickel (Ni), which has a lower thermal conductivity than copper (Cu), the material of the first metal film 411, is used as the material for the second metal film 412. The second metal film 412 is formed by nickel plating using a nickel plating solution containing a brightener (accelerator), for example. The second metal film 412 is disposed on the top layer of the protective film 410.

[0064] By laminating the first metal film 411 and the second metal film 412 to form the multilayer protective film 410, the thicknesses of the first metal film 411 and the second metal film 412 can be reduced. In other words, when forming the first metal film 411 and the second metal film 412, the current density in copper plating or nickel plating can be reduced and the promotion of plating deposition by brightener in the plating solution can be suppressed. This can suppress positional variations in the thicknesses of the first metal film 411 and the second metal film 412, so that the protective film 410 is formed with a uniform thickness along the surface of the pad 160 and the upper surface of the seed layer 121 around the pad 160.

[0065] Furthermore, by making the thickness of the first metal film 411 and the second metal film 412 equal to or less than the thickness of the surface processing layer 162, the thickness of the protective film 410 can be made more uniform.

[0066] After the protective film 410 is formed, the resist layer 230 is removed, for example, with an alkaline stripping liquid (step S202). Furthermore, the seed layer 121 in the portion that was in contact with the resist layer 230 is removed by flash etching, and the insulating layer 120 is exposed in the region other than the portion that is in contact with the protective film 310, as shown in Fig. 28. Fig. 28 is a diagram showing a specific example of the resist layer removal step.

[0067] After the resist layer 230 is removed, an insulating layer 130 is formed on the upper surface of the insulating layer 120 to cover the surface of the protective film 410 (step S203), as shown in FIG. 29 for example. FIG. 29 is a diagram illustrating a specific example of the insulating layer formation step. Although not shown in FIG. 29, after the insulating layer 130 is formed, another wiring layer is formed on the upper surface of the insulating layer 130, and this other wiring layer is connected to another wiring layer on the upper surface of the insulating layer 120 by vias that penetrate the insulating layer 130. At this time, no other wiring layer or vias are arranged in the region of the insulating layer 130 where the electronic component 170 is to be accommodated. In the example of FIG. 29, the electronic component 170 is to be accommodated in the region of the insulating layer 130 located above the protective film 410, so no other wiring layer or vias are arranged in this region.

[0068] Then, a cavity is formed in the region of the insulating layer 130 where the electronic component 170 is to be accommodated (step S204). Specifically, as shown in FIG. 30, the insulating layer 130 is cut out toward the protective film 410 to form the cavity 180. FIG. 30 is a diagram showing a specific example of the cavity formation step. The cavity formation step can be achieved by laser processing using, for example, a CO2 laser. By cutting out the insulating layer 130 down to the surface of the protective film 410, the surface of the protective film 410 is exposed at the bottom of the cavity 180.

[0069] In the cavity formation process, laser processing using a CO2 laser is performed in a state in which the surface of the pad 160 and the upper surface of the seed layer 121 around the pad 160 are covered with the protective film 410. Therefore, the CO2 laser is not directly irradiated onto the pad 160 and the seed layer 121 around the pad 160. In other words, the protective film 410 can shield the pad 160 and the seed layer 121 around the pad 160 from heat received by the CO2 laser irradiation. As a result, deterioration of the pad 160 and the seed layer 121 around the pad 160 due to laser processing can be suppressed.

[0070] Furthermore, in the cavity forming process, a cavity 180 is formed in the insulating layer 130 by laser processing, exposing the surface of the second metal film 412 disposed on the uppermost layer of the protective film 410. Nickel (Ni) forming the second metal film 412 has a lower thermal conductivity than copper (Cu) forming the first metal film 411. Therefore, the second metal film 412 does not easily transfer heat received by CO2 laser irradiation to the pad 160 and the seed layer 121 around the pad 160. As a result, deterioration of the pad 160 and the seed layer 121 around the pad 160 due to laser processing can be further suppressed.

[0071] When the surface of the protective film 410 (second metal film 412) is exposed on the bottom surface of the cavity 180, the exposed protective film 410 is removed (step S205). That is, the second metal film 412 and the first metal film 411 constituting the protective film 410 are removed in this order. First, the second metal film 412 exposed on the bottom surface of the cavity 180 is removed by wet etching using a nickel (Ni) etchant. Next, the first metal film 411 is removed by wet etching using a copper (Cu) etchant. At this time, the pad 160 and the seed layer 121 around the pad 160 are exposed, and the copper (Cu) etchant comes into contact with and dissolves the seed layer 121 in the portion not overlapping with the pad 160. That is, the first metal film 411 is removed, and the seed layer 121 in the portion not overlapping with the pad 160 is also removed. This eliminates the short circuit between the pad 160 and the other pads, and the pad 160 having the pad body 161 and the surface treatment layer 162 is completed.

[0072] Because the protective film 410 has a uniform thickness, the protective film removal step can achieve just etching, in which the entire protective film 410 is removed almost simultaneously by wet etching. This reduces the possibility that a cell will be formed by the surface treatment layer 162, the protective film 410, and the etching solution, and as a result, it is possible to suppress the occurrence of bimetallic corrosion, i.e., galvanic corrosion, of the surface treatment layer 162.

[0073] Furthermore, in the protective film removal process, the seed layer 121 in the portion that does not overlap with the pad 160 is removed together with the first metal film 411, thereby improving the manufacturing efficiency of the wiring substrate 100 compared to when a separate process is performed to remove unnecessary portions of the seed layer 121.

[0074] As described above, in the method for manufacturing the wiring board 100 according to the second embodiment, the first metal film 411 and the second metal film 412 are stacked to form a multilayer protective film 410, thereby making the thickness of the protective film 410 uniform. This allows the entire protective film 410 to be removed almost simultaneously when the protective film 410 is removed by wet etching, thereby reducing the possibility that a cell will be formed by the surface treatment layer 162, the protective film 410, and the etching solution. As a result, it is possible to suppress galvanic corrosion from occurring in the surface treatment layer 162.

[0075] (Modification of the second embodiment) Next, various modified examples of the second embodiment will be described with reference to Figures 31 and 32. In the various modified examples described below, the same parts as those in the embodiment will be designated by the same reference numerals, and redundant explanations may be omitted.

[0076] In the second embodiment, the protective film 410 is formed by stacking one first metal film 411 and one second metal film 412, but the multi-layer structure of the protective film 410 is not limited to this. Specifically, as shown in FIG. 31, for example, the protective film 410 may be formed by alternately stacking a plurality of (here, two) first metal films 411 and a plurality of (here, two) second metal films 412. FIG. 31 is a diagram showing a first modified example of the protective film forming step. The thickness of the protective film 410 can be, for example, about 8 μm. The thicknesses of the first metal film 411 and the second metal film 412 are preferably equal to or less than the thickness of the surface treatment layer 162, and can be, for example, about 2 μm.

[0077] By alternately stacking a plurality of first metal films 411 and a plurality of second metal films 412, it is possible to reduce the thickness of each of the first metal films 411 and the second metal films 412. This makes it possible to further suppress the occurrence of positional variations in the thickness of the first metal films 411 and the second metal films 412, and therefore the protective film 410 can be formed with a more uniform thickness.

[0078] Furthermore, in the second embodiment described above, the first metal film 411 and the second metal film 412 in the protective film 410 have the same thickness, but the first metal film 411 and the second metal film 412 may have different thicknesses. Specifically, for example, as shown in Fig. 32, when forming the protective film 410, the second metal film 412 may be thicker than the first metal film 411. Fig. 32 is a diagram showing a second modification of the protective film forming step.

[0079] Nickel (Ni) forming the second metal film 412 has a lower thermal conductivity than copper (Cu) forming the first metal film 411. Because the thickness of the second metal film 412 is thicker than the thickness of the first metal film 411, in the cavity formation step using laser processing, the second metal film 412 does not easily transfer the heat received by CO2 laser irradiation to the pad 160 and the seed layer 121 around the pad 160. As a result, deterioration of the pad 160 and the seed layer 121 around the pad 160 due to laser processing can be further suppressed.

[0080] In addition, in the second embodiment, the first metal film 411 is disposed in contact with the seed layer 121 at the bottom of the protective film 410, and the second metal film 412 is disposed in the top of the protective film 410, but the positions of the first metal film 411 and the second metal film 412 may be reversed. That is, the second metal film 412 may be disposed in contact with the seed layer 121 at the bottom of the protective film 410, and the first metal film 411 may be disposed in the top of the protective film 410.

[0081] As described above, the manufacturing method of the wiring board (for example, wiring board 100) according to the embodiment includes the steps of: laminating a seed layer (for example, seed layer 121) made of metal on the upper surface of a first insulating layer (for example, insulating layer 120) (for example, step S103); forming, on the upper surface of the seed layer, a pad (for example, pad 160) having a pad body (for example, pad body 161) made of metal and a surface treatment layer (for example, surface treatment layer 162) that covers the upper surface and side surfaces of the pad body and has a metal layer (for example, gold (Au) layer) made of a metal different from the pad body on at least a portion of the pad body (for example, steps S105 and S108); The method includes steps of forming a protective film (e.g., protective film 310, 410) covering the upper surface of the first insulating layer (steps S111, S201), forming a second insulating layer (e.g., insulating layer 130) on the upper surface of the first insulating layer to cover the surface of the protective film (steps S113, S203), forming a cavity (e.g., cavity 180) in the second insulating layer by laser processing to expose the surface of the protective film (steps S114, S204), removing the protective film exposed in the cavity by etching (steps S115, S205), and removing portions of the seed layer that do not overlap with the pads (steps S115, S205). This makes it possible to suppress deterioration of the pads and the seed layer around the pads due to laser processing. [Explanation of symbols]

[0082] 100 wiring board 120 insulating layer 121 seed layer 130 Insulating layer 140 Filled resin layer 160 pads 161 Pad body 162 Surface treatment layer 170 Electronic Components 180 cavity 310, 410 Protective film 411 First metal film 412 Second metal film

Claims

1. depositing a seed layer made of metal on the top surface of the first insulating layer; forming a pad on the upper surface of the seed layer, the pad having a pad body made of metal and a surface treatment layer covering the upper surface and side surfaces of the pad body and including a metal layer on at least a portion of the pad body made of a metal different from that of the pad body; forming a protective film covering the surface of the pad and the upper surface of the seed layer around the pad; forming a second insulating layer on the upper surface of the first insulating layer to cover the surface of the protective film; forming a cavity in the second insulating layer by laser processing, exposing a surface of the protective film; removing the protective film exposed in the cavity by etching; removing the portion of the seed layer that does not overlap the pad; 1. A method for manufacturing a wiring substrate, comprising:

2. mounting an electronic component on the pad in the cavity; forming a filled resin layer that fills the cavity and covers the electronic component and the pad; 2. The method for manufacturing a wiring board according to claim 1, further comprising:

3. The step of forming the protective film includes: The protective film is formed as a single layer made of a metal different from the metal layer of the surface treatment layer.

2. The method for manufacturing a wiring board according to claim 1.

4. The metal forming the protective film is the same metal as the metal forming the seed layer, Removing the portions of the seed layer comprises: This is carried out simultaneously with the step of removing the protective film.

4. The method for manufacturing a wiring board according to claim 3.

5. The step of forming the protective film includes: The protective film is formed by laminating a first metal film made of a first metal different from the metal layer of the surface treatment layer and a second metal film made of a second metal different from the metal layer of the surface treatment layer and the first metal.

2. The method for manufacturing a wiring board according to claim 1.

6. The thickness of the first metal film and the second metal film is Each of these is equal to or less than the thickness of the surface treatment layer.

6. The method for manufacturing a wiring board according to claim 5.

7. The step of forming the protective film includes: The protective film is formed by alternately stacking a plurality of the first metal films and a plurality of the second metal films.

6. The method for manufacturing a wiring board according to claim 5.

8. The first metal forming the first metal film is the same metal as the metal forming the seed layer, The step of forming the protective film includes: forming the protective film by stacking the first metal film and the second metal film so that the first metal film is disposed in contact with the seed layer at the bottom of the protective film; The step of removing the protective film includes: removing the first metal film disposed at the bottom of the protective film; Removing the portions of the seed layer comprises: This is performed simultaneously with the step of removing the first metal film.

6. The method for manufacturing a wiring board according to claim 5.

9. The second metal forming the second metal film is a metal having a thermal conductivity lower than that of the first metal forming the first metal film, The step of forming the protective film includes: forming the protective film by stacking the first metal film and the second metal film so that the second metal film is disposed on the uppermost layer of the protective film; The step of forming the cavity includes: The cavity that exposes the surface of the second metal film is formed in the second insulating layer by the laser processing.

6. The method for manufacturing a wiring board according to claim 5.

10. The second metal forming the second metal film is a metal having a thermal conductivity lower than that of the first metal forming the first metal film, The step of forming the protective film includes: In the protective film, the thickness of the second metal film is made thicker than the thickness of the first metal film.

6. The method for manufacturing a wiring board according to claim 5.

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