Semiconductor device

Abstract

To provide a semiconductor device capable of achieving an improvement in temperature measurement accuracy.SOLUTION: A semiconductor device 1 includes: a chip having a first main surface 3; a plurality of diode trench structures arranged at intervals in a first direction X in a temperature measurement region set on the main surface; a unit diode formed in a mesa portion that is formed by being sandwiched by the plurality of diode trench structures adjacent to each other, the unit diode having a pn junction; and a temperature sensitive diode including the unit diode. The temperature sensitive diode includes: a first diode Di1 including two unit diodes; a second diode Di2 including two unit diodes and formed to be electrically separated from the first diode Di1; and a first connection wiring structure 150 connecting the first diode Di1 and the second diode Di2 in series.SELECTED DRAWING: Figure 15A

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a chip having a first main surface, a diode region provided on the first main surface, a plurality of diode trench structures formed at intervals on the first main surface in the diode region, and a diode having a pn junction in a region between the plurality of diode trench structures. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 002767

[0004] [overview] An embodiment of the present disclosure provides a semiconductor device that can improve the accuracy of temperature measurement.

[0005] One embodiment of the present disclosure provides a semiconductor device including: a chip having a main surface; a plurality of diode trench structures arranged at intervals in a temperature detection region defined on the main surface in a first direction along the main surface and extending in a strip-like shape in a second direction intersecting the first direction, the plurality of diode trench structures having an electrode structure including upper and lower electrodes vertically embedded in the trenches with an insulator sandwiched therebetween; a unit diode having a p-n junction formed in a mesa portion sandwiched between adjacent plurality of diode trench structures; and a temperature sensing diode including the unit diode. The temperature sensing diode may include a first diode having at least one unit diode, a second diode having at least one unit diode and formed so as to be electrically isolated from the first diode, and a first connecting wiring structure connecting the first diode and the second diode in series. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. [Figure 3] FIG. 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a schematic circuit diagram showing the configuration of the output transistor. [Figure 5] FIG. 5 is a schematic circuit diagram showing the configuration of the overheat protection circuit shown in FIG. [Figure 6] FIG. 6 is a plan view showing the output area shown in FIG. [Figure 7] FIG. 7 is an enlarged view of the area surrounded by the dashed line VII in FIG. [Figure 8] FIG. 8 is a further enlarged view of the area surrounded by the dashed line VII in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. [Figure 14] FIG. 14 is an enlarged view of the area surrounded by the dashed line XIV in FIG. [Figure 15A] FIG. 15A is a plan view showing the layout of the first wiring layer, and corresponds to FIG. [Figure 15B] FIG. 15B is a plan view showing the layout of the first wiring layer, and is a diagram showing an area adjacent to the area shown in FIG. 15A in the first direction. [Figure 15C] FIG. 15C is a cross-sectional view taken along line XVC-XVC shown in FIG. 15B. [Figure 16] FIG. 16 is an enlarged view of the portion surrounded by the dashed line XVI in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. [Figure 19A] FIG. 19A is a cross-sectional view taken along line XIX-XIX shown in FIG. [Figure 19B] FIG. 19B is a cross-sectional view taken along line XIXB-XIXB shown in FIG. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. [Figure 21A] FIG. 21A is a cross-sectional view taken along line XXIA-XXIA shown in FIG. [Figure 21B] FIG. 21B is a cross-sectional view taken along line XXIB-XXIB shown in FIG. [Figure 22] FIG. 22 is an electric circuit diagram of the first temperature sensitive diode according to the first embodiment. [Figure 23] FIG. 23 is an electrical circuit diagram of the mesa portion. [Figure 24] FIG. 24 is a front view showing the layout of a chip according to a first modified example of the first embodiment of the present disclosure, and is a view corresponding to FIG. [Figure 25] FIG. 25 is a front view showing the layout of the first wiring layer according to the first modification, and corresponds to FIG. 15A. [Figure 26] FIG. 26 is an electric circuit diagram of a first temperature sensitive diode according to a first modified example. [Figure 27] FIG. 27 is a front view showing the layout of the chip according to the second embodiment of the present disclosure, and corresponds to FIG. [Figure 28] FIG. 28 is a front view showing the layout of the first wiring layer according to the second embodiment, and corresponds to FIG. 15A. [Figure 29] FIG. 29 is a cross-sectional view taken along line XXIX-XXIX shown in FIG. [Figure 30] FIG. 30 is a cross-sectional view taken along the line XXX-XXX shown in FIG. [Figure 31] FIG. 31 is a cross-sectional view taken along line XXXI-XXXI shown in FIG. [Figure 32A] FIG. 32A is a diagram showing a current flow in the first temperature sensitive diode according to the second embodiment. [Figure 32B] FIG. 32B is an electric circuit diagram of the first temperature sensitive diode according to the second embodiment. [Figure 33] FIG. 33 is a front view showing the layout of a chip according to a second modified example of the second embodiment of the present disclosure, and corresponds to FIG. [Figure 34] FIG. 34 is a front view showing the layout of the first wiring layer according to the second modification, and corresponds to FIG. [Figure 35] FIG. 35 is a front view showing the layout of the chip according to the third embodiment of the present disclosure, and corresponds to FIG. [Figure 36] FIG. 36 is a front view showing the layout of the first wiring layer according to the third embodiment, and corresponds to FIG. 15A. [Figure 37] FIG. 37 is a front view showing the layout of the second wiring layer according to the third embodiment, and corresponds to FIG. 15A. [Figure 38] 38 is a cross-sectional view taken along line XXXVIII-XXXVIII shown in FIG. [Figure 39] 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in FIG. [Figure 40] FIG. 40 is a cross-sectional view taken along the line XL-XL shown in FIG. [Figure 41] FIG. 41 is a cross-sectional view taken along line XLI-XLI shown in FIG. [Figure 42] FIG. 42 is a diagram showing a current flow in the first temperature sensitive diode according to the second embodiment. [Figure 43] FIG. 43 is an electric circuit diagram of the first temperature sensitive diode according to the second embodiment. [Figure 44]FIG. 44 is a front view showing the layout of a chip according to a third modified example of the third embodiment of the present disclosure, and corresponds to FIG. [Figure 45] FIG. 45 is a front view showing the layout of the first wiring layer according to the third modified example, and corresponds to FIG. [Figure 46] FIG. 46 is a front view showing the layout of the second wiring layer according to the third modified example, and corresponds to FIG.

[0007] [Detailed explanation] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0008] When the phrase "substantially equal" is used in a description in which a comparison target is present, this phrase includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation, and are not attached with the intent of limiting the names of each structure.

[0009] Fig. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. With reference to Figs. 1 and 2, the semiconductor device 1 includes a chip 2 formed in a rectangular parallelepiped shape. In this embodiment, the chip 2 is a Si chip including a Si single crystal.

[0010] The chip 2 may be a wide bandgap chip including a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). For example, the chip 2 may be a SiC chip including a single crystal of SiC.

[0011] The chip 2 has a first main surface (principal surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0012] The first main surface 3 is a circuit surface on which various circuit structures that constitute an electronic circuit are formed. The second main surface 4 is a non-circuit surface that does not have any circuit structures. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0013] 1, the semiconductor device 1 includes an output region 6 provided on the first main surface 3. The output region 6 is a region having an electronic circuit (circuit device) configured to generate an output signal to be output to the outside. In this embodiment, the output region 6 is defined in a region on the first side surface 5A side of the first main surface 3. The output region 6 is defined in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0014] The semiconductor device 1 includes a control region 7 provided in a region on the first main surface 3 that is different from the output region 6. The control region 7 is a region having a plurality of types of electronic circuits (circuit devices) configured to generate control signals that control the output region 6. In this embodiment, the control region 7 is defined in a region on the second side surface 5B side of the output region 6, and faces the output region 6 in the second direction Y. In this embodiment, the control region 7 is defined in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0015] The semiconductor device 1 includes at least one temperature measurement region 8 on the first main surface 3. The semiconductor device 1 may include a plurality of temperature measurement regions 8. In this embodiment, the number of temperature measurement regions 8 is two.

[0016] The multiple temperature detection areas 8 are set at intervals on the first main surface 3 so that the temperature of the chip 2 is detected in different areas. In this embodiment, the multiple temperature detection areas 8 include a first temperature detection area 8A and a second temperature detection area 8B. The first temperature detection area 8A is set adjacent to the output area 6 and detects the temperature of the output area 6. The second temperature detection area 8B is set adjacent to the control area 7 and detects the temperature of the control area 7.

[0017] In this embodiment, the first temperature detection area 8A has a planar area smaller than the planar area of ​​the output area 6 and is defined inside the output area 6. The first temperature detection area 8A is surrounded (all around) by the output area 6 in a planar view. In other words, the first temperature detection area 8A is adjacent to the output area 6 in four directions in a planar view.

[0018] The first temperature detection area 8A may be sandwiched between the output areas 6 from one side and the other side in the first direction X, or may be sandwiched between the output areas 6 from one side and the other side in the second direction Y. The first temperature detection area 8A may also be adjacent to the output area 6 in the first direction X and the second direction Y. Although not shown in the figures, the first temperature detection area 8A may also be adjacent to the output area 6 in two or three directions.

[0019] In this embodiment, the second temperature measurement area 8B has a planar area smaller than the planar area of ​​the control area 7 and is defined inside the control area 7. In other words, in this embodiment, the second temperature measurement area 8B is adjacent to the control area 7 in four directions in a plan view. It is preferable that the second temperature measurement area 8B has a planar area smaller than the planar area of ​​the control area 7. It is preferable that the second temperature measurement area 8B has a planar area approximately equal to the planar area of ​​the first temperature measurement area 8A.

[0020] 2, semiconductor device 1 includes an n-type (first conductivity type) drain region 10 formed in a surface layer portion of second main surface 4. The n-type impurity concentration of drain region 10 is 1×10 18 cm -3 More than 1×10 21 cm -3 The drain region 10 may have a thickness of 50 μm or more and 400 μm or less. The drain region 10 is formed in a layer shape extending along the second main surface 4 over the entire surface portion of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The drain region 10 may have a thickness of 50 μm or more and 400 μm or less. The drain region 10 preferably has a thickness of 50 μm or more and 200 μm or less, and more preferably has a thickness of 150 μm or less. In this embodiment, the drain region 10 is formed of an n-type semiconductor substrate (Si substrate).

[0021] The semiconductor device 1 includes an n-type drift region 11 formed in a surface layer portion of the first main surface 3. The drift region 11 has a lower n-type impurity concentration than the drain region 10. The n-type impurity concentration of the drift region 11 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 11 is formed in a layer extending along the first main surface 3 in the output region 6 and the control region 7. Specifically, the drift region 11 is formed in a layer extending along the first main surface 3 over the entire surface layer portion of the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0022] The drift region 11 is electrically connected to the drain region 10 within the chip 2. The drift region 11 has a thickness less than that of the drain region 10. The thickness of the drift region 11 may be 1 μm or more and 20 μm or less. The thickness of the drift region 11 is preferably 5 μm or more and 15 μm or less. The thickness of the drift region 11 is particularly preferably 10 μm or less. In this embodiment, the drift region 11 is formed by an n-type epitaxial layer (Si epitaxial layer).

[0023] The semiconductor device 1 includes an interlayer insulating layer 12 that covers the first main surface 3. The interlayer insulating layer 12 collectively covers the output region 6 and the control region 7. The interlayer insulating layer 12 may cover the entire first main surface 3 so as to be continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). Of course, the interlayer insulating layer 12 may be formed at a distance inward from the periphery of the first main surface 3 so as to expose the periphery of the first main surface 3.

[0024] In this embodiment, the interlayer insulating layer 12 has a multilayer wiring structure in which multiple insulating layers and multiple wiring layers are alternately stacked. Each insulating layer may include at least one of a silicon oxide film and a silicon nitride film. Each wiring layer (e.g., the first wiring layer 16 and the second wiring layer 17 described below) may include at least one of a pure Al layer (an Al layer with a purity of 99% or more), a Cu layer (a Cu layer with a purity of 99% or more), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0025] The semiconductor device 1 includes a plurality of terminals 13 to 15 arranged on either or both (in this embodiment, both) of the first main surface 3 and the second main surface 4. The plurality of terminals 13 to 15 includes a source terminal 13, a plurality of control terminals 14, and a drain terminal 15.

[0026] In this embodiment, the source terminal 13 is provided as an output terminal electrically connected to a load, and is disposed on a portion of the interlayer insulating layer 12 that covers the output region 6. The source terminal 13 may cover the entire output region 6 in a plan view. The source terminal 13 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0027] 1 and 2, the control terminals 14 are terminals electrically connected to various electronic circuits in the control region 7, and are arranged on a portion of the interlayer insulating layer 12 that covers the control region 7. The control terminals 14 are arranged at intervals along the periphery of the control region 7 (the periphery of the first main surface 3).

[0028] The planar area of ​​each control terminal 14 is set within a range that allows connection of a bonding wire. The planar area of ​​each control terminal 14 may be 1 / 10 or less of the planar area of ​​the source terminal 13. The plurality of control terminals 14 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0029] The multiple control terminals 14 include at least one ground terminal 14a fixed to a ground potential and at least one input terminal 14b that applies an electrical signal to the control region 7. The location of the ground terminal 14a is arbitrary. In a plan view, the ground terminal 14a may be located inside the control region 7, along one side of the first main surface 3, or at a corner of the first main surface 3. The ground terminal 14a is connected to a bonding wire, and a ground potential is applied to the ground terminal 14a from the outside via the bonding wire.

[0030] The location of input terminal 14b is arbitrary. In plan view, input terminal 14b may be located inside control region 7, along one side of first main surface 3, or at a corner of first main surface 3.

[0031] In this embodiment, an example is shown in which the input terminal 14b is a test terminal to which a test signal for testing the electrical characteristics of the control circuit 23 during the manufacturing process is input. The test terminal is provided as a contact target for a probe of an electrical characteristic test device, and is configured to receive a test signal from the probe.

[0032] The input terminal 14b is a structure that is not to be connected with a bonding wire in the manufactured semiconductor device 1. In other words, the input terminal 14b is formed as an open terminal (dummy terminal). An open terminal is a terminal that does not receive a signal (electric potential) from the outside and is formed in an electrically floating state.

[0033] For example, when the semiconductor device 1 is mounted in a semiconductor package, the entire area of ​​the input terminal 14b is covered with an insulator (e.g., a sealing resin containing a plurality of fillers and a matrix resin) and is electrically insulated from other structures. Of course, the input terminal 14b may be electrically connected to a lead terminal of the semiconductor package via a bonding wire so that a test signal can be input even after the semiconductor device 1 is mounted in the semiconductor package.

[0034] 2, in this embodiment, drain terminal 15 is provided as a power supply terminal and directly covers second main surface 4 of chip 2. That is, in this embodiment, semiconductor device 1 is a high-side switching device electrically interposed between a power supply and a load. Drain terminal 15 is electrically connected to drain region 10 on second main surface 4. Drain terminal 15 covers the entire second main surface 4 so as to be continuous with the periphery of second main surface 4 (first to fourth side surfaces 5A to 5D).

[0035] Fig. 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device 1 shown in Fig. 1. Fig. 4 is a schematic circuit diagram showing the configuration of the output transistor 20. Fig. 5 is a schematic circuit diagram showing the configuration of the overheat protection circuit 27 shown in Fig. 4.

[0036] FIG. 3 shows an example in which an inductive load L as an example of a load is electrically connected to the source terminal 13 to illustrate an operation example of the semiconductor device 1. The inductive load L is not a component of the semiconductor device 1. Therefore, a configuration including the semiconductor device 1 and the inductive load L may be referred to as an "inductive load driving device" or an "inductive load control device." Examples of the inductive load L include a relay, a solenoid, a lamp, and a motor. The inductive load L may be an inductive load for an automobile. That is, the semiconductor device 1 may be an inductive load for an automobile.

[0037] The semiconductor device 1 includes an output transistor 20 formed in the output region 6. In this embodiment, the output transistor 20 is a split-gate transistor including one main drain, one main source, and multiple main gates. The main drain is electrically connected to a drain terminal 15. The main source is electrically connected to a source terminal 13.

[0038] The multiple main gates are configured to receive multiple electrically independent gate signals (gate potentials) individually. The output transistor 20 generates a single output current Io (output signal) in response to the multiple gate signals. In other words, the output transistor 20 is a multiple-input, single-output switching device. The output current Io is a drain-source current that flows between the main drain and main source. The output current Io is output to the outside of the chip 2 (to an inductive load L) via the source terminal 13.

[0039] The output transistor 20 includes a plurality of (two or more) system transistors 21 that are electrically controlled independently. In this embodiment, the plurality of system transistors 21 includes a first system transistor 21A and a second system transistor 21B. The plurality of system transistors 21 are formed together in the output region 6. The plurality of system transistors 21 are connected in parallel so that a plurality of gate signals are inputted individually, and are configured so that the system transistors 21 in the on state and the system transistors 21 in the off state coexist.

[0040] Each of the plurality of system transistors 21 includes a system drain, a system source, and a system gate. The plurality of system drains are electrically connected to a main drain (drain terminal 15). The plurality of system sources are electrically connected to a main source (source terminal 13). Each system gate is electrically connected to a respective main gate. In other words, each system gate constitutes a respective main gate.

[0041] The multiple system transistors 21 each generate a system current Is in response to a corresponding gate signal. Each system current Is is a drain-source current flowing between the system drain and the system source of each system transistor 21. The multiple system currents Is may have different values ​​or may have approximately the same value. The multiple system currents Is are added between the main drain and the main source. As a result, a single output current Io consisting of the added value of the multiple system currents Is is generated.

[0042] 4, each of the multiple system transistors 21 includes a single or multiple unit transistors 22 that are grouped together as individual control targets. Specifically, each of the multiple system transistors 21 is formed of a parallel circuit including a single unit transistor 22 or multiple unit transistors 22. In this embodiment, each of the multiple unit transistors 22 is of a trench gate vertical type. The multiple system transistors 21 may be formed of the same number of unit transistors 22, or may be formed of different numbers of unit transistors 22.

[0043] Each unit transistor 22 includes a unit drain, a unit source, and a unit gate. The unit drain of each unit transistor 22 is electrically connected to the system drain of the corresponding system transistor 21. The unit source of each unit transistor 22 is electrically connected to the system source of the corresponding system transistor 21. The unit gate of each unit transistor 22 is electrically connected to the system gate of the corresponding system transistor 21.

[0044] Each of the unit transistors 22 generates a unit current Iu in response to a corresponding gate signal. Each unit current Iu is a drain-source current that flows between the unit drain and unit source of the unit transistor 22. The unit currents Iu may have different values ​​or may have approximately the same value. The unit currents Iu are added together between the corresponding system drains and system sources. This generates a system current Is consisting of the sum of the unit currents Iu.

[0045] That is, the output transistor 20 is configured so that the first system transistor 21A and the second system transistor 21B are on / off controlled in a state where they are electrically independent of each other. That is, the output transistor 20 is configured so that both the first system transistor 21A and the second system transistor 21B are on at the same time. Also, the output transistor 20 is configured so that either the first system transistor 21A or the second system transistor 21B is on, and the other is off.

[0046] When both the first system transistor 21A and the second system transistor 21B are simultaneously turned on, the channel utilization rate of the output transistor 20 increases and the on-resistance decreases. When either the first system transistor 21A or the second system transistor 21B is turned on while the other is turned off, the channel utilization rate of the output transistor 20 decreases and the on-resistance increases. In other words, the output transistor 20 is a variable on-resistance switching device.

[0047] 1 and 3, the semiconductor device 1 includes a plurality of temperature sensing diodes 9. The plurality of temperature sensing diodes 9 includes a first temperature sensing diode 9A formed in the first temperature sensing region 8A and a second temperature sensing diode 9B formed in the second temperature sensing region 8B. In this embodiment, the first temperature sensing diode 9A is formed in the output region 6, and the second temperature sensing diode 9B is formed in the control region 7.

[0048] When the output region 6 generates an output signal and the control region 7 generates a control signal, the output region 6 is at a first temperature TE1 and the control region 7 is at a second temperature TE2 (TE2 <TE1)になる。

[0049] The first temperature sensitive diode 9A includes an anode and a cathode. An anode potential is applied to the anode of the first temperature sensitive diode 9A, and a cathode potential is applied to the cathode of the first temperature sensitive diode 9A. The voltage between the anode potential and the cathode potential may be equal to or greater than the forward voltage of the first temperature sensitive diode 9A (for example, 5 V or greater). The anode potential may be any high potential (for example, the power supply potential VBB). The cathode potential may be any low potential lower than the anode potential (for example, a potential approximately 5 V lower than the power supply potential VBB).

[0050] In the first temperature detection region 8A, the first temperature sensing diode 9A generates a first temperature detection signal ST1 (FIG. 3) that detects a first temperature TE1 in the output region 6. The first temperature sensing diode 9A has a first forward voltage Vf1 with a temperature characteristic that varies in accordance with the first temperature TE1 in the output region 6. Specifically, the first forward voltage Vf1 has a negative temperature characteristic in which the first forward voltage Vf1 decreases linearly as the first temperature TE1 increases. The first temperature detection signal ST1 (first forward voltage Vf1 (FIG. 3)) varies in accordance with the first temperature TE1 in the output region 6, and indirectly detects the first temperature TE1.

[0051] The second temperature sensing diode 9B includes an anode and a cathode. An anode potential is applied to the anode of the second temperature sensing diode 9B, and a cathode potential is applied to the cathode of the second temperature sensing diode 9B. The voltage between the anode potential and the cathode potential may be equal to or higher than the forward threshold voltage of the second temperature sensing diode 9B (for example, 5V or higher). The anode potential may be any high potential (for example, the power supply potential VBB). The cathode potential may be any low potential lower than the anode potential (for example, a potential about 5V lower than the power supply potential VBB).

[0052] The second temperature sensing diode 9B generates a second temperature detection signal ST2 (FIG. 3) for detecting the second temperature TE2 of the control region 7 in the second temperature detection region 8B. The second temperature sensing diode 9B has a second forward voltage Vf2 having a temperature characteristic that varies according to the second temperature TE2 of the control region 7. Specifically, the second forward voltage Vf2 has a negative temperature characteristic in which the second forward voltage Vf2 linearly decreases as the second temperature TE2 increases. The second temperature detection signal ST2 (the second forward voltage Vf2 (FIG. 3)) varies according to the second temperature TE2 of the control region 7 and indirectly detects the second temperature TE2.

[0053] The second temperature sensing diode 9B preferably has substantially the same configuration as the first temperature sensing diode 9A and substantially the same electrical characteristics as the first temperature sensing diode 9A. When the output transistor 20 generates the output current Io, the second temperature TE2 is less than the first temperature TE1 (TE1 > TE2). Therefore, when the output current Io is generated, the second forward voltage Vf2 of the second temperature sensing diode 9B exceeds the first forward voltage Vf1 of the first temperature sensing diode 9A (Vf1 < Vf2). Since the second temperature sensing diode 9B has substantially the same configuration as the first temperature sensing diode 9A, a detailed description of the second temperature sensing diode 9B will be omitted.

[0054] 1 and 3, the semiconductor device 1 includes a control circuit 23 formed in the control region 7 so as to be electrically connected to the output transistor 20. The control circuit 23 may also be referred to as a "control IC." The control circuit 23 includes various functional circuits and, together with the output transistor 20, constitutes an IPD (Intelligent Power Device). The IPD may also be referred to as an "IPM (Intelligent Power Module)," an "IPS (Intelligent Power Switch)," a "smart power driver," a "smart MISFET (Smart MOSFET)," or a "protected MISFET (Protected MOSFET)."

[0055] In this embodiment, the control circuit 23 includes a gate control circuit 24, a current monitor circuit 25, an overcurrent protection circuit 26, an overheat protection circuit 27, an undervoltage malfunction avoidance circuit 28, an open load detection circuit 29, an active clamp circuit 30, a power supply reverse connection protection circuit 31, a logic circuit 32, a test circuit 33 (FIG. 3), and an amplifier circuit 34 (FIG. 3). The control circuit 23 does not necessarily need to include all of these functional circuits at the same time, and it is sufficient if it includes at least one of these functional circuits.

[0056] The current monitor circuit 25 may be referred to as a CS circuit (Current Sense circuit). The overcurrent protection circuit 26 may be referred to as an OCP circuit (Over Current Protection circuit). The overheat protection circuit 27 may be referred to as a TSD circuit (Thermal shut down circuit). The low voltage malfunction prevention circuit 28 may be referred to as a UVLO circuit (Under Voltage Lock Out circuit). The open load detection circuit 29 may be referred to as an OLD circuit (Open Load Detection circuit). The power supply reverse connection protection circuit 31 may be referred to as an RBP circuit (Reverse Battery Protection circuit). The amplifier circuit 34 may be referred to as an AMP circuit (Amplifier circuit).

[0057] The gate control circuit 24 is configured to generate gate signals that control the on / off of the output transistors 20. Specifically, the gate control circuit 24 generates a plurality of gate signals that individually control the on / off of the plurality of system transistors 21. That is, in this embodiment, the gate control circuit 24 generates a first gate signal that individually controls the on / off of the first system transistors 21A, and a second gate signal that individually controls the on / off of the second system transistors 21B electrically independent of the first system transistors 21A.

[0058] The current monitor circuit 25 generates a monitor current that monitors the output current Io of the output transistor 20 and outputs the monitor current to another circuit. For example, the monitor circuit may include a transistor having a similar configuration to the output transistor 20, and be configured to generate a monitor current linked to the output current Io by being on / off controlled simultaneously with the output transistor 20. Of course, the current monitor circuit 25 may also be configured to generate a monitor current linked to one or more system currents Is.

[0059] The overcurrent protection circuit 26 generates an electrical signal for controlling the gate control circuit 24 based on the monitor current from the current monitor circuit 25, and cooperates with the gate control circuit 24 to control the on / off of the output transistor 20. For example, the overcurrent protection circuit 26 may be configured to determine that the output transistor 20 is in an overcurrent state when the monitor current is equal to or greater than a predetermined threshold, and to control some or all of the output transistors 20 (plurality of system transistors 21) to an off state in cooperation with the gate control circuit 24. Alternatively, the overcurrent protection circuit 26 may be configured to cooperate with the gate control circuit 24 to transition the output transistor 20 to normal operation when the monitor current is less than a predetermined threshold.

[0060] The overheat protection circuit 27 is electrically connected to the gate control circuit 24 and both the first and second temperature sensing diodes 9A and 9B. The overheat protection circuit 27 is configured to receive a first temperature detection signal ST1 from the first temperature sensing diode 9A and a second temperature detection signal ST2 from the second temperature sensing diode 9B.

[0061] Specifically, the overheat protection circuit 27 is configured to protect the output transistor 20 from overheating by controlling the gate signal generated by the gate control circuit 24 in response to the first temperature detection signal ST1 and the second temperature detection signal ST2, and limiting the output current Io to a predetermined value or less (for example, 0 A).

[0062] 5, the overheat protection circuit 27 may include, for example, a low potential applying unit 43, a first current source 44, a second current source 45, a difference circuit 46, a logic circuit 48, and an offset circuit 49. The low potential applying unit 43 applies a low potential lower than the power supply potential VBB to other circuits. The low potential applying unit 43 may be a circuit device such as a constant voltage regulator or a Zener diode, or may be any low potential wiring.

[0063] The first current source 44 is electrically connected to the first temperature sensitive diode 9A and the low potential applying unit 43, and supplies a constant current to the low potential applying unit 43. A first node N1 is formed between the first current source 44 and the first temperature sensitive diode 9A. The second current source 45 is electrically connected to the second temperature sensitive diode 9B and the low potential applying unit 43, and supplies a constant current to the low potential applying unit 43. The second current source 45 may be configured to generate a constant current substantially equal to that of the first current source 44. A second node N2 is formed between the second current source 45 and the second temperature sensitive diode 9B.

[0064] The differential circuit 46 is electrically connected to a first node N1 and a second node N2. The differential circuit 46 may include a comparator 47 having a non-inverting input terminal (-) and an inverting input terminal (+). The comparator 47 may have a hysteresis characteristic that reduces noise between the non-inverting input terminal (-) and the inverting input terminal (+). The first node N1 may be electrically connected to the non-inverting input terminal (-) of the comparator 47, and the second node N2 may be electrically connected to the inverting input terminal (+) of the comparator 47.

[0065] The differential circuit 46 is configured to output a differential signal ΔVf (ΔVf=Vf2-Vf1, Vf2>Vf1) indicating the difference between the first temperature detection signal ST1 (first forward voltage Vf1) and the second temperature detection signal ST2 (second forward voltage Vf2). The differential signal ΔVf indirectly indicates the temperature difference ΔTj (ΔTj=TE1-TE2) between the first temperature TE1 in the power domain 6 and the second temperature TE2 in the control domain 7.

[0066] The logic circuit 48 is electrically connected to the difference circuit 46 and the gate control circuit 24. For example, when the difference signal ΔVf exceeds a predetermined threshold value VT (ΔVf>VT), the logic circuit 48 is configured to generate an overheat detection signal and output the overheat detection signal to the gate control circuit 24. The overheat detection signal is a signal for restricting some or all of the n gate signals generated in the gate control circuit 24 to be turned off.

[0067] At the second node N2, the offset circuit 49 is connected to the inverting input terminal (+) of the comparator 47. In order to actually operate the overheat protection circuit 27 in the control circuit 23, an appropriate offset voltage is required between the non-inverting input terminal (-) and the inverting input terminal (+) of the comparator 47, and the offset circuit 49 is a circuit for generating that offset voltage.

[0068] The gate control circuit 24 controls part or all of the output transistor 20 to an off state in response to the overheat detection signal, suppressing the temperature rise in the output region 6. Also, the gate control circuit 24 controls part or all of the system transistor 21 to an off state in response to the overheat detection signal, suppressing the temperature rise in the output region 6. The logic circuit 48, for example, shifts the gate control circuit 24 to normal control when the differential signal ΔVf becomes less than or equal to the threshold value VT (ΔVf≦VT).

[0069] Of course, the overheat protection circuit 27 may be configured to receive only the first temperature detection signal ST1 from the first temperature sensing diode 9A and control the gate signal only in response to the first temperature detection signal ST1. In this case, the overheat protection circuit 27 may be configured to control part or all of the output transistor 20 to an off state when the first temperature detection signal ST1 exceeds the threshold value VT (ST1>VT), and control the output transistor 20 to an on state when the first temperature detection signal ST1 is less than or equal to the threshold value VT (ST1<VT).

[0070] Referring again to FIG. 3, the low-voltage malfunction avoidance circuit 28 is configured to avoid malfunction of various functional circuits in the control circuit 23 when the startup voltage for starting the control circuit 23 is less than a predetermined value. For example, the low-voltage malfunction avoidance circuit 28 may be configured to start the control circuit 23 when the startup voltage becomes equal to or higher than a predetermined threshold voltage, and stop the control circuit 23 when the startup voltage is less than the threshold voltage. The threshold voltage may have a hysteresis characteristic.

[0071] The load open detection circuit 29 determines the electrical connection state of the inductive load L. For example, the load open detection circuit 29 may be configured to monitor the voltage between the terminals of the output transistor 20 and determine that the inductive load L is in an open state when the voltage between the terminals becomes equal to or higher than a predetermined threshold value. For example, the load open detection circuit 29 may be configured to determine that the inductive load L is in an open state when the monitor current becomes less than or equal to a predetermined threshold value.

[0072] The active clamp circuit 30 is electrically connected to the main drain and at least one main gate (for example, the system gate of the first system transistor 21A) of the output transistor 20. The active clamp circuit 30 includes a Zener diode and a pn junction diode connected in series with the Zener diode in a reverse bias state. The pn junction diode is a backflow prevention diode that prevents backflow from the output transistor 20.

[0073] The active clamp circuit 30 is configured to cooperate with the gate control circuit 24 to control some or all of the output transistors 20 to the ON state when a back electromotive force caused by the inductive load L is applied to the output transistors 20. Specifically, the output transistors 20 are controlled in a plurality of operation modes including a normal operation, a first OFF operation, an active clamp operation, and a second OFF operation.

[0074] In normal operation, both the first system transistor 21A and the second system transistor 21B are controlled to be in the ON state at the same time. This increases the channel utilization rate of the output transistor 20 and reduces the ON resistance. In the first OFF operation, both the first system transistor 21A and the second system transistor 21B are controlled to be changed from the ON state to the OFF state at the same time. This causes the back electromotive force caused by the inductive load L to be applied to both the first system transistor 21A and the second system transistor 21B.

[0075] The active clamp operation is an operation in which the energy stored in the inductive load L is absorbed (consumed) by the output transistor 20, and is executed when the back electromotive force caused by the inductive load L becomes equal to or greater than a predetermined threshold voltage. In the active clamp operation, the first system transistor 21A is controlled to change from an off state to an on state, and at the same time, the second system transistor 21B is controlled (maintained) in an off state.

[0076] The channel utilization rate of the output transistor 20 during active clamp operation is less than the channel utilization rate of the output transistor 20 during normal operation. The on-resistance of the output transistor 20 during active clamp operation is greater than the on-resistance of the output transistor 20 during normal operation. This suppresses a sudden temperature rise in the output transistor 20 during active clamp operation, improving the active clamp withstand capability.

[0077] The second off operation is executed when the back electromotive force voltage becomes less than a predetermined threshold voltage. In the second off operation, the first system transistor 21A is controlled from the on state to the off state, and at the same time, the second system transistor 21B is controlled (maintained) in the off state. In this way, the back electromotive force (energy) of the inductive load L is absorbed by a part of the output transistor 20 (here, the first system transistor 21A). Of course, during active clamp operation, the first system transistor 21A may be controlled (maintained) in the off state, and at the same time, the second system transistor 21B may be controlled to the on state.

[0078] The power supply reverse connection protection circuit 31 is configured to detect a reverse voltage when the power supply is connected in reverse, and protect the control circuit 23 and the output transistor 20 from the reverse voltage (reverse current). The logic circuit 32 is configured to generate an electrical signal to be supplied to various circuits in the control circuit 23.

[0079] 3, test circuit 33 is formed on first main surface 3 (FIG. 1) so as to be electrically interposed between input terminal 14b and drain terminal 15, and is electrically connected to input terminal 14b and drain terminal 15. Test circuit 33 is formed to indirectly evaluate the electrical characteristics of control circuit 23 during the manufacturing process. Test circuit 33 is preferably arranged in a region adjacent to input terminal 14b in a plan view.

[0080] For example, when the semiconductor device 1 is mounted on a vehicle, the amplifier circuit 34 is configured to amplify detection signals input to the semiconductor device 1 from various sensors mounted on the vehicle (e.g., pressure sensors, inertial sensors, MR sensors, etc.).

[0081] The structure of the output region 6 side will be described below with reference to FIGS. 6 to 13. FIG. 6 is a plan view showing the output region 6. FIG. 7 is an enlarged view of the area surrounded by the dashed-dotted line VII in FIG. 6. FIG. 8 is a further enlarged view of the area surrounded by the dashed-dotted line VII in FIG. 6. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 7. FIG. 10 is a cross-sectional view taken along line XX in FIG. 7. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 7. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 7. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 7.

[0082] The semiconductor device 1 includes a first trench isolation structure 60 formed in the first main surface 3 so as to define the output region 6. The first trench isolation structure 60 electrically isolates the output region 6 from the control region 7 within the chip 2. In this form, a source potential is applied to the first trench isolation structure 60. The first trench isolation structure 60 is part of the output region 6 and forms the outermost periphery of the output region 6.

[0083] The first trench isolation structure 60 is formed in a ring shape surrounding the output region 6 in plan view. In this embodiment, the first trench isolation structure 60 is formed in a polygonal ring shape (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in plan view. The first trench isolation structure 60 is formed at a distance from the bottom of the drift region 11 towards the first main surface 3, and faces the drain region 10 with a part of the drift region 11 in between.

[0084] 7, in this embodiment, the first trench isolation structure 60 has isolation corners 68 connecting a portion extending in the first direction X and a portion extending in the second direction Y. In this embodiment, the isolation corners 68 (the four corners of the first trench isolation structure 60) are formed in an arc shape. That is, the output region 6 is defined by a quadrangle having four arc-shaped corners. More specifically, the isolation corners 68 preferably have a constant first width W1. The isolation corners 68 are strip-shaped extending in a direction inclined with respect to the first direction X and the second direction Y. Although not shown, the isolation corners 68 may also be strip-shaped extending in a direction inclined with respect to the first direction X and the second direction Y. In this case, for example, the isolation corners 68 may be inclined at 45° with respect to each of the first direction X and the second direction Y.

[0085] The first trench isolation structure 60 has a first width W1. The first width W1 is the width in a direction perpendicular to the extension direction of the first trench isolation structure 60. The first width W1 may be 0.4 μm or more and 2.5 μm or less. The first width W1 may have a value belonging to any one of the ranges of 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The first width W1 is preferably 1.25 μm or more and 1.75 μm or less.

[0086] 9 to 11, the first trench isolation structure 60 has a first depth D1. The first depth D1 may be 1 μm or more and 6 μm or less. The first depth D1 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The first depth D1 is preferably 3 μm or more and 5 μm or less.

[0087] The aspect ratio D1 / W1 of the first trench isolation structure 60 may be greater than 1 and not greater than 5. The aspect ratio D1 / W1 is the ratio of the first depth D1 to the first width W1. The aspect ratio D1 / W1 is preferably 2 or greater.

[0088] The first trench isolation structure 60 includes a first isolation trench 61, a first isolation insulating layer 62, and a first isolation electrode 63. In other words, the first trench isolation structure 60 has a single electrode structure including a single electrode (first isolation electrode 63) embedded in the first isolation trench 61 with an insulator (first isolation insulating layer 62) sandwiched therebetween. The first trench isolation structure 60 may also be referred to as a DTI (deep trench isolation) structure.

[0089] The first isolation trench 61 is formed in the first main surface 3 and defines the wall surface of the first trench isolation structure 60. The first isolation insulating layer 62 covers the wall surface of the first isolation trench 61. The first isolation insulating layer 62 may include a silicon oxide film. The first isolation insulating layer 62 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The first isolation electrode 63 is embedded in the first isolation trench 61 with the first isolation insulating layer 62 sandwiched therebetween. The first isolation electrode 63 may include conductive polysilicon.

[0090] The semiconductor device 1 may include an n-type high-concentration drift region 64 formed in a surface layer portion of the drift region 11 in the output region 6. The high-concentration drift region 64 has a higher n-type impurity concentration than the drift region 11. In this case, the high-concentration drift region 64 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 with a part of the drift region 11 in between. The high-concentration drift region 64 has a bottom located closer to the bottom of the drift region 11 than the bottom wall of the first isolation trench 61. The formation of the high-concentration drift region 64 is optional.

[0091] 6, as described above, the semiconductor device 1 includes an output transistor 20 formed on the first main surface 3 in the output region 6. The output transistor 20 includes a plurality of unit transistors 22 (see FIG. 8) formed in a concentrated manner on the first main surface 3 of the output region 6. The following configuration will be described as components of the semiconductor device 1, but they are also components of the output transistor 20.

[0092] 9 to 13, semiconductor device 1 includes a p-type (second conductivity type) first body region (body region) 67 formed in a surface layer portion of drift region 11 in output region 6. First body region 67 extends in a layered form along first main surface 3 throughout output region 6, and is connected to a wall surface of first trench isolation structure 60. That is, in this embodiment, first body region 67 is not formed in a region outside first trench isolation structure 60.

[0093] The first body region 67 is formed shallower than the first trench isolation structure 60, and has a bottom located closer to the first main surface 3 than the bottom wall of the first trench isolation structure 60. The bottom of the first body region 67 is preferably located closer to the first main surface 3 than the middle of the depth range of the first trench isolation structure 60.

[0094] 6 to 8, the semiconductor device 1 includes a plurality of trench gate structures 70 formed on the first main surface 3 in the output region 6. The plurality of trench gate structures 70 are formed inward of the output region 6 at intervals from the first trench isolation structure 60. The plurality of trench gate structures 70 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of trench gate structures 70 are arranged in a stripe shape extending in the second direction Y. The plurality of trench gate structures 70 have a first end portion on one side in the longitudinal direction (second direction Y) and a second end portion (not shown in FIG. 7) on the other side in the longitudinal direction (second direction Y).

[0095] 7 to 10, the plurality of trench gate structures 70 have a second width W2. The second width W2 is the width in a direction perpendicular to the extension direction of the trench gate structures 70 (i.e., the first direction X). The second width W2 may be approximately equal to the first width W1 of the first trench isolation structure 60. The second width W2 is preferably equal to or smaller than the first width W1. It is particularly preferable that the second width W2 be smaller than the first width W1.

[0096] The second width W2 may be 0.4 μm or more and 2 μm or less. The second width W2 may have a value belonging to any one of the ranges of 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The second width W2 is preferably 0.8 μm or more and 1.2 μm or less.

[0097] The trench gate structures 70 are arranged in the first direction X at a first interval I1. The first interval I1 is also the mesa width of the mesa portion defined in the region between two adjacent trench gate structures 70. The first interval I1 is preferably equal to or smaller than the first width W1 of the first trench isolation structure 60. The first interval I1 is preferably equal to or smaller than the second width W2. It is particularly preferable that the first interval I1 be smaller than the second width W2. The first interval I1 may be equal to or larger than 0.5 μm and equal to or smaller than 2 μm.

[0098] The trench gate structure 70 has a second depth D2. The second depth D2 may be approximately equal to the first depth D1 of the first trench isolation structure 60. Preferably, the second depth D2 is equal to or less than the first depth D1. It is particularly preferred that the second depth D2 be less than the first depth D1.

[0099] The second depth D2 may be 1 μm or more and 6 μm or less. The second depth D2 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The second depth D2 is preferably 2.5 μm or more and 4.5 μm or less.

[0100] The internal configuration of one trench gate structure 70 will be described below. The trench gate structure 70, like the first trench isolation structure 60, may be referred to as a DTI (deep trench isolation) structure. That is, the aspect ratio D2 / W2 of the trench gate structure 70 may be greater than 1 and not greater than 5. The aspect ratio D2 / W2 is the ratio of the second depth D2 to the second width W2. The aspect ratio D2 / W2 is preferably 2 or greater.

[0101] More specifically, the trench gate structure 70 includes a gate trench 71, an insulating layer 72, an upper electrode 73, a lower electrode 74, and an intermediate insulating layer 75. In other words, the trench gate structure 70 has a multi-electrode structure including multiple electrodes (upper electrode 73 and lower electrode 74) vertically embedded in the gate trench 71 with an insulator (insulating layer 72 and intermediate insulating layer 75) sandwiched therebetween.

[0102] The gate trench 71 is formed in the first main surface 3 and defines a wall surface of the trench gate structure 70. The insulating layer 72 covers the wall surface of the gate trench 71. The insulating layer 72 includes an upper insulating layer 76 and a lower insulating layer 77.

[0103] The upper insulating layer 76 covers the wall surface of the gate trench 71 on the opening side relative to the bottom of the first body region 67. The upper insulating layer 76 partially covers the wall surface of the gate trench 71 on the bottom wall side relative to the bottom of the first body region 67. The upper insulating layer 76 is thinner than the first isolation insulating layer 62. The upper insulating layer 76 is formed as a gate insulating layer. The upper insulating layer 76 may include a silicon oxide film. The upper insulating layer 76 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0104] The lower insulating layer 77 covers the wall surface of the gate trench 71 on the bottom wall side relative to the bottom of the first body region 67. The lower insulating layer 77 is thicker than the upper insulating layer 76. The thickness of the lower insulating layer 77 may be approximately equal to the thickness of the first isolation insulating layer 62. The lower insulating layer 77 may include a silicon oxide film. The lower insulating layer 77 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0105] The upper electrode 73 is embedded in the opening side of the gate trench 71 with an insulating layer 72 sandwiched therebetween. Specifically, the upper electrode 73 is embedded in the opening side of the gate trench 71 with an upper insulating layer 76 sandwiched therebetween, and faces the first body region 67 with the upper insulating layer 76 sandwiched therebetween. The upper electrode 73 may include conductive polysilicon.

[0106] The lower electrode 74 is embedded in the bottom wall of the gate trench 71 with an insulating layer 72 sandwiched therebetween. Specifically, the lower electrode 74 is embedded in the bottom wall of the gate trench 71 with a lower insulating layer 77 sandwiched therebetween, and faces the drift region 11 with the lower insulating layer 77 sandwiched therebetween. The lower electrode 74 of the outermost trench gate structure 70 faces the drift region 11 with the lower insulating layer 77 sandwiched therebetween.

[0107] When the semiconductor device 1 includes an n-type high-concentration drift region 64 formed in the surface layer portion of the drift region 11 in the output region 6, the lower electrode 74 may be embedded in the bottom wall side of the gate trench 71 with a lower insulating layer 77 in between, and may face the high-concentration drift region 64 with the lower insulating layer 77 in between. The lower electrode 74 of the outermost trench gate structure 70 may face the high-concentration drift region 64 with the lower insulating layer 77 in between.

[0108] The lower electrode 74 has an upper end portion that protrudes from the lower insulating layer 77 toward the upper electrode 73 so as to engage with the bottom portion of the upper electrode 73. The upper end portion of the lower electrode 74 faces the upper insulating layer 76 across the lower end portion of the upper electrode 73 in the lateral direction along the first main surface 3. The lower electrode 74 may include conductive polysilicon.

[0109] The intermediate insulating layer 75 is interposed between the upper electrode 73 and the lower electrode 74, and electrically insulates the upper electrode 73 and the lower electrode 74 within the gate trench 71. The intermediate insulating layer 75 is continuous with the upper insulating layer 76 and the lower insulating layer 77. The intermediate insulating layer 75 is thinner than the lower insulating layer 77. The intermediate insulating layer 75 may include a silicon oxide film. The intermediate insulating layer 75 preferably includes a silicon oxide film made of an oxide of the lower electrode 74.

[0110] 7 and 8, the semiconductor device 1 includes a plurality of channel cells 78 formed on both sides of each trench gate structure 70 as control targets of each trench gate structure 70. In this embodiment, the two channel cells 78 arranged on both sides of one trench gate structure 70 are controlled by that one trench gate structure 70 and are not controlled by the other trench gate structure 70.

[0111] 8, the plurality of channel cells 78 are formed in a region along the inner portion of the trench gate structure 70 at intervals from both ends of the trench gate structure 70 in the longitudinal direction (second direction Y). The plurality of channel cells 78 expose the first body region 67 from a region of the first main surface 3 that is sandwiched between both ends of the plurality of trench gate structures 70.

[0112] Each channel cell 78 includes a plurality of n-type source regions 79 and a plurality of p-type contact regions 80. In FIGS. 7 and 8, the source regions 79 are hatched for clarity. The contact regions 80 may also be referred to as "back gate regions." The n-type impurity concentration of each source region 79 is 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following:

[0113] The multiple source regions 79 are arranged at intervals along each trench gate structure 70. The multiple source regions 79 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3, and face the upper electrode 73 with the insulating layer 72 (upper insulating layer 76) interposed therebetween.

[0114] Each contact region 80 has a higher p-type impurity concentration than the first body region 67. The p-type impurity concentration of each contact region 80 is 1×10 18 cm -3 More than 1×10 21 cm -3 The plurality of contact regions 80 are arranged alternately with the plurality of source regions 79 along each trench gate structure 70. The plurality of contact regions 80 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3, and face the upper electrode 73 with the insulating layer 72 (upper insulating layer 76) interposed therebetween.

[0115] With respect to two channel cells 78 formed on both sides of one trench gate structure 70, the source regions 79 in one channel cell 78 face the source regions 79 in the other channel cell 78 across the trench gate structure 70. Furthermore, the contact regions 80 in one channel cell 78 face the contact regions 80 in the other channel cell 78 across the trench gate structure 70.

[0116] Of course, the plurality of source regions 79 in one channel cell 78 may face the plurality of contact regions 80 in the other channel cell 78 across the trench gate structure 70. Also, the plurality of contact regions 80 in one channel cell 78 may face the plurality of source regions 79 in the other channel cell 78 across the trench gate structure 70.

[0117] With respect to two channel cells 78 interposed between two trench gate structures 70, a plurality of source regions 79 in one channel cell 78 are connected in the first direction X to a plurality of contact regions 80 in the other channel cell 78. Also, a plurality of contact regions 80 in one channel cell 78 are connected in the first direction X to a plurality of source regions 79 in the other channel cell 78.

[0118] Of course, the plurality of source regions 79 in one channel cell 78 may be connected in the first direction X to the plurality of source regions 79 in the other channel cell 78. Also, the plurality of contact regions 80 in one channel cell 78 may be connected in the first direction X to the plurality of contact regions 80 in the other channel cell 78.

[0119] Of the two channel cells 78 formed on both sides of the outermost trench gate structure 70, the channel cell 78 located on the inner side faces the drift region 11 across a part of the first body region 67 in the thickness direction. On the other hand, the channel cell 78 located on the outer side does not include a source region 79, but includes only a contact region 80. This suppresses the formation of a current path in the region between the first trench isolation structure 60 and the outermost trench gate structure 70.

[0120] 7 and 8, the output transistor 20 includes a plurality of unit transistors 22. Each of the plurality of unit transistors 22 includes one trench gate structure 70 and two channel cells 78 formed on both sides of the trench gate structure 70. For each unit transistor 22, the trench gate structure 70 forms a unit gate, the plurality of source regions 79 (two channel cells 78) form a unit source, and the drain region 10 (drift region 11) forms a unit drain.

[0121] 3 and 4, the output transistor 20 includes first system transistors 21A and second system transistors 21B. The first system transistors 21A include a plurality of unit transistors 22 that have been grouped together as targets for individual control from a plurality of unit transistors 22. The second system transistors 21B include a plurality of unit transistors 22 that have been grouped together as targets for individual control from a plurality of unit transistors 22 other than the first system transistors 21A.

[0122] In this embodiment, the output transistor 20 includes a plurality of block regions 81 provided in the output region 6. The plurality of block regions 81 include a plurality of first block regions 81A and a plurality of second block regions 81B. The plurality of first block regions 81A are regions where one or more (a plurality in this embodiment) unit transistors 22 for the first system transistors 21A are arranged, respectively. The plurality of second block regions 81B are regions where one or more (a plurality in this embodiment) unit transistors 22 for the second system transistors 21B are arranged.

[0123] The multiple first block regions 81A are arranged at intervals in the first direction X. The number of unit transistors 22 in each first block region 81A is arbitrary. In this embodiment, two unit transistors 22 are arranged in each first block region 81A. As the number of unit transistors 22 in each first block region 81A increases, the amount of heat generated in each first block region 81A increases. Therefore, it is preferable that the number of unit transistors 22 in each first block region 81A be between two and five.

[0124] The second block regions 81B are arranged alternately with the first block regions 81A in the first direction X so as to sandwich one first block region 81A therebetween. This allows the second block regions 81B to thin out heat generating areas caused by the first block regions 81A, and at the same time, allows the first block regions 81A to thin out heat generating areas caused by the second block regions 81B.

[0125] Each second block region 81B may have any number of unit transistors 22. In this embodiment, two unit transistors 22 are arranged in each second block region 81B. As the number of unit transistors 22 in each second block region 81B increases, the amount of heat generated in each second block region 81B increases.

[0126] Therefore, the number of unit transistors 22 in each second block region 81B is preferably between 2 and 5. In consideration of in-plane temperature variations in the output region 6, the number of unit transistors 22 in the second block region 81B is preferably the same as the number of unit transistors 22 in the first block region 81A.

[0127] 6 and 7, the semiconductor device 1 includes two trench connection structures 90 that connect both ends of a plurality of (two in this embodiment) trench gate structures 70 to be organized (grouped) in each block region 81. That is, the two trench connection structures 90 connect both ends of the plurality of trench gate structures 70 to be organized as system transistors 21, respectively.

[0128] 6, the trench connection structure 90 on one side connects, in an arch shape, first ends of a plurality of (two in this embodiment) corresponding trench gate structures 70 in a plan view. The trench connection structure 90 on the other side connects, in an arch shape, second ends of a plurality of (two in this embodiment) corresponding trench gate structures 70 in a plan view.

[0129] Specifically, the trench connection structure 90 on one side has a first portion extending in a first direction X and a plurality of (two in this embodiment) second portions extending in a second direction Y. The first portion faces first ends of the plurality of trench gate structures 70 in a plan view. The plurality of second portions extend from the first portion toward the plurality of first ends so as to be connected to the plurality of first ends.

[0130] The other trench connection structure 90 has a first portion extending in a first direction X and a plurality of (two in this embodiment) second portions extending in a second direction Y. The first portion faces the second ends of the plurality of trench gate structures 70 in a plan view. The plurality of second portions extend from the first portion toward the plurality of second ends so as to be connected to the plurality of second ends. The plurality of trench connection structures 90, together with the plurality of trench gate structures 70, form a ring-shaped or ladder-shaped trench structure in each block region 81.

[0131] Referring to FIG. 6, a plurality of trench connection structures 90 are formed at intervals from the bottom of drift region 11 toward first main surface 3, and face drain region 10 with part of drift region 11 interposed therebetween.

[0132] 7, the plurality of trench connection structures 90 may be formed with approximately the same width and depth as the trench gate structure 70. Of course, the first and second portions of the trench connection structure 90 may have different widths. For example, the second portion of the trench connection structure 90 may be formed narrower than the first portion of the trench connection structure 90.

[0133] In this case, the first portion may have a width approximately equal to the width of the first trench isolation structure 60, and the second portion may have a width approximately equal to the width of the trench gate structure 70. Furthermore, in this case, the first portion may have a depth approximately equal to the depth of the first trench isolation structure 60, and the second portion may have a depth approximately equal to the depth of the trench gate structure 70.

[0134] 6, the trench connection structure 90 on the other side has the same structure as the trench connection structure 90 on one side, except that it is connected to the second end of the trench gate structure 70. Hereinafter, the configuration of the trench connection structure 90 on one side will be described, and a description of the configuration of the trench connection structure 90 on the other side will be omitted.

[0135] 7 and 11 to 13, trench connection structure 90 includes a connection trench 91, a connection insulating layer 92, and a connection electrode 93. Connection trench 91 is formed in first main surface 3 and defines a wall surface of trench connection structure 90. Connection trench 91 is connected to a plurality of gate trenches 71.

[0136] The connection insulating layer 92 covers the wall surface of the connection trench 91. The connection insulating layer 92 is connected to the upper insulating layer 76, the lower insulating layer 77, and the intermediate insulating layer 75 at the communicating portion between the connection trench 91 and the gate trench 71. The connection insulating layer 92 is thicker than the upper insulating layer 76. The thickness of the connection insulating layer 92 may be approximately equal to the thickness of the lower insulating layer 77. The connection insulating layer 92 may include a silicon oxide film. The connection insulating layer 92 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0137] The connection electrode 93 is embedded in the connection trench 91 with a connection insulating layer 92 sandwiched therebetween, and faces the drift region 11 and the first body region 67 with the connection insulating layer 92 sandwiched therebetween. The connection electrode 93 is connected to the lower electrode 74 at the communicating portion between the connection trench 91 and the gate trench 71, and is electrically insulated from the upper electrode 73 by an intermediate insulating layer 75. The connection electrode 93 is formed by an extension portion of the lower electrode 74 that is extended from inside the gate trench 71 into the connection trench 91. The connection electrode 93 may include conductive polysilicon.

[0138] 9 and 10 , semiconductor device 1 includes a main surface insulating layer 94 that selectively covers first main surface 3 in output region 6. Main surface insulating layer 94 is connected to insulating layer 72 (upper insulating layer 76) and connecting insulating layer 92, and exposes first isolated electrode 63, upper electrode 73, and connecting electrode 93.

[0139] The main surface insulating layer 94 is thinner than the first isolation insulating layer 62. The main surface insulating layer 94 is thinner than the lower insulating layer 77. The main surface insulating layer 94 is thinner than the connection insulating layer 92. The main surface insulating layer 94 may have a thickness approximately equal to that of the upper insulating layer 76. The main surface insulating layer 94 may include a silicon oxide film. The main surface insulating layer 94 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0140] 9 to 13, semiconductor device 1 includes a field insulating layer 95 that selectively covers first main surface 3 inside and outside output region 6. Field insulating layer 95 is thicker than main surface insulating layer 94. Field insulating layer 95 is thicker than upper insulating layer 76. Field insulating layer 95 may have a thickness approximately equal to that of first isolation insulating layer 62. Field insulating layer 95 may include a silicon oxide film. Field insulating layer 95 may include a silicon oxide film made of an oxide of chip 2, or may include a silicon oxide film formed by a CVD method.

[0141] The field insulating layer 95 covers the first main surface 3 along the inner wall of the first trench isolation structure 60 within the output region 6, and is connected to the first isolation insulating layer 62, the connection insulating layer 92, and the main surface insulating layer 94. The field insulating layer 95 covers the first main surface 3 along the outer wall of the first trench isolation structure 60 outside the output region 6, and is integrally connected to the first isolation insulating layer 62. The field insulating layer 95 is drawn out from the first isolation trench 61 in the horizontal direction along the first main surface 3.

[0142] 9 to 13, the interlayer insulating layer 12 described above covers the first trench isolation structure 60, the trench gate structure 70, the trench connection structure 90, the main surface insulating layer 94, and the field insulating layer 95 in the output region 6.

[0143] The interlayer insulating layer 12 is formed of an insulator such as silicon oxide or silicon nitride. The interlayer insulating layer 12 may include multiple insulating layers. The multiple insulating layers may be divided based on the hierarchical levels of the wiring layers formed on their respective main surfaces. For example, the insulating layer on which the first wiring layer of a multilayer wiring structure formed inside the interlayer insulating layer 12 is formed may be the first insulating layer, and the insulating layer on which the second wiring layer is formed may be the second insulating layer. The number of layers in the interlayer insulating layer 12 may increase as the number of hierarchical levels of the multilayer wiring structure increases.

[0144] In this embodiment, the interlayer insulating layer 12 includes a first insulating layer 84 in contact with the upper electrode 73, a second insulating layer 85 laminated on the first insulating layer 84, and a third insulating layer 86 laminated on the second insulating layer 85. The first insulating layer 84, the second insulating layer 85, and the third insulating layer 86 may be USG films formed by a high density plasma CVD method (HDP-USG: High Density Plasma CVD-Undoped Silica Glass) film.

[0145] The semiconductor device 1 includes a first wiring layer 16 and a second wiring layer 17 disposed in an interlayer insulating layer 12. The first wiring layer 16 is formed on a first insulating layer 84, and the second wiring layer 17 is formed on a second insulating layer 85. As will be described later, the first wiring layer 16 includes a first gate wiring 181 and a first source wiring 191. The second wiring layer 17 includes a second gate wiring 182 and a second source wiring 192.

[0146] 6, as described above, the semiconductor device 1 includes a plurality of gate wirings 18 arranged in the interlayer insulating layer 12. The plurality of gate wirings 18 are routed to the output region 6 and the control region 7, and are electrically connected to the output transistors 20 in the output region 6, and are electrically connected to the control circuit 23 (see FIG. 4; gate control circuit 24) in the control region 7. The plurality of gate wirings 18 individually transmit a plurality of gate signals generated by the control circuit 23 (see FIG. 4; gate control circuit 24) to the output transistors 20.

[0147] The plurality of gate wirings 18 include first-system gate wirings 18A and second-system gate wirings 18B. The first-system gate wirings 18A individually transmit gate signals to the first-system transistors 21A. The first-system gate wirings 18A are electrically connected to the plurality of trench gate structures 70 for the first-system transistors 21A through a plurality of via electrodes 97 arranged in the interlayer insulating layer 12. Specifically, the first-system gate wirings 18A are electrically connected to the corresponding plurality of upper electrodes 73 and the corresponding plurality of connection electrodes 93 through the plurality of via electrodes 97.

[0148] That is, the upper electrode 73 and the lower electrode 74 for the first system transistor 21A are simultaneously turned on and off by the same gate signal. This suppresses the voltage drop between the upper electrode 73 and the lower electrode 74, and suppresses undesired electric field concentration. As a result, the decrease in breakdown voltage caused by the electric field concentration is suppressed.

[0149] The second-system gate wiring 18B transmits gate signals individually to the second-system transistors 21B, electrically independent from the first-system gate wiring 18A. The second-system gate wiring 18B is electrically connected to the plurality of trench gate structures 70 for the second-system transistors 21B through a plurality of via electrodes 97 arranged in the interlayer insulating layer 12. Specifically, the second-system gate wiring 18B is electrically connected to the corresponding plurality of upper electrodes 73 and the corresponding plurality of connection electrodes 93 through the plurality of via electrodes 97.

[0150] That is, the upper electrode 73 and the lower electrode 74 for the second system transistor 21B are simultaneously turned on and off by the same gate signal. This suppresses a voltage drop between the upper electrode 73 and the lower electrode 74, thereby suppressing undesired electric field concentration. As a result, a decrease in breakdown voltage caused by the electric field concentration is suppressed.

[0151] 10 to 13, the gate wiring 18 includes a first gate wiring 181 included in the first wiring layer 16 and a second gate wiring 182 included in the second wiring layer 17. The first gate wiring 181 may include a first-system gate wiring 18A and a second-system gate wiring 18B. The second gate wiring 182 may include the first-system gate wiring 18A and the second-system gate wiring 18B.

[0152] 9 to 13, semiconductor device 1 includes a source wiring 19 disposed in interlayer insulating layer 12. Source wiring 19 is electrically connected to source terminal 13, first trench isolation structure 60, and a plurality of channel cells 78. Specifically, source wiring 19 is electrically connected to first trench isolation structure 60 and a plurality of channel cells 78 through a plurality of via electrodes 97 disposed in interlayer insulating layer 12.

[0153] 7, the via electrode 97 for each channel cell 78 is arranged so as to straddle two adjacent channel cells 78, and is formed in a strip shape extending along each channel cell 78 in plan view. As a result, the source terminal 13 is electrically connected to the system sources of all the system transistors 21 (the unit sources of the unit transistors 22).

[0154] 9 to 13, the source wiring 19 includes a first source wiring 191 included in the first wiring layer 16 and a second source wiring 192 included in the second wiring layer 17. The first source wiring 191 and the second source wiring 192 are electrically connected through a via electrode (not shown). A plurality of the first source wiring 191 and the second source wiring 192 are formed so as to overlap, in plan view, over substantially the entire region of the first main surface 3 where the output transistor 20 is formed.

[0155] 6, as described above, the semiconductor device 1 further includes a first temperature detection region 8A defined in the inner portion of the output region 6. A first temperature sensing diode 9A is formed in the first temperature detection region 8A. The first temperature sensing diode 9A includes a plurality of diodes Di1 and Di2 connected in series in the forward direction.

[0156] In this embodiment, the number of diodes (diodes Di1 and Di2) is two. In other words, the first temperature sensitive diode 9A includes a first diode Di1 and a second diode Di2 connected in series. The first diode Di1 and the second diode Di2 are aligned in the first direction X. The first diode Di1 is arranged on one side of the first direction X (the third side surface 5C (FIG. 1) side), and the second diode Di2 is arranged on the other side of the first direction X (the fourth side surface 5D (FIG. 1) side).

[0157] In this embodiment, the first diode Di1 and the second diode Di2 are each formed of a single diode element, and have the same size and structure as each other.

[0158] 14 is an enlarged view of a region surrounded by dashed-dotted line XIV in FIG. 6. FIG. 15A is a plan view showing the layout of the first wiring layer 16, and corresponds to FIG. 14. FIG. 15B is a plan view showing the layout of the first wiring layer 16, illustrating a region adjacent to one side (first side surface 5C (FIG. 1) side) of the region shown in FIG. 15A in the first direction X. FIG. 15C is a cross-sectional view taken along line XVC-XVC in FIG. 15B. FIG. 16 is an enlarged view of a portion surrounded by dashed-dotted line XVI in FIG. 14. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 16. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 16. FIG. 19A is a cross-sectional view taken along line XIX-XIX in FIG. 16. FIG. 19B is a cross-sectional view taken along line XIXB-XIXB in FIG. 16. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 16. Fig. 21A is a cross-sectional view taken along line XXIA-XXIA in Fig. 14. Fig. 21B is a cross-sectional view taken along line XXIB-XXIB in Fig. 14. Fig. 22 is an electrical circuit diagram of a first temperature sensitive diode 9A according to the first embodiment. Fig. 23 is an electrical circuit diagram of a mesa portion 110. In Figs. 14 and 16, the cathode region 179 is hatched for clarity.

[0159] 14, the semiconductor device 1 includes second trench isolation structures (isolation structures) 100 as an example of a region isolation structure that defines the first temperature detection region 8A on the first main surface 3. The number of second trench isolation structures 100 is two. The two second trench isolation structures 100 surround the first diode Di1 and the second diode Di2, respectively. The two second trench isolation structures 100 have the same structure.

[0160] The first diode Di1 is formed in an inner region of one of the second trench isolation structures 100. The second diode Di2 is formed in an inner region of the other of the second trench isolation structures 100. One of the second trench isolation structures 100 may be referred to as a "DTI (deep trench isolation) structure." The second trench isolation structures 100 may also be referred to as an "inner isolation structure" and a "diode isolation structure."

[0161] One second trench isolation structure 100 electrically isolates each of the diodes Di1 and Di2 from the region outside the second trench isolation structure 100. In other words, the two second trench isolation structures 100 electrically isolate the first diode Di1 and the second diode Di2 from each other. That is, the first diode Di1 and the second diode Di2 are formed so as to be electrically isolated from each other. The first diode Di1 functions as a single element diode because it is surrounded by one second trench isolation structure 100. The second diode Di2 functions as a single element diode because it is surrounded by one second trench isolation structure 100.

[0162] Each second trench isolation structure 100 is formed in a ring shape surrounding the outer peripheries of the diodes Di1 and Di2 in plan view. In this embodiment, the second trench isolation structure 100 is formed in a substantially quadrangular ring shape having four sides parallel to the first to fourth side surfaces 5A to 5D in plan view. The second trench isolation structure 100 may have any planar shape, and may be formed in a polygonal ring shape.

[0163] The structure of one of the first diode Di1 and the second diode Di2, the first diode Di1, will be described in detail below. In addition to the description of the first diode Di1, the structure of one second trench isolation structure 100 surrounding the first diode Di1 will also be described in detail.

[0164] Since the second diode Di2 has the same structure as the first diode Di1, a detailed description of the structure of the second diode Di2 will be omitted. Also, a detailed description of the structure of the second trench isolation structure 100 surrounding the second diode Di2 will be omitted.

[0165] 17 etc., the second trench isolation structure 100 includes a second isolation trench 101, a second isolation insulating layer 102, and a second isolation electrode 103. That is, the second trench isolation structure 100 has a single electrode structure including a single electrode embedded in the second isolation trench 101 with an insulator sandwiched therebetween.

[0166] The second isolation trench 101 is dug down from the first main surface 3 toward the second main surface 4. The second isolation trench 101 is formed at an interval from the bottom of the drift region 11 toward the first main surface 3. The second isolation insulating layer 102 covers the wall surface of the second isolation trench 101. The second isolation insulating layer 102 may include a silicon oxide film. The second isolation insulating layer 102 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The second isolation electrode 103 is buried in the second isolation trench 101 with the second isolation insulating layer 102 sandwiched therebetween. The second isolation electrode 103 may include conductive polysilicon.

[0167] The second trench isolation structure 100 has a third width W3 and a third depth D3. The third depth D3 may be the same as the first depth D1 (FIG. 10, etc.) (D3=D1). The third depth D3 is preferably greater than the second depth D2 (FIG. 10, etc.) (D3>D2). The third width W3 is the width in a direction perpendicular to the direction in which the second trench isolation structure 100 extends in a plan view. The third width W3 may be the same as the first width W1 (FIG. 10, etc.) (W3=W1).

[0168] The aspect ratio D3 / W3 of the second trench isolation structure 100 may be greater than 1 and less than or equal to 5. The aspect ratio D3 / W3 is the ratio of the third depth D3 to the third width W3. The aspect ratio D3 / W3 is preferably greater than or equal to 2. The bottom wall of the second trench isolation structure 100 is preferably spaced from the bottom of the drift region 11 by a distance of 1 μm to 5 μm.

[0169] 16, the second trench isolation structure 100 has corners that connect portions extending in the first direction X and the second direction Y in an arc shape (curved shape). In this embodiment, the four corners of the second trench isolation structure 100 are formed in an arc shape. The corners of the second trench isolation structure 100 preferably have a constant third width W3 along the arc direction.

[0170] 17 and other figures, second isolation trench 101 includes a sidewall and a bottom wall. The angle that the sidewall of second isolation trench 101 forms with first main surface 3 within chip 2 may be 90° or more and 92° or less. Second isolation trench 101 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. Corners of the bottom wall of second isolation trench 101 are preferably formed in a curved shape. The entire bottom wall of second isolation trench 101 may be formed in a curved shape toward second main surface 4.

[0171] The second isolation insulating layer 102 is formed on the wall surface of the second isolation trench 101. Specifically, the second isolation insulating layer 102 is formed in the form of a film on the entire wall surface of the second isolation trench 101, and defines a recess space within the second isolation trench 101. The second isolation insulating layer 102 preferably includes a silicon oxide film. It is particularly preferable that the second isolation insulating layer 102 includes a silicon oxide film made of an oxide of the chip 2.

[0172] The second isolated electrode 103 is embedded in the second isolation trench 101 as an integrated member with the second isolation insulating layer 102 sandwiched therebetween. In this embodiment, the second isolated electrode 103 includes conductive polysilicon. A source potential is applied to the second isolated electrode 103. The second isolated electrode 103 has an electrode surface (isolated electrode surface) exposed from the second isolation trench 101. The electrode surface of the second isolated electrode 103 may be recessed in a curved shape toward the bottom wall of the second isolation trench 101. The electrode surface of the second isolated electrode 103 is preferably spaced from the first main surface 3 to the bottom wall of the second isolation trench 101 in the depth direction of the second isolation trench 101.

[0173] The field insulating layer 95 covers the first main surface 3 in the first temperature detection region 8A. The field insulating layer 95 covers the first main surface 3 along the inner wall of the second trench isolation structure 100 in the first temperature detection region 8A and is connected to the second isolation / insulation layer 102.

[0174] The semiconductor device 1 includes a second body region (body region) 167 formed in the first temperature detection region 8A in the surface layer portion of the first main surface 3. The p-type impurity concentration of the second body region 167 is 1×10 16 cm -3 More than 1×10 18 cm -3or less. The p-type impurity concentration of the second body region 167 is preferably approximately equal to the p-type impurity concentration of the first body region 67. The second body region 167 preferably has approximately the same thickness (depth) as the first body region 67. With this structure, the second body region 167 can be formed simultaneously with the first body region 67. The second body region 167 is formed over the entire surface layer portion of the first main surface 3 in the first temperature detection region 8A. The second body region 167 is in contact with the inner circumferential wall of the second trench isolation structure 100.

[0175] 16, the semiconductor device 1 includes a plurality of diode trench structures 170 formed on the first main surface 3 in the first temperature detection region 8A. The diode trench structures 170 are electrically independent from the trench gate structure 70 of the output transistor 20. The number of the plurality of diode trench structures 170 may be any number as long as it is plural, and is adjusted according to the size of the first temperature detection region 8A. In this embodiment, the semiconductor device 1 includes four diode trench structures 170.

[0176] The multiple diode trench structures 170 are arranged at intervals in the first direction X in plan view, and are each formed in a band shape extending in the second direction Y. That is, the multiple diode trench structures 170 are formed in a stripe shape extending in the second direction Y in plan view. Each of the multiple diode trench structures 170 has a first end 170a on one side and a second end 170b on the other side in the longitudinal direction (second direction Y).

[0177] 17, the plurality of diode trench structures 170 have a fourth width W4. The fourth width W4 is the width in a direction perpendicular to the extension direction of the diode trench structures 170 (i.e., the first direction X). In this embodiment, the fourth width W4 is approximately equal to the second width W2 (FIG. 10) of the trench gate structure 70. The fourth width W4 is preferably equal to or less than the third width W3. It is particularly preferable that the fourth width W4 be less than the third width W3.

[0178] The fourth width W4 may be 0.4 μm or more and 2 μm or less. The fourth width W4 may have a value belonging to any one of the ranges of 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The fourth width W4 is preferably 0.8 μm or more and 1.2 μm or less.

[0179] The plurality of diode trench structures 170 are arranged in the first direction X at a second interval I2. The second interval I2 also corresponds to the mesa width of the mesa portion 110, which will be described next. The second interval I2 is preferably equal to or smaller than the second width W2 of the second trench isolation structure 100. The second interval I2 is preferably equal to or smaller than the fourth width W4. It is particularly preferable that the second interval I21 be smaller than the fourth width W4. The second interval I2 may be equal to or larger than 0.5 μm and equal to or smaller than 2 μm.

[0180] The diode trench structure 170 has a fourth depth D4. The fourth depth D4 may be approximately equal to the third depth D3 of the second trench isolation structure 100. The fourth depth D4 is preferably equal to or less than the third depth D3. It is particularly preferred that the fourth depth D4 be less than the third depth D3.

[0181] The fourth depth D4 may be 1 μm or more and 6 μm or less. The fourth depth D4 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The fourth depth D4 is preferably 2.5 μm or more and 4.5 μm or less. A mesa portion 110 formed by a part of the chip 2 (drift region 11) is defined in the region between two adjacent diode trench structures 170. One mesa portion 110 is formed by being sandwiched between two adjacent diode trench structures 170. The mesa portion 110 may also be referred to as an "element mesa portion." The width of the mesa portion 110 in the first direction X is determined by the interval I2 between the diode trench structures 170.

[0182] The multiple mesa portions 110 are arranged at intervals in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. In other words, the multiple mesa portions 110 are formed in a stripe shape extending in the second direction Y in a plan view.

[0183] The internal configuration of one diode trench structure 170 will be described below. The aspect ratio D4 / W4 of the diode trench structure 170 may be greater than 1 and less than or equal to 5. The aspect ratio D4 / W4 is the ratio of the fourth depth D4 to the fourth width W4. The aspect ratio D4 / W4 is preferably 2 or greater.

[0184] The diode trench structure 170 includes a diode trench 171, a first insulating layer 172, a first upper electrode 173, a first lower electrode 174, and a first intermediate insulating layer 175. In other words, the diode trench structure 170 has a multi-electrode structure including a plurality of electrodes (first upper electrode 173 and first lower electrode 174) vertically embedded in the diode trench 171 with an insulator (first insulating layer 172 and first intermediate insulating layer 175) sandwiched therebetween.

[0185] The diode trench 171 is formed in the first main surface 3 and defines the wall surface of the diode trench structure 170. The first insulating layer 172 covers the wall surface of the diode trench 171. The first insulating layer 172 includes a first upper insulating layer 176 and a first lower insulating layer 177.

[0186] The first upper insulating layer 176 covers the wall surface of the diode trench 171 on the opening side relative to the bottom of the second body region 167. The first upper insulating layer 176 partially covers the wall surface of the diode trench 171 on the bottom wall side relative to the bottom of the second body region 167. The first upper insulating layer 176 is thinner than the second isolation insulating layer 102. The first upper insulating layer 176 is formed as a gate insulating layer. The first upper insulating layer 176 may include a silicon oxide film. The first upper insulating layer 176 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0187] The first lower insulating layer 177 covers the wall surface on the bottom wall side of the diode trench 171 relative to the bottom of the second body region 167. The first lower insulating layer 177 is thicker than the first upper insulating layer 176. The thickness of the first lower insulating layer 177 may be approximately equal to the thickness of the second isolation / insulation layer 102. The first lower insulating layer 177 may include a silicon oxide film. The first lower insulating layer 177 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0188] The first upper electrode 173 is embedded in the opening side of the diode trench 171 with the first insulating layer 172 sandwiched therebetween. Specifically, the first upper electrode 173 is embedded in the opening side of the diode trench 171 with the first upper insulating layer 176 sandwiched therebetween, and faces the second body region 167 with the first upper insulating layer 176 sandwiched therebetween. The first upper electrode 173 may include conductive polysilicon. The first upper electrode 173 is formed as a high-potential electrode. It is preferable that a potential other than a gate potential (gate signal) be applied to the first upper electrode 173. An anode potential may be applied to the first upper electrode 173.

[0189] The first lower electrode 174 is embedded in the bottom wall of the diode trench 171 with the first insulating layer 172 sandwiched therebetween. Specifically, the first lower electrode 174 is embedded in the bottom wall of the diode trench 171 with the first lower insulating layer 177 sandwiched therebetween, and faces the drift region 11 with the first lower insulating layer 177 sandwiched therebetween. The first lower electrode 174 of the outermost diode trench structure 170 faces the drift region 11 with the first lower insulating layer 177 sandwiched therebetween.

[0190] The first lower electrode 174 has an upper end that protrudes from the first lower insulating layer 177 toward the first upper electrode 173 so as to engage with the bottom of the first upper electrode 173. The upper end of the first lower electrode 174 faces the first upper insulating layer 176 across the lower end of the first upper electrode 173 in the lateral direction along the first main surface 3. The first lower electrode 174 may include conductive polysilicon.

[0191] The first lower electrode 174 may include conductive polysilicon. A potential other than the gate potential (gate signal) is preferably applied to the first lower electrode 174. The first lower electrode 174 is preferably fixed to the same potential as the first upper electrode 173. In other words, an anode potential may be applied to the first lower electrode 174.

[0192] The first intermediate insulating layer 175 is interposed between the first upper electrode 173 and the first lower electrode 174, and electrically insulates the first upper electrode 173 and the first lower electrode 174 within the diode trench 171. The first intermediate insulating layer 175 is continuous with the first upper insulating layer 176 and the first lower insulating layer 177. The first intermediate insulating layer 175 is thinner than the first lower insulating layer 177. The first intermediate insulating layer 175 may include a silicon oxide film. The first intermediate insulating layer 175 preferably includes a silicon oxide film made of an oxide of the first lower electrode 174.

[0193] 14 and 16, as described above, the semiconductor device 1 includes a first temperature-sensitive diode 9A formed in the first temperature detection region 8A (FIG. 16). The first temperature-sensitive diode 9A includes a first diode Di1 and a second diode Di2 (FIG. 14) connected in series. The first diode Di1 and the second diode Di2 have the same structure. The first diode Di1 includes a plurality of unit diodes D. The second diode Di2 includes a plurality of unit diodes D. In this embodiment, the number of unit diodes D included in both the first diode Di1 and the second diode Di2 is three.

[0194] 16 , one unit diode D has a pn junction formed in a surface layer portion of the first main surface 3 in one mesa portion 110. Specifically, the pn junction is formed in a surface layer portion of the second body region 167. In this embodiment, the pn junction is not formed in the mesa region between the second trench isolation structure 100 and the diode trench structure 170.

[0195] One unit diode D has a one-to-one correspondence with one mesa portion 110. One mesa portion 110 is formed so as to be electrically isolated from other mesas 110 by a diode trench structure 170 and a diode connection structure 190, which will be described next. Therefore, one unit diode D can be considered as an independent diode.

[0196] Specifically, one unit diode D includes a p-type anode region 180 and an n-type cathode region 179 formed in a surface layer portion of the second body region 167 (FIG. 17). The cathode region 179 is formed in the surface layer portion of the second body region 167 so as to form a p-n junction with the anode region 180. In this embodiment, the unit diode D includes two anode regions 180 and one cathode region 179. The two anode regions 180 are arranged (arranged) so as to sandwich one cathode region 179 therebetween. There may be a plurality of anode regions 180 and a plurality of cathode regions 179. In this case, the plurality of anode regions 180 may be arranged alternately with the plurality of cathode regions 179 in the second direction Y so as to sandwich one cathode region 179 therebetween. In one mesa portion 110, the total planar area of ​​the anode regions 180 is greater than the total planar area of ​​the cathode regions 179.

[0197] The plurality of anode regions 180 and the plurality of cathode regions 179 are in contact with the plurality of diode trench structures 170. The plurality of anode regions 180 and the plurality of cathode regions 179 face the first upper electrode 173 with the first upper insulating layer 176 interposed therebetween with respect to the plurality of diode trench structures 170. An anode potential is applied to the plurality of anode regions 180, and a cathode potential is applied to the plurality of cathode regions 179. In other words, the plurality of anode regions 180 are fixed to the same potential as either or both of the first upper electrode 173 ( FIG. 17 ) and the first lower electrode 174 ( FIG. 17 ).

[0198] Each anode region 180 has a concentration gradient in which the p-type impurity concentration increases and decreases along the second direction Y. Specifically, each anode region 180 includes a high-concentration region 180a and a low-concentration region 180b formed along the second direction Y. The high-concentration region 180a is a region having a higher p-type impurity concentration than the second body region 167. The low-concentration regions 180b are both regions having a lower p-type impurity concentration than the high-concentration region 180a.

[0199] 18 , the high-concentration region 180a is formed on the first main surface 3 side from the bottom of the second body region 167 with a gap therebetween, and faces the drift region 11 across a part of the second body region 167. The high-concentration region 180a preferably has a p-type impurity concentration substantially equal to that of the contact region 80 of the output region 6. The high-concentration region 180a preferably has a thickness (depth) substantially equal to that of the contact region 80. The high-concentration region 180a may be formed simultaneously with the contact region 80.

[0200] 16 and 20, the high-concentration region 180a is located on one side of the low-concentration region 180b in the second direction Y. The high-concentration region 180a is located on the other side of the low-concentration region 180b in the second direction Y. In other words, the two high-concentration regions 180a sandwich the low-concentration region 180b in the second direction Y. In this embodiment, the low-concentration regions 180b are formed using part of the second body region 167. Therefore, all of the low-concentration regions 180b have the p-type impurity concentration of the second body region 167. In one mesa portion 110, the total planar area of ​​the high-concentration regions 180a is greater than the total planar area of ​​the low-concentration regions 180b.

[0201] 17 , the cathode regions 179 are formed at intervals from the bottom of the second body region 167 toward the first main surface 3, and face the drift region 11 across a part of the second body region 167. Each cathode region 179 preferably has an n-type impurity concentration approximately equal to that of the source region 79 of the output region 6. Each cathode region 179 preferably has a thickness (depth) approximately equal to that of the source region 79. The cathode regions 179 may be formed simultaneously with the source region 79.

[0202] 16 and 19A, the semiconductor device 1 includes two diode connection structures 190 formed on the first main surface 3 in the first temperature detection region 8A. The two diode connection structures 190 include a diode connection structure 190 on one side (the first side surface 5A (FIG. 1) side) and a diode connection structure 190 on the other side (the second side surface 5B (FIG. 1) side) that face each other with a plurality of diode trench structures 170 interposed therebetween in the second direction Y.

[0203] The diode connection structure 190 on one side connects first ends of the two diode trench structures 170 in an arch shape in plan view. The diode connection structure 190 on the other side connects second ends of the two diode trench structures 170 in an arch shape in plan view. The two diode connection structures 190 and the multiple diode trench structures 170 form one annular trench structure.

[0204] The other side diode connection structure 190 has the same structure as the one side diode connection structure 190 except that it is connected to the second end of the diode trench structure 170. Below, the configuration of one side diode connection structure 190 will be described, and a description of the configuration of the other side diode connection structure 190 will be omitted.

[0205] The plurality of diode connection structures 190 are formed at intervals from the bottom of the drift region 11 toward the first main surface 3, and face the drain region 10 across a portion of the drift region 11. The plurality of diode connection structures 190 may have a width substantially equal to the fourth width W4 of the diode trench structure 170. The plurality of diode connection structures 190 may be formed to a depth equal to the diode trench structure 170. Of course, the first and second portions of the diode connection structure 190 may have widths different from each other. For example, the second portion of the diode connection structure 190 may be formed narrower than the first portion of the diode connection structure 190.

[0206] The diode connection structure 190 includes a diode connection trench 196, a diode connection insulating layer 197, and a diode connection electrode 193. The diode connection trench 196 is formed in the first main surface 3 and defines a wall surface of the diode connection structure 190. The diode connection trench 196 is connected to the plurality of diode trenches 171.

[0207] The diode-connection insulating layer 197 covers the wall surface of the diode-connection trench 196. The diode-connection insulating layer 197 is connected to the first upper insulating layer 176, the first lower insulating layer 177, and the first intermediate insulating layer 175 at the communicating portion between the diode-connection trench 196 and the diode trench 171. The diode-connection insulating layer 197 is thicker than the first upper insulating layer 176. The thickness of the diode-connection insulating layer 197 may be approximately equal to the thickness of the first lower insulating layer 177. The diode-connection insulating layer 197 may include a silicon oxide film. The diode-connection insulating layer 197 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0208] The diode-connection electrode 193 is embedded in the diode-connection trench 196 with a diode-connection insulating layer 197 sandwiched therebetween, and faces the drift region 11 and the second body region 167 with the diode-connection insulating layer 197 sandwiched therebetween. Although not shown, the diode-connection electrode 193 is connected to the first lower electrode 174 ( FIG. 17 , etc.) at a communicating portion between the diode-connection trench 196 and the diode trench 171 ( FIG. 17 , etc.), and is electrically insulated from the first upper electrode 173 by a first intermediate insulating layer 175 ( FIG. 17 , etc.). The diode-connection electrode 193 is formed by an extension portion of the first lower electrode 174 extended from inside the diode trench 171 into the diode-connection trench 196. The diode-connection electrode 193 may include conductive polysilicon.

[0209] 22, as described above, the first temperature-sensitive diode 9A includes a first diode Di1 and a second diode Di2 connected in series. The first diode Di1 and the second diode Di2 have the same structure. The anode of the first diode Di1 is the anode of the first temperature-sensitive diode 9A, and the cathode of the second diode Di2 is the cathode of the first temperature-sensitive diode 9A.

[0210] The first temperature sensitive diode 9A (semiconductor device 1) includes an anode wiring 151 and a cathode wiring 153. One end of the anode wiring 151 is connected to the anode of the first diode Di1. One end of the cathode wiring 153 is connected to the cathode of the second diode Di2. An anode potential is applied to the other end of the anode wiring 151. A cathode potential is applied to the other end of the cathode wiring 153.

[0211] 15A, the semiconductor device 1 includes a first connection wiring structure 150 that connects a first diode Di1 and a second diode Di2 in series. The first connection wiring structure 150 includes a first connection wiring 152 that connects the cathode of the first diode Di1 and the anode of the second diode Di2.

[0212] The first connection wiring structure 150 includes a plurality of via electrodes 161 to 166 embedded in the interlayer insulating layer 12. The plurality of via electrodes 161 to 166 includes a plurality of first via electrodes 161, a plurality of second via electrodes 162, a plurality of third via electrodes 163, a plurality of fourth via electrodes 164, a plurality of fifth via electrodes 165, and a plurality of sixth via electrodes 166.

[0213] The first via electrode 161 is a plug electrode that transmits a cathode potential to the cathode regions 179 of the plurality of unit diodes D included in each of the diodes Di1 and Di2. The second via electrode 162 is a plug electrode that transmits an anode potential to the anode regions 180 (high-concentration regions 180a) of the plurality of unit diodes D included in each of the diodes Di1 and Di2. The third via electrode 163 is a plug electrode that transmits a potential to the diode connection electrode 193 (FIG. 19A) of the diode connection structure 190 (FIG. 19A). The fourth via electrode 164 is a plug electrode that transmits a potential to the mesa region between the second trench isolation structure 100 and the diode trench structure 170. The fifth via electrode 165 is a plug electrode that transmits a potential to the second isolation electrode 103 (FIG. 17, etc.) of the second trench isolation structure 100. The plurality of sixth via electrodes 166 are plug electrodes that transmit a potential to the first upper electrode 173.

[0214] Each of the via electrodes 161 to 166 may include a first electrode and a second electrode. The first electrode coats the wall surface of a via hole formed in the interlayer insulating layer 12 in the form of a film. The first electrode may include either a Ti film or a Ti alloy film, or both. The Ti alloy film may be a TiN film. The second electrode is embedded in the via hole via the first electrode. The second electrode may include at least one of W, Al, an Al alloy, Cu, and a Cu alloy. The Al alloy may include at least one of an AlSi alloy, an AlCu alloy, and an AlSiCu alloy.

[0215] Each of the via electrodes 161 to 166 may be formed in a triangular, quadrangular, rectangular, polygonal, circular, or elliptical shape in a plan view. Of course, each of the via electrodes 161 to 166 may be formed in a strip shape (for example, a rectangular shape) extending in the first direction X.

[0216] The structures of the anode wiring 151, the cathode wiring 153, and the first connection wiring 152 will be described below.

[0217] The anode wiring 151 may also be referred to as an "anode pad wiring." The anode wiring 151 extends in the first direction X. The anode wiring 151 faces the first connection wiring 152 in the first direction X. Both ends of the anode wiring 151 in the second direction Y are located outside the both ends of the second trench isolation structure 100 in the second direction Y. In other words, the width of the anode wiring 151 in the second direction Y is greater than the length of the second trench isolation structure 100 in the second direction Y.

[0218] The anode wiring 151 includes at least one outer anode lead-out wiring 151a led out to the other side in the first direction X (the fourth side surface 5D (FIG. 1) side) at both ends in the second direction Y. In this embodiment, the number of outer anode lead-out wirings 151a is two. The outer anode lead-out wiring 151a is electrically connected to the diode connection electrode 193 (FIG. 19A) of the unit diode D (FIG. 16) included in the first diode Di1 via a third via electrode 163. The outer anode lead-out wiring 151a is electrically connected to the second separated electrode 103 (FIG. 17, etc.) of the first diode Di1 via a fifth via electrode 165. The outer anode lead-out wiring 151a is electrically connected to the first upper electrode 173 of the unit diode D (FIG. 16) included in the first diode Di1 via a sixth via electrode 166.

[0219] The anode wiring 151 includes at least one inner anode lead wiring 151b led out to the other side in the first direction X (the fourth side surface 5D (FIG. 1) side) in the central portion in the second direction Y. In this embodiment, the number of inner anode lead wirings 151b is two. The inner anode lead wiring 151b is electrically connected to the high-concentration region 180a (FIG. 16) of the unit diode D included in the first diode Di1 through the second via electrode 162.

[0220] In this configuration, the two inner anode lead wires 151b are sandwiched between the two outer anode lead wires 151a in the second direction Y. In other words, the two outer anode lead wires 151a sandwich the two inner anode lead wires 151b in the second direction Y.

[0221] The base of the anode wiring 151 (the part of the anode wiring 151 excluding the outer anode lead-out wiring 151a and the inner anode lead-out wiring 151b) is connected to the mesa region of the unit diode D included in the second diode Di2 (the mesa region between the second trench isolation structure 100 and the diode trench structure 170) via the fourth via electrode 164.

[0222] 17 and other figures, the anode wiring 151 is included in both the first wiring layer 16 and the second wiring layer 17. The anode wiring 151 (first wiring layer 16) and the anode wiring 151 (second wiring layer 17) are electrically connected through a via electrode (not shown).

[0223] 15A, the cathode wiring 153 may be referred to as a "cathode pad wiring." The cathode wiring 153 extends in a first direction X. The cathode wiring 153 faces the first connection wiring 152 in the first direction X. In this embodiment, the cathode wiring 153 sandwiches the first connection wiring 152 between itself and the anode wiring 151 in the first direction X.

[0224] The cathode wiring 153 includes at least one cathode lead-out wiring 153d led out from the base 153c to one side in the first direction X (the side of the third side surface 5C (FIG. 1)) in the central portion in the second direction Y. In this embodiment, the number of cathode lead-out wirings 153d is one. The cathode lead-out wiring 153d is electrically connected to the cathode region 179 of the unit diode D (FIG. 16) included in the second diode Di2 through the first via electrode 161. The width in the second direction Y of the cathode lead-out wiring 153d may be equal to the width in the second direction Y of the inner anode lead-out wiring 151b.

[0225] 21A and other drawings, the cathode wiring 153 is included in both the first wiring layer 16 and the second wiring layer 17. The cathode wiring 153 (first wiring layer 16) and the cathode wiring 153 (second wiring layer 17) are electrically connected through a via electrode (not shown).

[0226] 15A, the first connection wiring 152 may also be referred to as a "first connection pad wiring." The first connection wiring 152 extends in the first direction X. The first connection wiring 152 is sandwiched in the first direction X by the anode wiring 151 and the cathode wiring 153. Both ends of the first connection wiring 152 in the second direction Y are located outside the both ends of the second trench isolation structure 100 in the second direction Y. In other words, the width of the first connection wiring 152 in the second direction Y is greater than the length of the second trench isolation structure 100 in the second direction Y.

[0227] The first connection wiring 152 includes at least one outer lead connection wiring 152a led out to the other side in the first direction X (the fourth side surface 5D (FIG. 1) side) at both ends in the second direction Y. In this embodiment, the number of outer lead connection wirings 152a is two.

[0228] The outer extension connection wiring 152a is electrically connected to the diode connection electrode 193 (FIG. 19A) of the second diode Di2 through a third via electrode 163. The outer extension connection wiring 152a is electrically connected to the second separated electrode 103 (FIG. 17, etc.) of the second diode Di2 through a fifth via electrode 165. The outer extension connection wiring 152a is electrically connected to the first upper electrode 173 of the second diode Di2 through a sixth via electrode 166.

[0229] The first connection wiring 152 includes at least one inner lead-out connection wiring 152b led out to the other side in the first direction X (toward the fourth side surface 5D (FIG. 1)) in the central portion in the second direction Y. In this embodiment, the number of inner lead-out connection wirings 152b is two. The inner lead-out connection wiring 152b is electrically connected to the high-concentration region 180a (FIG. 16) of the unit diode D included in the second diode Di2 through the second via electrode 162.

[0230] In this configuration, the two inner outgoing connection wirings 152b are sandwiched between the two outer outgoing connection wirings 152a in the second direction Y. In other words, the two outer outgoing connection wirings 152a sandwich the two inner outgoing connection wirings 152b in the second direction Y.

[0231] In this embodiment, two inner lead-out connection wirings 152b sandwich one cathode lead-out wiring 153d in the second direction Y. In other words, one cathode lead-out wiring 153d is sandwiched in the second direction Y by two inner lead-out connection wirings 152b.

[0232] The first connection wiring 152 includes a narrow portion 152c drawn out to one side in the first direction X (toward the third side surface 5C (Figure 1)) at the center in the second direction Y, and at least one inner drawn connection wiring 152d drawn out to one side in the first direction X (toward the third side surface 5C (Figure 1)) at the center of the narrow portion 152c.

[0233] In this embodiment, the number of inner lead-out connecting wirings 152d is 1. The inner lead-out connecting wirings 152d are electrically connected to the cathode region 179 (FIG. 16) of the unit diode D included in the first diode Di1 through the first via electrode 161.

[0234] The width of the inner lead-out connection wiring 152d in the second direction Y may be equal to the width of the inner anode lead-out wiring 151b in the second direction Y. In this embodiment, one inner lead-out connection wiring 152d is sandwiched in the second direction Y by two inner anode lead-out wirings 151b.

[0235] The base of the first connection wiring 152 (the portion of the first connection wiring 152 between the narrow portion 152c and the inner lead-out connection wiring 152b) is connected to the mesa region of the unit diode D included in the first diode Di1 (the mesa region between the second trench isolation structure 100 and the diode trench structure 170) via the fourth via electrode 164.

[0236] 17 and other figures, the first connection wiring 152 is included in both the first wiring layer 16 and the second wiring layer 17. The first connection wiring 152 (first wiring layer 16) and the first connection wiring 152 (second wiring layer 17) are electrically connected through via electrodes (not shown).

[0237] The anode wiring 151, the first connection wiring 152, and the cathode wiring 153 may all be included in the same wiring layer. That is, the anode wiring 151, the first connection wiring 152, and the cathode wiring 153 may be included only in the first wiring layer 16, or only in the second wiring layer 17. That is, one of the first wiring layer 16 and the second wiring layer 17 (for example, the second wiring layer 17) may be omitted from the configurations shown in Figures 15C, 17 to 19B, 21A, and 21B, etc. (The same applies to the configurations in Figures 29 to 31, which will be described later).

[0238] 15B and 15C, the semiconductor device 1 further includes a second connection wiring structure 401 that electrically connects the anode wiring 151 and the drift region 11. As shown in FIG.

[0239] The second connection wiring structure 401 includes a connection pad wiring 402 connected to the anode wiring 151, and a plurality (a large number) of connection via electrodes 403 that electrically connect the connection pad wiring 402 and the drift region 11.

[0240] 15C, the output region 6 includes a via electrode arrangement region 404 adjacent to one side in the first direction X (the third side surface 5C side) of the first temperature detection region 8A via the second trench isolation structure 100. In the via electrode arrangement region 404, the first main surface 3 is selectively covered with a main surface insulating layer 94. The via electrode arrangement region 404 is a region for arranging a plurality (a large number) of connection via electrodes 403 on the first main surface 3. The via electrode arrangement region 404 is a region insulated and separated from the first temperature detection region 8A. In this embodiment, the via electrode arrangement region 404 is formed in a part of the output region 6.

[0241] The via electrode arrangement region 404 may be a region on the first main surface 3 that is insulated and separated from the output region 6. That is, the via electrode arrangement region 404 may be a region that is insulated and separated from both the first temperature detection region 8A and the output region 6.

[0242] In the via electrode arrangement region 404, an n-type high concentration region 405 is formed in a surface layer portion of the first main surface 3. The main surface insulating layer 94 is connected to the high concentration region 405. A connection pad wiring 402 faces above the high concentration region 405.

[0243] The high concentration region 405 preferably has an n-type impurity concentration approximately equal to that of the source region 79 of the output region 6. The high concentration region 405 preferably has a thickness (depth) approximately equal to that of the source region 79 (cathode region 179) of the output region 6. The high concentration region 405 may be formed simultaneously with the source region 79 (cathode region 179).

[0244] The connection pad wiring 402 has a quadrangular shape in a plan view. Both ends of the connection pad wiring 402 in the second direction Y are located outside in the second direction Y compared to both ends of the mesa portion 110 in the second direction Y. In other words, the length of the connection pad wiring 402 in the second direction Y is longer than the length of the mesa portion 110 in the second direction Y.

[0245] The connection pad wiring 402 is in contact with the anode wiring 151 over the entire area in the second direction Y. The connection pad wiring 402 is included in the first wiring layer 16. The connection pad wiring 402 may be included in the first wiring layer 16 as long as it is in the same layer as the anode wiring 151.

[0246] The upper ends of the multiple connection via electrodes 403 are in contact with the lower surface of the connection pad wiring 402. The lower ends of the multiple connection via electrodes 403 penetrate the main surface insulating layer 94 and are in contact with the high-concentration region 405. That is, the multiple connection via electrodes 403 are in contact with both the connection pad wiring 402 and the high-concentration region 405. As a result, the anode wiring 151 is electrically connected to the drift region 11 via the connection pad wiring 402, the multiple connection via electrodes 403, and the high-concentration region 405.

[0247] One connection via electrode 403 may include a first electrode and a second electrode. The first electrode coats the wall surface of a via hole formed in the interlayer insulating layer 12 in the form of a film. The first electrode may include either or both of a Ti film and a Ti alloy film. The Ti alloy film may be a TiN film.

[0248] One connection via electrode 403 may be formed in a triangular, quadrangular, rectangular, polygonal, circular or elliptical shape in plan view. Of course, the connection via electrode 403 may be formed in a strip shape (for example, a rectangular shape) extending in the first direction X.

[0249] 23, the anode wiring 151 (FIG. 15, etc.) is electrically connected to the drift region 11 via a connection pad wiring 402 and a plurality of connection via electrodes 403. A power supply potential VBB is applied to the drift region 11. The potential applied to the anode wiring 151 is the same as the potential of the second body region 167. The second body region 167 is fixed to the same potential as the drift region 11.

[0250] Specifically, when the anode potential (power supply potential VBB) is 40 V, the potential of the drift region 11 is 40 V. At this time, the potential of the second body region 167 is 40 V. Furthermore, the potential of the cathode region 179 that forms a diode (unit diode D) with the second body region 167 is, for example, 39 V.

[0251] A first connection wiring 152 is electrically connected to both the cathode regions 179 of the three mesa portions 110 (FIG. 16) of the first diode Di1 and the anode regions 180 of the three mesa portions 110 (FIG. 16) of the second diode Di2. In this case, as shown in FIG. 22, in each of the first diode Di1 and the second diode Di2, a plurality of unit diodes D (three in this embodiment) are connected in parallel. Furthermore, the first diode Di1 and the second diode Di2 are connected in series by the first connection wiring 152.

[0252] As described above, according to this embodiment, the first temperature-sensitive diode 9A includes a first diode Di1 having a plurality (three) of unit diodes D and a second diode Di2 having a plurality (three) of unit diodes D. The second diode Di2 is formed so as to be electrically isolated from the first diode Di1. The first diode Di1 and the second diode Di2 are connected in series by the first connection wiring structure 150. Therefore, compared to when only the first diode Di1 is used for the first temperature-sensitive diode 9A, the overall forward voltage can be increased (doubled). This increases the voltage difference during abnormal heat generation, reducing the impact of voltage variations in the overheat protection circuit 27. As a result, the accuracy of temperature detection during abnormal heat generation can be improved. Therefore, the accuracy of control by the overheat protection circuit 27 can be improved.

[0253] Furthermore, according to this embodiment, the inner lead-out connection wiring 152d of the first connection wiring 152 is sandwiched between the anode wiring 151 in the second direction Y. Furthermore, the inner lead-out connection wiring 152b of the first connection wiring 152 sandwiches the cathode wiring 153 in the second direction Y. By such ingenious layout of the first connection wiring 152, it is possible to prevent the first connection wiring 152 from becoming large. This makes it possible to reduce the planar area of ​​the first temperature sensitive diode 9A. Therefore, it is possible to reduce the planar area of ​​the chip 2.

[0254] Furthermore, according to this embodiment, the anode wiring 151 and the drift region 11 are electrically connected by the second connection wiring structure 401.

[0255] When the first diode Di1 and the second diode Di2, each including a unit diode D, are connected in series, a current may be generated by a parasitic npn transistor. If the potential difference between the second body region 167 and the drift region 11 is large, a large current may be generated by the parasitic transistor, which may lead to the destruction of the semiconductor device 1.

[0256] According to this embodiment, the anode wiring 151 and the drift region 11 are electrically connected, so the second body region 167 can be fixed at the same potential as the drift region 11. Therefore, even when the first diode Di1 and the second diode Di2, each including a unit diode D, are connected in series, it is possible to suppress the generation of a large current due to a parasitic transistor. This makes it possible to increase the voltage difference during abnormal heat generation without risking damage to the semiconductor device 1.

[0257] Furthermore, according to this embodiment, the second connection wiring structure 401 includes a connection pad wiring 402 and a plurality of connection via electrodes 403. In this case, the planar area of ​​the second connection wiring structure 401 only requires the planar area of ​​the connection pad wiring 402. This makes it possible to reduce the planar area of ​​the second connection wiring structure 401. Therefore, it is possible to reduce the planar area of ​​the chip 2.

[0258] Fig. 24 is a front view showing the layout of a chip 2 according to a first modified example of the first embodiment of the present disclosure, and is a diagram corresponding to Fig. 14. Fig. 25 is a front view showing the layout of a first wiring layer 16 according to the first modified example, and is a diagram corresponding to Fig. 15A. Fig. 26 is an electrical circuit diagram of a first temperature sensitive diode 9A according to the first modified example.

[0259] The semiconductor device 1 shown in FIGS. 24 to 26 differs from the semiconductor device 1 shown in FIGS. 1 to 23 in that the number of diode elements included in the first temperature sensitive diode 9A is changed from two to three.

[0260] 24, in a first modified example, the first temperature sensitive diode 9A includes a third diode Di3 in addition to a first diode Di1 and a second diode Di2. Each of the first diode Di1, the second diode Di2, and the third diode Di3 is formed by one diode element.

[0261] The first diode Di1, the second diode Di2, and the third diode Di3 are arranged in this order at intervals from one side (the third side surface 5C side) to the other side (the fourth side surface 5D side) in the first direction X. The first diode Di1, the second diode Di2, and the third diode Di3 are connected in series.

[0262] The third diode Di3 has the same size and structure as the first diode Di1 and the second diode Di2. That is, like the first diode Di1 and the second diode Di2, the third diode Di3 includes a plurality (three) of unit diodes D. The first diode Di1, the second diode Di2, and the third diode Di3 are arranged at equal intervals in the first direction X.

[0263] 25, in the first modification, the first connection wiring structure 150 includes a second connection wiring 154 in addition to a first connection wiring 152. The first connection wiring 152 and the second connection wiring 154 are arranged in this order at an interval from one side (the third side surface 5C side) to the other side (the fourth side surface 5D side) in the first direction X.

[0264] The second connection wiring 154 has the same structure as the first connection wiring 152. That is, the second connection wiring 154 includes at least one (for example, two) outer lead-out connection wirings 152a, at least one (for example, two) inner lead-out connection wirings 152b, a narrow width portion 152c, and at least one (for example, one) inner lead-out connection wiring 152d.

[0265] Furthermore, the inner lead-out connection wiring 152b of the second connection wiring 154 sandwiches one cathode lead-out wiring 153d in the second direction Y. Furthermore, the inner lead-out connection wiring 152d of the second connection wiring 154 is sandwiched in the second direction Y by two inner lead-out connection wirings 152b of the first connection wiring 152.

[0266] The outer leading connection wiring 152a of the second connection wiring 154 is electrically connected to the diode connection electrode 193 (FIG. 19A) of the unit diode D included in the third diode Di3 through a third via electrode 163. The outer leading connection wiring 152a of the second connection wiring 154 is electrically connected to the second separated electrode 103 (FIG. 17, etc.) of the third diode Di3 through a fifth via electrode 165. The outer leading connection wiring 152a of the second connection wiring 154 is electrically connected to the first upper electrode 173 of the unit diode D included in the third diode Di3 through a sixth via electrode 166.

[0267] The inner lead-out connection wiring 152b of the second connection wiring 154 is electrically connected through a second via electrode 162 to the high concentration region 180a (FIG. 16) of the unit diode D included in the third diode Di3.

[0268] The inner lead-out connection wiring 152d of the second connection wiring 154 is electrically connected through a first via electrode 161 to the cathode region 179 (FIG. 16) of the unit diode D included in the second diode Di2.

[0269] In the first modification, the cathode lead wiring 153d is electrically connected through a first via electrode 161 to the cathode region 179 (FIG. 16) of the unit diode D included in the third diode Di3.

[0270] 26, in each of the first diode Di1, the second diode Di2, and the third diode Di3, a plurality of (three in this embodiment) unit diodes D are connected in parallel. The first diode Di1, the second diode Di2, and the third diode Di3 are connected in series by a first connection wiring 152 and a second connection wiring 154.

[0271] FIG. 27 is a front view showing the layout of a chip 2 of a semiconductor device 201 according to a second embodiment of the present disclosure, and corresponds to FIG. 14 . FIG. 28 is a front view showing the layout of a first wiring layer 16 according to the second embodiment, and corresponds to FIG. 15A . FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 27 . FIG. 30 is a cross-sectional view taken along line XXX-XXX in FIG. 27 . FIG. 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 27 . FIG. 32A is a diagram showing a current flow in a first temperature-sensitive diode 209A according to the second embodiment. FIG. 32B is an electrical circuit diagram of the first temperature-sensitive diode 209A according to the second embodiment. In FIGS. 27 and 32A , the cathode region 179 is hatched for clarity.

[0272] 1 to 23 in that the semiconductor device 201 includes a first temperature sensitive diode 209A instead of the first temperature sensitive diode 9A. In the second embodiment, only the parts that are different from the first embodiment will be mainly described, and the same reference numerals will be used to designate the same components as those described so far, and their description will be omitted.

[0273] Referring to FIG. 27, the first temperature sensitive diode 209A includes one second trench isolation structure 100. A plurality of stripe-shaped diode trench structures 170 are formed in the region inside the second trench isolation structure 100. A mesa portion 110 is defined in the region between two adjacent diode trench structures 170. The plurality of mesa portions 110 are formed in stripes extending in the second direction Y in plan view. In this embodiment, the number of diode trench structures 170 is five. The number of mesa portions 110 is four.

[0274] As described above, one unit diode D has a one-to-one correspondence with one mesa portion 110. One unit diode D can be regarded as an independent diode.

[0275] The multiple mesa portions 110 are, in order from one side in the first direction X (the third side surface 5C (FIG. 1) side), a first mesa portion 110A, a second mesa portion 110B, a third mesa portion 110C, and a fourth mesa portion 110D.

[0276] Specifically, one unit diode D includes a p-type anode region 180 and an n-type cathode region 179 formed in a surface layer portion of the second body region 167. In this embodiment, the patterns of the p-type anode region 180 and the n-type cathode region 179 are common to the first mesa portion 110A and the second mesa portion 110B, and common to the third mesa portion 110C and the fourth mesa portion 110D. The patterns of the p-type anode region 180 and the n-type cathode region 179 are different between the first mesa portion 110A and the second mesa portion 110B and the third mesa portion 110C and the fourth mesa portion 110D.

[0277] In the first mesa portion 110A and the second mesa portion 110B, the unit diode D includes three anode regions 180 and two cathode regions 179. The three anode regions 180 are arranged in the second direction Y so as to sandwich the two cathode regions 179. In the unit diodes D corresponding to the first mesa portion 110A and the second mesa portion 110B, the total planar area of ​​the anode regions 180 is greater than the total planar area of ​​the cathode regions 179.

[0278] In this embodiment, the anode region 180 specifically includes a high-concentration region 180a and a low-concentration region 180b formed along the second direction Y. The two low-concentration regions 180b sandwich the high-concentration region 180a in the second direction Y. In the unit diode D corresponding to the first mesa portion 110A and the second mesa portion 110B, the total planar area of ​​the high-concentration regions 180a is larger than the total planar area of ​​the low-concentration regions 180b.

[0279] In the third mesa portion 110C and the fourth mesa portion 110D, the unit diode D includes two anode regions 180 and one cathode region 179. The two anode regions 180 are arranged (aligned) to sandwich the one cathode region 179. In the unit diodes D corresponding to the third mesa portion 110C and the fourth mesa portion 110D, the total planar area of ​​the anode regions 180 is larger than the total planar area of ​​the cathode regions 179.

[0280] The two low-concentration regions 180b sandwich the high-concentration region 180a in the second direction Y. In the unit diode D corresponding to the third mesa portion 110C and the fourth mesa portion 110D, the total planar area of ​​the high-concentration regions 180a is larger than the total planar area of ​​the low-concentration regions 180b.

[0281] The first temperature sensitive diode 209A includes a first diode Di21 and a second diode Di22 that are formed to be electrically isolated from each other. The first diode Di21 has a plurality of (for example, two) unit diodes D. The two unit diodes D are a unit diode D corresponding to the first mesa portion 110A and a unit diode D corresponding to the second mesa portion 110B, respectively.

[0282] The second diode Di22 has a plurality of (for example, two) unit diodes D. The two unit diodes D are a unit diode D corresponding to the third mesa portion 110C and a unit diode D corresponding to the fourth mesa portion 110D, respectively.

[0283] In this embodiment, the first diode Di21 and the second diode Di22, which are formed to be electrically isolated from each other, are surrounded by a single second trench isolation structure 100. In other words, the second trench isolation structure 100 collectively surrounds the first diode Di21 and the second diode Di22. That is, the second trench isolation structure 100 electrically isolates the first diode Di21 and the second diode Di22 from regions outside the second trench isolation structure 100.

[0284] The cathode region 179 included in the first diode Di21 faces the high-concentration region 180a included in the second diode Di22 in the first direction X. The cathode region 179 included in the second diode Di22 faces the high-concentration region 180a included in the first diode Di21 in the first direction X.

[0285] The cathode region 179 included in the first diode Di21 does not face the cathode region 179 included in the second diode Di22 in the first direction X. In other words, the cathode region 179 included in the first diode Di21 is shifted in the second direction Y relative to the cathode region 179 included in the second diode Di22.

[0286] 28 and 32B, the semiconductor device 201 includes a first connection wiring structure 250 that connects a first diode Di21 and a second diode Di22 in series. The first connection wiring structure 250 includes two first connection wirings 252. The first connection wiring 252 connects the cathode of the first diode Di21 and the anode of the second diode Di22.

[0287] 28, the first connection wiring structure 250 includes a plurality of via electrodes 161-166 embedded in the interlayer insulating layer 12. The structures of the anode wiring 251, the cathode wiring 253, and the first connection wiring 252 will be described below.

[0288] The anode wiring 251 may also be referred to as an "anode pad wiring." The anode wiring 251 extends in the first direction X. The anode wiring 251 faces the first connection wiring 252 in the first direction X. Both ends of the anode wiring 251 in the second direction Y are located outside the both ends of the second trench isolation structure 100 in the second direction Y. The width of the anode wiring 251 in the second direction Y is greater than the length of the second trench isolation structure 100 in the second direction Y.

[0289] The anode wiring 251 includes at least one outer anode lead-out wiring 251a led out to the other side in the first direction X (the fourth side surface 5D (FIG. 1) side) at both ends in the second direction Y. In this embodiment, the number of outer anode lead-out wirings 251a is two. The outer anode lead-out wiring 251a is electrically connected to the second separated electrode 103 (FIG. 29, etc.) through a fifth via electrode 165.

[0290] The anode wiring 251 includes at least one inner anode lead-out wiring 251b that is led out to the other side in the first direction X (the fourth side surface 5D (FIG. 1) side) in the central portion in the second direction Y. In this embodiment, the number of inner anode lead-out wirings 251b is three. The inner anode lead-out wirings 251b are electrically connected to the high-concentration region 180a (FIG. 27) of the unit diode D included in the first diode Di21 through the second via electrode 162.

[0291] In this configuration, the three inner anode lead wires 251b are sandwiched between the two outer anode lead wires 251a in the second direction Y. In other words, the two outer anode lead wires 251a sandwich the three inner anode lead wires 251b in the second direction Y.

[0292] The base of the anode wiring 251 (the part of the anode wiring 251 excluding the outer anode lead-out wiring 251a and the inner anode lead-out wiring 251b) is connected to the mesa region of the unit diode D included in the second diode Di22 (the mesa region between the second trench isolation structure 100 and the diode trench structure 170) via the fourth via electrode 164.

[0293] 29 etc., the anode wiring 251 is included in both the first wiring layer 16 and the second wiring layer 17. The anode wiring 251 (first wiring layer 16) and the anode wiring 251 (second wiring layer 17) are electrically connected through a via electrode (not shown).

[0294] Although not shown, the semiconductor device 201 includes a second connection wiring structure 401 (FIGS. 15B and 15C) that electrically connects the anode wiring 251 and the drift region 11. A connection pad wiring 402 (FIGS. 15B and 15C) of the second connection wiring structure 401 contacts the anode wiring 251 over the entire area in the second direction Y. This electrically connects the connection pad wiring 402 and the anode wiring 251.

[0295] 28, the cathode wiring 253 may be referred to as a "cathode pad wiring." The cathode wiring 253 extends in the first direction X. The cathode wiring 253 faces the first connection wiring 252 in the first direction X. In this embodiment, the cathode wiring 253 sandwiches the first connection wiring 252 between itself and the anode wiring 251 in the first direction X.

[0296] The cathode wiring 253 includes at least one outer cathode lead-out wiring 253a led out to one side in the first direction X (the third side surface 5C (FIG. 1) side) at both ends in the second direction Y. In this embodiment, the number of outer cathode lead-out wirings 253a is two. The outer cathode lead-out wiring 253a is electrically connected to the diode-connecting electrode 193 (FIG. 19A) through the third via electrode 163. The outer cathode lead-out wiring 253a is electrically connected to the first upper electrode 173 through the sixth via electrode 166.

[0297] The cathode wiring 253 includes at least one inner cathode lead-out wiring 253b led out from the base 253c to one side in the first direction X (toward the third side surface 5C (FIG. 1)) in the central part in the second direction Y. In this embodiment, the number of inner cathode lead-out wirings 253b is one. The inner cathode lead-out wiring 253b is electrically connected to the cathode region 179 (FIG. 27) of the unit diode D included in the second diode Di22 through the first via electrode 161. The width in the second direction Y of the inner cathode lead-out wiring 253b may be equal to the width in the second direction Y of the inner anode lead-out wiring 251b.

[0298] 29 etc., the cathode wiring 253 is included in both the first wiring layer 16 and the second wiring layer 17. The cathode wiring 253 (first wiring layer 16) and the cathode wiring 253 (second wiring layer 17) are electrically connected through a via electrode (not shown).

[0299] 28, the first connection wirings 252 may be referred to as "first connection pad wirings." The two first connection wirings 252 each have a polygonal shape (e.g., a hexagonal shape) extending in the first direction X and are arranged at an interval in the second direction Y. The two first connection wirings 252 are symmetrical with respect to the X-axis line along the center of the anode wiring 251 in the second direction Y. The two first connection wirings 252 are sandwiched in the first direction X and the second direction Y by the anode wiring 251 and the cathode wiring 253. Portions of the two first connection wirings 252 are sandwiched in the second direction Y by three inner anode lead-out wirings 251b. Other portions of the two first connection wirings 252 sandwich one inner cathode lead-out wiring 253b in the second direction Y.

[0300] The first connection wiring 252 is electrically connected to the cathode region 179 (FIG. 27) of the unit diode D included in the first diode Di21 through the first via electrode 161. The first connection wiring 252 is also electrically connected to the high-concentration region 180a (FIG. 27) of the unit diode D included in the second diode Di22 through the second via electrode 162. That is, the first connection wiring 252 electrically connects the cathode region 179 (FIG. 27) of the unit diode D included in the first diode Di21 and the high-concentration region 180a (FIG. 27) of the unit diode D included in the second diode Di22.

[0301] 32A, the cathode region 179 of the unit diode D included in the first diode Di21 is electrically connected to the high-concentration region 180a of the unit diode D included in the second diode Di22. In other words, the cathode of the first diode Di21 is electrically connected to the anode of the second diode Di22. Therefore, as shown in bold in FIG. 32A, a current path is formed from the cathode of the first diode Di21 to the anode of the second diode Di22.

[0302] 32B, in each of the first diode Di21 and the second diode Di22, a plurality of (two in this embodiment) unit diodes D are connected in parallel. The first diode Di21 and the second diode Di22 are connected in series by a first connection wiring 252.

[0303] The semiconductor device 201 according to the second embodiment of the present disclosure provides the same effects as those described in relation to the first embodiment.

[0304] Furthermore, according to the semiconductor device 201, the first diode Di21 and the second diode Di22, which are formed so as to be electrically isolated from each other, are surrounded by a single second trench isolation structure 100. This makes it possible to reduce the planar area of ​​the first temperature sensitive diode 209A compared to the first embodiment. This allows for a further reduction in the planar area of ​​the chip 2.

[0305] In addition, since all the unit diodes D are included in the area surrounded by one second trench isolation structure 100, variations in diode characteristics can be reduced.

[0306] Fig. 33 is a front view showing the layout of the chip 2 according to the second modified example of the second embodiment of the present disclosure, and corresponds to Fig. 27. Fig. 34 is a front view showing the layout of the first wiring layer 16 according to the second modified example, and corresponds to Fig. 28.

[0307] 33 and 34 differs from the semiconductor device 201 shown in FIGS. 27 to 32B in that the number of mesa portions 110 is changed from four to six. As described above, one unit diode D corresponds one-to-one to one mesa portion 110. One unit diode D can be regarded as an independent diode.

[0308] The multiple mesa portions 110 are, in order from one side in the first direction X (the side of the third side surface 5C (Figure 1)), a first mesa portion 110A, a second mesa portion 110B, a third mesa portion 110C, a fourth mesa portion 110D, a fifth mesa portion 110E, and a sixth mesa portion 110F.

[0309] In the fifth mesa portion 110E and the sixth mesa portion 110F, the unit diode D includes three anode regions 180 and two cathode regions 179. The three anode regions 180 are arranged (arranged) so as to sandwich the two cathode regions 179. The patterns of the p-type anode regions 180 and the n-type cathode regions 179 are common to the fifth mesa portion 110E and the sixth mesa portion 110F. The patterns of these p-type anode regions 180 and n-type cathode regions 179 are also common to the first mesa portion 110A and the second mesa portion 110B.

[0310] In the second modification, the first temperature sensitive diode 209A includes a third diode Di23 in addition to the first diode Di21 and the second diode Di22. The third diode Di23 is formed so as to be electrically isolated from each of the first diode Di21 and the second diode Di22.

[0311] The third diode Di23 has a plurality of (for example, two) unit diodes D. The two unit diodes D are a unit diode D corresponding to the fifth mesa portion 110E and a unit diode D corresponding to the sixth mesa portion 110F, respectively.

[0312] In the second modification, the first diode Di21, the second diode Di22, and the third diode Di23, which are formed so as to be electrically isolated from one another, are surrounded by a single second trench isolation structure 100. The first diode Di21, the second diode Di22, and the third diode Di23 are connected in series in this order.

[0313] The cathode region 179 included in the third diode Di23 faces the high-concentration region 180a included in the second diode Di22 in the first direction X. The cathode region 179 included in the second diode Di22 faces the high-concentration region 180a included in the third diode Di23 in the first direction X.

[0314] The cathode region 179 included in the third diode Di23 does not face the cathode region 179 included in the second diode Di22 in the first direction X. In other words, the cathode region 179 included in the third diode Di23 is shifted in the second direction Y relative to the cathode region 179 included in the second diode Di22.

[0315] 34, in the second modification, a first connection wiring structure 250 includes, in addition to a first connection wiring 252, two second connection wirings 254 and one third connection wiring 255.

[0316] The two second connection wirings 254 are electrically connected through second via electrodes 162 to the high concentration regions 180a (FIG. 27) of the unit diode D included in the third diode Di23.

[0317] One third connection wiring 255 connects the cathode of the second diode Di22 and the anode of the third diode Di23. The number of third connection wirings 255 is not limited to one, and may be plural.

[0318] The third connection wiring 255 may be referred to as a "third connection pad wiring." The third connection wiring 255 has a quadrangular shape extending in the first direction X. One third connection wiring 255 is sandwiched in the first direction X and the second direction Y by the anode wiring 251 and the cathode wiring 253. A part of one third connection wiring 255 is sandwiched in the second direction Y by two second connection wirings 254. The other part of one third connection wiring 255 is sandwiched in the second direction Y by two inner cathode lead-out wirings 253b.

[0319] The third connection wiring 255 is electrically connected to the cathode region 179 (FIG. 27) of the unit diode D included in the second diode Di22 through the first via electrode 161. The third connection wiring 255 is also electrically connected to the high-concentration region 180a (FIG. 27) of the unit diode D included in the third diode Di23 through the second via electrode 162. That is, the third connection wiring 255 electrically connects the cathode region 179 of the unit diode D included in the second diode Di22 and the high-concentration region 180a of the unit diode D included in the third diode Di23. In other words, the cathode of the second diode Di22 and the anode of the third diode Di23 are electrically connected.

[0320] As a result, in each of the first diode Di21, the second diode Di22, and the third diode Di23, a plurality of (two in this embodiment) unit diodes D are connected in parallel, and the first diode Di21, the second diode Di22, and the third diode Di23 are connected in series.

[0321] FIG. 35 is a front view showing the layout of a chip 2 of a semiconductor device 301 according to a third embodiment of the present disclosure, corresponding to FIG. 14 . FIG. 36 is a front view showing the layout of a first wiring layer 16 according to the third embodiment, corresponding to FIG. 15A . FIG. 37 is a front view showing the layout of a second wiring layer 17 according to the third embodiment, corresponding to FIG. 15A . FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in FIG. 35 . FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX in FIG. 35 . FIG. 40 is a cross-sectional view taken along line XL-XL in FIG. 35 . FIG. 41 is a cross-sectional view taken along line XLI-XL in FIG. 35 . FIG. 42 is a diagram showing a current flow in a first temperature-sensitive diode 309A according to the third embodiment. FIG. 43 is an electrical circuit diagram of the first temperature-sensitive diode 309A according to the third embodiment. In FIGS. 35 and 42 , the cathode region 179 is hatched for clarity.

[0322] 1 to 23 in that the semiconductor device 301 includes a first temperature sensitive diode 309A instead of the first temperature sensitive diode 9A. In the third embodiment, only the parts that differ from the first embodiment will be mainly described, and the same reference numerals will be used to designate the same components as those described so far, and their description will be omitted.

[0323] Referring to FIG. 35, the first temperature sensitive diode 309A includes one second trench isolation structure 100. A plurality of stripe-shaped diode trench structures 170 are formed in the region inside the second trench isolation structure 100. A mesa portion 110 is defined in the region between two adjacent diode trench structures 170. The plurality of mesa portions 110 are formed in stripes extending in the second direction Y in plan view. In this embodiment, the number of diode trench structures 170 is seven. The number of mesa portions 110 is six.

[0324] As described above, one unit diode D has a one-to-one correspondence with one mesa portion 110. One unit diode D can be regarded as an independent diode.

[0325] The multiple mesa portions 110 are, in order from one side in the first direction X (the side of the third side surface 5C (Figure 1)), a first mesa portion 110A, a second mesa portion 110B, a third mesa portion 110C, a fourth mesa portion 110D, a fifth mesa portion 110E, and a sixth mesa portion 110F.

[0326] Specifically, one unit diode D includes a p-type anode region 180 and an n-type cathode region 179 formed in a surface layer portion of the second body region 167. In this embodiment, the patterns of the p-type anode region 180 and the n-type cathode region 179 are the same in the first to sixth mesa portions 110A to 110F.

[0327] One unit diode D includes two anode regions 180 and one cathode region 179. The two anode regions 180 are arranged (arranged) to sandwich one cathode region 179. In each mesa portion 110 (unit diode D), the total planar area of ​​the anode regions 180 is greater than the total planar area of ​​the cathode regions 179.

[0328] The two high-concentration regions 180a sandwich the low-concentration region 180b in the second direction Y. In each mesa portion 110 (unit diode D), the total plane area of ​​the high-concentration regions 180a is greater than the total plane area of ​​the low-concentration regions 180b.

[0329] The first temperature sensitive diode 309A includes a first diode Di31 and a second diode Di32 that are formed to be electrically isolated from each other. The first diode Di31 has a plurality of (for example, three) unit diodes D. The three unit diodes D are a unit diode D corresponding to the first mesa portion 110A, a unit diode D corresponding to the second mesa portion 110B, and a unit diode D corresponding to the third mesa portion 110C.

[0330] The second diode Di32 has a plurality of (for example, three) unit diodes D. The three unit diodes D are a unit diode D corresponding to the fourth mesa portion 110D, a unit diode D corresponding to the fifth mesa portion 110E, and a unit diode D corresponding to the sixth mesa portion 110F.

[0331] In this embodiment, the first diode Di31 and the second diode Di32, which are formed to be electrically isolated from each other, are surrounded by a single second trench isolation structure 100. In other words, the second trench isolation structure 100 collectively surrounds the first diode Di31 and the second diode Di32. That is, the second trench isolation structure 100 electrically isolates the first diode Di31 and the second diode Di32 from regions outside the second trench isolation structure 100.

[0332] The cathode region 179 included in the first diode Di31 faces the cathode region 179 included in the second diode Di32 in the first direction X. In other words, the cathode region 179 included in the first diode Di31 is aligned in the second direction Y with the cathode region 179 included in the second diode Di32.

[0333] The high-concentration region 180a included in the first diode Di31 faces the high-concentration region 180a included in the second diode Di32 in the first direction X. In other words, the high-concentration region 180a included in the first diode Di31 is aligned in the second direction Y with the high-concentration region 180a included in the second diode Di32.

[0334] The low-concentration region 180b included in the first diode Di31 faces the low-concentration region 180b included in the second diode Di32 in the first direction X. In other words, the low-concentration region 180b included in the first diode Di31 is aligned in the second direction Y with the low-concentration region 180b included in the second diode Di32.

[0335] 36, 37, and 43, the semiconductor device 301 includes a first connection wiring structure 350 that connects a first diode Di31 and a second diode Di32 in series. The first connection wiring structure 350 includes one first lower connection wiring 352A (FIG. 36, lower wiring) included in the first wiring layer 16, two second lower connection wirings 352B (FIG. 36, lower wiring) included in the first wiring layer 16, and one first upper connection wiring 356 (FIG. 37, upper wiring) included in the second wiring layer 17. The one first lower connection wiring 352A, the two second lower connection wirings 352B, and the one first upper connection wiring 356 connect the cathode of the first diode Di31 and the anode of the second diode Di32.

[0336] 36, the first connection wiring structure 350 includes a plurality of via electrodes 161-166 embedded in the interlayer insulating layer 12. The structures of the anode wiring 351, the cathode wiring 353, the first lower connection wiring 352A, the second lower connection wiring 352B, and the first upper connection wiring 356 will be described below.

[0337] The anode wiring 351 may also be referred to as an "anode pad wiring." The anode wiring 351 extends in the first direction X. The anode wiring 351 faces two second lower connection wirings 352B in the first direction X. In this configuration, the anode wiring 351 sandwiches one first lower connection wiring 352A between itself and the cathode wiring 353 in the first direction X. The cathode wiring 353 sandwiches two second lower connection wirings 352B in the second direction Y. Both ends of the anode wiring 351 in the second direction Y are located outside the both ends of the second trench isolation structure 100 in the second direction Y. The width of the anode wiring 351 in the second direction Y is greater than the length of the second trench isolation structure 100 in the second direction Y.

[0338] The anode wiring 351 includes at least one outer anode lead-out wiring 351a led out to the other side in the first direction X (the fourth side surface 5D (FIG. 1) side) at both ends in the second direction Y. In this embodiment, the number of outer anode lead-out wirings 351a is two. The outer anode lead-out wiring 351a is electrically connected to the second separated electrode 103 (FIG. 38, etc.) through a fifth via electrode 165.

[0339] The anode wiring 351 includes at least one inner anode lead-out wiring 351b that is led out to the other side in the first direction X (the fourth side surface 5D (FIG. 1) side) in the center in the second direction Y. In this embodiment, the number of inner anode lead-out wirings 351b is two. The inner anode lead-out wiring 351b is electrically connected to the high-concentration region 180a (FIG. 35) of the unit diode D included in the first diode Di31 through the second via electrode 162.

[0340] In this configuration, the two inner anode lead wires 351b are sandwiched between the two outer anode lead wires 351a in the second direction Y. In other words, the two outer anode lead wires 351a sandwich the two inner anode lead wires 351b in the second direction Y.

[0341] The base of the anode wiring 351 (the portion of the anode wiring 351 excluding the outer anode lead wiring 351a and the inner anode lead wiring 351b) is connected to the mesa region (the mesa region between the second trench isolation structure 100 and the diode trench structure 170) of the unit diode D ( FIG. 35 ) included in the first diode Di31 through the fourth via electrode 164. In this embodiment, the anode wiring 351 is included in the first wiring layer 16, but is not included in the second wiring layer 17.

[0342] Although not shown, the semiconductor device 301 includes a second connection wiring structure 401 (FIGS. 15B and 15C) that electrically connects the anode wiring 351 and the drift region 11. A connection pad wiring 402 (FIGS. 15B and 15C) of the second connection wiring structure 401 contacts the anode wiring 351 over the entire area in the second direction Y. This electrically connects the connection pad wiring 402 and the anode wiring 351.

[0343] The cathode wiring 353 may also be referred to as a "cathode pad wiring." The cathode wiring 353 extends in the first direction X. The cathode wiring 353 faces the first lower connection wiring 352A in the first direction X. In this configuration, the cathode wiring 353 sandwiches one first lower connection wiring 352A between itself and the anode wiring 351 in the first direction X. The cathode wiring 353 sandwiches two second lower connection wirings 352B in the second direction Y.

[0344] The cathode wiring 353 includes at least one outer cathode lead-out wiring 353a led out to one side in the first direction X (the third side surface 5C (FIG. 1) side) at both ends in the second direction Y. In this embodiment, the number of outer cathode lead-out wirings 353a is two. The outer cathode lead-out wiring 353a is electrically connected to the diode-connecting electrode 193 (FIG. 19A) through the third via electrode 163. The outer cathode lead-out wiring 353a is electrically connected to the first upper electrode 173 through the sixth via electrode 166.

[0345] The cathode wiring 353 includes at least one inner cathode lead-out wiring 353b led out from the base 353c to one side in the first direction X (toward the third side surface 5C (FIG. 1)) in the center in the second direction Y. In this embodiment, the number of inner cathode lead-out wirings 353b is one. The inner cathode lead-out wiring 353b is electrically connected to the cathode region 179 (FIG. 35) of the unit diode D included in the second diode Di32 through the first via electrode 161. The width in the second direction Y of the inner cathode lead-out wiring 353b may be equal to the width in the second direction Y of the inner anode lead-out wiring 351b. In this embodiment, the cathode wiring 353 is included in the first wiring layer 16, but is not included in the second wiring layer 17.

[0346] The first lower connection wiring 352A may be referred to as a "first connection pad wiring." The first lower connection wiring 352A has a rectangular shape extending in the first direction X. One first lower connection wiring 352A is sandwiched in the first direction X and the second direction Y by the anode wiring 351 and the cathode wiring 353. One first lower connection wiring 352A is sandwiched in the second direction Y by two inner anode lead-out wirings 351b. The first lower connection wiring 352A faces the inner cathode lead-out wiring 353b in the first direction X.

[0347] The first lower connection wiring 352A is electrically connected through a first via electrode 161 to the cathode region 179 (FIG. 35) of the unit diode D included in the first diode Di31.

[0348] The second lower connection wirings 352B may also be referred to as "second connection pad wirings." Each of the two second lower connection wirings 352B has a rectangular shape extending in the first direction X. The two second lower connection wirings 352B are sandwiched in the first direction X and the second direction Y by the anode wiring 351 and the cathode wiring 353. The two second lower connection wirings 352B sandwich one inner cathode lead-out wiring 353b in the second direction Y. The second lower connection wiring 352B faces the inner anode lead-out wiring 351b in the first direction X.

[0349] The second lower connection wiring 352B is electrically connected through the second via electrode 162 to the high concentration region 180a (FIG. 35) of the unit diode D included in the second diode Di32.

[0350] 37, the first upper connection wiring 356 is U-shaped in a plan view. The first upper connection wiring 356 includes a base 356a and two outer lead-out wirings 356b led out from both ends in the second direction Y from the base 356a to the other side in the first direction X (the fourth side surface 5D (FIG. 1) side). The first upper connection wiring 356 is electrically connected to both the first lower connection wiring 352A and the second lower connection wiring 352B via a sixth connection via 361.

[0351] That is, the connection wirings 352A, 352B, and 356 electrically connect the cathode region 179 (FIG. 35) of the unit diode D included in the first diode Di31 and the high-concentration region 180a (FIG. 35) of the unit diode D included in the second diode Di32.

[0352] 42, the cathode region 179 of the unit diode D included in the first diode Di31 is electrically connected to the high-concentration region 180a of the unit diode D included in the second diode Di32. In other words, the cathode of the first diode Di31 is electrically connected to the anode of the second diode Di32. Therefore, as shown in bold in FIG. 42, a current path is formed from the cathode of the first diode Di31 to the anode of the second diode Di32.

[0353] 43, in each of the first diode Di31 and the second diode Di32, a plurality of (three in this embodiment) unit diodes D are connected in parallel. The first diode Di31 and the second diode Di32 are connected in series by the first lower connecting wiring 352A, the second lower connecting wiring 352B, and the first upper connecting wiring 356.

[0354] The semiconductor device 301 according to the third embodiment of the present disclosure provides the same effects as those described in relation to the first embodiment.

[0355] Furthermore, according to the semiconductor device 301, the first diode Di31 and the second diode Di32, which are formed so as to be electrically isolated from each other, are surrounded by a single second trench isolation structure 100. This makes it possible to reduce the planar area of ​​the first temperature sensitive diode 309A compared to the first embodiment. This allows for a further reduction in the planar area of ​​the chip 2.

[0356] In addition, since all the unit diodes D are included in the area surrounded by one second trench isolation structure 100, variations in diode characteristics can be reduced.

[0357] Fig. 44 is a front view showing the layout of a chip 2 according to a third modified example of the third embodiment of the present disclosure, and corresponds to Fig. 35. Fig. 45 is a front view showing the layout of a first wiring layer 16 according to the third modified example, and corresponds to Fig. 36. Fig. 46 is a front view showing the layout of a second wiring layer 17 according to the third modified example, and corresponds to Fig. 37.

[0358] The semiconductor device 301 shown in Figures 44 to 46 differs from the semiconductor device 301 shown in Figures 35 to 43 in that the number of mesa portions 110 is changed from six to nine. As described above, one unit diode D corresponds one-to-one to one mesa portion 110. One unit diode D can be regarded as an independent diode.

[0359] The multiple mesa portions 110 are, in order from one side in the first direction X (the side of the third side surface 5C (Figure 1)), a first mesa portion 110A, a second mesa portion 110B, a third mesa portion 110C, a fourth mesa portion 110D, a fifth mesa portion 110E, a sixth mesa portion 110F, a seventh mesa portion 110G, an eighth mesa portion 110H, and a ninth mesa portion 110J.

[0360] In the seventh to ninth mesa portions 110G to 110J, the unit diodes D include two anode regions 180 and one cathode region 179. The patterns of these p-type anode regions 180 and n-type cathode regions 179 are common to the first mesa portion 110A and the second mesa portion 110B.

[0361] In the third modification, the first temperature sensitive diode 309A includes a third diode Di33 in addition to the first diode Di31 and the second diode Di32. The third diode Di33 is formed so as to be electrically isolated from each of the first diode Di31 and the second diode Di32.

[0362] The third diode Di33 has a plurality of (for example, three) unit diodes D. The three unit diodes D are a unit diode D corresponding to the seventh mesa portion 110G, a unit diode D corresponding to the eighth mesa portion 110H, and a unit diode D corresponding to the ninth mesa portion 110J, respectively.

[0363] In the third modification, the first diode Di31, the second diode Di32, and the third diode Di33, which are formed so as to be electrically isolated from one another, are surrounded by a single second trench isolation structure 100. The first diode Di31, the second diode Di32, and the third diode Di33 are connected in series in this order.

[0364] The cathode region 179 included in the third diode Di33 faces the cathode region 179 included in the second diode Di32 in the first direction X. In other words, the cathode region 179 included in the third diode Di33 is aligned in the second direction Y with the cathode region 179 included in the second diode Di32.

[0365] The high-concentration region 180a included in the third diode Di33 faces the high-concentration region 180a included in the second diode Di32 in the first direction X. In other words, the high-concentration region 180a included in the third diode Di33 is aligned in the second direction Y with the high-concentration region 180a included in the second diode Di32.

[0366] The low-concentration region 180b included in the third diode Di33 faces the low-concentration region 180b included in the second diode Di32 in the first direction X. In other words, the low-concentration region 180b included in the third diode Di33 is aligned in the second direction Y with the low-concentration region 180b included in the second diode Di32.

[0367] Referring to Figures 45 and 46, in the third modified example, the first connection wiring structure 350 includes, in addition to the connection wirings 352A, 352B, and 356, one third lower connection wiring 354A (Figure 45, lower wiring) included in the first wiring layer 16, two fourth lower connection wirings 354B (Figure 45, lower wiring) included in the first wiring layer 16, and one second upper connection wiring 357 (Figure 46, upper wiring) included in the second wiring layer 17.

[0368] The third lower connection wiring 354A may be referred to as a "third connection pad wiring." The third lower connection wiring 354A has a rectangular shape extending in the first direction X. One third lower connection wiring 354A is sandwiched in the first direction X and the second direction Y by the anode wiring 351 and the cathode wiring 353. One third lower connection wiring 354A is sandwiched in the second direction Y by two second lower connection wirings 352B. The third lower connection wiring 354A is sandwiched in the first direction X by the first lower connection wiring 352A and the inner cathode lead-out wiring 353b.

[0369] The third lower connecting wire 354A is electrically connected through the first via electrode 161 to the cathode region 179 (FIG. 35) of the unit diode D included in the second diode Di32.

[0370] The two fourth lower connection wirings 354B may also be referred to as "fourth connection pad wirings." Each of the two fourth lower connection wirings 354B has a rectangular shape extending in the first direction X. The two fourth lower connection wirings 354B are sandwiched in the first direction X and the second direction Y by the anode wiring 351 and the cathode wiring 353. The two fourth lower connection wirings 354B sandwich one inner cathode lead-out wiring 353b in the second direction Y. The two fourth lower connection wirings 354B each face two second lower connection wirings 352B in the first direction X.

[0371] The two fourth lower connection wirings 354B are electrically connected through the second via electrodes 162 to the high concentration regions 180a (FIG. 35) of the unit diode D included in the third diode Di33.

[0372] 46, the second upper connection wiring 357 includes a base 357c and two outer extraction wirings 357d extracted from the base 357c to one side in the first direction X (toward the third side surface 5C (FIG. 1)) at the center in the second direction Y. The second upper connection wiring 357 is electrically connected to both the third lower connection wiring 354A and the fourth lower connection wiring 354B through a sixth connection via 361.

[0373] That is, the connection wirings 354A, 354B, and 357 electrically connect the cathode region 179 (FIG. 44) of the unit diode D included in the second diode Di32 and the high-concentration region 180a (FIG. 44) of the unit diode D included in the third diode Di33. In other words, the cathode of the second diode Di32 and the anode of the third diode Di33 are electrically connected.

[0374] As a result, in each of the first diode Di31, the second diode Di32, and the third diode Di33, a plurality of (three in this embodiment) unit diodes D are connected in parallel, and the first diode Di31, the second diode Di32, and the third diode Di33 are connected in series.

[0375] The forward voltage Vf and the variation in the Vf value for the first temperature sensitive diode 9A in the embodiment (first embodiment) of FIG. 16 and the embodiment (first modified example) of FIG. 25, the first temperature sensitive diode 209A in the embodiment (second embodiment) of FIG. 27 and the embodiment (second modified example) of FIG. 33, and the first temperature sensitive diode 309A in the embodiment (third embodiment) of FIG. 35 and the embodiment (third modified example) of FIG. 44 are as follows. The variation in the Vf value is the standard deviation (σ) of the Vf value when, for example, 50 first temperature sensitive diodes 9A, 209A, 309A are measured. The smaller the value of the standard deviation (σ), the smaller the variation in the Vf value.

[0376] In this case, for the first temperature-sensitive diode 9A of the example (first embodiment) of Figure 16, Vf = 1.2V and σ = 4mV, and for the first temperature-sensitive diode 9A of the example (second embodiment) of Figure 25, Vf = 1.6V and σ = 10mV.

[0377] In the first temperature sensitive diode 209A of the embodiment (second embodiment) of Figure 27, Vf = 1.3V and σ = 3mV, and in the first temperature sensitive diode 209A of the embodiment (second modified example) of Figure 33, Vf = 1.8V and σ = 8mV.

[0378] In the first temperature sensitive diode 309A of the embodiment (third embodiment) of Figure 35, Vf = 1.3V and σ = 2mV, and in the first temperature sensitive diode 309A of the embodiment (third modified example) of Figure 44, Vf = 1.8V and σ = 8mV.

[0379] 27 (second embodiment), the embodiment (second modified example) of FIG. 33, the embodiment (third embodiment) of FIG. 35, and the embodiment (third modified example) of FIG. 44, the variation (standard deviation (σ)) of the Vf value is small. In other words, in the embodiment in which the first diodes Di21, Di31 and the second diodes Di22, Di32 (and the third diodes Di23, Di33) are surrounded by a single second trench isolation structure 100, the variation (standard deviation (σ)) of the Vf value is small.

[0380] While several embodiments of the present disclosure have been described, the present disclosure may be embodied in still other forms.

[0381] Although the number of unit diodes D included in the first diode Di1, the second diode Di2, the third diode Di3, the first diode Di21, the second diode Di22, the third diode Di23, the first diode Di31, the second diode Di32, and the third diode Di33 is two or three, the number of unit diodes D included in these may be four or more. The number of unit diodes D included in these may not be multiple, but may be single.

[0382] In the first to third embodiments, the anode wirings 151, 251, and 351 are described as being arranged on one side in the first direction X (the third side surface 5C (FIG. 1) side), and the cathode wirings 153, 253, and 353 are described as being arranged on the other side in the first direction X (the fourth side surface 5D (FIG. 1) side). Alternatively, the anode wirings 151, 251, and 351 may be arranged on the other side in the first direction X (the fourth side surface 5D (FIG. 1) side), and the cathode wirings 153, 253, and 353 may be arranged on one side in the first direction X (the third side surface 5C (FIG. 1) side).

[0383] Furthermore, in each of the above-described embodiments, examples have been described in which a two-layer structure having a first wiring layer 16 and a second wiring layer 17 is adopted as the wiring structure, but the wiring structure is not limited to a two-layer structure, and may be a three-layer structure or a multi-layer structure in which four or more layers are stacked.

[0384] In addition, in each of the above-described embodiments, examples have been described in which the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings.

[0385] The embodiments of the present disclosure are to be considered in all respects as illustrative and not restrictive, and are intended to include modifications in all respects.

[0386] The following additional features can be extracted from the description of this specification and the drawings. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments.

[0387] [Appendix 1-1] a chip (2) having a main surface (3); a plurality of trench structures (170) arranged at intervals in a first direction (X) along the main surface (3) in a temperature measuring region (8) set on the main surface (3) and extending in a strip-like shape in a second direction (Y) intersecting the first direction (X), the plurality of trench structures (170) having an electrode structure including an upper electrode (173) and a lower electrode (174) vertically embedded in the trenches (171) with an insulator (172) sandwiched therebetween; a unit diode (D) having a pn junction formed in a mesa portion (110) sandwiched between a plurality of adjacent trench structures (170); a temperature-sensitive diode (9) having the unit diode (D), The temperature sensitive diode (9) a first diode (Di1, Di21, Di31) having at least one unit diode (D); second diodes (Di2, Di22, Di32) each having at least one unit diode (D) and formed so as to be electrically isolated from the first diodes (Di1, Di21, Di31); a first connection wiring structure (150, 250, 350) that connects the first diode (Di1, Di21, Di31) and the second diode (Di2, Di22, Di32) in series;

[0388] According to this configuration, the temperature-sensitive diode (9) includes first diodes (Di1, Di21, Di31) having a unit diode (D) and second diodes (Di2, Di22, Di32) having a unit diode (D). The second diodes (Di2, Di22, Di32) are formed so as to be electrically isolated from the first diodes (Di1, Di21, Di31). The first diodes (Di1, Di21, Di31) and the second diode (Di1) are connected in series by the first connection wiring structure (150, 250, 350). Therefore, the overall forward voltage can be increased compared to, for example, when only the first diodes (Di1, Di21, Di31) are used as the temperature-sensitive diode (9). This increases the voltage difference during abnormal heat generation. As a result, the temperature measurement accuracy can be improved.

[0389] [Appendix 1-2] The semiconductor device (1, 201, 301) according to Supplementary Note 1-1, wherein at least one of the first diode (Di1, Di21, Di31) and the second diode (Di2, Di22, Di32) includes a plurality of the unit diodes (D).

[0390] [Appendix 1-3] The semiconductor device (1, 201, 301) according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the first connection wiring structure (150, 250, 350) includes connection wiring (152, 154, 252, 254, 255, 352A, 352B, 354A, 354B, 356, 357) that electrically connects the anodes of the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32) to the cathodes of the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32).

[0391] [Appendix 1-4] anode wirings (151, 251, 351) electrically connected to the anodes of the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32); cathode wirings (153, 253, 353) electrically connected to the cathodes of the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32); a first conductivity type drift region (11) formed in a surface layer portion of the main surface (3); the temperature detection region (8) further includes a body region (167) of a second conductivity type formed in a surface layer portion of the drift region (11) on the main surface (3) side, The trench structure (170) is formed so as to extend from the main surface (3) through the body region (167) to the drift region (11), The semiconductor device (1, 201, 301) according to appendix 1-3, further comprising a second connection wiring structure (401) that electrically connects the anode wiring (151, 251, 351) and the drift region (11).

[0392] According to this configuration, the anode wirings (151, 251, 351) and the drift region (11) are electrically connected by the second connection wiring structure (401).

[0393] For example, when first diodes (Di1, Di21, Di31) and second diodes (Di2, Di22, Di32), each including a unit diode (D) formed in a mesa portion (110), are connected in series, a current may be generated by a parasitic transistor (npn). If the potential difference between the body region (167) and the drift region (11) is large, a large current may be generated by the parasitic transistor, which may cause damage to the semiconductor device (1, 201, 301).

[0394] In this configuration, the anode wiring (151, 251, 351) and the drift region (11) are electrically connected, so the body region (167) can be fixed at the same potential as the drift region (11). Therefore, even when the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32), each including a unit diode (D), are connected in series, the generation of a large current due to a parasitic transistor can be suppressed. This allows the voltage difference during abnormal heat generation to be increased without risk of damage to the semiconductor device (1, 201, 301).

[0395] [Appendix 1-5] 5. The semiconductor device (1, 201, 301) according to claim 4, wherein the second connection wiring structure (401) includes a connection pad wiring (402) connected to the anode wiring (151, 251, 351), and a plurality of connection via electrodes (403) electrically connecting the connection pad wiring (402) and the drift region (11).

[0396] [Appendix 1-6] anode wirings (151, 251, 351) electrically connected to the anodes of the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32); cathode wirings (153, 253, 353) electrically connected to the cathodes of the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32); a first conductivity type drift region (11) formed in a surface layer portion of the main surface (3); the temperature detection region (8) further includes a body region (167) of a second conductivity type formed in a surface layer portion of the drift region (11) on the main surface (3) side, The semiconductor device (1, 201, 301) according to any one of Supplementary Notes 1-3 to 1-5, wherein the connection wiring (152, 154, 252, 254, 255, 352A, 352B, 354A, 354B, 356, 357) is sandwiched in the second direction (Y) by the anode wiring (151, 251, 351).

[0397] [Appendix 1-7] The semiconductor device (1, 201, 301) according to appendix 1-6, wherein the connection wirings (152, 154, 252, 254, 255, 352A, 352B, 354A, 354B, 356, 357) sandwich the cathode wiring (153, 253, 353) in the second direction (Y).

[0398] [Appendix 1-8] The semiconductor device (301) according to any one of Appendices 1-3 to 1-7, wherein the connection wirings (352A, 352B, 354A, 354B, 356, 357) include lower wirings (352A, 352B, 354A, 354B) included in a first wiring layer (16) and upper wirings (356, 357) electrically connected to the lower wirings (352A, 352B, 354A, 354B) and included in a second wiring layer (17) arranged above the first wiring layer (16).

[0399] [Appendix 1-9] a first conductivity type drift region (11) formed in a surface layer portion of the main surface (3); the temperature detection region (8) further includes a body region (167) of a second conductivity type formed in a surface layer portion of the drift region (11) on the main surface (3) side, The trench structure (170) is formed so as to extend from the main surface (3) through the body region (167) to the drift region (11), The semiconductor device (1, 201, 301) according to any one of Supplementary Notes 1-1 to 1-8, wherein the body region (167) is fixed to the same potential as the drift region (11).

[0400] For example, when first diodes (Di1, Di21, Di31) and second diodes (Di2, Di22, Di32), each including a unit diode (D) formed in a mesa portion (110), are connected in series, a current may be generated by a parasitic transistor (npn). If the potential difference between the body region (167) and the drift region (11) is large, a large current may be generated by the parasitic transistor, which may cause damage to the semiconductor device (1, 201, 301).

[0401] In this configuration, the anode wiring (151, 251, 351) and the drift region (11) are electrically connected, so the body region (167) can be fixed at the same potential as the drift region (11). Therefore, even when the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32), each including a unit diode (D), are connected in series, the generation of a large current due to a parasitic transistor can be suppressed. This allows the voltage difference during abnormal heat generation to be increased without risk of damage to the semiconductor device (1, 201, 301).

[0402] [Appendix 1-10] A semiconductor device (1, 201, 301) according to appendix 1-9, wherein the unit diode (D) includes an anode region (180) of a second conductivity type formed in the body region (167), and a cathode region (179) of a first conductivity type formed in the body region (167) so as to form the pn junction with the anode region (180).

[0403] [Appendix 1-11] The semiconductor device (1, 201, 301) according to appendix 1-10, wherein the cathode region (179) is sandwiched between two of the anode regions (180) in the second direction (Y).

[0404] [Appendix 1-12] A semiconductor device (201) according to appendix 1-11, wherein the cathode regions (179) included in the first diodes (Di1, Di21, Di31) are shifted in the second direction (Y) relative to the cathode regions (179) included in the second diodes (Di2, Di22, Di32).

[0405] [Appendix 1-13] A semiconductor device (1, 201, 301) according to any one of Appendices 1-1 to 1-12, including an isolation structure (100) formed in the temperature detection region (8), surrounding the periphery of each of the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32), and electrically isolating the first diodes (Di1, Di21, Di31) and the second diodes (Di2, Di22, Di32) from each other.

[0406] [Appendix 1-14] A semiconductor device (1, 201, 301) according to any one of Appendices 1-1 to 1-12, including an isolation structure (100) formed in the temperature detection region (8) and surrounding the first diode (Di1, Di21, Di31) and the second diode (Di2, Di22, Di32), electrically isolating the first diode (Di1, Di21, Di31) and the second diode (Di2, Di22, Di32) from regions outside the isolation structure (100).

[0407] [Appendix 1-15] the temperature-sensitive diode (9) has at least one unit diode (D) and further includes a third diode (Di3, Di23, Di33) formed so as to be electrically isolated from the first diode (Di1, Di21, Di31) and the second diode (Di2, Di22, Di32); A semiconductor device (1, 201, 301) according to any one of Supplementary Notes 1-1 to 1-14, wherein the first connection wiring structure (150, 250, 350) connects the first diode (Di1, Di21, Di31), the second diode (Di2, Di22, Di32), and the third diode (Di3, Di23, Di33) in series. [Explanation of symbols]

[0408] 1: Semiconductor device 2: Tip 3: First main surface (main surface) 4: Second main surface 5A: 1st side 5B: 2nd side 5C: 3rd side 5D: 4th side 6: Output area 7: Control area 8: Temperature measurement area 8A: First temperature measurement area 8B: Second temperature measurement area 9: Temperature-sensitive diode 9A: First temperature sensing diode 9B: Second temperature sensing diode 10: Drain region 11: Drift region 12: Interlayer insulating layer 13: Source terminal 14: Control terminal 14a: Ground terminal 14b: Input terminal 15: Drain terminal 16: 1st wiring layer 17: 2nd wiring layer 18: Gate wiring 18A: 1st system gate wiring 18B: Second system gate wiring 19: Source wiring 19A: First source wiring 19B: Second source wiring 20: Output transistor 21: System transistor 21A: 1st system transistor 21B: Second system transistor 22: Unit transistor 23: Control circuit 24: Gate control circuit 25: Current monitor circuit 26: Overcurrent protection circuit 27: Overheat protection circuit 28: Low voltage malfunction prevention circuit 29: Open load detection circuit 30: Active clamp circuit 31: Power supply reverse connection protection circuit 32: Logic circuit 33: Test circuit 34: Amplification circuit 43: Low potential application part 44: 1st current source 45:Second current source 46:Differential circuit 47: Comparator 48: Logic circuit 49: Offset circuit 60: First trench isolation structure 61: First isolation trench 62: First isolation insulating layer 63: 1st separation electrode 64: High concentration drift region 67: First body region 68: Separation corner 70: Trench gate structure 71: Gate trench 72: Insulating layer 73: Upper electrode 74: Lower electrode 75: Intermediate insulating layer 76: Upper insulating layer 77: Lower insulating layer 78: Channel cell 79: Source area 80: Contact area 81: Block area 81A: First block area 81B: Second block area 84: First insulating layer 85: Second insulating layer 86: Third insulating layer 90: Trench connection structure 91: Connection trench 92: Connection insulation layer 93: Connection electrode 94: Main surface insulating layer 95: Field insulation layer 97: Via electrode 100: Second trench isolation structure (isolation structure) 101: Second isolation trench 102: Second isolation insulating layer 103:Second separation electrode 110: Mesa section 110A: First mesa section 110B: Second mesa section 110C: Third Mesa 110D: 4th Mesa 110E: 5th Mesa 110F: 6th Mesa 110G: 7th Mesa 110H: 8th Mesa 110J: 9th Mesa 150: First connection wiring structure 151: Anode wiring 151a: Outer anode lead wiring 151b: Inner anode lead wiring 152: First connection wiring (connection wiring) 152a: External lead-out connection wiring 152b: Inner lead-out connection wiring 152c: Narrow part 152d: Internal drawer connection wiring 154: Second connection wiring (connection wiring) 153: Cathode wiring 153d: Cathode lead wiring 161: First via electrode 162: Second via electrode 163: Third via electrode 164: Fourth via electrode 165: 5th via electrode 166: 6th via electrode 167: Second body region (body region) 170: Diode trench structure 170a: 1st end 170b: Second end 171: Diode trench 172: First insulating layer 173: 1st upper electrode 174: 1st lower electrode 175: First intermediate insulating layer 176: First upper insulating layer 177: First lower insulating layer 179: Cathode region 180: Anode region 180a: High concentration area 180b: Low concentration area 181: First gate wiring 182: Second gate wiring 190: Diode connection structure 191: First source wiring 192: Second source wiring 193: Diode connection electrode 196: Diode connection trench 197: Diode connection insulating layer 201: Semiconductor device 209A: First temperature sensing diode 250: First connection wiring structure 251: Anode wiring 251a: Outer anode lead wiring 251b: Inner anode lead wiring 252: First connection wiring (connection wiring) 253: Cathode wiring 253a: Outer cathode lead wiring 253b: Inner cathode lead wiring 253c: base 254: Second connection wiring (connection wiring) 255: Third connection wiring (connection wiring) 301: Semiconductor device 309A: First temperature sensing diode 350: First connection wiring structure 351: Anode wiring 351a: Outer anode lead wiring 351b: Inner anode lead wiring 352A: 1st lower connection wiring (lower wiring) 352B: Second lower connection wiring (lower wiring) 354A: Third lower connection wiring (lower wiring) 354B: 4th lower connection wiring (lower wiring) 353: Cathode wiring 353a: Outer cathode lead wiring 353b: Inner cathode lead wiring 353c: base 356: First upper connection wiring (upper wiring) 356a: base 356b: External wiring 357: Second upper connection wiring (upper wiring) 357c: base 357d: External wiring 361: 6th connection via 401: Second connection wiring structure 402: Connection pad wiring 403: Connection via electrode 404: Via electrode placement area 405: High concentration area D: Unit diode D1: First depth D2: Second depth D3: Third depth D4: Fourth depth Di1: First diode Di2: Second diode Di3: Second diode Di21: First diode Di22: Second diode Di23: Third diode Di31: First diode Di32: Second diode Di33: Third diode I1: First interval I2: Second interval Io: Output current Is: Grid current Iu: unit current L: Inductive load N1: First node N2: Second node ST1: First temperature detection signal ST2: Second temperature detection signal VBB: Power supply potential W1: 1st width W2: Second width W3: 3rd width W4: 4th width X: 1st direction Y: Second direction Z: Vertical direction

Claims

1. a chip having a major surface; a plurality of diode trench structures arranged at intervals in a first direction along the main surface in a temperature measurement region set on the main surface and extending in a strip-like shape in a second direction intersecting the first direction, the plurality of diode trench structures having electrode structures including upper and lower electrodes vertically embedded in the first trenches with an insulator sandwiched therebetween; a unit diode having a pn junction and formed in a mesa portion sandwiched between a plurality of adjacent diode trench structures; a temperature sensitive diode having the unit diode; The temperature sensitive diode is a first diode having at least one unit diode; a second diode having at least one unit diode and formed so as to be electrically isolated from the first diode; a first connection wiring structure that connects the first diode and the second diode in series.

2. The semiconductor device according to claim 1 , wherein at least one of said first diode and said second diode includes a plurality of said unit diodes.

3. 2. The semiconductor device according to claim 1, wherein said first connection wiring structure includes a connection wiring that electrically connects one of said first diode and said second diode to a cathode of said first diode and a cathode of said second diode.

4. an anode wiring electrically connected to the anodes of the first diode and the second diode; a cathode wiring electrically connected to the cathodes of the first diode and the second diode; a first conductivity type drift region formed in a surface layer portion of the main surface; the temperature measuring region further includes a body region of a second conductivity type formed in a surface layer portion of the drift region on the main surface side, the diode trench structure is formed so as to extend from the main surface through the body region to the drift region, 4. The semiconductor device according to claim 3, further comprising a second connection wiring structure electrically connecting said anode wiring and said drift region.

5. 5. The semiconductor device according to claim 4, wherein the second connection wiring structure includes a connection pad wiring connected to the anode wiring, and a plurality of connection via electrodes electrically connecting the connection pad wiring and the drift region.

6. an anode wiring electrically connected to the anodes of the first diode and the second diode; a cathode wiring electrically connected to the cathodes of the first diode and the second diode, 4. The semiconductor device according to claim 3, wherein said connection wiring is sandwiched between said anode wirings in said second direction.

7. The semiconductor device according to claim 6 , wherein the connection wirings sandwich the cathode wiring in the second direction.

8. The semiconductor device according to any one of claims 3 to 7, wherein the connection wiring includes a lower wiring included in a first wiring layer and an upper wiring included in a second wiring layer electrically connected to the lower wiring and arranged above the first wiring layer.

9. a first conductivity type drift region formed in a surface layer portion of the main surface; the temperature measuring region further includes a body region of a second conductivity type formed in a surface layer portion of the drift region on the main surface side, the diode trench structure is formed so as to extend from the main surface through the body region to the drift region, 2. The semiconductor device according to claim 1, wherein said body region is fixed to the same potential as said drift region.

10. 10. The semiconductor device according to claim 9, wherein the unit diode includes an anode region of the second conductivity type formed in the body region, and a cathode region of the first conductivity type formed in the body region so as to form the pn junction with the anode region.

11. The semiconductor device according to claim 10 , wherein the cathode region is sandwiched between two of the anode regions in the second direction.

12. The semiconductor device according to claim 10 , wherein the cathode region included in the first diode is shifted in the second direction relative to the cathode region included in the second diode.

13. 10. The semiconductor device according to claim 1, further comprising: isolation structures formed in the temperature detection region, surrounding the first diode and the second diode, respectively, to electrically isolate the first diode and the second diode from each other.

14. 10. The semiconductor device according to claim 1, further comprising an isolation structure formed in the temperature detection region, surrounding the first diode and the second diode collectively, and electrically isolating the first diode and the second diode from a region outside the isolation structure.

15. the temperature-sensitive diode has at least one unit diode and further includes a third diode formed so as to be electrically isolated from the first diode and the second diode; 10. The semiconductor device according to claim 1, wherein said first connection wiring structure connects said first diode, said second diode, and said third diode in series.

Images