Power supply device

Abstract

To provide a power supply device for a capacitive load which stabilizes a voltage at a connection terminal between a current generator and the capacitive load at least either when the capacitive load is charged or when discharged regardless of the electrostatic capacitance of the capacitive load.SOLUTION: A power supply device 12 includes: a current generator CG that generates a charging-and-discharging current which charges or discharges a capacitive load 14; a measuring unit MP that outputs the measuring result of a rate of change per unit time of the potential at an output node Nout between the current generator CG and the capacitive load 14; and an adjusting unit AP that transmits, to the current generator CG, a control signal which controls the charging-and-discharging current based on the output result by the measuring unit MP.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a power supply device. [Background technology]

[0002] For example, Patent Document 1 discloses a current limiter configured by inserting and connecting a series circuit of an IGBT element and a current detection resistor into a charge / discharge line, connecting the base and emitter of a transistor to one end and the other end of the current detection resistor, respectively, and connecting the collector of this transistor to the gate of the IGBT element.When a drive signal is applied to the gate of the IGBT element and the voltage across the current detection resistor increases, the current limiter lowers the gate voltage level of the IGBT element, thereby limiting the current flowing from the collector to the emitter of the IGBT element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-217780 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure aims to provide a power supply device in which the voltage at the connection terminal between a current generating unit and a capacitive load is stable when at least one of charging and discharging the capacitive load, regardless of the capacitance of the capacitive load. [Means for solving the problem]

[0005] The power supply device of the present disclosure includes a current generating unit that generates a charge / discharge current that charges and discharges a capacitive load, a measuring unit that outputs the results of measuring the amount of change per unit time in the potential at the connection terminal between the current generating unit and the capacitive load, and an adjusting unit that transmits a control signal to the current generating unit that controls the charge / discharge current based on the output result of the measuring unit.

[0006] In this power supply device, the adjustment unit transmits a control signal to the current generating unit to control the amount of change in potential at the connection terminal between the current generating unit and the capacitive load based on the output result of the measurement unit. Therefore, with the power supply device according to this aspect, the voltage at the connection terminal between the current generating unit and the capacitive load is stable when at least one of charging and discharging the capacitive load is performed, regardless of the capacitance of the capacitive load. [Effects of the Invention]

[0007] According to the present disclosure, a power supply device is provided in which the voltage at the connection terminal between the current generating unit and the capacitive load is stable when at least one of charging and discharging the capacitive load, regardless of the capacitance of the capacitive load. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a drive circuit having a power supply device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a current generating unit in a power supply device according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a diagram illustrating a configuration of a measurement unit in a power supply device according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a diagram illustrating a configuration of an adjustment unit in a power supply device according to an embodiment of the present disclosure. [Figure 5] 10 is a first example illustrating how a capacitive load is charged by a power supply device according to an embodiment of the present disclosure, and is a time chart illustrating the potentials of capacitors and nodes in a measurement unit and an adjustment unit. [Figure 6] 6 is a first example showing how a capacitive load is charged by a power supply device according to an embodiment of the present disclosure, following FIG. 5, and is a time chart showing the potentials of capacitors and nodes in a measurement unit and an adjustment unit. [Figure 7] 10 is a second example illustrating how a capacitive load is charged by a power supply device according to an embodiment of the present disclosure, and is a time chart illustrating the potentials of capacitors and nodes in a measurement unit and an adjustment unit. [Figure 8]8 is a second example showing how a capacitive load is charged by a power supply device according to an embodiment of the present disclosure, following FIG. 7, showing the potentials of the capacitors and nodes in the measurement unit and the adjustment unit. [Figure 9] 10 is a third example illustrating how a capacitive load is charged by a power supply device according to an embodiment of the present disclosure, and is a time chart illustrating the potentials of capacitors and nodes in a measurement unit and an adjustment unit. [Figure 10] 10 is a third example following FIG. 9 showing how a capacitive load is charged by a power supply device according to an embodiment of the present disclosure, and is a time chart showing the potentials of capacitors and nodes in the measurement unit and adjustment unit. [Figure 11] FIG. 10 is a diagram illustrating the configuration of a measurement unit in a power supply device according to a first modified example of the present disclosure. [Figure 12] FIG. 10 is a diagram illustrating a configuration of an adjustment unit in a power supply device according to a second modification of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] An example of an embodiment of the present disclosure will be described below with reference to the drawings. In each drawing, the same or equivalent components and parts are designated by the same reference numerals. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions.

[0010] In the following explanation, "true value" refers to the high-level value of the binary data, and "false value" refers to the low-level value of the binary data. For example, when it is written "outputting a true value," it refers to outputting the high-level value of the binary data that can be output by any configuration, and when it is written "outputting a false value," it refers to outputting the low-level value. Furthermore, the "true value" and "false value" are not limited to specific values, and for example, a "false value" includes cases where there is no increase in potential or where the value is negative, i.e., an output value of 0 or less.

[0011] In addition, in each element described below, unless otherwise specified, multiple elements of the same type that are provided have the same specifications (for example, equivalent resistance, capacitance, and inductance).

[0012] [Embodiment] (composition) Fig. 1 is a block diagram showing a drive circuit 10 according to this embodiment. As shown in Fig. 1, the drive circuit 10 according to this embodiment has a power supply device 12 connected to a capacitive load 14. As shown in Fig. 1, the power supply device 12 also includes a current generating unit CG, a measuring unit MP, and an adjusting unit AP.

[0013] The current generating unit CG, the specific configuration of which will be described later, is a component that receives a current from a DC power supply and generates a charging current that charges the capacitive load 14 or a discharging current that discharges the capacitive load 14. The measuring unit MP, the specific configuration of which will be described later, is a component that is connected to an output node Nout, which is a node between the output terminal of the current generating unit CG and the capacitive load 14, and measures the potential of the output node Nout. The adjusting unit AP is a component that transmits a control signal, via an eleventh node N11 (to be described later), that controls the current generated by the current generating unit CG based on the amount of change in the potential of the output node Nout transmitted from the measuring unit MP. In this embodiment, the output node Nout is an example of a connection terminal between the current generating unit CG and the capacitive load 14.

[0014] Next, the specific configuration of each component will be described with reference to FIGS.

[0015] (Current generating part CG) FIG. 2 shows a specific configuration of the current generator CG in this embodiment. As shown in FIG. 2, the current generator CG has four N-type transistors: a first N-type transistor NT1, a second N-type transistor NT2, a third N-type transistor NT3, and a fourth N-type transistor NT4; and four P-type transistors: a first P-type transistor PT1, a second P-type transistor PT2, a third P-type transistor PT3, and a control P-type transistor PC. The current generator CG also has two voltage-dividing capacitors: a first voltage-dividing capacitor CD1 and a second voltage-dividing capacitor CD2. The current generator CG also has a first comparator Comp1 and a logical OR circuit OR1.

[0016] 2, the first N transistor NT1, the second N transistor NT2, and the third N transistor NT3 are each connected separately between a power supply potential point VDD and ground GND (reference potential), and their gates are connected to a common node. More specifically, the node to which the drain of the first N transistor NT1 is connected is connected to the gates of the first N transistor NT1, the second N transistor NT2, and the third N transistor NT3. As a result, the first N transistor NT1, the second N transistor NT2, and the third N transistor NT3 form current mirror circuits. In other words, a current equal to the current flowing from the drain to the source of the first N transistor NT1 can flow from the drain to the source of the second N transistor NT2 and the third N transistor NT3.

[0017] 2, the first P transistor PT1 and the second P transistor PT2 are each connected separately between a power supply potential point VDD and ground GND (reference potential), and have a common node to which their gates are connected. More specifically, the node to which the drain of the first P transistor PT1 is connected is connected to the gates of the first P transistor PT1 and the second P transistor PT2. This forms a current mirror circuit between the first P transistor PT1 and the second P transistor PT2. In other words, a current equal to the current flowing from the source to the drain of the first P transistor PT1 can flow from the source to the drain of the second P transistor PT2.

[0018] The drain of the first P transistor PT1 is connected to the drain of the second N transistor NT2, and the drain of the second P transistor PT2 is connected to the drain of the third N transistor NT3 via the third P transistor PT3 and the fourth N transistor NT4, as will be described later.

[0019] 2, the third P transistor PT3 is connected between the drain of the second transistor PT2 and the third N transistor NT3. More specifically, the source of the third P transistor PT3 is connected to the drain of the second P transistor PT2, and the drain of the third P transistor PT3 is connected to the drain of a fourth N transistor NT4 (described later). The gate of the third P transistor PT3 is connected to a node on the output side of the OR circuit OR1.

[0020] 2, the fourth N transistor NT4 is connected between the third N transistors NT3 on the drain side of the third P transistor PT3. More specifically, the drain of the fourth N transistor NT4 is connected to the drain of the third P transistor PT3, and the source of the fourth N transistor NT4 is connected to the drain of the third N transistor NT3. In addition, the gate of the fourth N transistor NT4 is connected to the discharge signal terminal LoN, as will be described later.

[0021] The control P-type transistor PC is disposed on the drain side of the first N-type transistor NT1. More specifically, the source of the control P-type transistor PC is connected to the power supply potential point VDD, and the drain of the control P-type transistor PC is connected to the drain of the first N-type transistor NT1. As shown in FIG. 2, the gate of the control P-type transistor PC is connected to an eleventh node N11 (described later), and the conduction between the source and drain is controlled based on a control signal transmitted from the adjustment unit AP (described later).

[0022] 2, the first voltage dividing capacitor CD1 and the second voltage dividing capacitor CD2 are connected in series between the output node Nout and the ground GND. That is, the potential of the output node Nout with respect to the ground GND is divided at the node between the first voltage dividing capacitor CD1 and the second voltage dividing capacitor CD2.

[0023] The first comparator Comp1 is connected to a node between the first voltage-dividing capacitor CD1 and the second voltage-dividing capacitor CD2, a first reference potential point Vref1, and an input terminal of the OR circuit OR1. The first comparator Comp1 compares the potential of the node between the first voltage-dividing capacitor CD1 and the second voltage-dividing capacitor CD2 with the potential of the first reference potential point Vref1 and outputs the comparison result as binary data. More specifically, the first comparator Comp1 outputs a true value when the potential of the first reference potential point Vref1 connected to the positive input terminal is higher than the potential of the node between the first voltage-dividing capacitor CD1 and the second voltage-dividing capacitor CD2 connected to the negative input terminal. The first comparator Comp1 also outputs a false value when the potential of the node between the first voltage-dividing capacitor CD1 and the second voltage-dividing capacitor CD2 connected to the negative input terminal is higher than the potential of the first reference potential point Vref1 connected to the positive input terminal. The potential of the first reference potential point Vref1 is lower than the potential of the power supply potential point VDD.

[0024] 2, the OR circuit OR1 has input terminals connected to the output node Nout of the first comparator Comp1 and the charging signal terminal HiN, and an output terminal connected to the gate of the third P transistor PT3. Therefore, when at least one of the values ​​input to the OR circuit OR1, i.e., the output of the charging signal terminal HiN or the first comparator Comp1, is true, the OR circuit OR1 outputs a true value. Furthermore, when both the output of the charging signal terminal HiN and the output of the first comparator Comp1 are false, the OR circuit OR1 outputs a false value.

[0025] The threshold voltages of the four P-type transistors in the current generating unit CG are all lower than the voltage of the signal input to the charging signal terminal HiN and the potential of the first reference potential point Vref1. In other words, the third P-type transistor PT3 cuts off the connection between its source and drain when the OR circuit OR1 outputs a true value.

[0026] The threshold voltages of the four N-type transistors in the current generating unit CG are all lower than the voltage of the signal input to the discharge signal terminal LoN. In other words, the fourth N-type transistor NT4 cuts off the connection between its drain and source when a signal is input to the discharge signal terminal LoN.

[0027] Next, a description will be given of how the current generating unit CG according to this embodiment charges or discharges the capacitive load 14 as shown in FIG. 1. During charging, the potential of the capacitive load 14 (i.e., the potential of the output node Nout) is assumed to be lower than the first reference potential point Vref1. During discharging, the potential of the capacitive load 14 is assumed to be higher than the first reference potential point Vref1. In the following description, when a transistor is described as being "conductive," it means that the source and drain of the transistor are electrically connected, and when a transistor is described as being "cut off," it means that the source and drain of the transistor are electrically cut off. When a transistor is described as "current flows," it means that the current flows between the source and drain of the transistor, regardless of the direction of the current.

[0028] (Charging operation) First, when the potentials of the charging signal terminal HiN and the discharging signal terminal LoN are false, the first P transistor PT1, the second P transistor PT2, and the third P transistor PT3 are conductive. The fourth N transistor NT4 is cut off. The first N transistor NT1, the second N transistor NT2, and the third N transistor NT3 are conductive.

[0029] In this state, if the potential at the gate of the control P transistor PC is false, the control P transistor PC is conductive, causing a current to flow through the first N transistor NT1. Furthermore, a current equivalent to the current flowing through the first N transistor NT1 connected to the power supply potential point VDD via the control P transistor PC can flow through the second N transistor NT2 via the current mirror circuit. Furthermore, the current flowing through the second N transistor NT2 flows through the second P transistor PT2 connected in series. Furthermore, a current equivalent to the current flowing through the second N transistor NT2 connected to the power supply potential point VDD via the first P transistor PT1 can flow through the second P transistor PT2 via the current mirror circuit. In other words, the control P transistor PC is an example of a switch element in this embodiment.

[0030] Here, because the third P transistor PT3 is conductive and the fourth N transistor NT4 is cut off, the current flowing through the second P transistor PT2 is transmitted to the output node Nout and charges the capacitive load 14. As the capacitive load 14 is charged by the current flowing toward the capacitive load 14, the voltage required to charge the capacitive load 14, i.e., the potential of the output node Nout, increases.

[0031] The potential of the output node Nout is divided by a first voltage dividing capacitor CD1 and a second voltage dividing capacitor CD2 and input to a first comparator Comp1. When the potential input to the first comparator Comp1 becomes higher than the potential of the first reference electrode, the first comparator Comp1 outputs a true value.

[0032] 2, the output terminal of the first comparator Comp1 is connected to the input of the OR circuit OR1, so when the first comparator Comp1 outputs a true value, the OR circuit OR1 also outputs a true value. In other words, when the potential of the output node Nout exceeds the potential of the first reference potential point Vref1, which is a predetermined threshold, a true value is applied to the gate of the third P transistor PT3, causing the third P transistor PT3 to turn off.

[0033] Then, when the third P transistor PT3 is turned off, current stops flowing through the third P transistor PT3, thereby stopping charging of the capacitive load 14. In this way, in the current generator of this embodiment, when the potential of the output node Nout exceeds the potential of the first reference potential point Vref1, which is a predetermined threshold, charging of the capacitive load 14 stops.

[0034] In this way, a charging current flows through the second P transistor PT2 and the third P transistor PT3 to charge the capacitive load 14. Regardless of the status of the charging operation, if the capacitive load 14 is not to be charged, the third P transistor PT3 is turned off by inputting a true value to the charging signal terminal HiN. In other words, the second P transistor PT2, the third P transistor PT3, and the charging signal terminal HiN in the current generating unit CG are an example of the charging unit CP in this embodiment.

[0035] Next, the discharging operation of the current generator will be described.

[0036] (Discharge operation) First, when the potentials of the charging signal terminal HiN and the discharging signal terminal LoN are true, the first P transistor PT1, the second P transistor PT2, and the third P transistor PT3 are turned off. The fourth N transistor NT4 is turned on. The first N transistor NT1, the second N transistor NT2, and the third N transistor NT3 are turned on.

[0037] In this state, if the potential at the gate of the control P-type transistor PC is false, the control P-type transistor PC becomes conductive, causing a current to flow through the first N-type transistor NT1. Also, a current equivalent to the current flowing through the first N-type transistor NT1 connected to the power supply potential point VDD via the control P-type transistor PC can flow through the third N-type transistor NT3 due to the current mirror circuit.

[0038] Here, because the third P transistor PT3 is cut off, the current flowing through the second P transistor PT2 is not transmitted to the output node Nout. Furthermore, because the third N transistor NT3 and the fourth N transistor NT4 are both conductive, a current can flow from the output node Nout through the fourth N transistor NT4 and the third N transistor NT3. Then, a current flows from the capacitive load 14 connected to the output node Nout through the third N transistor NT3 and the fourth N transistor NT4, causing the capacitive load 14 to discharge.

[0039] In this way, a discharge current flows through the third N-type transistor NT3 and the fourth N-type transistor NT4 to discharge the capacitive load 14. Regardless of the state of the discharge operation, if the capacitive load 14 is not to be discharged, the fourth N-type transistor NT4 is turned off by inputting a false value to the discharge signal terminal LoN. In other words, the third N-type transistor NT3, the fourth N-type transistor NT4, and the discharge signal terminal LoN in the current generating unit CG are an example of the discharge unit DCP in this embodiment.

[0040] Next, a specific configuration of the measurement unit MP in this embodiment will be described with reference to FIG.

[0041] (Measurement part MP) 3, the measurement section MP in this embodiment includes a first potential change amount measuring unit PC1, a second potential change amount measuring unit PC2, and a potential difference output unit PD. The first potential change amount measuring unit PC1 and the second potential change amount measuring unit PC2 are connected to a measurement node Nout' as shown in FIG.

[0042] As shown in FIG. 3, the first potential change amount measuring unit PC1 includes a first switch S11, a capacitor C1, a second switch S12, a third switch S13, and a first unity gain buffer UGB1.

[0043] 3, the first switch S11 is connected to the measurement node Nout', the power supply potential point VDD, and the first node N1, and switches the node connected to the first node N1 between the measurement node Nout' and the power supply potential point VDD. Note that the first switch S11 may have any configuration, but as will be described later, it is possible to switch the node to be connected based on the value of a clock signal.

[0044] As shown in FIG. 3, the capacitor C1 is connected to a first node N1 and a second node N2.

[0045] The second switch S12 is connected to the second node N2, ground GND, and the third node N3, and switches the node connected to the second node N2 between ground GND and the third node N3. The configuration of the second switch S12 is the same as that of the first switch S11.

[0046] The third switch S13 is connected to the third node N3 and ground GND, and switches between connecting and disconnecting the third node N3 and ground GND. The third switch S13 may have any configuration, but as will be described later, it is capable of switching the node to be connected based on the value of a clock signal.

[0047] The first unity gain buffer UGB1 outputs a potential equivalent to the potential of a third node N3, which is a node connected to the input side, to a third node N3', which is a node connected to the output side. In this embodiment, the potential of the third node N3' is equivalent to the potential of the third node N3, and unless otherwise specified, the term "third node N3" refers to either or both of the third node N3 and the third node N3'.

[0048] The operations of the first switch S11, the second switch S12, and the third switch S13 are based on the value of a clock signal output by a clock signal source CLK connected to the first potential change amount measurement unit PC1. In this embodiment, the clock signal is signal data that can alternately take on two values, true and false, and one cycle of the clock signal is determined by the passage of one true value and one false value. The operations of the first switch S11, the second switch S12, and the third switch S13 in the first potential change amount measurement unit PC1 are determined as follows.

[0049] First, when the value of the clock signal is false, the first switch S11 connects the first node N1 to the measurement node Nout', the second switch S12 connects the second node N2 to ground GND, and the third switch S13 connects the third node N3 to ground GND, as shown in Figure 3. Also, when the value of the clock signal is true, the first switch S11 connects the first node N1 to the power supply potential point VDD, the second switch S12 connects the second node N2 to the third node N3, and the third switch S13 disconnects the third node N3 from ground GND.

[0050] As shown in FIG. 3, the second potential change amount measuring unit PC2 includes a first switch S21, a capacitor C2, a second switch S22, a third switch S23, and a second unity gain buffer UGB2.

[0051] 3, the first switch S21 is connected to the measurement node Nout', the power supply potential point VDD, and the fourth node N4, and switches the node connected to the fourth node N4 between the measurement node Nout' and the power supply potential point VDD. Note that the first switch S21 may have any configuration, but as will be described later, it is capable of switching the node to be connected based on the value of a clock signal.

[0052] As shown in FIG. 3, the capacitor C2 is connected to the fourth node N4 and the fifth node N5.

[0053] The second switch S22 is connected to the fifth node N5, ground GND, and a sixth node N6, and switches the node connected to the fifth node N5 between ground GND and the sixth node N6. The configuration of the second switch S22 is similar to that of the first switch S21.

[0054] The third switch S23 is connected to the sixth node N6 and ground GND, and switches between connecting and disconnecting the sixth node N6 and ground GND. The third switch S23 may have any configuration, but as will be described later, it is capable of switching the node to be connected based on the value of a clock signal.

[0055] The second unity gain buffer UGB2 outputs a potential equivalent to the potential of a sixth node N6, which is a node connected to the input side, to a sixth node N6', which is a node connected to the output side. In this embodiment, the potential of the sixth node N6 is equivalent to the potential of the sixth node N6', and unless otherwise specified, the term "sixth node N6" refers to either or both of the sixth node N6 and the sixth node N6'.

[0056] Similarly to the first potential change amount measuring unit PC1, the operations of the first switch S21, the second switch S22, and the third switch S23 are based on the value of the clock signal output by the clock signal source CLK connected to the second potential change amount measuring unit PC2. The operations of the first switch S21, the second switch S22, and the third switch S23 in the second potential change amount measuring unit PC2 are determined as follows.

[0057] First, when the value of the clock signal is false, the first switch S21 connects the fourth node N4 to the power supply potential point VDD, the second switch S22 connects the fifth node N5 to the sixth node N6, and the third switch S23 disconnects the sixth node N6 from ground GND, as shown in Figure 3. On the other hand, when the value of the clock signal is true, the first switch S21 connects the fourth node N4 to the measurement node Nout', the second switch S22 connects the fifth node N5 to ground GND, and the third switch S23 connects the sixth node N6 to ground GND.

[0058] As shown in FIG. 3, the potential difference output unit PD includes a first switch S31, a capacitor C3, and a second switch S32.

[0059] 3, the first switch S31 is connected to the third node N3, the sixth node N6, and the seventh node N7, and switches the node connected to the seventh node N7 between the third node N3 and the sixth node N6. Note that the first switch S31 may have any configuration, but as will be described later, it is capable of switching the node to be connected based on the value of a clock signal.

[0060] As shown in FIG. 3, the capacitor C3 is connected to the seventh node N7 and the eighth node N8.

[0061] The second switch S32 is connected to the eighth node N8, the power supply potential point VDD, and the ninth node N9, and switches the node connected to the eighth node N8 between the power supply potential point VDD and the ninth node N9. The configuration of the second switch S32 is similar to that of the first switch S31.

[0062] Similarly to the first potential change amount measuring unit PC1 or the second potential change amount measuring unit PC2, the operations of the first switch S31 and the second switch S32 are based on the value of the clock signal output by the clock signal source CLK connected to the potential difference output unit PD. The operations of the first switch S31 and the second switch S32 in the potential difference output unit PD are determined as follows.

[0063] First, when the value of the clock signal is false, the first switch S31 connects the seventh node N7 to the sixth node N6, and the second switch S32 connects the eighth node N8 to the ninth node N9, as shown in Figure 3. Also, when the value of the clock signal is true, the first switch S31 connects the seventh node N7 to the third node N3, and the second switch S32 connects the eighth node N8 to the power supply potential point VDD.

[0064] 3, the measurement node Nout' in this embodiment is connected to the output node Nout via a third unity gain buffer UGB3. More specifically, the output node Nout is connected to the input side of the third unity gain buffer UGB3, and outputs the potential value of the output node Nout to the measurement node Nout' connected to the output side of the third unity gain buffer UGB3. The third unity gain buffer UGB3 is an example of a measurement unity gain buffer in this embodiment.

[0065] Next, the adjustment unit AP will be described with reference to FIG.

[0066] (Adjustment part AP) As shown in FIG. 4, in this embodiment, the adjustment unit AP has a second comparator Comp2 and a flip-flop circuit FF1.

[0067] The second comparator Comp2 is connected to the ninth node N9, the second reference potential point Vref2, and the tenth node N10. The second comparator Comp2 compares the potential of the ninth node N9 with the potential of the second reference potential point Vref2 and outputs the comparison result as binary data. More specifically, the second comparator Comp2 outputs a true value when the potential of the second reference potential point Vref2 connected to the positive input terminal is higher than the potential of the ninth node N9 connected to the negative input terminal. The second comparator Comp2 outputs a false value when the potential of the ninth node N9 connected to the negative input terminal is higher than the potential of the second reference potential point Vref2 connected to the positive input terminal. The potential of the second reference potential point Vref2 is lower than the potential of the power supply potential point VDD.

[0068] The flip-flop circuit FF1 is a so-called D-type flip-flop circuit, and has a tenth node N10 connected to its input side and an eleventh node N11 connected to its output side. The flip-flop circuit FF1 is also connected to a clock signal source CLK.

[0069] More specifically, the flip-flop circuit FF1 outputs the value of the tenth node N10 at the time when the value of the clock signal becomes true to the eleventh node N11, and maintains the previous value until the value of the clock signal becomes false. Note that, because binary data is output from the second comparator Comp2 to the tenth node N10, the signal output to the eleventh node N11 is binary data.

[0070] 1 and 2, the eleventh node N11 is connected to the gate of the control P transistor PC of the current generating unit CG. That is, the potential of the eleventh node N11, which is the value output by the flip-flop circuit FF1, is an example of a control signal that controls the conduction or cut-off of the control P transistor PC.

[0071] In this embodiment, the clock signals output from the clock signal source CLK connected to the components of the measurement unit MP and the adjustment unit AP have the same value. In other words, the components of the measurement unit MP and the adjustment unit AP operate based on the same clock signal.

[0072] Next, the operation of the measurement unit MP and the adjustment unit AP in the power supply device 12 of this embodiment will be described with appropriate reference to Figures 5 to 10. Note that in the following description, the voltages of the capacitors C1, C2, and C3 will be described assuming that the electrode closer to the measurement node Nout' is positive. More specifically, the voltage of the capacitor C1 is the potential of the first node N1 minus the potential of the second node N2, the voltage of the capacitor C2 is the potential of the fourth node N4 minus the potential of the fifth node N5, and the voltage of the capacitor C3 is the potential of the seventh node N7 minus the potential of the eighth node N3.

[0073] (Operation of the measurement unit MP and adjustment unit AP) <First example of charging the capacitive load 14> 5 and 6 show time charts illustrating the potentials of the capacitors and nodes of the measurement unit MP and the adjustment unit AP in a first example illustrating the state of charging the capacitive load 14. Although not shown in FIGS. 5 and 6, it is assumed that the potentials of the capacitors and nodes of the measurement unit MP and the adjustment unit AP are equal to the potential of ground GND before time 0. In the description of this embodiment, a charging current flows through the capacitive load 14 from time 0. In the description of this embodiment, the clock signal has a false value at time 0.

[0074] (potential of each node at time 0) First, as shown in Figure 5, when the clock signal indicates time 0, in other words, during the period from time 0 to time 1, the clock signal takes a false value, and the connection state of the measurement unit MP and the adjustment unit AP is as shown below.

[0075] The first switch S11 of the first potential change measurement unit PC1 connects the first node N1 to the measurement node Nout', the second switch S12 connects the second node N2 to ground GND, and the third switch S13 connects the third node N3 to ground GND. The first switch S21 of the second potential change measurement unit PC2 connects the fourth node N4 to the power supply potential point VDD, the second switch S22 connects the fifth node N5 to a sixth node N6, and the third switch S23 disconnects the sixth node N6 from ground GND. The first switch S31 of the potential difference output unit PD connects the seventh node N7 to the sixth node N6, and the second switch S32 connects the eighth node N8 to a ninth node N9.

[0076] In this case, as shown in FIG. 5, a charging current flows through the output node Nout to charge the capacitive load 14, and the potential of the output node Nout increases over time. Furthermore, the potential of the output node Nout is also transmitted to the measurement node Nout', and the potential of the first node N1 connected to the measurement node Nout' increases over time. As shown in FIG. 5, during the period from time 0 to time 1, the capacitor C1 of the first potential change amount measuring unit PC1 connects the first node N1 to ground GND, and the voltage value of the capacitor C1 becomes equal to the voltage of the measurement node Nout'. Furthermore, since the third node N3 is connected to ground GND, the potential of the third node N3 becomes equal to the potential of ground GND.

[0077] 5, the fourth node N4 is connected to the power supply potential point VDD, and therefore the potential of the fourth node N4 is equivalent to the power supply potential point VDD. Furthermore, the fifth node N5 and the sixth node N6, which are connected to the fourth node N4 via the capacitor C2, are not connected to ground GND, and therefore have the same potential as the power supply potential point VDD. Therefore, the capacitor C2 of the second potential change amount measuring unit PC2 is not charged, and maintains the potential at time 0, as shown in FIG.

[0078] 5 and 6, the seventh node N7, eighth node N8, and ninth node N9 connected to the sixth node N6 also have the same potential as the power supply potential point VDD, so the voltage of the capacitor C3 of the potential difference output unit PD becomes zero.

[0079] Since the potential of the ninth node N9 is equal to the eighth node N8, i.e., the power supply potential, the potential of the negative input terminal of the second comparator Comp2 is higher than the potential of the second reference potential point Vref2, and therefore the second comparator Comp2 outputs a false value to the tenth node N10.

[0080] During the period from time 0 to time 1, the clock signal takes a false value, so the flip-flop circuit FF1 outputs a false value to the eleventh node N11. As a result, the control P transistor PC of the current generator CG remains conductive. In other words, the current generator CG continues to charge the capacitive load 14, as shown in FIG. 5.

[0081] (potential of each node at time 1) Also, as shown in Figure 5, when the clock signal indicates time 1, in other words, the clock signal takes on a true value during the period from time 1 to time 2, the connection state of the measurement unit MP and the adjustment unit AP is as shown below.

[0082] The first switch S11 of the first potential change measurement unit PC1 connects the first node N1 to the power supply potential point VDD, the second switch S12 connects the second node N2 to the third node N3, and the third switch S13 disconnects the third node N3 from ground GND. The first switch S21 of the second potential change measurement unit PC2 connects the fourth node N4 to the measurement node Nout′, the second switch S22 connects the fifth node N5 to ground GND, and the third switch S23 connects the sixth node N6 to ground GND. The first switch S31 of the potential difference output unit PD connects the seventh node N7 to the third node N3, and the second switch S32 connects the eighth node N8 to the power supply potential point VDD.

[0083] In this case, as shown in FIG. 5, a charging current flows through the output node Nout to charge the capacitive load 14, and the potential of the output node Nout increases over time. Furthermore, the potential of the output node Nout is also transmitted to the measurement node Nout', and the potential of the fourth node N4 connected to the measurement node Nout' increases over time. As shown in FIG. 5, during the period from time 1 to time 2, the capacitor C2 of the second potential change measurement unit PC2 is connected to the fourth node N4 and ground GND, and the voltage of the capacitor C2 becomes equal to the value of the measurement node Nout'. Furthermore, since the sixth node N6 is connected to ground GND, the potential of the sixth node N6 becomes equal to the potential of ground GND.

[0084] 5, the first node N1 is connected to the power supply potential point VDD, so the potential of the first node N1 is equivalent to the power supply potential point VDD. Furthermore, the second node N2 and the third node N3, which are connected to the first node N1 via the capacitor C1, are not connected to ground GND, so they are at the same potential as the power supply potential point VDD. Therefore, the capacitor C1 of the first potential change amount measuring unit PC1 is not charged, as shown in FIG. 5, and maintains the potential at time 1.

[0085] 5 and 6, the eighth node N8 is connected to the power supply potential point VDD, and the seventh node N7 is connected to the third node N3. In other words, of the nodes connected to the capacitor C3 of the potential difference output unit PD, the eighth node N8 has a higher potential than the seventh node N7. Therefore, as shown in FIG. 6, the voltage of the capacitor C3 of the potential difference output unit PD corresponds to the voltage of the capacitor C1 of the first potential change amount measuring unit PC1 at time 0 minus the voltage of the capacitor C2 of the second potential change amount measuring unit PC2 at time 1. In other words, as shown in FIG. 6, the voltage of the capacitor C3 of the potential difference output unit PD at time 1 is a negative value.

[0086] At time 1, the second switch S32 of the potential difference output unit PD disconnects the ninth node N9 from the eighth node N8, and the potential of the ninth node N9 becomes undefined. In other words, since no signal is input to the negative input terminal of the second comparator Comp2, the second comparator Comp2 outputs a false value to the tenth node N10.

[0087] During the period from time 1 to time 2, the clock signal assumes a true value, so the flip-flop circuit FF1 outputs a false value to the eleventh node N11. As a result, the control P-transistor PC of the current generator CG remains conductive. In other words, the current generator CG continues to charge the capacitive load 14, as shown in FIG. 5.

[0088] (potential of each node at time 2) Also, as shown in Figure 5, when the clock signal indicates time 2, in other words, during the period from time 2 to time 3, the clock signal takes a false value, so the connection state of the measurement unit MP and the adjustment unit AP is the same as at time 0.

[0089] 5, since the fourth node N4 is connected to the power supply potential point VDD, the potential of the fourth node N4 is equivalent to the power supply potential point VDD. Furthermore, since the fifth node N5 and the sixth node N6 connected to the fourth node N4 via the capacitor C2 are not connected to ground GND, the potentials of these nodes are lower by an amount equal to the power supply potential minus the voltage of the capacitor C2 of the second potential change amount measuring unit PC2.

[0090] Furthermore, as shown in FIGS. 5 and 6, the potential of the seventh node N7 is connected to the sixth node N6, and therefore is equal to the potential of the sixth node N6.

[0091] Meanwhile, at time 2, the potential of the eighth node N8 becomes equal to the power supply potential plus the voltage value of the capacitor C3 of the potential difference output unit PD. In other words, the potential of the eighth node N8 at time 2 becomes a value subtracted from the power supply potential. Then, the potential of the ninth node N9 also becomes equal to that of the eighth node N8, and the value of the negative input terminal of the second comparator Comp2 decreases. Here, as shown in FIG. 6, if the potential of the eighth node N8 at time 2 becomes lower than the potential of the second reference potential point Vref2, the second comparator Comp2 outputs a true value to the tenth node N10.

[0092] Then, at time 2, a true value is input from the tenth node N10, so that the flip-flop circuit FF1 outputs the true value, which is the output signal of the tenth node N10, to the eleventh node N11. As a result, the control P transistor PC of the current generating unit CG is turned off, and the current generating unit CG stops charging the capacitive load 14, as shown in FIG.

[0093] In this case, as shown in Figure 5, the potential of the output node Nout does not change, and the potential of the first node N1 connected to the measurement node Nout' maintains the value at time 2. Also, as shown in Figure 5, during the period from time 2 to time 3, the voltage value of the capacitor C1 of the first potential change amount measuring unit PC1 becomes equal to the value of the measurement node Nout'. Note that the capacitor C2 of the second potential change amount measuring unit PC2 also maintains the potential at time 2, as shown in Figure 5.

[0094] (potential of each node at time 3) Also, as shown in Figure 5, when the clock signal indicates time 3, in other words, during the period from time 3 to time 4, the clock signal takes on a true value, so the connection state of the measurement unit MP and the adjustment unit AP is the same as at time 1.

[0095] 5, the first node N1 is connected to the power supply potential point VDD, so the potential of the first node N1 is equivalent to the power supply potential point VDD. In addition, the potentials of the second node N2 and the third node N3, which are connected to the first node N1 via the capacitor C1, are lower by an amount equal to the power supply potential minus the voltage of the capacitor C1, because they are not connected to ground GND.

[0096] 5 and 6, the potential of the seventh-node N7 is connected to the third-node N3, and therefore becomes equal to the potential of the third-node N3. That is, the potential of the seventh-node N7 does not change during the period from time 3 to time 4.

[0097] Meanwhile, at time 3, the eighth node N8 is connected to the power supply potential point VDD, so the potential of the eighth node N8 becomes the power supply potential. At time 3, the second switch S32 of the potential difference output unit PD disconnects the ninth node N9 from the eighth node N8, so the potential of the ninth node N9 becomes undefined. In other words, no signal is input to the negative input terminal of the second comparator Comp2, so the second comparator Comp2 outputs a false value to the tenth node N10.

[0098] However, at time 3, the clock signal takes on a true value, so that the flip-flop circuit FF1 maintains the true value, which is the output signal of the tenth node N10 immediately before time 3, as the signal to be output to the eleventh node N11. As a result, the control P transistor PC of the current generating unit CG is turned off, and the current generating unit CG continues to stop charging the capacitive load 14, as shown in FIG.

[0099] In this case, as shown in Figure 5, the potential of the output node Nout does not change, so the potential of the fourth node N4 connected to the measurement node Nout' maintains the value at time 3. Also, as shown in Figure 5, during the period from time 3 to time 4, the voltage of the capacitor C2 becomes equal to the value of the measurement node Nout'. Note that the capacitor C1 also maintains the potential at time 3, as shown in Figure 5.

[0100] (potential of each node after time 4) Also, as shown in Figure 5, when the clock signal indicates time 4, in other words, during the period from time 4 to time 5, the clock signal takes a false value, and the connection state of the measurement unit MP and the adjustment unit AP becomes equivalent to time 0.

[0101] 6, the value of the eleventh node N11 becomes false, so the control P transistor PC becomes conductive and a charging current flows from the current generating unit CG to the capacitive load 14. Therefore, as shown in FIG. 5, the potential of the output node Nout increases again during the period from time 4 to time 5.

[0102] 5, the potentials of the fifth node N5 and the sixth node N6 are lowered by an amount equal to the power supply potential minus the voltage of the capacitor C2, as in the state at time 2. Furthermore, as shown in FIGS. 5 and 6, since the seventh node N7 is connected to the sixth node N6, the potential of the seventh node N7 becomes equal to the potential of the sixth node N6.

[0103] Also, at time 4, the potential of the eighth node N8 becomes the power supply potential plus a voltage value corresponding to the voltage of capacitor C3, as at time 2. However, as shown in Figure 5, at time 4, the voltage of capacitor C3 becomes 0, and therefore the potential of the eighth node N8 becomes equivalent to the power supply potential. In other words, at time 4, the potential of the eighth node N8 becomes equivalent to that at time 0, and therefore the potentials of the ninth node N9, tenth node N10, and eleventh node N11 also become equivalent to that at time 0.

[0104] Also, as shown in Figure 5, when the clock signal indicates time 5, in other words, from time 5 to time 6, the clock signal takes a false value, so the connection state of the measurement unit MP and the adjustment unit AP is equivalent to time 1.

[0105] 5, the potentials of the second node N2 and the third node N3 are lowered by an amount equal to the power supply potential minus the voltage of the capacitor C2, as in the state at time 3. Furthermore, as shown in FIGS. 5 and 6, since the seventh node N7 is connected to the third node N3, the potential of the seventh node N7 becomes equal to the potential of the third node N3.

[0106] Furthermore, at time 5, the potential of the eighth node N8 becomes equal to the power supply potential plus a voltage value corresponding to the voltage of the capacitor C3, as at time 3. In other words, at time 5, the potential of the eighth node N8 becomes equal to that at time 1, and therefore the potentials of the ninth node N9, the tenth node N10, and the eleventh node N11 also become equal to that at time 1.

[0107] 5 and 6, capacitors C1 and C2 output the difference between the voltages charged in capacitor C2 to capacitor C3 every time 2 elapses. More specifically, after time 2, capacitor C1 outputs the difference between the voltage of capacitor C2 and the voltage of capacitor C1 to capacitor C3 every time 2 elapses. Capacitor C3 then outputs the difference in the voltages of the capacitors to second comparator Comp2 of measurement unit MP.

[0108] The difference between the voltage of capacitor C2 and the voltage of capacitor C1 corresponds to the potential of measurement node Nout' at the time when capacitor C2 is charged and the potential of measurement node Nout' at the time when capacitor C1 is charged. In other words, the difference between the voltage of capacitor C2 and the voltage of capacitor C1 corresponds to the amount of change in the potential of output node Nout in one cycle of the clock signal. In other words, the measurement unit MP in this embodiment outputs the amount of change in the potential of output node Nout to the adjustment unit AP for each cycle of the clock signal. In this embodiment, one cycle of the clock signal is an example of a unit time.

[0109] Therefore, in the first example showing how the capacitive load 14 is charged, after time 4, the state of the eighth node N8 becomes the same every two cycles of the clock signal, and the value output to the eleventh node N11 is also repeated every two cycles.

[0110] In this way, in this example, the charging current that charges the capacitive load 14 is controlled based on the signal output to the eleventh node N11. As a result, in this example, the increase in potential at the output node Nout in Fig. 5 changes from the increase indicated by the dashed dotted line to the increase indicated by the solid line.

[0111] Next, a second example showing how the capacitive load 14 is charged in this embodiment will be described with reference to FIGS.

[0112] <Second example of charging the capacitive load 14> 7 and 8 show time charts illustrating the potentials of the capacitors and nodes in the measurement unit MP and the adjustment unit AP in a second example illustrating the charging of the capacitive load 14. Although not shown in FIGS. 7 and 8, it is assumed that the potentials of the capacitors and nodes in the measurement unit MP and the adjustment unit AP are equal to the potential of ground GND before time 0. In the description of this embodiment, a charging current flows through the capacitive load 14 from time 0. In the description of this embodiment, the clock signal has a false value at time 0.

[0113] The only difference between the first example and this example in charging the capacitive load 14 is the rate of increase in potential per unit time at the output node Nout, as shown in Fig. 7. More specifically, the rate of increase in potential per unit time at the output node Nout in this example is smaller than that in the first example. In other words, the rate of increase in potential per unit time at the output node Nout in this example is slower than that in the first example.

[0114] The operation timing and operation state of each of the other switches are the same as those in the first example.

[0115] (Electric potential of each node at time 0 and time 1) 7 and 8, the potential of each node from time 0 to time 1 changes in the same way as in Example 1. However, in this example, the rate of change of the potential at the output node Nout is smaller than in Example 1, so the voltage of the capacitor C3 of the potential difference output unit PD at time 1 is smaller than in Example 1.

[0116] (potential of each node at time 2) For this reason, in this example, the potential of the eighth node N8 is unlikely to decrease at time 2, as shown in Fig. 8. Then, as shown in Fig. 8, when the potential of the eighth node N8 at time 2 is higher than the potential of the second reference potential point Vref2, the second comparator Comp2 outputs a false value to the tenth node N10.

[0117] Therefore, in this example, the flip-flop circuit FF1 outputs a false value to the eleventh node N11 at time 2. As a result, the control P transistor PC of the current generator CG is in a conducting state, and the current generator CG continues to charge the capacitive load 14, as shown in FIG.

[0118] (potential of each node after time 3) In this example, the potential of each node also changes at time 3 in the same way as at time 1. That is, in this example, the difference between the voltage of capacitor C2 and the voltage of capacitor C1 corresponds to the amount of potential of output node Nout in one cycle of the clock signal. In other words, in this example, the measurement unit MP of this embodiment also outputs the amount of change in the potential of output node Nout to the adjustment unit AP for each cycle of the clock signal.

[0119] In addition, as in this example, the continuous output of a charging current that charges the capacitive load 14 from the current generating unit CG is also included in an example of being controlled based on the signal output to the eleventh node N11 in this embodiment.

[0120] Next, a third example showing how the capacitive load 14 is charged in this embodiment will be described with reference to FIGS.

[0121] <Third example of charging the capacitive load 14> 9 and 10 show time charts illustrating the potentials of the capacitors and nodes in the measurement unit MP and the adjustment unit AP in a third example illustrating the charging of the capacitive load 14. Although not shown in FIGS. 9 and 10, it is assumed that the potentials of the capacitors and nodes in the measurement unit MP and the adjustment unit AP are equal to the potential of ground GND before time 0. In addition, in the description of this embodiment, a charging current flows through the capacitive load 14 from time 0. In addition, in the description of this embodiment, at time 0, the clock signal has a false value.

[0122] The only difference between the first example of charging the capacitive load 14 and this example is the period of the clock signal, as shown in Fig. 9. More specifically, the period of the clock signal at the output node Nout in this example is shorter than that in the first example. In other words, the unit time at the output node Nout in this example is shorter than that in the first example.

[0123] The operation timing and operation state of each of the other switches are the same as those in the first example.

[0124] (Electric potential of each node at time 0 and time 1) 9 and 10, the potential of each node from time 0 to time 1 changes in the same way as in the first example. However, in this example, the period of the clock signal is smaller than in the first example, so the voltage of capacitor C3 at time 1 is smaller than in the first example.

[0125] (potential of each node at time 2) For this reason, in this example, as shown in Fig. 10, the potential of the eighth node N8 at time 2 is unlikely to decrease. Then, as shown in Fig. 10, when the potential of the eighth node N8 at time 2 is higher than the potential of the second reference potential point Vref2, the second comparator Comp2 outputs a false value to the tenth node N10.

[0126] Therefore, in this example, the flip-flop circuit FF1 outputs a false value to the eleventh node N11 at time 2. As a result, the control P transistor PC of the current generating unit CG is in a conducting state, and the current generating unit CG continues to charge the capacitive load 14, as shown in FIG.

[0127] (potential of each node after time 3) In this example, the potential of each node also changes at time 3 in the same way as at time 1. That is, in this example, the difference between the voltage of capacitor C2 and the voltage of capacitor C1 corresponds to the amount of potential of output node Nout in one cycle of the clock signal. In other words, in this example, the measurement unit MP of this embodiment also outputs the amount of change in the potential of output node Nout to the adjustment unit AP for each cycle of the clock signal.

[0128] In addition, as in this example, the continuous output of a charging current that charges the capacitive load 14 from the current generating unit CG is also included in an example of being controlled based on the signal output to the eleventh node N11 in this embodiment.

[0129] In the power supply device 12 according to this embodiment, the drive circuit 10 that drives the capacitive load 14 includes a current generator CG, a measurement unit MP, and an adjustment unit AP, but a configuration that does not include the measurement unit MP or the adjustment unit AP and includes only the current generator CG is also capable of driving the capacitive load 14. However, in a configuration that does not include the measurement unit MP or the adjustment unit AP and includes only the current generator CG, the voltage at the output node Nout may become unstable if the capacitance of the capacitive load 14 is significantly larger or smaller than the charging current or discharging current.

[0130] In the power supply device 12 according to this embodiment, based on the output result of the measurement unit MP, the adjustment unit AP transmits to the current generation unit CG a control signal that controls the amount of change in the potential of the output node Nout between the current generation unit CG and the capacitive load 14. Therefore, according to the power supply device 12 of this embodiment, the voltage of the output node Nout between the current generation unit CG and the capacitive load 14 is stabilized when at least one of charging and discharging the capacitive load 14 is performed, regardless of the capacitance of the capacitive load 14.

[0131] Furthermore, in the power supply device 12 of this embodiment, the control P transistor PC of the current generating unit CG switches in response to a control signal to control the constant current supplied to the current mirror circuit. Therefore, with the power supply device 12 of this embodiment, the configuration of the current generating unit CG can be simplified compared to when the amount of current to be supplied to the capacitive load 14 is set based on a multi-level signal or an analog signal.

[0132] Furthermore, power supply device 12 of this embodiment outputs the amount of change per unit time at the output terminal of current generating unit CG as a potential difference to adjustment unit AP. Therefore, power supply device 12 of this embodiment makes it easier to improve the time resolution compared to when the amount of change per unit time in voltage is output as a binary waveform value.

[0133] In addition, in the power supply device 12 of this embodiment, the first voltage change amount measuring unit synchronizes with the clock signal to hold the amount of change in the potential of the output node Nout of the current generating unit CG relative to a reference potential as a potential, and the second voltage change amount measuring unit holds the amount of change in the potential of the output node Nout of the current generating unit CG relative to the reference potential as a potential at a time when the clock signal differs from that of the first voltage change amount measuring unit by a half cycle.The potential difference output unit PD synchronizes with the clock signal to output the difference between the potential held by the first potential change amount measuring unit PC1 and the potential held by the second potential change amount measuring unit PC2 as a result of measuring the amount of change.As a result, the power supply device 12 of this embodiment can feed back the amount of change in the potential of the output node Nout of the current generating unit CG for each cycle of the clock signal.

[0134] Furthermore, in power supply device 12 of this embodiment, the first voltage change amount measuring unit is connected to the potential difference output unit PD via a first unity gain buffer UGB1, and the second voltage change amount measuring unit is connected to the potential difference output unit PD via a second unity gain buffer UGB2. Therefore, according to power supply device 12 of this embodiment, compared to a case where the first unity gain buffer UGB1 and the second unity gain buffer UGB2 are not provided, the first voltage change amount measuring unit and the second voltage change amount measuring unit can each maintain the potential of the output node Nout relative to the reference potential without relying on the operation of the potential difference output unit PD.

[0135] For example, the power supply device 12 according to this embodiment includes the first unity gain buffer UGB1, and therefore can separate the influence of other elements at the boundary between the third node N3 and the third node N3'. More specifically, compared to a configuration that does not include the first unity gain buffer UGB1, the influence of a change in the potential at the seventh node N7 can be prevented from spreading to the third node N3. Therefore, the configuration that includes the first unity gain buffer UGB1 simplifies the design of the measurement unit MP. The same applies to the second unity gain buffer UGB2.

[0136] Furthermore, in power supply device 12 of this embodiment, measurement unit MP measures the potential of output node Nout via third unity gain buffer UGB3. Therefore, power supply device 12 of this embodiment can measure the amount of change per unit time in the potential of output node Nout of current generating unit CG regardless of the specifications of capacitive load 14 connected to current generating unit CG, compared to when the amount of change in potential is measured without going through third unity gain buffer UGB3.

[0137] Furthermore, the power supply device 12 of this embodiment has a charging unit CP that causes a charging current to flow through the capacitive load 14 and a discharging unit DCP that causes a discharging current to flow through the capacitive load 14. Therefore, the power supply device 12 of this embodiment can stabilize the voltage of the capacitive load 14 when charging and discharging, regardless of the capacitance of the capacitive load 14.

[0138] Furthermore, according to the power supply device 12 of this embodiment, the charging current output to the output node Nout can be controlled by arbitrarily setting the potential of the second reference potential point Vref2. Furthermore, according to the power supply device 12 of this embodiment, the charging current output to the output node Nout can be arbitrarily controlled by changing the cycle of the clock signal used in the measurement unit MP and the adjustment unit AP.

[0139] (First Modification) Next, a first modified example of the power supply device 12 of this embodiment will be described with reference to FIG.

[0140] FIG. 11 is a diagram showing a modified example of the measurement unit MP as a first modified example of this embodiment. As shown in FIG. 11, in the measurement unit MP according to this modified example, the potential difference output unit PD further includes a third switch S33. In this modified example, although not shown, the node connected to the input terminal of the second comparator Comp2 is reversed from that in the embodiment. More specifically, in this modified example, the ninth node N9 is connected to the positive input terminal of the second comparator Comp2, and the second reference potential point Vref2 is connected to the negative input terminal.

[0141] The third switch S33 switches the node connected to the second switch S32 between the power supply potential point VDD or the ground GND, as shown in Fig. 11. The third switch S33 may have any configuration.

[0142] In this modification, the state in which the third switch S33 sets the node connected to the second switch S32 to the power supply potential point VDD is the same as the state shown in Fig. 3. On the other hand, in the state in which the third switch S33 sets the node connected to the second switch S32 to the ground GND, the capacitor C3 is connected to the ground GND via the eighth node N8 by the operation of the second switch S32.

[0143] In the power supply device 12 according to this modification, the third switch S33 sets the node connected to the second switch S32 to the ground GND, so that the discharge current can be controlled in the same way as in the power supply device 12 according to the embodiment, even when discharging the charged capacitive load 14. More specifically, when the potential of the output node Nout is measured in discharging the capacitive load 14, the potentials of the nodes shown in Fig. 5 are inverted, and therefore the potential of the seventh node N7 and the potential of the capacitor C3 shown in Fig. 6 are also inverted.

[0144] 6. More specifically, in the present modification, when the potential of the eighth node N8 becomes lower than the potential of the second reference potential point Vref2 in the embodiment, the potential of the eighth node N8 becomes higher than the potential of the second reference potential point Vref2, and when the potential of the eighth node N8 becomes higher than the potential of the second reference potential point Vref2 in the embodiment, the potential of the eighth node N8 becomes lower than the potential of the second reference potential point Vref2 in the present modification. In other words, in the present modification, similar to the first embodiment, when the amount of change in potential per unit time at the output node Nout is large, the potential of the eighth node N8 becomes higher than the potential of the second reference potential point Vref2.

[0145] In this modification, the ninth node N9 is connected to the positive input terminal of the second comparator Comp2, and the second reference potential point Vref2 is connected to the negative input terminal thereof, so that when the amount of change in potential per unit time at the output node Nout is large, a positive value is output to the tenth node N10, as in the embodiment. Therefore, in this modification, the discharge current when discharging the charged capacitive load 14 can be controlled in the same way as in the embodiment.

[0146] (Second Modification) Next, a second modified example of the power supply device 12 of this embodiment will be described with reference to FIG.

[0147] 12 is a diagram showing a modified example of the adjustment unit AP as a second modified example of the present embodiment. As shown in Fig. 12, the adjustment unit AP according to the modified example further includes a first voltage dividing resistor RD1, a second voltage dividing resistor RD2, and an operational amplifier OP.

[0148] As shown in FIG. 12, the operational amplifier OP is inserted between the ninth node N9 and the second comparator Comp2 with respect to the adjustment unit AP in this embodiment. Here, the upstream side (the eighth node N8 side) of the operational amplifier OP is simply referred to as the ninth node N9, and the downstream side (the second comparator Comp2 side) of the operational amplifier OP is referred to as the ninth node N9'. The operational amplifier OP amplifies the potential of the ninth node N9 connected to its input terminal and transmits the amplified potential to the ninth node N9'. The gain of the operational amplifier OP can be set arbitrarily.

[0149] 12, the first voltage dividing resistor RD1 and the second voltage dividing resistor RD2 are connected in series between the output node of the operational amplifier OP and ground GND. That is, at a ninth node N9′ connected between the first voltage dividing resistor RD1 and the second voltage dividing resistor RD2, the potential of the output node of the operational amplifier OP with respect to ground GND is divided.

[0150] According to this modification, the value of the ninth node N9' at which the second comparator Comp2 outputs false can be set by arbitrarily setting the amplification factor of the operational amplifier OP or the ratio of the resistance values ​​of the first voltage dividing resistor RD1 and the second voltage dividing resistor RD2. In other words, according to this modification, the potential of the ninth node N9' at which the adjustment unit AP outputs a control signal to the eleventh node N11 can be arbitrarily set.

[0151] (Other variations) In the above description, the current generating unit CG has a current mirror circuit and a control P transistor PC that supplies a constant current to the current mirror circuit, but the power supply device 12 according to this embodiment is not limited to this. In the power supply device 12 according to this embodiment, the configuration of the current generating unit CG is not particularly limited as long as it is possible to control power based on the control signal output by the adjustment unit AP to the eleventh node N11.

[0152] In the above description, the measuring unit MP outputs the amount of change per unit time in the potential at the output node Nout to the adjusting unit AP as a potential difference to the ninth node N9, but the power supply device 12 according to this embodiment is not limited to this. For example, another element may be provided at the ninth node N9, and the amount of change in potential may be output as binary data, or as an amount of change in current.

[0153] In the above description, the measurement section MP has two change amount measurement units, the first potential change amount measurement unit PC1 and the second potential change amount measurement unit PC2, but the power supply device 12 according to this embodiment is not limited to this. For example, it is sufficient that there are multiple change amount measurement units, and three or more potential change amount measurement units may be provided.

[0154] Furthermore, in the above description, the measurement unit MP has the first unity gain buffer UGB1, the second unity gain buffer UGB2, and the third unity gain buffer UGB3, but the power supply device 12 according to this embodiment is not limited to this. By appropriately setting the specifications of each element included in the current generation unit CG, the measurement unit MP, and the adjustment unit AP, the power supply device 12 may be configured without the first unity gain buffer UGB1, the second unity gain buffer UGB2, and the third unity gain buffer UGB3.

[0155] Furthermore, in the above description, the current generating unit CG has a charging unit CP and a discharging unit DCP, but the power supply device 12 according to this embodiment is not limited to this. For example, the current generating unit CG may have only a charging unit CP and no function of discharging the capacitive load 14, or may have only a discharging unit DCP and no function of charging the capacitive load 14.

[0156] These modifications also provide the same functions and effects as the power supply device 12 according to this embodiment.

[0157] The above describes an embodiment of the present disclosure with reference to the accompanying drawings. However, it is clear that a person with ordinary knowledge in the field of technology to which the present disclosure pertains can conceive of various modifications or applications within the scope of the technical ideas set forth in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0158] Further preferred aspects of the present disclosure will be described below.

[0159] (Appendix 1) a current generating unit that generates a charge / discharge current that charges / discharges the capacitive load; a measurement unit that outputs a result of measuring a change in potential per unit time at a connection terminal between the current generation unit and a capacitive load; an adjusting unit that transmits a control signal to the current generating unit to control a charge / discharge current based on an output result of the measuring unit; A power supply device comprising:

[0160] (Appendix 2) the current generating unit includes a current mirror circuit and a switch element that supplies a constant current to the current mirror circuit; The switch element switches in response to the control signal. 10. The power supply device of claim 1.

[0161] (Appendix 3) The measurement unit outputs the amount of change per unit time to the adjustment unit as a potential difference. 10. The power supply device of claim 1 or 2.

[0162] (Appendix 4) the measurement unit includes a first potential change amount measurement unit, a second potential change amount measurement unit, and a potential difference output unit; the first potential change amount measuring unit holds the potential of the connection terminal with respect to a reference potential for each half cycle of a clock signal; the second potential change amount measuring unit holds the potential of the connection terminal with respect to a reference potential for each half cycle of a clock signal at a different time from that of the first potential change amount measuring unit; the potential difference output unit outputs a difference between the potential held by the first potential change amount measuring unit and the potential held by the second potential change amount measuring unit as a result of measuring the amount of change; 1. A power supply device as described in Appendix 3.

[0163] (Appendix 5) the first potential change amount measuring unit further includes a first unity gain buffer, and is connected to the potential difference output unit via the first unity gain buffer; the second potential change amount measuring unit further includes a second unity gain buffer, and is connected to the potential difference output unit via the second unity gain buffer; 10. The power supply device of claim 4.

[0164] (Appendix 6) the measurement unit further includes a measurement unity gain buffer, and measures the potential of the connection terminal via the measurement unity gain buffer. 6. The power supply device of any one of claims 1 to 5.

[0165] (Appendix 7) The current generating unit has a charging unit that causes a charging current to flow through the capacitive load and a discharging unit that causes a discharging current to flow through the capacitive load. 7. The power supply device of any one of claims 1 to 6. [Explanation of symbols]

[0166] 10. Drive circuit 12 Power supply 14 Capacitive load AP adjustment section CG current generator CP live part DCP discharge section FF1 flip-flop circuit GND Ground (an example of reference potential) HiN charging signal terminal LoN discharge signal terminal MP measurement section Nout Output node (an example of a connection terminal) PC: Control P transistor (an example of a switch element) PC1 First potential change measurement unit PC2 Second potential change measurement unit PD Potential Difference Output Unit UGB1 First unity gain buffer UGB2 Second unity gain buffer UGB3 Third unity gain buffer (example of a unity gain buffer for measurement) VDD power supply potential point Vref1 First reference potential point Vref2 Second reference potential point

Claims

1. a current generating unit that generates a charge / discharge current that charges / discharges the capacitive load; a measurement unit that outputs a result of measuring a change in potential per unit time at a connection terminal between the current generation unit and a capacitive load; an adjusting unit that transmits a control signal to the current generating unit to control a charge / discharge current based on an output result of the measuring unit; A power supply device comprising:

2. the current generating unit includes a current mirror circuit and a switch element that supplies a constant current to the current mirror circuit; The switch element switches in response to the control signal. The power supply device according to claim 1 .

3. The measurement unit outputs the amount of change per unit time to the adjustment unit as a potential difference. The power supply device according to claim 1 .

4. the measurement unit includes a first potential change amount measurement unit, a second potential change amount measurement unit, and a potential difference output unit; the first potential change amount measuring unit holds the potential of the connection terminal with respect to a reference potential for each half cycle of a clock signal; the second potential change amount measuring unit holds the potential of the connection terminal with respect to a reference potential for each half cycle of a clock signal at a different time from that of the first potential change amount measuring unit; the potential difference output unit outputs a difference between the potential held by the first potential change amount measuring unit and the potential held by the second potential change amount measuring unit as a result of measuring the amount of change; The power supply device according to claim 3 .

5. the first potential change amount measuring unit further includes a first unity gain buffer, and is connected to the potential difference output unit via the first unity gain buffer; the second potential change amount measuring unit further includes a second unity gain buffer, and is connected to the potential difference output unit via the second unity gain buffer; The power supply device according to claim 4 .

6. the measurement unit further includes a measurement unity gain buffer, and measures the potential of the connection terminal via the measurement unity gain buffer. The power supply device according to claim 1 .

7. The current generating unit has a charging unit that causes a charging current to flow through the capacitive load and a discharging unit that causes a discharging current to flow through the capacitive load. The power supply device according to any one of claims 1 to 6.

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