Image sensor and method of manufacturing image sensor

Abstract

To enable an image sensor to suppress an afterimage and injection while suppressing a feedthrough lowering the potential of floating diffusion.SOLUTION: A multi-layer wiring layer ML is laminated on a wafer wf. Wiring formed on the multi-layer wiring layer ML includes capacity control wiring FDC and FD-SF wiring. The capacity control wiring FDC is capacitively coupled to floating diffusion FD, and transmits a boost signal raising the potential of the floating diffusion FD. The FD-SF wiring connects the floating diffusion FD and a source follower transistor SF. The multi-layer wiring layer ML comprises an FD connection layer M1 and a first control line layer M2. The FD-SF wiring is formed in the FD connection layer M1. The capacity control wiring FDC is formed in the first control line layer M2. In the multi-layer wiring layer ML, the first control line layer M2 is the wiring layer closest to the FD connection layer M1.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] This specification discloses an image sensor and a method for manufacturing the same. [Background technology]

[0002] For example, Patent Document 1 discloses a photoelectric conversion device. Charges accumulated in a photoelectric conversion section (photodiode) are transferred to a floating diffusion section (floating diffusion) by a transfer transistor. The photoelectric conversion device includes a wiring layer. This wiring layer is provided with transfer control lines, connection lines, and shield lines. A drive signal to the transfer transistor is transmitted to the transfer control lines. The connection lines connect the floating diffusion section and the gate of the amplification transistor. Furthermore, shield lines are provided between the connection lines and the transfer control lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2023 / 0179883 Summary of the Invention [Problem to be solved by the invention]

[0004] The charge accumulated in the photodiode is transferred to the floating diffusion. The conversion efficiency is used as a value indicating the charge detection efficiency. Conversion efficiency refers to the signal voltage [μV] or digital value (DN) obtained per signal electron. If a large signal voltage or digital value can be obtained with a small number of electrons, the conversion efficiency is high. For this reason, the smaller the capacity of the floating diffusion, the higher the conversion efficiency.

[0005] The floating diffusion can be likened to a well that stores electric charge. To increase the conversion efficiency of the floating diffusion, it is necessary to reduce the capacitance and increase the potential. If the potential is small, it becomes more likely to cause "lag," where electric charge remains in the photodiode, or "injection," where electric charge is injected from the floating diffusion into the photodiode.

[0006] In addition, when a pulse signal is applied to a terminal within the image sensor, a "feedthrough" occurs, which fluctuates the potential of another terminal through parasitic capacitance. If the feedthrough lowers the potential of the floating diffusion (making the well shallower), image retention and injection become more likely to occur.

[0007] Therefore, this specification discloses an image sensor and a method for manufacturing the image sensor that can suppress afterimages and injection while suppressing feedthrough that lowers the potential of the floating diffusion. [Means for solving the problem]

[0008] The image sensor disclosed in this specification includes at least one wafer and a multilayer wiring layer. A photodiode, a floating diffusion FD, and a source follower transistor SF are formed on the wafer. The photodiode photoelectrically converts incident light. The floating diffusion temporarily holds the charge accumulated in the photodiode. The source follower transistor has a gate connected to the floating diffusion. A multilayer wiring layer is stacked on the wafer. Wiring formed in the multilayer wiring layer includes a capacitance control wiring and an FD-SF wiring. The capacitance control wiring is capacitively coupled to the floating diffusion and transmits a boost signal that increases the potential of the floating diffusion. The FD-SF wiring connects the floating diffusion and the source follower transistor. The multilayer wiring layer includes an FD connection layer and a first control line layer. The FD-SF wiring is formed in the FD connection layer. The capacitance control wiring is formed in the first control line layer. In the multilayer wiring layer, the first control line layer is the wiring layer closest to the FD connection layer.

[0009] According to the above configuration, the FD-SF wiring and the capacitance control wiring are arranged close to each other. Therefore, a large amount of wiring capacitance occurs between the FD-SF wiring and the capacitance control wiring. When a boost signal is transmitted to the capacitance control wiring to transfer the charge stored in the photodiode to the floating diffusion, the potential of the floating diffusion is sufficiently raised (the well becomes deeper). Furthermore, by locating the first control line layer closest to the FD connection layer, wiring layers that lower the potential of the floating diffusion are separated from the FD connection layer. In other words, the wiring pitch is widened, which reduces the wiring capacitance accordingly.

[0010] In the above configuration, a transfer transistor may be formed. The transfer transistor transfers the charge photoelectrically converted by the photodiode to the floating diffusion. Here, a transfer wiring is formed in the first control line layer. A transfer signal to the transfer transistor is transmitted to the transfer wiring.

[0011] 2, the potential of the floating diffusion is raised by the feed-through when the transfer signal is transmitted (TX: Lo → Hi), as shown at time t4 in Fig. 2 (described later). By forming the transfer wiring in the first control line layer, the potential of the floating diffusion is raised sufficiently by the feed-through.

[0012] In the above configuration, the image sensor may be formed with a reset transistor. The reset transistor resets the potential of the floating diffusion to a reference potential. The wiring formed in the multilayer wiring layer includes a reset wiring. The reset wiring transmits a reset signal to the reset transistor. The multilayer wiring layer further includes a second control line layer in which the reset wiring is formed.

[0013] As shown at time t2 in Figure 2 (described later), when the reset signal is switched (RST: Hi → Lo), the potential of the floating diffusion is lowered by feedthrough (the well becomes shallower). By separating the reset wiring from the first control layer, the effect of feedthrough due to the reset signal can be suppressed.

[0014] In the above configuration, a row selection transistor may be formed in the image sensor. The row selection transistor is connected to the source of the source follower transistor. In this case, a row selection wiring is formed in the second control line layer to send a row selection signal to the row selection transistor.

[0015] As illustrated at time t11 in Figure 6 (described later), when a row selection signal is transmitted (RS: Lo → Hi), the potential of the floating diffusion is lowered (the well becomes shallower) by feedthrough. By separating the row selection wiring from the first control layer, the influence of feedthrough by the row selection signal can be suppressed.

[0016] In the above configuration, the FD-SF wiring may intersect with the transfer wiring and the capacitance control wiring in a circuit plan view.

[0017] According to the above configuration, the distance between the FD-SF wiring and the transfer wiring, and the distance between the FD-SF wiring and the capacitance control wiring are both close to each other, so that a relatively large wiring capacitance is formed.

[0018] In the above configuration, the FD connection layer may be formed in the first layer of the multi-layer wiring layer, and in this case, the first control line layer is formed in the second layer of the multi-layer wiring layer.

[0019] According to the above configuration, it is possible to generate a wiring capacitance between the transfer wiring and the capacitance control wiring in the vicinity of the floating diffusion.

[0020] In the above configuration, in the multi-wiring layer, the second control line layer may be formed three or more layers away from the FD connection layer.

[0021] According to the above configuration, it is possible to reduce the influence of feedthrough caused by the reset signal and the row selection signal on the floating diffusion.

[0022] In the above configuration, the multilayer wiring layer may include a constant voltage wiring layer, the constant voltage wiring layer including a reference potential wiring to which a reference potential is applied, and the constant voltage wiring layer is further formed between the first control line layer and the second control line layer.

[0023] Feedthrough occurs due to voltage fluctuations around the wiring capacitance. In other words, feedthrough does not occur in principle due to a constant voltage wiring layer. By placing a wiring layer that does not cause feedthrough closer to the floating diffusion than the second control line layer, it is possible to suppress the potential drop of the floating diffusion due to feedthrough.

[0024] In the above configuration, the wafer may include a pixel portion wafer and a logic circuit portion wafer. In this case, a photodiode, a floating diffusion, and a transfer transistor are formed in the pixel portion wafer. A reset transistor and a source follower transistor are formed in the logic circuit portion wafer. The FD connection layer is formed in the first layer of the multilayer wiring layer of the pixel portion wafer. The first control line layer is formed in the second layer of the multilayer wiring layer of the pixel portion wafer. The second control line layer is formed in the multilayer wiring layer of the logic circuit portion wafer. The multilayer wiring layer of the logic circuit portion wafer is stacked facing the multilayer wiring layer of the pixel portion wafer.

[0025] According to the above configuration, wiring and terminals that cause feedthrough, which leads to a potential drop in the floating diffusion, are arranged on the logic circuit wafer, thereby suppressing potential drops due to feedthrough in the floating diffusion formed on the pixel wafer.

[0026] In the above configuration, the multilayer wiring layer may include a constant voltage wiring layer. The constant voltage wiring layer includes a reference potential wiring to which a reference potential is applied. The second control line layer is formed as a first layer in the multilayer wiring layer of the logic circuit wafer. The constant voltage wiring layer is formed as a second layer in the multilayer wiring layer of the logic circuit wafer. The constant voltage wiring layer on the logic circuit wafer is stacked on the first control line layer on the pixel wafer.

[0027] In the above configuration, the wafer may include a pixel portion wafer and a logic circuit portion wafer. In this case, a photodiode, a floating diffusion, a source follower transistor, and a transfer transistor are formed in the pixel portion wafer. A reset transistor and a row selection transistor are formed in the logic circuit portion wafer. The FD connection layer is formed in the first layer of the multilayer wiring layer of the pixel portion wafer. The first control line layer is formed in the second layer of the multilayer wiring layer of the pixel portion wafer. The second control line layer is formed in the multilayer wiring layer of the logic circuit portion wafer. The multilayer wiring layer of the logic circuit portion wafer is stacked facing the multilayer wiring layer of the pixel portion wafer.

[0028] In the above configuration, an additional capacitance and a selective conversion gain transistor may be formed on the wafer. is provided between the additional capacitance and the floating diffusion. The wiring formed in the multi-layer wiring layer includes a selective conversion gain wiring. The connection wiring transmits a selective conversion gain signal to the selective conversion gain transistor.

[0029] The image sensor disclosed in this specification includes at least one wafer and a multilayer wiring layer. A photodiode, a transfer transistor, a floating diffusion, a reset transistor, and a source follower transistor are formed on the wafer. The photodiode photoelectrically converts incident light. The transfer transistor transfers the charge photoelectrically converted by the photodiode. The floating diffusion temporarily holds the charge transferred from the transfer transistor. The reset transistor resets the potential of the floating diffusion to a reference potential. The source follower transistor has a gate connected to the floating diffusion. A multilayer wiring layer is stacked on the wafer. Wiring formed in the multilayer wiring layer includes a transfer wiring, a capacitance control wiring, a reset wiring, and an FD-SF wiring. A transfer signal to the transfer transistor is transmitted through the transfer wiring. The capacitance control wiring is capacitively coupled to the floating diffusion. A boost signal that increases the potential of the floating diffusion is transmitted through the capacitance control wiring. A reset signal to the reset transistor is transmitted through the reset wiring. The FD-SF wiring connects the floating diffusion and the source follower transistor. In the multi-layer wiring layer, the transfer wiring, capacitance control wiring, and reset wiring are formed in a single layer. Furthermore, the transfer wiring and capacitance control wiring are wider than the reset wiring.

[0030] As illustrated at time t2 in FIG. 2 (described later), when the reset signal switches (RST: Hi → Lo), the potential of the floating diffusion is pulled down by the feedthrough (the well becomes shallower). Also, as illustrated at times t3 and t4 in FIG. 2, when the boost signal and the transfer signal are transmitted, the potential of the floating diffusion is pulled up by the feedthrough. By making the wiring width of the transfer wiring and the capacitance control wiring wider than that of the reset wiring, the extent to which the potential is pulled up by the feedthrough increases. Also, by making the wiring width of the reset wiring narrower than that of the transfer wiring and the capacitance control wiring, the potential pull-down by the feedthrough is suppressed.

[0031] In the above configuration, a row selection transistor connected to the source of the source follower transistor may be formed on the wafer. In this case, the wiring formed in the multilayer wiring layer includes a row selection wiring. A row selection signal is transmitted to the row selection transistor through the row selection wiring. In the multilayer wiring layer, in addition to the transfer wiring, capacitance control wiring, and reset wiring, the row selection wiring is formed in a single layer. Furthermore, the row selection wiring has a wiring width narrower than that of the transfer wiring and capacitance control wiring.

[0032] 6, the potential of the floating diffusion is lowered (the well becomes shallower) by the feedthrough when the row selection signal is transmitted (RS: Lo→Hi), as shown at time t11 in FIG. 6. By making the wiring width of the row selection wiring narrower than the wiring widths of the transfer wiring and the capacitance control wiring, the potential lowering due to the feedthrough is suppressed.

[0033] This specification also discloses a method for manufacturing an image sensor. In this manufacturing method, a photodiode, a floating diffusion, and a source follower transistor are formed on at least one wafer. The photodiode photoelectrically converts incident light. The floating diffusion temporarily holds the charge accumulated in the photodiode. The source follower transistor has a gate connected to the floating diffusion. In this manufacturing method, a multilayer wiring layer is further stacked on the wafer. The wiring included in the multilayer wiring layer includes a capacitance control wiring and an FD-SF wiring. The capacitance control wiring is capacitively coupled to the floating diffusion. A boost signal is transmitted to the capacitance control wiring. The boost signal increases the potential of the floating diffusion. The FD-SF wiring connects the floating diffusion and the source follower transistor. In addition, an FD connection layer and a first control line layer are formed as the multilayer wiring layer. Of the wiring layers in the multilayer wiring layer, the first control line layer is disposed closest to the FD connection layer.

[0034] In the above configuration, a transfer transistor may be formed on the wafer. The transfer transistor transfers charges photoelectrically converted by the photodiode to the floating diffusion. A transfer wiring is formed in the first control line layer. A transfer signal to the transfer transistor is transmitted through the transfer wiring.

[0035] In the above configuration, a reset transistor may be formed in the image sensor. The reset transistor resets the potential of the floating diffusion to a reference potential. The wiring formed in the multilayer wiring layer includes a reset wiring. A reset signal to the reset transistor is transmitted through the reset wiring. A second control line layer is formed as the multilayer wiring layer. The reset wiring is formed in the second control line layer.

[0036] In the above configuration, a row selection transistor may be formed in the image sensor. The row selection transistor is connected to the source of the source follower transistor. A row selection wiring is formed in the second control line layer. A row selection signal is transmitted to the row selection transistor through the row selection wiring.

[0037] In the above configuration, the wafer may include a pixel portion wafer and a logic circuit portion wafer. In this case, a photodiode, a floating diffusion, and a transfer transistor are formed in the pixel portion wafer. Furthermore, a reset transistor and a source follower transistor are formed in the logic circuit portion wafer. An FD connection layer is formed in the first layer of a multilayer wiring layer of the pixel portion wafer. A first control line layer is formed in the second layer of the multilayer wiring layer of the pixel portion wafer. A second control line layer is formed in the multilayer wiring layer of the logic circuit portion wafer. Furthermore, the multilayer wiring layer of the logic circuit portion wafer is stacked facing the multilayer wiring layer of the pixel portion wafer.

[0038] This specification also discloses a method for manufacturing an image sensor. In this manufacturing method, a photodiode, a transfer transistor, a floating diffusion, a reset transistor, and a source follower transistor are formed on at least one wafer. The photodiode photoelectrically converts incident light. The transfer transistor transfers the charge photoelectrically converted by the photodiode. The floating diffusion temporarily holds the charge transferred from the transfer transistor. The reset transistor resets the potential of the floating diffusion to a reference potential. The source follower transistor has a gate connected to the floating diffusion. A multilayer wiring layer is also stacked on the wafer. Wiring formed in the multilayer wiring layer includes a transfer wiring, a capacitance control wiring, a reset wiring, and an FD-SF wiring. A transfer signal to the transfer transistor is transmitted through the transfer wiring. The capacitance control wiring is capacitively coupled to the floating diffusion. A boost signal is transmitted through the capacitance control wiring. The boost signal increases the potential of the floating diffusion. A reset signal to the reset transistor is transmitted through the reset wiring. The FD-SF wiring connects the floating diffusion and the source follower transistor. In the multi-layer wiring layer, the transfer wiring, capacitance control wiring, and reset wiring are formed in a single layer. Furthermore, the transfer wiring and capacitance control wiring are formed with a wiring width wider than that of the reset wiring. [Effects of the Invention]

[0039] According to the image sensor and the method for manufacturing the image sensor disclosed in this specification, it is possible to suppress afterimages and injection while suppressing feedthrough that lowers the potential of the floating diffusion. [Brief explanation of the drawings]

[0040] [Figure 1] FIG. 2 is a diagram illustrating a circuit configuration of an image sensor according to the present embodiment. [Figure 2] FIG. 2 is a diagram illustrating a timing chart of the image sensor according to the embodiment. [Figure 3] FIG. 1 is a diagram illustrating the charge transfer process (1 / 3). [Figure 4] FIG. 1 is a diagram illustrating the charge transfer process (2 / 3). [Figure 5] FIG. 10 is a diagram illustrating the charge transfer process (3 / 3). [Figure 6] FIG. 10 is a diagram illustrating a timing chart (with row selection) of the image sensor according to the present embodiment. [Figure 7] FIG. 2 is a plan view illustrating a wiring structure of the image sensor according to the first embodiment. [Figure 8] 1 is a cross-sectional view illustrating the structure of an image sensor according to a first embodiment; [Figure 9] FIG. 10 is a plan view illustrating the wiring structure of the image sensor according to the second embodiment. [Figure 10] FIG. 10 is a cross-sectional view illustrating the structure of an image sensor according to a second embodiment. [Figure 11] FIG. 10 is a diagram illustrating a circuit configuration of an image sensor according to a third embodiment. [Figure 12] FIG. 10 is a cross-sectional view illustrating the structure of an image sensor according to a third embodiment. [Figure 13] FIG. 10 is a diagram illustrating a circuit configuration of an image sensor according to a variation of the third embodiment. [Figure 14] FIG. 11 is a cross-sectional view illustrating the structure of an image sensor according to a variation of the third embodiment. [Figure 15] FIG. 10 is a diagram illustrating a circuit configuration of an image sensor according to a fourth embodiment. [Figure 16] FIG. 10 is a diagram illustrating a timing chart of an image sensor according to a fourth embodiment. [Figure 17] FIG. 10 is a plan view illustrating a wiring structure of an image sensor according to a fourth embodiment. [Figure 18] FIG. 10 is a cross-sectional view illustrating the structure of an image sensor according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0041] The image sensor and its manufacturing method will be described below with reference to the drawings. The shapes, materials, quantities, and values ​​described below are examples for the purpose of explanation. These shapes, etc. can be changed as appropriate depending on the specifications of the image sensor. Furthermore, the same reference numerals will be used to designate equivalent elements in all drawings below.

[0042] 7, 9, and 17 show plan views of the image sensor 10 according to this embodiment. Also, Figures 8, 10, 12, 14, and 18 show cross-sectional views of the image sensor 10 according to this embodiment. The cross-sectional views are taken perpendicular to the plan views.

[0043] 1. Circuit configuration FIG. 1 illustrates a circuit diagram of an image sensor 10 according to first to third embodiments. The image sensor 10 is configured as a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The image sensor 10 is a so-called shared pixel type image sensor. That is, in the image sensor 10, multiple photodiodes PD1-PD4 share a floating diffusion amplifier. By using such a circuit configuration, the number of transistors per pixel can be reduced.

[0044] Referring to FIG. 1, photodiodes PD1-PD4 photoelectrically convert incident light. Transfer transistors TX1-TX4 transfer the charges photoelectrically converted by photodiodes PD1-PD4 to floating diffusions FD. The floating diffusions FD temporarily hold the charges accumulated in the photodiodes PD1-PD4. The reset transistor RST resets the potential of the floating diffusions FD to a reference potential VDD. The gate of the source follower transistor SF is opened in response to the potential of the floating diffusions FD. The row selection transistor outputs a signal (voltage signal) to the bit line when a row selection signal RS_sig is applied to its gate.

[0045] The photodiodes PD1-PD4 are connected to a floating diffusion FD via transfer transistors TX1-TX4, respectively. The floating diffusion FD is connected to the gate of a source follower transistor SF. The floating diffusion FD is also connected to the source of a reset transistor RST. The drains of the source follower transistor SF and the reset transistor RST are connected to a reference potential line L_VDD. The source of the source follower transistor SF is connected to the drain of a row select transistor RS. The source of the row select transistor RS is connected to a bit line.

[0046] Furthermore, wiring capacitance occurs between the floating diffusion FD and the capacitance control wiring FDC. For example, a boost signal, which is a voltage signal, is transmitted to the capacitance control wiring FDC. As shown at time t3 in Figure 2 (described later), the boost signal is output (FDC: Lo → Hi), temporarily increasing the potential of the floating diffusion FD during charge transfer.

[0047] 2 illustrates a timing chart illustrating the operation of each terminal of the image sensor 10. Referring to FIGS. 2 and 3, at time t1, the reset transistor RST is turned on (Hi). In other words, the reset signal RST_sig is switched from off to on. This resets the floating diffusion FD to the reference potential VDD. Furthermore, charge is accumulated in the photodiodes PD1-PD4 by photoelectric conversion.

[0048] 2 and 3, at time t2, the reset transistor RST switches from an on state to an off state (Lo). At this time, feedthrough occurs via the parasitic capacitance formed between the reset transistor RST and the floating diffusion FD. That is, as illustrated in FIG. 4, as the voltage (reset signal) of the reset line L_RST (see FIG. 7) connected to the reset transistor RST changes from Hi to Lo, the potential of the floating diffusion FD drops.

[0049] 2, at time t3, the capacitance control line FDC switches from an off state (Lo) to an on state (Hi). That is, a predetermined boost signal (voltage signal) is applied to the capacitance control line FDC. As a result, the potential of the floating diffusion FD increases (the well deepens) via the parasitic capacitance between the floating diffusion FD and the capacitance control line FDC.

[0050] 2 and 5, at time t4, at least one of the transfer transistors TX1-TX4 switches from an off state (Lo) to an on state (Hi). At this time, feedthrough occurs via the parasitic capacitance formed between the transfer transistors TX1-TX4 and the floating diffusion FD. That is, as the voltage of at least one of the transfer wirings L_TX1-L_TX4 (see FIG. 7) connected to the transfer transistors TX1-TX4 changes from Lo to Hi, the potential of the floating diffusion FD increases (the well deepens).

[0051] At times t3 and t4, the potential of the floating diffusion FD temporarily rises during charge transfer. As a result, the potential difference between the photodiodes PD1-PD4 (simply referred to as PD in FIG. 5) and the floating diffusion FD increases, as illustrated in FIG. 5. As a result, the occurrence of image lag and injection is suppressed.

[0052] After that, at time t5, the transfer transistors TX1-TX4 are switched from the on state to the off state, at which time the potential of the floating diffusion FD drops due to feedthrough (the well becomes shallower).

[0053] Furthermore, at time t6, the capacitance control wiring FDC switches from the on state to the off state, at which time the potential of the floating diffusion FD drops due to the feedthrough (the well becomes shallower).

[0054] That is, after time t6, charges are detected with high conversion efficiency. As described above, in the image sensor 10 according to this embodiment, when charges are transferred from the photodiodes PD1-PD4 to the floating diffusion FD, the potential of the floating diffusion FD temporarily increases. This ensures high conversion efficiency while suppressing image lag and injection during charge transfer.

[0055] Fig. 6 illustrates a timing chart different from that of Fig. 2. In Fig. 6, at time t11, the row selection transistor RS switches from an off state to an on state. Note that in Fig. 2, the operations other than those of the row selection transistor are the same as those in the timing chart of Fig. 2.

[0056] At time t11, when the row select transistor RS switches from an off state to an on state, feedthrough occurs via the parasitic capacitance formed between the row select transistor RS and the floating diffusion FD. That is, as the voltage of the row select wiring L_RS (see FIG. 7) connected to the row select transistor RS changes from Lo to Hi, the potential of the floating diffusion FD increases. That is, the potential of the floating diffusion FD decreases (the well becomes shallower).

[0057] 2 and 6, between time t4 and time t6, the charges accumulated in the photodiodes PD1-PD4 are transferred to the floating diffusion FD. During this charge transfer, the potential of the floating diffusion FD is pulled down (the well becomes shallower) due to feedthrough caused by the operation of the reset transistor RST (time t2) and the operation of the row select transistor (time t11). In addition, the potential of the floating diffusion FD is pulled up (the well becomes deeper) due to feedthrough caused by the transmission of a boost signal to the capacitance control wiring FDC (time t3) and the operation of the transfer transistors TX1-TX4 (time t4).

[0058] As described above, during charge transfer from the photodiodes PD1-PD4 to the floating diffusion FD, it is necessary to temporarily raise the potential of the floating diffusion FD. The operation of the reset transistor RST (time t2) and the operation of the row select transistor (time t11) lower the potential of the floating diffusion FD during charge transfer. Meanwhile, the transmission of a boost signal to the capacitance control wiring FDC (time t3) and the operation of the transfer transistors TX1-TX4 (time t4) raise the potential of the floating diffusion FD during charge transfer.

[0059] Therefore, in the following embodiments 1 to 4, a wiring layout is adopted in which the wiring capacitance between the reset transistor RST and the row select transistor RS and the floating diffusion FD is relatively low, and in the embodiments 1 to 4, a wiring layout is adopted in which the wiring capacitance between the capacitance control wiring FDC and the transfer transistors TX1 to TX4 is relatively high.

[0060] 2. First embodiment 7 and 8 illustrate an image sensor 10 according to the first embodiment. Fig. 7 illustrates a plan view of the image sensor 10. Fig. 8 illustrates a cross-sectional view of the image sensor. In Fig. 7, the wiring formed in each wiring layer M1, M2, M3, and M4 is indicated by different hatching patterns.

[0061] The image sensor 10 includes a wafer wf and a multilayer wiring layer ML. For example, the image sensor 10 is a back-illuminated CMOS image sensor.

[0062] The wafer wf is formed with pixel terminals and logic circuit terminals of the image sensor 10. Specifically, the wafer wf is formed with photodiodes PD, transfer transistors TX, and floating diffusions FD.

[0063] A multilayer wiring layer ML is stacked on the wafer wf. The multilayer wiring layer ML includes multiple wiring layers M1, M2, M3, and M4. Wiring is formed horizontally in the wiring layers M1, M2, M3, and M4 along the surface of the wafer wf.

[0064] The multilayer wiring layer ML also includes a plurality of interlayer insulating films ILD1, ILD2, ILD3, and ILD4. The interlayer insulating films ILD1, ILD2, ILD3, and ILD4 are disposed between the wafer wf and the wiring layers M1, M2, M3, and M4. Contacts C and vias (not shown) are formed in the interlayer insulating films ILD1, ILD2, ILD3, and ILD4. The contacts C and vias extend perpendicular to the surface of the wafer wf.

[0065] Of the multi-layer wiring layers ML, the first wiring layer M1 has an FD-SF wiring formed therein. The FD-SF wiring is a wiring that connects the floating diffusion FD and the source follower transistor SF (see FIG. 1). For example, the FD-SF wiring is connected to the floating diffusion FD via a contact C. Because the FD-SF wiring is formed therein, the first wiring layer M1 is also referred to as the "FD connection layer" hereinafter as appropriate.

[0066] The second wiring layer M2 has transfer wirings L_TX1, L_TX2, L_TX3, and L_TX4 and capacitance control wiring FDC. The transfer wirings L_TX1, L_TX2, L_TX3, and L_TX4 are connected to the transfer transistors TX1, TX2, TX3, and TX4. In addition, the transfer wirings L_TX1, L_TX2, L_TX3, and L_TX4 transmit transfer signals TX1_sig to TX4_sig, which are on / off signals (voltage signals) for the transfer transistors TX1, TX2, TX3, and TX4.

[0067] The capacitance control wiring FDC is capacitively coupled to the floating diffusion FD. A boost signal, which is a voltage signal, is transmitted to the capacitance control wiring FDC. When the boost signal is applied to the capacitance control wiring FDC, the potential of the floating diffusion FD temporarily increases. Hereinafter, the second wiring layer M2 will also be referred to as the "first control line layer" where appropriate.

[0068] Bit lines are formed in the third wiring layer M3. Also, referring to Fig. 7, reference potential wiring L_VDD and ground wiring L_GND are formed in the wiring layer M3. Although the voltage of the bit lines fluctuates, the third wiring layer M3 is also called a "constant voltage wiring layer" because it includes the reference potential wiring L_VDD and ground wiring L_GND, which are constant potential wiring.

[0069] Furthermore, a reset line L_RST and a row selection line L_RS are formed on the fourth wiring layer M4. A reset transistor RST is connected to the reset line L_RST. A reset signal RST_sig, which is an on / off signal (voltage signal) for the reset transistor RST, is transmitted to the reset line L_RST. A row selection signal RS_sig, which is an on / off signal for the row selection transistor RS, is transmitted to the row selection line L_RS. Hereinafter, the fourth wiring layer M4 will also be referred to as the "second control line layer" where appropriate.

[0070] 8, wiring capacitance occurs between the wiring formed in the multi-layer wiring layer ML and the FD-SF wiring. In the multi-layer wiring layer ML, the first control line layer M2 is the wiring layer closest to the FD connection layer M1. Therefore, the wiring capacitance C between the transfer wirings L_TX1, L_TX2, L_TX3, and L_TX4 formed in the first control line layer M2 and the capacitance control wiring FDC and the FD-capacitance control wiring FDC-FD (parasitic capacitance) becomes relatively large.

[0071] 7, the FD-SF wiring intersects with the transfer wirings L_TX1, L_TX2, L_TX3, and L_TX4, and the capacitance control wiring FDC in a circuit plan view. That is, the distances between the FD-SF wiring and each of the transfer wirings L_TX1, L_TX2, L_TX3, and L_TX4, and the capacitance control wiring FDC are all equal.

[0072] The second control line layer M4 is spaced apart from the FD connection layer M1. For example, the second control line layer M4 is formed three or more layers away from the FD connection layer M1. With this layer arrangement, the wiring capacitance C between the reset line L_RST and row selection line L_RS formed in the second control line layer M4 and the FD-reset line is RST-FD , C RS-FD (parasitic capacitance) becomes relatively small.

[0073] As described above, the image sensor 10 according to the first embodiment has a control line layer separated into two layers. That is, wiring that generates a feedthrough that temporarily increases the potential of the floating diffusion FD (deepens the well) is formed in the first control line layer M2.

[0074] On the other hand, a wiring that generates a feedthrough that temporarily lowers the potential of the floating diffusion FD (makes the well shallower) is formed in the second control line layer M4. By separating the second control line layer M4 from the FD-SF wiring, the potential fluctuation due to the feedthrough is suppressed.

[0075] 3. Second embodiment (wide L_TX and wide FDC) 9 and 10 illustrate an image sensor 10 according to a second embodiment. Fig. 9 illustrates a plan view of the image sensor 10. Fig. 10 illustrates a cross-sectional view of the image sensor. In Fig. 9, the wiring formed in each of the wiring layers M1, M2, and M3 is indicated by different hatching patterns.

[0076] The image sensor 10 includes a wafer wf and a multilayer wiring layer ML. The wafer wf has the same structure as that of the first embodiment. Therefore, a detailed description of the wafer wf will be omitted.

[0077] Of the multilayer wiring layers ML, the first wiring layer M1 is an FD connection layer as in the first embodiment, and the third wiring layer M3 is a constant voltage wiring layer as in the first embodiment.

[0078] The second wiring layer M2 is a control line layer. That is, the wiring layer M2 includes transfer lines L_TX1, L_TX2, L_TX3, and L_TX4, capacitance control lines FDC, reset lines L_RST, and row selection lines L_RS. That is, in the image sensor 10 according to the second embodiment, unlike the first embodiment, the transfer lines L_TX1, L_TX2, L_TX3, and L_TX4, capacitance control lines FDC, reset lines L_RST, and row selection lines L_RS are formed in a single layer.

[0079] Additionally, in the wiring layer M2, the wiring width of the reset wiring L_RST and the row selection wiring L_RS is narrower than the wiring width of the transfer wiring L_TX1, L_TX2, L_TX3, L_TX4, and the capacitance control wiring FDC. In other words, the wiring width of the transfer wiring L_TX1, L_TX2, L_TX3, L_TX4, and the capacitance control wiring FDC is wider than the wiring width of the reset wiring L_RST and the row selection wiring L_RS.

[0080] By narrowing the width of the reset line L_RST and row selection line L_RS overall, the wiring capacitance between these lines and the FD-SF lines can be reduced, and the wiring capacitance between the transfer lines L_TX1, L_TX2, L_TX3, and L_TX4, the capacitance control line FDC, and the FD-SF lines can be increased.

[0081] 4. Third embodiment (two-wafer type image sensor) 11 and 12 illustrate an image sensor 10 according to a third embodiment. In this embodiment, an image sensor 10 having two type wafers is disclosed.

[0082] That is, the image sensor 10 includes a pixel wafer wf1 and a logic circuit wafer wf2. The pixel wafer wf1 has the same structure as the wafer wf in embodiment 1. Therefore, a detailed description thereof will be omitted here.

[0083] 11 and 12, logic circuit terminals of the image sensor 10 are formed on the logic circuit wafer wf2. For example, source follower transistors SF, reset transistors RST, and row select transistors RS are formed on the logic circuit wafer wf2. For example, the surface of the pixel wafer wf1 on which the transfer transistors TX1-TX4 are formed faces the surface of the logic circuit wafer wf2 on which the source follower transistors SF and the like are formed.

[0084] 12, a multilayer wiring layer ML1 is formed on a pixel portion wafer wf1. A first layer M1A of the multilayer wiring layer ML1 is an FD connection layer. A second layer M2A is a first control line layer. This first control line layer has the same structure as the same layer in the first embodiment.

[0085] A multilayer wiring layer ML2 is also formed on the logic circuit wafer wf2. The first layer M1B of the multilayer wiring layer ML2 is a second control line layer. This second control line layer has the same structure as the same layer in the first embodiment.

[0086] The second layer M2B of the multilayer wiring layer ML2 is a constant-voltage wiring layer identical to the wiring layer M3 of the first embodiment. In the image sensor 10, the multilayer wiring layer ML1 of the pixel wafer wf1 and the multilayer wiring layer ML2 of the logic circuit wafer wf2 are stacked facing each other. That is, the M2B of the logic circuit wafer wf2 is stacked on the first control line layer M2A of the pixel wafer wf1. For example, the uppermost interlayer insulating film ILD3A of the pixel wafer wf1 and the uppermost interlayer insulating film ILD3B of the logic circuit wafer wf2 are bonded together.

[0087] According to the above configuration, wiring and terminals that cause feedthrough, which leads to a potential drop in the floating diffusion FD, are arranged on the logic circuit wafer wf2, thereby suppressing a potential drop due to feedthrough in the floating diffusion FD formed on the pixel wafer wf1.

[0088] 13 and 14 show an image sensor 10 according to a variation of the third embodiment. In this embodiment, similarly to the image sensor 10 shown in FIGS. 11 and 12, an image sensor 10 having two types of wafers is disclosed.

[0089] The logic circuit wafer wf2 has logic circuit terminals of the image sensor 10 formed thereon. For example, the logic circuit wafer wf2 has reset transistors RST and row select transistors RS formed thereon. For example, the surface of the pixel wafer wf1 on which the transfer transistors TX1-TX4 and source follower transistors SF are formed faces the surface of the logic circuit wafer wf2 on which the reset transistors RST, row select transistors RS, etc. are formed.

[0090] Furthermore, a multilayer wiring layer ML1 is formed on the pixel portion wafer wf1. The first layer M1A of the multilayer wiring layer ML1 is an FD connection layer. The second layer M2A is a first control line layer. This first control line layer has the same structure as the same layer in the first embodiment.

[0091] A multilayer wiring layer ML2 is also formed on the logic circuit wafer wf2. The first layer M1B of the multilayer wiring layer ML2 is a second control line layer. This second control line layer has the same structure as the same layer in the first embodiment.

[0092] The second layer M2B of the multilayer wiring layer ML2 is a constant-voltage wiring layer identical to the wiring layer in the first embodiment. In the image sensor 10, the multilayer wiring layer ML1 of the pixel wafer wf1 and the multilayer wiring layer ML2 of the logic circuit wafer wf2 are stacked facing each other. That is, the constant-voltage wiring layer M2B of the logic circuit wafer wf2 is stacked on the first control line layer M2 of the pixel wafer wf1. For example, the uppermost interlayer insulating film ILD3A of the pixel wafer wf1 and the uppermost interlayer insulating film ILD3B of the logic circuit wafer wf2 are bonded together.

[0093] According to the above configuration, wiring and terminals that cause feedthrough, which leads to a potential drop in the floating diffusion FD, are arranged on the logic circuit wafer wf2, thereby suppressing a potential drop due to feedthrough in the floating diffusion FD formed on the pixel wafer wf1.

[0094] The difference between the image sensor 10 according to FIGS. 11 and 12 and the image sensor 10 according to FIGS. 13 and 14 is the arrangement of the source follower transistor SF. In the image sensor 10 according to FIGS. 11 and 12, the source follower transistor SF is located on the pixel unit wafer wf1. In the image sensor 10 according to FIGS. 13 and 14, the source follower transistor SF is located on the logic circuit unit wafer wf2 (see FIG. 14). Because the source follower transistor SF is affected by the second control line, the source follower transistor SF is located on the pixel unit wafer wf1 in the image sensors according to FIGS. 13 and 14. However, in FIGS. 13 and 14, the terminals and wiring within the layers are changed depending on the ease of layout, etc.

[0095] 5. Fourth embodiment (selective conversion gain type image sensor) 15 illustrates an image sensor 10 according to the fourth embodiment. The image sensor 10 is a so-called dual conversion gain type (DCG) or selective conversion gain type image sensor.

[0096] 1, the circuit diagram of FIG. 15 adds an additional capacitance FD2 and a dual conversion gain transistor DFD to the image sensor 10. For example, the additional capacitance FD2 and the dual conversion gain transistor DFD are provided between the floating diffusion FD and the reset transistor RST. The dual conversion gain transistor DFD is provided between the floating diffusion FD and the additional capacitance FD2. The additional capacitance FD2 is also connected to an additional capacitance control wiring FDC2 or a ground wiring GND.

[0097] The image sensor 10 illustrated in FIG. 15 can switch between two types of charge detection efficiency: high conversion efficiency (HCG) and low conversion efficiency (LCG). At high conversion efficiency, the dual conversion gain transistor DFD is set to the off state. In this case, the charge accumulated in the photodiodes PD1-PD4 is transferred only to the floating diffusion FD. At low conversion efficiency (LCG), the dual conversion gain transistor DFD is set to the on state. In this case, the charge accumulated in the photodiodes PD1-PD4 is transferred to the additional capacitance FD2 in addition to the floating diffusion FD. For example, when capturing an image in a dark place, the image is captured with the high conversion efficiency setting (i.e., DFD off). When capturing an image in a bright place, the image is captured with the low conversion efficiency setting (i.e., DFD on).

[0098] Fig. 16 illustrates a timing chart of the image sensor 10 illustrated in Fig. 15. The period from time t21 to time t23 is a reset period in the low conversion efficiency mode. The period from time t23 to time t25 is a reset period in the high conversion efficiency mode.

[0099] Furthermore, the period from time t25 to time t26 is a period in which charges are transferred from the photodiodes PD1-PD4 to the floating diffusion FD in the high conversion efficiency mode. Referring to the waveform of the capacitance control line FDC, in the high conversion efficiency mode, no boost signal is output.

[0100] The period from time t27 to time t30 is the charge transfer period from the photodiodes PD1-PD4 to the floating diffusion FD and the additional capacitance FD2 in the low conversion efficiency mode. Note that the timing chart in Figure 16 does not show the potential change of the additional capacitance FD2. Also, referring to the waveform of the capacitance control line FDC, the timing chart in Figure 16 shows that a boost signal is output in the low conversion efficiency mode.

[0101] 16, when the dual conversion gain transistor DFD switches from the on state to the off state, the potential of the floating diffusion FD is raised (the well becomes shallower) due to the feedthrough. Taking note of this phenomenon, the image sensor 10 has the wiring configurations exemplified in FIGS. 17 and 18.

[0102] 7 and 8, the dual conversion gain transistor wiring L_DFD, the ground wiring L_GND, the additional capacitance control wiring L_FDC2, and the FD2 wiring L_FD2 are arranged in the multilayer wiring layer ML in Figures 17 and 18. Note that either the ground wiring L_GND or the additional capacitance control wiring L_FDC2 may be omitted.

[0103] The dual conversion gain transistor wiring L_DFD is connected to the gate of the dual conversion gain transistor DFD. A dual conversion gain signal DFD_sig (voltage signal) to the dual conversion gain transistor DFD is transmitted to the dual conversion gain transistor wiring L_DFD. The ground wiring L_GND is connected to one end of the additional capacitance FD2. Alternatively, instead of the ground wiring L_GND, the additional capacitance control wiring L_FDC2 is connected to one end of the additional capacitance FD2.

[0104] 17 and 18, in the multilayer wiring layer ML, the dual conversion gain transistor wiring L_DFD, the ground wiring L_GND, the additional capacitance control wiring L_FDC2, and the FD2 wiring L_FD2 are formed in the second control line layer M4.

[0105] Forming the dual conversion gain transistor wiring L_DFD on the second control line layer M4 suppresses feedthrough at time t23 in the timing chart of Fig. 16. Furthermore, forming the additional capacitance control wiring L_FDC2 and the FD2 wiring L_FD2 on the second control line layer M4 suppresses capacitive coupling between the additional capacitance FD2 and the floating diffusion FD. [Explanation of symbols]

[0106] 10 Image sensor, C contact, C FDC-FD FD-Wiring capacitance with capacitance control wiring, C RST-FD Wiring capacitance with FD-reset wiring, DFD selective conversion gain transistor, DFD_sig selective conversion gain transistor signal, FD floating diffusion, FD2 additional capacitance, FDC capacitance control wiring, FDC2 additional capacitance control wiring, FD-SF wiring floating diffusion - source follower wiring, GND ground wiring, ILD1-ILD3 interlayer insulating film, ILD3A, ILD3B interlayer insulating film, ILD4 interlayer insulating film, L_DFD selective conversion gain transistor wiring, L_FD2 FD2 wiring, L_FDC2 additional capacitance control wiring, L_GND ground wiring, L_RS row selection wiring, L_RST reset wiring, L_TX1-L_TX4 transfer wiring, L_VDD reference potential wiring, M1, M1A FD connection layer (first layer), M2 , M2A, M1B first control line layer (second layer), M3, M2B Constant voltage wiring layer (third layer), M4 second control line layer (fourth layer), ML, ML1, ML2 multi-layer wiring layer, PD1-PD4 photodiode, RS row selection transistor, RST reset transistor, RST_sig reset signal, RS_sig row selection signal, SF source follower transistor, TX1-TX4 transfer transistor, TX1_sig-TX4_sig transfer signal, VDD reference potential, wf wafer, wf1 pixel wafer, wf2 logic circuit wafer, DFD selective conversion gain transistor, DFD sig selective conversion gain transistor signal.

Claims

1. a photodiode that converts incident light into an electric signal; a floating diffusion that temporarily holds the charge accumulated in the photodiode; a source follower transistor whose gate is connected to the floating diffusion; At least one wafer on which a multilayer wiring layer stacked on the wafer; Equipped with The wiring formed in the multilayer wiring layer includes: a capacitance control wiring that is capacitively coupled to the floating diffusion and transmits a boost signal that increases the potential of the floating diffusion; an FD-SF wiring that connects the floating diffusion and the source follower transistor; Contains, The multilayer wiring layer includes: an FD connection layer on which the FD-SF wiring is formed; a first control line layer in which the capacitance control wiring is formed; Equipped with In the multilayer wiring layer, the first control line layer is the wiring layer closest to the FD connection layer. Image sensor.

2. 2. The image sensor of claim 1, a transfer transistor that transfers charges photoelectrically converted by the photodiode to the floating diffusion is formed on the wafer; In the first control line layer, a transfer wiring is formed through which a transfer signal is transmitted to the transfer transistor. Image sensor.

3. 3. The image sensor according to claim 2, a reset transistor is formed to reset the potential of the floating diffusion to a reference potential; the wiring formed in the multilayer wiring layer includes a reset wiring through which a reset signal is transmitted to the reset transistor; the multilayer wiring layer includes a second control line layer in which the reset line is formed; Image sensor.

4. 4. The image sensor according to claim 3, a row select transistor connected to the source of the source follower transistor; The second control line layer is formed with a row selection wiring that transmits a row selection signal to the row selection transistor. Image sensor.

5. 5. The image sensor according to claim 4, the FD-SF wiring intersects with the transfer wiring and the capacitance control wiring in a circuit plan view; Image sensor.

6. 6. The image sensor according to claim 5, the FD connection layer is formed as a first layer of the multilayer wiring layer, the first control line layer is formed in a second layer of the multilayer wiring layer; Image sensor.

7. 7. The image sensor of claim 6, In the multilayer wiring layer, the second control line layer is formed three or more layers away from the FD connection layer. Image sensor.

8. 8. The image sensor of claim 7, the multilayer wiring layer includes a constant voltage wiring layer in which constant voltage wiring is formed, the constant voltage wiring including a reference potential wiring to which the reference potential is applied; the constant voltage wiring layer is formed between the first control line layer and the second control line layer; Image sensor.

9. 4. The image sensor according to claim 3, the wafer includes a pixel portion wafer and a logic circuit portion wafer, the photodiode, the floating diffusion, and the transfer transistor are formed on the pixel portion wafer; the reset transistor, the row selection transistor, and the source follower transistor are formed on the logic circuit wafer; the FD connection layer is formed as a first layer in the multilayer wiring layer of the pixel portion wafer, the first control line layer is formed as a second layer in the multilayer wiring layer of the pixel portion wafer, the second control line layer is formed in the multilayer wiring layer of the logic circuit wafer, the multilayer wiring layer of the logic circuit wafer is stacked on the multilayer wiring layer of the pixel wafer so as to face each other; Image sensor.

10. 10. The image sensor of claim 9, the multilayer wiring layer includes a constant voltage wiring layer in which constant voltage wiring is formed, including a reference potential wiring to which the reference potential is applied; the second control line layer is formed as a first layer in the multilayer wiring layer of the logic circuit wafer, the constant voltage wiring layer is formed as a second layer in the multilayer wiring layer of the logic circuit wafer, the constant voltage wiring layer on the logic circuit wafer is laminated on the first control line layer on the pixel wafer; Image sensor.

11. 4. The image sensor according to claim 3, the wafer includes a pixel portion wafer and a logic circuit portion wafer, the photodiode, the floating diffusion, the source follower transistor, and the transfer transistor are formed on the pixel portion wafer; the reset transistor and the row select transistor are formed on the logic circuit wafer; the FD connection layer is formed as a first layer in the multilayer wiring layer of the pixel portion wafer, the first control line layer is formed as a second layer in the multilayer wiring layer of the pixel portion wafer, the second control line layer is formed in the multilayer wiring layer of the logic circuit wafer, the multilayer wiring layer of the logic circuit wafer is stacked on the multilayer wiring layer of the pixel wafer so as to face each other; Image sensor.

12. 4. The image sensor according to claim 3, an additional capacitance and a selective conversion gain transistor provided between the additional capacitance and the floating diffusion are formed on the wafer; the wiring formed in the multilayer wiring layer includes a selective conversion gain transistor wiring through which a connection signal to the selective conversion gain transistor is transmitted; The selective conversion gain transistor wiring is formed in the second control line layer. Image sensor.

13. a photodiode that converts incident light into an electric signal; a transfer transistor that transfers the charges photoelectrically converted by the photodiode; a floating diffusion that temporarily holds the charge transferred from the transfer transistor; a reset transistor that resets the potential of the floating diffusion to a reference potential; a source follower transistor whose gate is connected to the floating diffusion; At least one wafer on which a multilayer wiring layer stacked on the wafer; Equipped with The wiring formed in the multilayer wiring layer includes: a transfer wiring through which a transfer signal to the transfer transistor is transmitted; a capacitance control wiring that is capacitively coupled to the floating diffusion and transmits a boost signal that increases the potential of the floating diffusion; a reset wiring through which a reset signal is transmitted to the reset transistor; an FD-SF wiring that connects the floating diffusion and the source follower transistor; Contains, In the multi-layer wiring layer, the transfer wiring, the capacitance control wiring, and the reset wiring are formed in a single layer; Furthermore, the transfer wiring and the capacitance control wiring have a wiring width greater than that of the reset wiring. Image sensor.

14. 14. The image sensor of claim 13, a row select transistor connected to the source of the source follower transistor is formed on the wafer; The wiring formed in the multilayer wiring layer includes a row selection wiring through which a row selection signal is transmitted to the row selection transistor; In the multi-layer wiring layer, the row selection wiring is formed in a single layer in addition to the transfer wiring, the capacitance control wiring, and the reset wiring; Furthermore, the row selection wiring has a wiring width narrower than that of the transfer wiring and the capacitance control wiring. Image sensor.

15. At least one wafer a photodiode that converts incident light into an electric signal; a floating diffusion that temporarily holds the charge accumulated in the photodiode; a source follower transistor whose gate is connected to the floating diffusion; Forming stacking a multilayer wiring layer on the wafer; The wiring included in the multilayer wiring layer is a capacitance control wiring that is capacitively coupled to the floating diffusion and transmits a boost signal that increases the potential of the floating diffusion; an FD-SF wiring that connects the floating diffusion and the source follower transistor; Including, The multilayer wiring layer includes: an FD connection layer on which the FD-SF wiring is formed; a first control line layer in which the capacitance control wiring is formed; Forming The first control line layer is disposed closest to the FD connection layer among the wiring layers in the multilayer wiring layer. Image sensor manufacturing method.

16. 16. A method for manufacturing an image sensor according to claim 15, comprising the steps of: forming a transfer transistor on the wafer, the transfer transistor transferring the charge photoelectrically converted by the photodiode to the floating diffusion; a transfer wiring for transmitting a transfer signal to the transfer transistor is formed in the first control line layer; Image sensor manufacturing method.

17. 17. A method for manufacturing an image sensor according to claim 16, comprising the steps of: forming a reset transistor that resets the potential of the floating diffusion to a reference potential; the wiring formed in the multilayer wiring layer includes a reset wiring through which a reset signal is transmitted to the reset transistor; forming a second control line layer in which the reset line is formed as the multilayer wiring layer; Image sensor manufacturing method.

18. 18. A method for manufacturing an image sensor according to claim 17, comprising the steps of: forming a row select transistor connected to the source of the source follower transistor; forming a row selection line in the second control line layer, through which a row selection signal is transmitted to the row selection transistor; Image sensor manufacturing method.

19. 18. A method for manufacturing an image sensor according to claim 17, comprising the steps of: the wafer includes a pixel portion wafer and a logic circuit portion wafer, forming the photodiode, the floating diffusion, and the transfer transistor on the pixel portion wafer; forming the reset transistor and the source follower transistor on the logic circuit wafer; The FD connection layer is formed as a first layer in the multilayer wiring layer of the pixel portion wafer, The first control line layer is formed as a second layer in the multilayer wiring layer of the pixel portion wafer; forming the second control line layer in the multilayer wiring layer of the logic circuit wafer; laminating the multilayer wiring layer of the logic circuit wafer so that the multilayer wiring layer of the pixel wafer faces the multilayer wiring layer of the logic circuit wafer; Image sensor manufacturing method.

20. At least one wafer a photodiode that converts incident light into an electric signal; a transfer transistor that transfers the charges photoelectrically converted by the photodiode; a floating diffusion that temporarily holds the charge transferred from the transfer transistor; a reset transistor that resets the potential of the floating diffusion to a reference potential; a source follower transistor whose gate is connected to the floating diffusion; Forming stacking a multilayer wiring layer on the wafer; The wiring formed in the multilayer wiring layer includes: a transfer wiring through which a transfer signal to the transfer transistor is transmitted; a capacitance control wiring that is capacitively coupled to the floating diffusion and transmits a boost signal that increases the potential of the floating diffusion; a reset wiring through which a reset signal is transmitted to the reset transistor; an FD-SF wiring that connects the floating diffusion and the source follower transistor; Contains, In the multi-layer wiring layer, the transfer wiring, the capacitance control wiring, and the reset wiring are formed in a single layer; Furthermore, the transfer wiring and the capacitance control wiring are formed to have a wiring width greater than that of the reset wiring. Image sensor manufacturing method.

Images