Semiconductor storage device and control method thereof

Abstract

To provide a semiconductor storage device capable of operating a sense amplifier of each bank at high speed even when an overdrive voltage is shared among a plurality of banks, and a control method thereof.SOLUTION: A semiconductor storage device includes: a plurality of banks 20, each of which includes at least one sense amplifier 10; a first voltage supply unit 30 that supplies an overdrive voltage VOD higher than an operational voltage VBLH of the sense amplifier 10 to each sense amplifier 10 of the plurality of banks 20, when an amplifying operation of voltages of bit lines BLT, TLC connected to each of the sense amplifiers 10 of the plurality of banks 10 is performed; and a control unit 40 that controls supplying a charging voltage for charging the overdrive voltage VOD so that the overdrive voltage VOD is supplied to the sense amplifier 10 of either bank 20 in a state where the overdrive voltage VOD does not drop in a voltage drop when the amplifying operation is performed in either bank 20 among the plurality of banks 20.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a control method thereof. [Background technology]

[0002] For example, semiconductor memory devices such as DRAMs (Dynamic Random Access Memory) are configured to generate a weak potential difference between a pair of complementary bit lines (hereinafter referred to as a "pair of bit lines") based on data stored in a memory cell, and to read data by amplifying this potential difference with a sense amplifier. Also, known semiconductor memory devices are configured to supply an overdrive voltage higher than the operating voltage of the sense amplifier to the sense amplifier at the start of the amplification operation in order to speed up the data read operation of the sense amplifier by speeding up the amplification operation of the bit line voltage (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-273346 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional semiconductor memory devices, in order to meet demands for chip size reduction and design efficiency, a VOD supply unit that supplies an overdrive voltage (VOD) is provided so as to be shared among multiple (two in the illustrated example) banks (Bank 0, Bank 1), each of which includes multiple memory cells and multiple sense amplifiers, as shown in Figure 1(a). In this configuration, when the voltage of a bit line connected to each sense amplifier of the multiple banks (Bank 0, Bank 1) is amplified, the VOD supply unit supplies the overdrive voltage to the sense amplifier of each bank.

[0005] FIG. 1(b) shows an example of voltage changes of each signal when the sense amplifiers of each of multiple banks (Bank 0, Bank 1) are operated. In the example shown in FIG. 1(b), at time t1, data stored in one of the memory cells in Bank 0 (BK0) is sent to the bit line BLT (BK0), causing a slight change in the voltage level of the bit line BLT (BK0). Next, at time t2, the bit line voltage amplification operation begins, and the voltage levels of the pair of bit lines BLT (BK0) and BLC (BK0) are amplified by the sense amplifier connected to the pair of bit lines BLT (BK0) and BLC (BK0). At this time, an overdrive voltage is supplied from the VOD supply unit to the sense amplifier of Bank 0 (BK0), causing a voltage drop at node VOD_BK01 between the VOD supply unit and each bank (Bank 0, Bank 1).

[0006] Next, at time t3, when the voltage levels of the pair of bit lines BLT (BK0) and BLC (BK0) of bank 0 (BK0) are amplified to voltages approximately equal to the operating voltage VBLH and the ground voltage VSS, the VOD supply unit stops supplying the overdrive voltage to the sense amplifier of bank 0 (BK0). At this time, the voltage of node VOD_BK01 starts to rise to return to its initial state (a state where no voltage drop has occurred).

[0007] However, at time t4, when the voltage of the node VOD_BK01 has not yet recovered to its initial state and the voltage amplification operation of the pair of bit lines BLT (BK1) and BLC (BK1) of another bank 1 (BK1) begins, the VOD supply unit supplies an overdrive voltage to the sense amplifier of bank 1 (BK1), causing the voltage of node VOD_BK01 (i.e., the overdrive voltage) to drop further from the voltage at time t2. As a result, the voltage of the bit line BLT (BK1) is amplified using the further dropped overdrive voltage. In this case, it takes longer for the voltage of the bit line BLT (BK1) to reach the operating voltage VBLH (i.e., the amplification operation takes longer), slowing down the data read operation of the sense amplifier of bank 1. Therefore, in the prior art, when the overdrive voltage is shared among multiple banks (bank 0 and bank 1), it may be difficult to operate the sense amplifier of each bank (bank 1 in this case) at high speed.

[0008] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a semiconductor memory device and a control method thereof that can operate the sense amplifiers of each bank at high speed even when an overdrive voltage is shared among multiple banks. [Means for solving the problem]

[0009] In order to solve the above problem, the present invention provides a semiconductor memory device comprising: a plurality of banks each having at least one sense amplifier; a first voltage supply unit that supplies an overdrive voltage higher than the operating voltage of the sense amplifier to each of the sense amplifiers of the plurality of banks when an amplification operation of the voltage of a bit line connected to the sense amplifier of each of the plurality of banks is performed; and a control unit that controls the supply of a charging voltage for charging the overdrive voltage so that when the amplification operation is performed in any of the plurality of banks, the overdrive voltage is supplied to the sense amplifier of the any of the banks without being voltage-dropped.

[0010] According to this invention, when an amplification operation is performed in a bank, an overdrive voltage that has not been voltage-reduced can be supplied to the sense amplifier of that bank, which makes it possible to speed up the amplification operation in that bank compared to, for example, a case in which an overdrive voltage that has been voltage-reduced is supplied to the sense amplifier of that bank, thereby enabling the sense amplifier of that bank to operate at high speed. This allows the sense amplifier of each bank to operate at high speed even when the overdrive voltage is shared among multiple banks.

[0011] The present invention also provides a control method for a semiconductor memory device, the semiconductor memory device comprising: a plurality of banks each having at least one sense amplifier; a first voltage supply unit that supplies an overdrive voltage higher than the operating voltage of the sense amplifier to each of the sense amplifiers of the plurality of banks when an amplification operation of the voltage of a bit line connected to the sense amplifier of each of the plurality of banks is performed; and a control unit, wherein the control unit executes a step of controlling the supply of a charging voltage for charging the overdrive voltage so that the overdrive voltage is supplied to the sense amplifier of any of the plurality of banks without being voltage-dropped when the amplification operation is performed in any of the plurality of banks. [Effects of the Invention]

[0012] According to the semiconductor memory device and the control method thereof of the present invention, even when the overdrive voltage is shared among a plurality of banks, the sense amplifiers of each bank can be operated at high speed. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1A is a diagram showing an example of the configuration of a portion of a semiconductor memory device according to the prior art, and FIG. 1B is a diagram showing an example of the voltage changes of each signal when operating each sense amplifier of multiple banks according to the prior art. [Figure 2] 1A and 1B are diagrams showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention. [Figure 3] 10A and 10B are diagrams illustrating an example of changes in the voltage of each signal when sense amplifiers of each of a plurality of banks are operated in this embodiment. [Figure 4] FIG. 10 is a diagram showing an example of changes in the voltage of each signal when sense amplifiers of each of a plurality of banks are operated in a modified example of the present invention. [Figure 5] FIG. 10 is a diagram showing an example of the configuration of a semiconductor memory device according to a modified example of the present invention. [Figure 6] FIG. 10 is a diagram showing an example of the configuration of a semiconductor memory device according to a modified example of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] 2A and 2B are diagrams showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 2A, the semiconductor memory device includes a plurality of sense amplifiers 10 connected to a plurality of memory cells MC. Note that in the example shown in FIG. 2A, only one memory cell MC and one sense amplifier 10 are shown to avoid obscuring the diagram. Each of the memory cells MC and the sense amplifier 10 may have a configuration similar to a well-known configuration.

[0015] As shown in FIG. 2(a), a sense amplifier 10 is connected to a pair of bit lines BLT and BLC, and a memory cell MC is connected to the bit line BLT. A node on the high-voltage power supply side of the sense amplifier 10 is connected to an operating voltage VBLH via a switch 11, and to an overdrive voltage VOD via a switch 12. A control unit 40 (described later) controls the on / off of the switches 11 and 12, thereby connecting the node on the high-voltage power supply side of the sense amplifier 10 to the operating voltage VBLH or the overdrive voltage VOD. A node on the low-voltage power supply side of the sense amplifier 10 is connected to a ground voltage VSS. Note that FIG. 2(a) shows an example in which each of the switches 11 and 12 is configured as an N-channel field effect transistor (nMOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)), but each of the switches 11 and 12 may be configured as another circuit, etc.

[0016] As shown in FIG. 2B, the semiconductor memory device according to this embodiment includes a plurality of banks 20 (two in this example), a first voltage supply unit 30, and a control unit 40. Each of the banks 20 includes at least one memory cell MC and at least one sense amplifier 10. That is, each of the banks 20 includes at least one of the configurations shown in FIG. 2A. The first voltage supply unit 30 is connected to each of the banks 20 via a node VOD_BK01, and is configured to supply an overdrive voltage VOD higher than the operating voltage VBLH of the sense amplifier 10 to each of the banks 20 when amplifying the voltages of a pair of bit lines BLT and BLC connected to the sense amplifier 10 of each of the banks 20. The first voltage supply unit 30 may be configured to generate the overdrive voltage VOD based on an externally supplied power supply.

[0017] The control unit 40 controls the supply of a charging voltage for charging the overdrive voltage VOD so that when an amplification operation is performed in any of the multiple banks 20, the overdrive voltage VOD is supplied to the sense amplifier 10 of any of the banks 20 without being voltage-dropped.

[0018] Furthermore, the control unit 40 may be configured to stop supplying the charging voltage when an amplification operation is started in any of the banks 20. This makes it possible to prevent the charging voltage from being consumed when an amplification operation is started in any of the banks 20 (i.e., when the overdrive voltage VOD is supplied to the sense amplifier 10 of any of the banks 20).

[0019] Furthermore, the control unit 40 may be configured to start supplying a charging voltage when the voltage of the bit line BLT reaches substantially the same voltage as the operating voltage VBLH of the sense amplifier 10 during the amplification operation. Here, "substantially the same voltage" does not necessarily mean that the voltage of the bit line BLT and the operating voltage VBLH are exactly the same, but may also include, for example, a state in which the difference between the voltage of the bit line BLT and the operating voltage VBLH is small enough that the voltage of the bit line BLT and the operating voltage VBLH can be considered to be equal. This allows the control unit 40 to supply a charging voltage to the reduced overdrive voltage VOD when the voltage of the bit line BLT reaches substantially the same voltage as the operating voltage VBLH of the sense amplifier 10 (i.e., when the supply of the overdrive voltage VOD to the sense amplifier 10 of one of the banks 20 is stopped).

[0020] Furthermore, when an amplification operation is performed in a bank 20 other than the bank 20 after an amplification operation is performed in the bank 20, the control unit 40 may be configured to supply a charging voltage so that the overdrive voltage VOD is restored to a state in which there is almost no voltage drop by the time the amplification operation is started in the other bank 20. Here, the "state in which there is almost no voltage drop in the overdrive voltage VOD" is not limited to a state in which there is no voltage drop in the overdrive voltage VOD at all, but may also include, for example, a state in which the overdrive voltage VOD is dropped by a sufficiently small voltage value from the voltage value when there is no voltage drop at all (i.e., a state in which the value can be considered to be the same as the value of the overdrive voltage VOD when there is no voltage drop). In this way, when an amplification operation is started in the other bank 20, an overdrive voltage VOD with almost no voltage drop can be supplied to the sense amplifier 10 of the other bank 20.

[0021] As shown in FIG. 2B, the control unit 40 includes a switch 41 for controlling the supply of a charging voltage and a circuit (here, a capacitor 42) for charging the overdrive voltage VOD. The switch 41 is provided between a node VOD_BK01 and the capacitor 42. The switch 41 includes an nMOSFET and is configured to connect the capacitor 42 to the node VOD_BK01 (i.e., supply the charging voltage charged to the capacitor 42) when a high-level signal EN_VODR is input to the gate terminal of the nMOSFET. The capacitance of the capacitor 42 may be set so that the charging voltage charged to the capacitor 42 is higher than the overdrive voltage VOD. While the present embodiment describes an example in which the switch 41 includes an nMOSFET, the switch 41 may include, for example, a P-channel field-effect transistor (pMOSFET) or a switch circuit other than a MOSFET. While the present embodiment describes an example in which the circuit for charging the overdrive voltage VOD includes the capacitor 42, the circuit may have other configurations.

[0022] 3, an example of the operation of the control unit 40 when operating each of the sense amplifiers 10 of multiple banks 20 will be described. Note that here, a case where data stored in the memory cells MC of each bank 20 is read will be described. First, in the standby state, the voltages of the pairs of bit lines BLT(BK0), BLC(BK0), BLT(BK1), and BLC(BK1) connected to each of the sense amplifiers 10 of each bank (bank 0, bank 1) 20 are set to an equalizer voltage VBLEQ. Here, the height of the equalizer voltage VBLEQ may be, for example, half the operating voltage VBLH.

[0023] At time t11, data stored in any memory cell MC in bank 0 (BK0) is sent to the bit line BLT (BK0) connected to that memory cell MC, causing a slight change in the voltage level of that bit line BLT (BK0). Also, between time t11 and time t12, data stored in any memory cell MC in bank 1 (BK1) is sent to the bit line BLT (BK1) connected to that memory cell MC, causing a slight change in the voltage level of that bit line BLT (BK1).

[0024] Next, at time t12, when the amplification operation of the bit line voltage of bank 0 (BK0) begins, the control unit 40 stops supplying the charging voltage charged in the capacitor 42 to the overdrive voltage VOD. Specifically, the control unit 40 turns off the switch 41 by inputting a low-level signal EN_VODR to the gate terminal of the nMOSFET of the switch 41. This cuts off the connection between the capacitor 42 and the node VOD_BK01, and stops charging the overdrive voltage VOD. The control unit 40 also turns on the switch 12 connected to the sense amplifier 10, which amplifies the bit line voltage (i.e., inputs a high-level signal to the gate terminal of the nMOSFET of the switch 12). This causes the overdrive voltage VOD to be supplied from the first voltage supply unit 30 to the sense amplifier 10.

[0025] Next, at time t13, when the voltage levels of the pair of bit lines BLT (BK0), BLC (BK0) of bank 0 (BK0) are amplified to voltages substantially equal to the operating voltage VBLH and the ground voltage VSS, the control unit 40 starts supplying the charging voltage. Note that the timing at which the voltage levels of the pair of bit lines BLT (BK0), BLC (BK0) of bank 0 (BK0) are amplified to voltages substantially equal to the operating voltage VBLH and the ground voltage VSS may be determined, for example, by measurement in advance, or may be determined by a predetermined voltage detection circuit (not shown) detecting that the voltage levels of the pair of bit lines BLT (BK0), BLC (BK0) have reached voltages substantially equal to the operating voltage VBLH and the ground voltage VSS.

[0026] Here, the control unit 40 turns on the switch 41 by inputting a high-level signal EN_VODR to the gate terminal of the nMOSFET of the switch 41. This connects the capacitor 42 to the node VOD_BK01, and charging of the overdrive voltage VOD begins. The control unit 40 also turns off the switch 12 connected to the sense amplifier 10 that amplifies the voltage of the bit line (i.e., inputs a low-level signal to the gate terminal of the nMOSFET of the switch 12), and turns on the switch 11 connected to the sense amplifier 10 (i.e., inputs a high-level signal to the gate terminal of the nMOSFET of the switch 11). This stops the supply of the overdrive voltage VOD from the first voltage supply unit 30 to the sense amplifier 10, and the operating voltage VBLH is supplied to the sense amplifier 10. Furthermore, the voltage of the node VOD_BK01 (overdrive voltage VOD) rises as a result of the supply of the charging voltage.

[0027] Next, when the voltage of node VOD_BK01 (overdrive voltage VOD) recovers to approximately its initial state (no voltage drop), the control unit 40 stops supplying the charging voltage to the overdrive voltage VOD. Note that the timing at which the voltage of node VOD_BK01 recovers to approximately its initial state may be determined, for example, by measurement in advance, or may be determined by a predetermined voltage detection circuit (not shown) detecting that the voltage of node VOD_BK01 has recovered to approximately its initial state. In this way, when an amplification operation is performed in bank 1 (BK1) after an amplification operation is performed in bank 0 (BK0), the charging voltage is supplied so that the overdrive voltage VOD recovers to a state with almost no voltage drop by the time the amplification operation is started in bank 1 (BK1).

[0028] Then, at time t14, when the amplification operation of the voltage of the bit line of bank 1 (BK1) starts, the control unit 40 stops supplying the charging voltage charged in the capacitor 42 to the overdrive voltage VOD, similar to the operation at time t12. The control unit 40 also supplies the overdrive voltage VOD from the first voltage supply unit 30 to the sense amplifier 10 of bank 1 (BK1). At this time, the overdrive voltage VOD has already recovered to almost its initial state (a state in which no voltage drop has occurred), so when the amplification operation is performed in the sense amplifier 10 of bank 1 (BK1), the overdrive voltage VOD is supplied to the sense amplifier 10 of bank 1 (BK1) without being voltage-dropped.

[0029] 3, the timing at which the voltage of the node VOD_BK01 (overdrive voltage VOD) recovers to approximately its initial state (no voltage drop) and the timing at which the amplification operation of the voltage of the bit line of bank 1 (BK1) starts occur simultaneously. Here, the control unit 40 may, for example, perform control to wait for the start of the amplification operation of the voltage of the bit line of bank 1 (BK1) so that the amplification operation of the voltage of the bit line of bank 1 (BK1) starts after the voltage of the node VOD_BK01 (overdrive voltage VOD) recovers to approximately its initial state (no voltage drop). This makes it possible to reliably supply the overdrive voltage VOD to the sense amplifier 10 of bank 1 (BK1) in a state where the voltage is not dropped.

[0030] At time t15, when the voltage levels of the pair of bit lines BLT (BK1) and BLC (BK1) in bank 1 (BK1) are amplified to a voltage approximately equal to the operating voltage VBLH and the ground voltage VSS, the control unit 40 starts supplying a charging voltage, similar to the operation at time t13.

[0031] In this way, when an amplification operation is performed in any of the banks 20, it is possible to supply the overdrive voltage VOD that has not been voltage-dropped to the sense amplifiers 10 of the relevant bank 20.

[0032] As described above, according to the semiconductor memory device and the control method thereof of this embodiment, when an amplification operation is performed in any of the banks 20, the overdrive voltage VOD that has not been voltage-dropped can be supplied to the sense amplifier 10 of that bank 20. Therefore, compared to when a voltage-dropped overdrive voltage VOD is supplied to the sense amplifier 10 of that bank 20, the amplification operation in that bank 20 can be performed at a higher speed, and ultimately, the operation of the sense amplifier 10 of that bank 20 can be performed at a higher speed. As a result, even when the overdrive voltage VOD is shared among multiple banks 20, the sense amplifier 10 of each bank 20 can be operated at a higher speed.

[0033] In the above-described embodiment, the case where the amplification operation of the bit line voltage of bank 1 (BK1) is started after the amplification operation of the bit line voltage of bank 0 (BK0) is started has been described as an example, but the present invention is not limited to this case. For example, as shown in FIG. 4, the amplification operation of the bit line voltages of multiple banks 20 (bank 0, bank 1) may be performed simultaneously. In this case, the control unit 40 may be configured to always supply the charging voltage (i.e., always set the signal EN_VODR to a high level) when the amplification operation is performed simultaneously in at least two of the multiple banks 20. This ensures that the charging voltage is always supplied to the overdrive voltage VOD, thereby reducing the amount of drop in the overdrive voltage VOD caused by the simultaneous amplification operation of the bit line voltages of multiple banks 20 (bank 0, bank 1).

[0034] The operation of the control unit 40 at times t21, t22, and t23 in FIG. 4 may be the same as the operation at times t11, t12, and t13 described above, except that the voltage amplification operation of the bit lines of multiple banks 20 (bank 0, bank 1) is performed simultaneously, and the signal EN_VODR is always set to a high level.

[0035] In the above-described embodiment, the control unit 40 includes one switch 41 and one capacitor 42. However, the present invention is not limited to this. For example, as shown in FIG. 5, the control unit 40 may include the same number of control units (first control unit 40a and second control unit 40b in the illustrated example) as the number of banks 20, and each of the control units 40a and 40b may include one switch 41a and 41b and one capacitor 42a and 42b. Here, each of the control units 40a and 40b may be associated with one of the multiple banks 20. For example, the control unit 40a may be associated with bank 0 (BK0), and the control unit 40b may be associated with bank 1 (BK1).

[0036] The charging voltages charged to the capacitors 42a, 42b may be different from each other. This makes it possible to associate different charging voltages with each of the multiple banks 20. Furthermore, since it is considered that the amount of drop in the overdrive voltage VOD during amplification in any of the banks 20 increases as the position of that bank 20 becomes farther from the first voltage supply unit 30, the charging voltages charged to the capacitors 42a, 42b may be set to increase as the position of the corresponding bank 20 becomes farther from the first voltage supply unit 30.

[0037] Furthermore, the control unit 40 may be configured to supply a charging voltage corresponding to one of the banks 20 when an amplification operation is performed in the bank 20. This makes it possible to charge the charging voltage corresponding to the bank 20 in which the amplification operation is performed to the overdrive voltage VOD. Here, when an amplification operation is performed in bank 0 (BK0), the first control unit 40a of the control unit 40 may supply the charging voltage of the capacitor 42a to the overdrive voltage VOD by inputting a high-level signal EN_A to the gate terminal of the nMOSFET of the switch 41a. Furthermore, when the overdrive voltage VOD has recovered to a state in which there is almost no voltage drop, the first control unit 40a of the control unit 40 may stop supplying the charging voltage by inputting a low-level signal EN_A to the gate terminal of the nMOSFET of the switch 41a. Furthermore, when an amplification operation is performed in bank 1 (BK1), the second control unit 40b of the control unit 40 may supply the charging voltage of capacitor 42b as the overdrive voltage VOD by inputting a high-level signal EN_B to the gate terminal of the nMOSFET of switch 41b. Furthermore, when the overdrive voltage VOD has returned to a state where there is almost no voltage drop, the second control unit 40b of the control unit 40 may stop the supply of the charging voltage by inputting a low-level signal EN_B to the gate terminal of the nMOSFET of switch 41b.

[0038] Fig. 6 shows an example configuration of a control unit 40 according to another modification of the present invention. As shown in Fig. 6, the control unit 40 may include a second voltage supply unit 43. Here, the second voltage supply unit 43 may be configured to charge a plurality of different charging voltages to the capacitor 42. Furthermore, each of the plurality of different charging voltages may be associated with one of the plurality of banks 20, as in the modification shown in Fig. 5. For example, the charging voltage charged to the capacitor 42 may be set to be higher as the position of the bank 20 corresponding to the charging voltage is farther from the first voltage supply unit 30.

[0039] In this modification, the control unit 40 is configured to supply one of a plurality of charging voltages to the overdrive voltage VOD. This makes it possible to charge the overdrive voltage VOD using different charging voltages. For example, when an amplification operation is performed in bank 0 (BK0), the control unit 40 may supply the charging voltage associated with bank 0 (BK0) from the second voltage supply unit 43 to the capacitor 42, and when an amplification operation is performed in bank 1 (BK1), the control unit 40 may supply the charging voltage associated with bank 1 (BK1) from the second voltage supply unit 43 to the capacitor 42.

[0040] In the above-described embodiment and modified examples, the control unit 40 includes at least one switch 41, 41 a, 41 b and at least one capacitor 42, 42 a, 42 b. However, the present invention is not limited to this. For example, the control unit 40 may be configured with other circuits that provide the same effects as those of the above-described embodiment and modified examples. [Explanation of symbols]

[0041] 10...Sense amplifier 20...Bank 30...First voltage supply unit 40...Control unit 40a...First control section 40b...Second control section 41, 41a, 41b...Switch 42, 42a, 42b...Capacitors 43...Second voltage supply unit EN_A, EN_B, EN_VODR… signals VBLEQ: Equalizer voltage VBLH: Operating voltage VOD: Overdrive voltage VSS: Ground voltage

Claims

1. a plurality of banks each including at least one sense amplifier; a first voltage supply unit that supplies an overdrive voltage higher than an operating voltage of the sense amplifier to each of the plurality of banks when an amplification operation of a voltage of a bit line connected to the sense amplifier of each of the plurality of banks is performed; a control unit that controls supply of a charging voltage for charging the overdrive voltage so that the overdrive voltage is supplied to the sense amplifier of the bank without being dropped when the amplification operation is performed in the bank among the plurality of banks, Semiconductor memory device.

2. the control unit is configured to stop supplying the charging voltage when the amplifying operation is started in any one of the plurality of banks.

2. The semiconductor memory device according to claim 1.

3. the control unit is configured to start supplying the charging voltage when the voltage of the bit line reaches a voltage substantially equal to an operating voltage of the sense amplifier during the amplifying operation.

2. The semiconductor memory device according to claim 1.

4. the control unit is configured to supply the charging voltage when the amplification operation is performed in another bank other than the one of the banks after the amplification operation is performed in the one of the banks, so that the overdrive voltage is restored to a state in which there is almost no voltage drop until the amplification operation is started in the other bank.

2. The semiconductor memory device according to claim 1.

5. the control unit is configured to always supply the charging voltage when the amplifying operation is simultaneously performed in at least two banks among the plurality of banks.

2. The semiconductor memory device according to claim 1.

6. the control unit includes a circuit for charging the overdrive voltage; 2. The semiconductor memory device according to claim 1.

7. the circuit includes a capacitor for charging the overdrive voltage; 7. The semiconductor memory device according to claim 6.

8. The control unit includes a switch for controlling the supply of the charging voltage.

2. The semiconductor memory device according to claim 1.

9. The switch includes a MOS transistor.

9. The semiconductor memory device according to claim 8.

10. a different charging voltage is associated with each of the plurality of banks, the control unit is configured to supply the charging voltage corresponding to one of the banks when the amplifying operation is performed in the one of the plurality of banks.

2. The semiconductor memory device according to claim 1.

11. The control unit is configured to supply any one of a plurality of charging voltages.

2. The semiconductor memory device according to claim 1.

12. the control unit includes a second voltage supply unit that supplies the plurality of charging voltages.

12. The semiconductor memory device according to claim 11.

13. A method for controlling a semiconductor memory device, comprising: The semiconductor memory device comprises: a plurality of banks each including at least one sense amplifier; a first voltage supply unit that supplies an overdrive voltage higher than an operating voltage of the sense amplifier to each of the plurality of banks when an amplification operation of a voltage of a bit line connected to the sense amplifier of each of the plurality of banks is performed; a control unit, The control unit executing a step of controlling supply of a charging voltage for charging the overdrive voltage so that the overdrive voltage is supplied to the sense amplifier of the bank without being dropped when the amplification operation is performed in the bank among the plurality of banks; A method for controlling a semiconductor memory device.

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