Semiconductor device and manufacturing method therefor

Abstract

To reduce the on-resistance.SOLUTION: A semiconductor device includes: a first electrode; a semiconductor layer provided on the first electrode; a second electrode provided on the semiconductor layer; a control electrode provided in the semiconductor layer via an insulating region; a first conductive portion facing the control electrode along a second direction orthogonal to a first direction oriented from the first electrode to the second electrode, electrically connected to the second electrode, and having a first work function; a first semiconductor region of a first conductivity type, provided in the semiconductor layer, sandwiched between the insulating region and the first conductive portion, and forming a Schottky junction with the first conductive portion; a second semiconductor region of the first conductivity type, provided in the semiconductor layer, located on the first semiconductor region, and having a higher impurity concentration than the first semiconductor region; and a second conductive portion electrically connected to the second electrode, having a second work function different from the first work function, and forming an ohmic junction with the second semiconductor region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices having switching functions, such as metal oxide semiconductor field effect transistors (MOSFETs), are known. In such semiconductor devices, it is preferable that the on-resistance is low. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-132195 [Patent Document 2] Japanese Patent Publication No. 2022-22074 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device capable of reducing the on-resistance. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment comprises a first electrode, a semiconductor layer provided on the first electrode, a second electrode provided on the semiconductor layer, a control electrode provided in the semiconductor layer via an insulating region, a first conductive portion facing the control electrode along a second direction perpendicular to a first direction from the first electrode to the second electrode, electrically connected to the second electrode, and having a first work function, a first semiconductor region of a first conductivity type provided in the semiconductor layer, sandwiched between the insulating region and the first conductive portion, and forming a Schottky junction with the first conductive portion, a second semiconductor region of the first conductivity type provided in the semiconductor layer, located above the first semiconductor region, and having a higher impurity concentration than the first semiconductor region, and a second conductive portion electrically connected to the second electrode, having a second work function different from the first work function, and forming an ohmic junction with the second semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged view of an area A in FIG. [Figure 3A] 2A to 2C are cross-sectional views illustrating an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 3B] 3B is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment, following FIG. 3A. FIG. [Figure 3C] 3C is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment, following FIG. 3B. [Figure 3D] 3D is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment, following FIG. 3C. [Figure 3E] 3D, a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 3F] 3E and 3F are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor device according to a modified example of the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 6A] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a semiconductor device according to a second embodiment. [Figure 6B] 6B is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the second embodiment, following FIG. 6A. FIG. [Figure 6C] FIG. 6C is a cross-sectional view illustrating an example of a manufacturing process of the semiconductor device according to the second embodiment, following FIG. 6B. [Figure 7] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 8] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a semiconductor device according to a third embodiment. [Figure 9] FIG. 11 is a cross-sectional view of a semiconductor device according to a modified example of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] For ease of explanation, an XYZ Cartesian coordinate system is adopted as shown in Figures 1 to 3. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. In addition, in the Z-axis direction, the source electrode side is also referred to as "upper" and the drain electrode side is also referred to as "lower." However, these expressions are for convenience and are unrelated to the direction of gravity. The Z-axis direction is the first direction in the claims. The Y-axis direction is the second direction in the claims. The X-axis direction is the third direction in the claims.

[0009] In the following description, n is used to indicate the relative level of impurity concentration in each conductivity type. +, n, n - , and ,p + , p, p - In some cases, the notation n + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than p. When both p-type and n-type impurities are contained in each region, these notations represent the relative high and low net impurity concentrations after the impurities compensate for each other. n-type, n + Shape and n - The p-type is an example of the first conductivity type in the claims. + Shape and p - The n-type is an example of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. In other words, the first conductivity type may be the p-type.

[0010] The impurity concentration of a semiconductor region can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS), and the relative level of the impurity concentration can be determined from the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM).

[0011] Furthermore, dimensions such as the width of the contact portion can be measured by surface and / or cross-sectional analysis using, for example, a transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (EDX), or a scanning electron microscope (SEM).

[0012] The composition of the conductive portion can be analyzed by energy dispersive X-ray spectroscopy.

[0013] (First embodiment) A semiconductor device 1 according to a first embodiment will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view of the semiconductor device 1 according to the first embodiment. Figure 2 is an enlarged view of region A in Figure 1.

[0014] The semiconductor device 1 according to this embodiment is a vertical transistor. More specifically, the semiconductor device 1 is a vertical MOSFET that switches between an on state and an off state by controlling the potential of a gate electrode (a gate electrode 13 described later) to control the thickness of a Schottky barrier.

[0015] As shown in FIG. 1, the semiconductor device 1 includes a drain electrode (first electrode) 11, a semiconductor layer 2 provided on the drain electrode 11, and a source electrode (second electrode) 12 provided on the semiconductor layer 2.

[0016] The drain electrode 11 functions as a drain electrode of the semiconductor device 1. In this embodiment, the drain electrode 11 is electrically connected to a drain region 22 provided in the semiconductor layer 2. The drain electrode 11 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), or the like.

[0017] The semiconductor layer 2 is provided with various semiconductor regions, which will be described later. The semiconductor layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) is used as the n-type impurity, and for example, boron (B) is used as the p-type impurity. The semiconductor layer 2 may also be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0018] The source electrode 12 functions as a source electrode of the semiconductor device 1. In this embodiment, the source electrode 12 is electrically connected to the conductive portion 30 (third conductive portion) and a conductive portion 31 that is a part of the conductive portion 30. The source electrode 12 is also electrically connected to the conductive portion 40 via the conductive portion 30. The source electrode 12 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), or the like.

[0019] Although not shown, the source electrode 12 may be composed of multiple metal layers made of different materials. For example, the source electrode 12 may have a first metal layer made of titanium (Ti) and / or titanium nitride (TiN) provided on the conductive portion 30, a second metal layer made of tungsten (W) provided on the first metal layer, and a third metal layer made of aluminum (Al) provided on the second metal layer.

[0020] The semiconductor layer 2 will now be described in detail. As shown in Fig. 1, a drift region 21, a drain region 22, a thinned region (first semiconductor region) 23, a top region (second semiconductor region) 24, a gate electrode (control electrode) 13, an insulating region 50, and a conductive portion (first conductive portion) 31 are provided in the semiconductor layer 2. In addition, a conductive portion (second conductive portion) 40 is provided on the top region 24.

[0021] The drift region 21 functions as the drift region of the semiconductor device 1. The drift region 21 is disposed above the drain region 22 (above the drain electrode 11). The drift region 21 is, for example, an n - The n-type impurity concentration of the drift region 21 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The following is the result.

[0022] The drain region 22 functions as the drain region of the semiconductor device 1. The drain region 22 is disposed between the drift region 21 and the drain electrode 11. The drain region 22 is, for example, an n +The n-type impurity concentration of the drain region 22 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0023] The drain region 22 may not be provided. In this case, the drift region 21 is provided directly on the drain electrode 11, and the drain electrode 11 is electrically connected to the drift region 21. Alternatively, the drift region 21 may not be provided. In this case, for example, the drain region 22 is also provided at the position of the drift region 21.

[0024] The thinned region 23 is located at the upper end portion of the drift region 21 in the semiconductor layer 2 and has an impurity concentration similar to that of the drift region 21. - The thinned region 23 is a semiconductor region having a shape similar to that of the drift region 21. The thinned region 23 is sandwiched between the insulating region 50 and the conductive portion 31 and extends in the X-axis direction. The impurity concentration of the thinned region 23 may be different from that of the drift region 21.

[0025] The top region 24 is provided in the semiconductor layer 2 and is located above the thinned region 23. The top region 24 extends in the X-axis direction. The top region 24 has a higher impurity concentration than the thinned region 23. The top region 24 is, for example, an n + The top region 24 has an n-type impurity concentration of, for example, 8×10 19 cm -3 5x10 or more 20 cm -3 The following is the result.

[0026] 2, the top region 24 is illustrated as a region different from the thinned region 23, but the boundary between the top region 24 and the thinned region 23 may be unclear because the impurity concentration changes continuously. However, no second semiconductor type semiconductor region, such as a base region, is provided between the top region 24 and the thinned region 23.

[0027] The gate electrode 13 functions as the gate electrode of the semiconductor device 1. The gate electrode 13 is provided in the semiconductor layer 2 via an insulating region 50 and extends in the X-axis direction. The gate electrode 13 is made of, for example, polysilicon containing p-type or n-type impurities. The insulating region 50 is, for example, an insulating film containing silicon oxide or silicon nitride.

[0028] The conductive portion 31 is provided so as to extend from the upper surface of the semiconductor layer 2 to the drift region 21. More specifically, as shown in FIGS. 1 and 2, the conductive portion 31 is provided so that a portion thereof faces the gate electrode 13 along a direction (Y-axis direction) perpendicular to the thickness direction of the semiconductor layer 2. Here, "a portion of the conductive portion 31 facing the gate electrode 13" means that the lower end (tip) of the conductive portion 31 faces the gate electrode 13 along the Y-axis direction. Also, as shown in FIG. 2, the direction from the boundary surface (Schottky junction surface) 31a between the conductive portion 31 and the drift region 21 to the gate electrode 13 is along the Y-axis direction. The conductive portion 31 extends in the X-axis direction.

[0029] The conductive portion 31 is electrically connected to the source electrode 12. In this embodiment, as shown in Figures 1 and 2, a conductive portion 30 made of the same conductive material as the conductive portion 31 is provided between the upper surface of the semiconductor layer 2 and the source electrode 12, and the conductive portion 31 is electrically connected to the source electrode 12 via the conductive portion 30.

[0030] As shown in FIG. 2, the conductive portion 31 is provided so as to contact the upper surface of the drift region 21 and the side surface of the thinned region 23. The conductive portion 31 includes a first conductive material having a first work function and forms a Schottky junction with the drift region 21 and the thinned region 23. When the first conductivity type is n-type, the first conductive material is platinum (Pt), cobalt (Co), nickel (Ni), or the like. That is, when the first conductivity type is n-type, the conductive portion 31 includes at least one of platinum, cobalt, and nickel. In this embodiment, the conductive portion 31 is made of platinum.

[0031] A Schottky junction between the conductive portion 31 and the drift region 21 forms a Schottky barrier near the interface 31a between the conductive portion 31 and the drift region 21. A Schottky junction between the conductive portion 31 and the thinned region 23 forms a Schottky barrier near the interface 31b between the conductive portion 31 and the thinned region 23. If these Schottky barriers are thick, substantially no current flows from the drain electrode 11 to the source electrode 12, and the semiconductor device 1 is in an off state. Conversely, if at least one of the Schottky barriers is thin, a current such as a tunneling current flows from the drain electrode 11 to the source electrode 12, and the semiconductor device 1 is in an on state. By controlling the potential of the gate electrode 13, the thicknesses of the Schottky barriers formed near the interfaces 31a and 31b can be controlled, thereby switching the semiconductor device 1 between an on state and an off state.

[0032] The conductive portion 40 is provided on the top region 24 and is electrically connected to the source electrode 12. In this embodiment, the conductive portion 30 is provided between the conductive portion 40 and the source electrode 12, and the conductive portion 40 is electrically connected to the source electrode 12 via the conductive portion 30. The conductive portion 40 extends in the X-axis direction.

[0033] The conductive portion 40 includes a second conductive material having a second work function different from the first work function and forms an ohmic junction with the top region 24. When the first conductivity type is n-type, the second work function is lower than the first work function. When the first conductivity type is n-type, the second conductive material is titanium silicide (TiSi), titanium nitride (TiN), titanium (Ti), platinum silicide (PtSi), cobalt silicide (CoSi), nickel silicide (NiSi), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), or the like. That is, when the first conductivity type is n-type, the conductive portion 40 includes at least one of titanium silicide, titanium nitride, titanium, platinum silicide, cobalt silicide, nickel silicide, tantalum, tantalum nitride, and hafnium. In this embodiment, the conductive portion 40 is made of titanium silicide. Note that when the first conductivity type is p-type, the second work function is higher than the first work function.

[0034] As shown in FIG. 1 , the semiconductor device 1 may include a field plate electrode (FP electrode) 14 provided in the semiconductor layer 2 via an insulating region 50. In this embodiment, the FP electrode 14 is provided below the gate electrode 13 and extends in the X-axis direction. The FP electrode 14 is made of, for example, polysilicon containing p-type or n-type impurities. The FP electrode 14 is electrically insulated from the semiconductor layer 2 by the insulating region 50 and electrically connected to the source electrode 12. By providing such an FP electrode 14, when the semiconductor device 1 is in an off state, a depletion layer extends from the FP electrode 14 to the surrounding drift region 21 due to a voltage applied between the drain electrode 11 and the source electrode 12. This depletion layer connects to the depletion layer of the adjacent FP electrode 14, improving the breakdown voltage of the semiconductor device 1. The semiconductor device 1 may also include a field plate provided in the semiconductor layer 2 via an insulating region (not shown) separate from the insulating region 50. The FP electrode 14 may also be provided to extend in a direction other than the X-axis direction (e.g., the Y-axis direction).

[0035] As described above, the semiconductor device 1 according to the first embodiment includes a gate electrode 13 provided in the semiconductor layer 2 via an insulating region 50, a conductive portion 31 facing the gate electrode 13 along the Y-axis direction, electrically connected to the source electrode 12, and having a first work function, a thinned region 23 of a first conductivity type provided in the semiconductor layer 2, sandwiched between the insulating region 50 and the conductive portion 31, and forming a Schottky junction with the conductive portion 31, a top region 24 of the first conductivity type provided in the semiconductor layer 2, located above the thinned region 23, and having a higher impurity concentration than the thinned region 23, and a conductive portion 40 electrically connected to the source electrode 12, having a second work function different from the first work function, and forming an ohmic junction with the top region 24.

[0036] That is, in this embodiment, in the semiconductor device 1 that switches between the on state and the off state by controlling the potential of the gate electrode 13 to control the thickness of the Schottky barrier, a conductive portion 40 that forms an ohmic junction with the top region 24 is provided in addition to the conductive portion 31 that forms a Schottky junction with the drift region 21 and the thinned region 23. This allows current to flow between the drain and source through an ohmic junction that has a lower contact resistance than a Schottky junction when the semiconductor device 1 is in the on state, thereby reducing the on-resistance of the semiconductor device 1.

[0037] In addition, in this embodiment, the top region 24, which forms an ohmic junction with the conductive portion 40, has a higher impurity concentration than the thinned region 23. This reduces the contact resistance between the conductive portion 40 and the top region 24, thereby further reducing the on-resistance of the semiconductor device 1.

[0038] 2, the upper end of the top region 24 may protrude from the upper surface 50a of the insulating region 50, and the conductive portion 40 may be provided to surround the upper end of the top region 24. More specifically, the conductive portion 40 may have a first portion 41 provided on the gate electrode 13 side of the top region 24, a second portion 42 provided on the conductive portion 31 side of the top region 24, and a third portion 43 provided on the upper side of the top region 24. In the example of FIG. 2, the first portion 41 of the conductive portion 40 contacts the first side surface 24a of the top region 24 on the gate electrode 13 side, the second portion 42 of the conductive portion 40 contacts the second side surface 24b of the top region 24 on the conductive portion 31 side, and the third portion 43 of the conductive portion 40 contacts the upper surface 24c of the top region 24 that connects the first side surface 24a and the second side surface 24b. By arranging the conductive portion 40 so as to surround the upper end of the top region 24 in this manner, the area of ​​the ohmic junction formed between the conductive portion 40 and the top region 24 is increased, thereby further reducing the on-resistance of the semiconductor device 1.

[0039] 2, the insulating region 50 may have an upper surface 50a and a slope 50b. The slope 50b connects the upper surface 50a to the lower end 41a of the first portion 41 of the conductive portion 40. Due to the provision of such a slope 50b, the lower end 41a of the first portion 41 is located below the upper surface 50a of the insulating region 50. This increases the area of ​​the ohmic junction formed between the conductive portion 40 and the top region 24, thereby further reducing the on-resistance of the semiconductor device 1. Note that the lower end 41a of the first portion 41 of the conductive portion 40 may be located lower than in the example of FIG. 2, as long as it is located above the upper end of the gate electrode 13. This further reduces the on-resistance of the semiconductor device 1.

[0040] 2, as long as the lower end 42a of the second portion 42 of the conductive portion 40 is located above the upper end of the gate electrode 13. This increases the area of ​​the ohmic junction formed between the conductive portion 40 and the top region 24, thereby enabling the on-resistance of the semiconductor device 1 to be further reduced.

[0041] <Method of Manufacturing Semiconductor Device 1> Next, an example of a manufacturing method of the semiconductor device 1 according to this embodiment will be described with reference to Figures 3A to 3F. Figures 3A to 3F are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device according to the first embodiment, and are enlarged views of a portion corresponding to region A in Figure 1.

[0042] First, a semiconductor layer is prepared that includes a drift region (first semiconductor region) 21 and a gate electrode (control electrode) 13 provided in the drift region 21 via an insulating region 50. Such a semiconductor layer can be obtained, for example, as follows: First, a semiconductor substrate that includes the drift region 21 is prepared. Then, a gate trench is formed on the upper surface of the semiconductor substrate by reactive ion etching (RIE) or the like. Then, an insulating region is formed in the gate trench by thermal oxidation or the like. Then, a portion of the insulating region is removed by RIE or the like to form a trench in the insulating region. Then, a conductive material such as polysilicon is deposited in the trench in the insulating region by chemical vapor deposition (CVD) or the like, and the excess conductive material is etched back to form the gate electrode 13. Then, an insulating material is deposited to bury the gate electrode 13 and cover the upper surface of the semiconductor substrate other than the gate trench. Then, the upper surface of the insulating material is planarized by chemical mechanical polishing (CMP) or the like. This forms the insulating region 50.

[0043] 3A, contact trenches CT facing the gate electrodes 13 are formed in the drift region 21 by RIE or the like. The contact trenches CT are formed at intervals from the insulating region 50. This forms a thinned region (second semiconductor region) 23, which is a region of the drift region 21 sandwiched between the insulating region 50 and the contact trenches CT.

[0044] Next, as shown in FIG. 3B, a sacrificial film 60 is formed to fill the contact trenches CT. The sacrificial film 60 is made of an insulating material such as silicon nitride (SiN). Specifically, the sacrificial film 60 is formed as follows. First, an insulating material such as silicon nitride is deposited by sputtering or the like so as to fill the contact trenches CT and cover the upper surface of the insulating region 50. Then, the upper surface of the insulating material is planarized by CMP or the like. Then, the upper portion of the insulating material is etched back by wet etching or the like to expose the insulating region 50. Note that by changing the height of the upper end of the sacrificial film 60, the height of the lower end 42a of the second portion 42 of the conductive portion (first conductive portion) 40, which will be formed in a later process, can be changed (see FIG. 3E).

[0045] Next, as shown in FIG. 3C , the upper portion of the insulating region 50 is removed by wet etching or the like to expose the upper surface of the thinned region 23. In this embodiment, the insulating region 50 is further removed to form a slope 50b connecting the upper surface 50a and the thinned region 23. This exposes not only the upper surface of the thinned region 23 but also the side surface of the thinned region 23 on the gate electrode 13 side. Note that this process may be stopped at the stage where the upper surface of the thinned region 23 is exposed, and the slope 50b may not be formed.

[0046] Next, as shown in FIG. 3D , ions of a first conductivity type impurity are implanted into the top of the thinned region 23. When the first conductivity type is n-type, the impurity is, for example, arsenic. This forms a planned region 240 above the thinned region 23, which will become the top region 24 upon activation by a subsequent heat treatment. The ion implantation amorphizes at least a portion of the planned region 240, facilitating silicidation in a subsequent process. Because the portion of the top surface of the semiconductor layer other than the thinned region 23 is covered by the insulating region 50 or the sacrificial film 60, the ion implantation in this process may be performed over a range on the top surface of the semiconductor layer that is wider than the width of the thinned region 23. This facilitates the formation of the planned region 240. The third semiconductor region in the claims relating to the semiconductor device manufacturing method may be the planned region 240 or the top region 24 after activation by a heat treatment.

[0047] Next, as shown in FIG. 3E, a metal layer 70 is formed to bury the planned region 240. The metal layer 70 is, for example, titanium. Then, heat treatment is performed to activate the ions implanted into the planned region 240, thereby forming a top region 24 of the first conductivity type. At the same time, the planned region 240 is silicided near the interface with the metal layer 70, forming a conductive portion 40. The top region 24 is a semiconductor region of the first conductivity type having a higher impurity concentration than the drift region 21 and the thinned region 23. The conductive portion 40 has a first work function and forms an ohmic junction with the top region 24. The conductive portion 40 is, for example, titanium silicide. The heat treatment may be performed before and after forming the metal layer 70. That is, the step of forming the top region 24 by activation through heat treatment and the step of forming the conductive portion 40 by silicidation through heat treatment may be performed separately.

[0048] Next, as shown in FIG. 3F, the metal layer 70 is removed by wet etching or the like. Thereafter, the sacrificial film 60 is removed by wet etching or the like to expose the contact trench CT. Thereafter, a conductive portion (second conductive portion) 31 filling the contact trench CT is formed by sputtering or the like. The conductive portion 31 has a second work function different from the first work function and forms a Schottky junction with the drift region 21 and the thinned region 23. Thereafter, a conductive portion 30 covering the conductive portion 31 and the conductive portion 40 is formed by sputtering or the like. Note that the conductive portion 30 may be formed immediately after the conductive portion 31 is formed.

[0049] Thereafter, although not shown, n-type impurities are ion-implanted into the lower surface of the semiconductor layer and heat treatment is performed to form a drain region 22. Thereafter, a drain electrode 11 and a source electrode 12 are formed to sandwich the semiconductor layer. That is, the drain electrode 11 is formed on the lower surface of the semiconductor layer, and the source electrode 12 is formed on the conductive portion 30.

[0050] Through the above steps, the semiconductor device 1 is manufactured.

[0051] According to the manufacturing method of this embodiment, by forming the conductive portion 31 so as to fill the contact trench CT, a Schottky junction can be formed between the conductive portion 31 and the thinned region 23 even if the step coverage of the material of the conductive portion 31 is low.

[0052] (Modification of the first embodiment) <Semiconductor device 1A> Next, a semiconductor device 1A according to a modification of the first embodiment will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of the semiconductor device 1A according to the modification of the first embodiment, and is an enlarged view of a portion corresponding to region A in Fig. 1. One of the differences between this modification and the first embodiment is the presence of a connection region 25. Below, this modification will be described, focusing on the differences from the first embodiment.

[0053] As shown in FIG. 4, the semiconductor device 1A further includes a connection region 25 in addition to the configuration of the semiconductor device 1 according to the first embodiment. The connection region 25 is an n-type semiconductor region provided between the thinned region 23 and the top region 24. The impurity concentration of the connection region 25 is, for example, higher than the impurity concentration of the thinned region 23 and lower than the impurity concentration of the top region 24. The n-type impurity concentration of the connection region 25 is, for example, 3×10 17 cm -3 Over 2×10 19 cm -3 4, the top region 24 is illustrated as a region distinct from the connection region 25, but the boundary between the top region 24 and the connection region 25 may be unclear because the impurity concentration varies continuously. The same applies to the boundary between the connection region 25 and the thinned region 23.

[0054] Connection region 25 is formed by ion implanting n-type impurities from the top surface of the semiconductor substrate and then performing heat treatment, for example, before forming contact trench CT in the manufacturing process of semiconductor device 1. Top region 24 is formed by ion implanting n-type impurities into the top of connection region 25 and then performing heat treatment in a process similar to that shown in FIG.

[0055] According to this modification, the provision of connection region 25 can further increase the impurity concentration in top region 24. As a result, the contact resistance between conductive portion 40 and top region 24 can be further reduced, and the on-resistance of semiconductor device 1A can be further reduced.

[0056] (Second embodiment) <Semiconductor device 1B> A semiconductor device 1B according to a second embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view of the semiconductor device 1B according to the second embodiment. The semiconductor device 1B according to this embodiment includes a conductive portion 40A that is wider than the conductive portion 40 of the first embodiment. The following description of this embodiment will focus on the differences from the first embodiment.

[0057] As shown in FIG. 5, semiconductor device 1B includes conductive portion 40A that is wider than top region 24. That is, the length of conductive portion 40A in the Y direction is longer than the length of top region 24 in the Y direction. Note that, as shown in FIG. 5, conductive portion 40A may be wider than thinned region 23. Conductive portion 40A is provided in place of conductive portion 40 of semiconductor device 1 according to the first embodiment. In addition, in this embodiment, conductive portion 40A is provided so as to fill a groove defined by slope 50b and first side surface 24a of top region 24.

[0058] According to this embodiment, the resistance of the conductive portion 40A can be reduced by providing the conductive portion 40A that is wider than the top region 24. As a result, the on-resistance of the semiconductor device 1B can be further reduced.

[0059] <Method of Manufacturing Semiconductor Device 1B> A method for manufacturing the semiconductor device 1B according to the second embodiment will be described with reference to Figures 6A to 6C. Figures 6A to 6C are cross-sectional views for explaining an example of a manufacturing process for the semiconductor device according to the second embodiment, and are enlarged views of a portion corresponding to region A in Figure 1.

[0060] First, the manufacturing process of the semiconductor device 1 according to the first embodiment described above is performed up to the step of forming the planned region 240 described in FIG. 3D. In this embodiment, taking into consideration that impurities contained in the planned region 240 will diffuse due to heating in a later epitaxial growth step, the planned region 240 may be formed so as to be shallower than the planned region 240 of the first embodiment, i.e., so that the lower end of the planned region 240 in FIG. 3D is positioned higher. Such a shallow planned region 240 can be formed, for example, by pulse plasma lateral aligned doping (PLAD) using a plasma doping device.

[0061] 6A, a wide region WP wider than the planned region 240 is formed on the planned region 240 by selective epitaxial growth or the like. For example, the width of the planned region 240 is 50 nm, and the width of the wide region WP is 200 nm.

[0062] Next, as shown in FIG. 6B, a metal layer 70 is formed on the wide region WP. Thereafter, heat treatment is performed to activate the ions implanted in the planned region 240, thereby forming the top region 24. At the same time, the wide region WP is silicided, thereby forming a conductive portion (first conductive portion) 40A. The conductive portion 40A has a first work function and forms an ohmic junction with the top region 24.

[0063] Next, as shown in FIG. 6C, excess metal layer 70 is removed by wet etching or the like. Thereafter, sacrificial film 60 is removed by wet etching or the like to expose contact trench CT. Thereafter, a conductive portion (second conductive portion) 31 filling contact trench CT is formed by sputtering or the like. Thereafter, conductive portion 30 covering conductive portion 31 and conductive portion 40 is formed by sputtering or the like. Note that conductive portion 30 may be formed immediately after conductive portion 31 is formed.

[0064] The subsequent steps are the same as those in the first embodiment.

[0065] Through the above steps, the semiconductor device 1B is manufactured.

[0066] According to the manufacturing method of this embodiment, by forming the wide region WP, the silicon concentration in the conductive portion 40A is relatively reduced, which prevents the conductive portion 40A from becoming high in resistance, thereby preventing an increase in the on-resistance of the semiconductor device 1A.

[0067] When forming the wide region WP by selective epitaxial growth, a dopant gas containing impurities of the first conductivity type may be supplied. This prevents the impurity concentration in the top region 24 from decreasing due to the diffusion of impurities caused by heating during epitaxial growth. This further prevents the on-resistance of the semiconductor device 1A from increasing.

[0068] After the wide region WP is formed, ion implantation of an impurity of the first conductivity type may be further performed into the wide region WP, thereby making at least a portion of the wide region WP amorphous and promoting silicidation of the wide region WP.

[0069] (Third embodiment) <Semiconductor device 1C> A semiconductor device 1C according to a third embodiment will be described with reference to FIG. 7. FIG. 7 is a cross-sectional view of the semiconductor device 1C according to the third embodiment, and is an enlarged view of a portion corresponding to region A in FIG. 1. One of the differences between this embodiment and the second embodiment is the mode of electrical connection between the source electrode 12 and the conductive portion 40A. The following description of this embodiment will focus on the differences from the second embodiment.

[0070] 7, the conductive portion (second conductive portion) 40A of the semiconductor device 1C is in direct contact with the source electrode (second electrode) 12. That is, the conductive portion 40A is in contact with the source electrode 12 without the conductive portion (third conductive portion) 30A therebetween.

[0071] According to this embodiment, it is possible to prevent the conductive portion 30 having the first work function from affecting the electrical connection between the conductive portion 40A having the second work function and the source electrode 12.

[0072] <Method of Manufacturing Semiconductor Device 1C> A method for manufacturing the semiconductor device 1C according to the third embodiment will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view for explaining an example of a manufacturing process of the semiconductor device 1C according to the third embodiment, and is an enlarged view of a portion corresponding to region A in Fig. 1.

[0073] First, the manufacturing process of the semiconductor device 1B according to the second embodiment described above is carried out up to the step of forming the conductive portion (second conductive portion) 31 and the conductive portion (second conductive portion) 30.

[0074] 8, the upper portion of the conductive portion 30 is removed by etching or the like to expose the upper surface of the conductive portion (first conductive portion) 40A. As a result, the conductive portion 30A that is thinner than the conductive portion 30 is formed.

[0075] The subsequent steps are the same as those in the second embodiment. However, when forming the source electrode 12, the source electrode 12 is formed so as to cover the upper surface of the conductive portion 40A. In this way, the source electrode 12 is formed in direct contact with the conductive portion 40A.

[0076] Through the above steps, the semiconductor device 1C is manufactured.

[0077] (Modification of the third embodiment) <Semiconductor device 1D> A semiconductor device 1D according to a modification of the third embodiment will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view of the semiconductor device 1D according to a modification of the third embodiment, and is an enlarged view of a portion corresponding to region A in Fig. 1. In the third embodiment described above, the conductive portion 40A in the second embodiment is in direct contact with the source electrode 12. In contrast, the modification of the third embodiment corresponds to the case where the conductive portion 40 in the first embodiment is in direct contact with the source electrode 12.

[0078] As shown in FIG. 9, the conductive portion (second conductive portion) 40 of the semiconductor device 1D is in direct contact with the source electrode 12 without the conductive portion (third conductive portion) 30 therebetween.

[0079] This improves the degree of freedom in designing the semiconductor device 1D.

[0080] The semiconductor device 1D can be manufactured, for example, as follows. First, the manufacturing process of the semiconductor device 1 according to the first embodiment is performed up to the step of forming the conductive portion (second conductive portion) 31 and the conductive portion (second conductive portion) 30. Then, the upper portion of the conductive portion 30 is removed by etching or the like to expose the upper surface of the conductive portion (first conductive portion) 40. This forms the conductive portion 30A. The subsequent steps are the same as those in the third embodiment.

[0081] In the above-described embodiments and modifications, the gate electrode 13, the conductive portion (first conductive portion) 31, the thinned region (first semiconductor region) 23, the top region (second semiconductor region) 24, and the conductive portion (second conductive portion) 40, 40A all extend in the X-axis direction. That is, the embodiments and modifications have been described as examples applied to a case where trenches such as gate trenches and contact trenches are arranged in parallel to each other in a stripe shape. However, the present invention is not limited to this, and the embodiments and modifications can also be applied to a case where trenches are arranged in a mesh shape in which trenches intersect when viewed in the thickness direction from the top surface of the semiconductor layer 2, or to a case where trenches are arranged in a dot shape.

[0082] Although several embodiments of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These embodiments and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and examples and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents.

[0083] (Appendix 1) A first electrode; a semiconductor layer provided on the first electrode; a second electrode provided on the semiconductor layer; a control electrode provided in the semiconductor layer via an insulating region; a first conductive portion facing the control electrode along a second direction perpendicular to a first direction from the first electrode toward the second electrode, electrically connected to the second electrode, and having a first work function; a first semiconductor region of a first conductivity type provided in the semiconductor layer, sandwiched between the insulating region and the first conductive portion, and forming a Schottky junction with the first conductive portion; a second semiconductor region of the first conductivity type provided in the semiconductor layer, located above the first semiconductor region, and having a higher impurity concentration than the first semiconductor region; a second conductive portion electrically connected to the second electrode, having a second work function different from the first work function, and forming an ohmic junction with the second semiconductor region; A semiconductor device comprising: (Appendix 2) 2. The semiconductor device according to claim 1, wherein the second conductive portion is wider than the second semiconductor region. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the second conductive portion is in direct contact with the second electrode. (Appendix 4) 3. The semiconductor device according to claim 1, wherein a third conductive portion made of the same conductive material as the first conductive portion is provided between the second conductive portion and the second electrode. (Appendix 5) The second conductive portion is a first portion provided on the control electrode side of the second semiconductor region; a second portion provided on the first conductive portion side of the second semiconductor region; a third portion provided above the second semiconductor region; 5. The semiconductor device according to any one of claims 1 to 4, comprising: (Appendix 6) 6. The semiconductor device according to claim 5, wherein the insulating region has an upper surface and a slope connecting the upper surface and a lower end of the first portion of the second conductive portion. (Appendix 7) 7. The semiconductor device according to claim 5, wherein lower ends of the first portion and the second portion of the second conductive portion are located closer to the second electrode than an upper end of the control electrode. (Appendix 8) 9. The semiconductor device according to any one of claims 1 to 8, wherein the first conductive portion is in contact with a side surface of the first semiconductor region. (Appendix 9) The semiconductor device according to any one of appendices 1 to 8, wherein the control electrode, the first conductive portion, the first semiconductor region, the second semiconductor region, and the second conductive portion all extend in a third direction perpendicular to the first direction and the second direction. (Appendix 10) 10. The semiconductor device according to any one of appendices 1 to 9, wherein the first conductivity type is n-type, and the first work function is higher than the second work function. (Appendix 11) the first conductive portion includes at least one of platinum, cobalt, and nickel; 11. The semiconductor device of claim 10, wherein the second conductive portion includes at least one of titanium silicide, titanium nitride, titanium, platinum silicide, cobalt silicide, nickel silicide, tantalum, tantalum nitride, and hafnium. (Appendix 12) 12. The semiconductor device of claim 11, wherein the first conductive portion includes platinum and the second conductive portion includes titanium silicide. (Appendix 13) A semiconductor layer is provided, the semiconductor layer including a first semiconductor region of a first conductivity type and a control electrode provided in the first semiconductor region via an insulating region; forming a trench in the first semiconductor region facing the control electrode; forming a sacrificial film to fill the trench; forming a third semiconductor region of the first conductivity type provided on the second semiconductor region and having a higher impurity concentration than the first semiconductor region by ion-implanting an impurity of a first conductivity type into a second semiconductor region of the first semiconductor region sandwiched between the insulating region and the trench; forming a first conductive portion having a first work function and forming an ohmic junction with the third semiconductor region; removing the sacrificial film to expose the trench; forming a second conductive portion that fills the second trench, has a second work function different from the first work function, and forms a Schottky junction with the first semiconductor region; forming a first electrode and a second electrode to sandwich the semiconductor layer; A method for manufacturing a semiconductor device. (Appendix 14) 14. The method for manufacturing a semiconductor device described in Appendix 13, wherein the first conductive portion is formed by forming the third semiconductor region, forming a metal layer on the third semiconductor region, and performing heat treatment. (Appendix 15) After forming the third semiconductor region, and before forming the first conductive portion, an upper portion of the third semiconductor region is epitaxially grown to form a wide region having a width wider than that of the third semiconductor region; 14. The method for manufacturing a semiconductor device according to claim 13, wherein the first conductive portion is formed by forming a metal layer on the wide region and performing a heat treatment. (Appendix 16) After forming the second conductive portion, and before forming the second electrode, removing a portion of the second conductive portion to expose the first conductive portion; 16. The method for manufacturing a semiconductor device according to any one of claims 13 to 15, wherein the second electrode is formed so as to cover the exposed first conductive portion. (Appendix 17) 17. The method for manufacturing a semiconductor device according to any one of appendices 13 to 16, wherein after forming the sacrificial film and before forming the third semiconductor region, an upper portion of the insulating region is removed to expose the control electrode side of the semiconductor region of the first semiconductor region that is sandwiched between the insulating region and the trench. [Explanation of symbols]

[0084] 1, 1A, 1B, 1C, 1D Semiconductor device 11 Drain electrode 12 Source electrode 13 Gate electrode 14 FP electrode 2. Semiconductor layer 21 Drift Region 22 Drain region 23 Thinning area 24 Top area 25 Connection Area 30,30A conductive part 31 Conductive part 31a Boundary surface 40,40A conductive part 41 Part 1 42 Part 2 43 Part 3 50 Insulation Area WP wide area

Claims

1. A first electrode; a semiconductor layer provided on the first electrode; a second electrode provided on the semiconductor layer; a control electrode provided in the semiconductor layer via an insulating region; a first conductive portion facing the control electrode along a second direction perpendicular to a first direction from the first electrode toward the second electrode, electrically connected to the second electrode, and having a first work function; a first semiconductor region of a first conductivity type provided in the semiconductor layer, sandwiched between the insulating region and the first conductive portion, and forming a Schottky junction with the first conductive portion; a second semiconductor region of the first conductivity type provided in the semiconductor layer, located above the first semiconductor region, and having a higher impurity concentration than the first semiconductor region; a second conductive portion electrically connected to the second electrode, having a second work function different from the first work function, and forming an ohmic junction with the second semiconductor region; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the second conductive portion is wider than the second semiconductor region.

3. The semiconductor device according to claim 1 , wherein the second conductive portion is in direct contact with the second electrode.

4. 2. The semiconductor device according to claim 1, wherein a third conductive portion made of the same conductive material as said first conductive portion is provided between said second conductive portion and said second electrode.

5. The second conductive portion is a first portion provided on the control electrode side of the second semiconductor region; a second portion provided on the first conductive portion side of the second semiconductor region; a third portion provided above the second semiconductor region; The semiconductor device according to claim 1 , comprising:

6. 6. The semiconductor device according to claim 5, wherein said insulating region has an upper surface and a slope connecting said upper surface to a lower end of said first portion of said second conductive portion.

7. The semiconductor device according to claim 1 , wherein the first conductive portion is in contact with a side surface of the first semiconductor region.

8. 8. The semiconductor device according to claim 1, wherein the first conductivity type is n-type, and the first work function is higher than the second work function.

9. the first conductive portion includes at least one of platinum, cobalt, and nickel; 9. The semiconductor device according to claim 8, wherein said second conductive portion includes at least one of titanium silicide, titanium nitride, titanium, platinum silicide, cobalt silicide, nickel silicide, tantalum, tantalum nitride, and hafnium.

10. 10. The semiconductor device according to claim 9, wherein said first conductive portion includes platinum and said second conductive portion includes titanium silicide.

11. A semiconductor layer is provided, the semiconductor layer including a first semiconductor region of a first conductivity type and a control electrode provided in the first semiconductor region via an insulating region; forming a trench in the first semiconductor region facing the control electrode; forming a sacrificial film to fill the trench; forming a third semiconductor region of the first conductivity type provided on the second semiconductor region and having a higher impurity concentration than the first semiconductor region by ion-implanting an impurity of a first conductivity type into a second semiconductor region of the first semiconductor region sandwiched between the insulating region and the trench; forming a first conductive portion having a first work function and forming an ohmic junction with the third semiconductor region; removing the sacrificial film to expose the trench; forming a second conductive portion filling the trench, having a second work function different from the first work function, and forming a Schottky junction with the second semiconductor region; forming a first electrode and a second electrode to sandwich the semiconductor layer; A method for manufacturing a semiconductor device.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein the first conductive portion is formed by forming a metal layer on the third semiconductor region and performing a heat treatment after forming the third semiconductor region.

13. After forming the third semiconductor region, and before forming the first conductive portion, an upper portion of the third semiconductor region is epitaxially grown to form a wide region having a width wider than that of the third semiconductor region; The method for manufacturing a semiconductor device according to claim 11 , wherein the first conductive portion is formed by forming a metal layer on the wide region and performing a heat treatment.

14. After forming the second conductive portion, and before forming the second electrode, removing a portion of the second conductive portion to expose the first conductive portion; 14. The method for manufacturing a semiconductor device according to claim 11, wherein the second electrode is formed so as to cover the exposed first conductive portion.

Images