Semiconductor device and method of manufacturing the same

Abstract

To improve the performance of a semiconductor device.SOLUTION: An n-type impurity region NEP is formed in a semiconductor substrate. A p-type well region PW1 and an n-type collector region (NC) are formed in the impurity region NEP. An n-type emitter region NE and a p-type base region PB are formed in the well region PW1. When a distance from a first junction surface JC1 to a second junction surface JC2 is Wb1, an impurity concentration of a part of the well region PW1 located under the junction surface JC1 is Na1, a distance from a junction surface JC3 to the base region PB is Wb2, and an impurity concentration of a part of the well region PW1 located between the junction surface JC3 and the base region PB is Na2, the relationship (Na1×Wb1)≤(Na2×Wb2) is satisfied.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Bipolar transistors or MISFETs (Metal Insulator Semiconductor Field Effect Transistors) are used in analog circuits and the like included in semiconductor devices. For example, Patent Document 1 discloses an NPN bipolar transistor. In Patent Document 1, an n-type well region is formed in a semiconductor substrate, and a p-type well region is formed in the n-type well region. A p-type base region and an n-type emitter region are formed in the p-type well region. Furthermore, an n-type collector region is formed in the n-type well region at a location separated from the p-type well region in a plan view.

[0003] The n-type well region and n-type collector region function as the collector of the bipolar transistor, the p-type well region and p-type base region function as the base of the bipolar transistor, and the n-type emitter region function as the emitter of the bipolar transistor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-96154 Summary of the Invention [Problem to be solved by the invention]

[0005] In the bipolar transistor described above, the concentration of the shallow portion of the p-type well region located near the upper surface of the semiconductor substrate may be reduced, and the concentration of the deep portion of the p-type well region located below the shallow portion may be increased. This makes it easier to prevent punch-through and ensure the breakdown voltage between the collector and the base.

[0006] However, due to the decrease in the concentration in the shallow part of the p-type well region, the base current I B is likely to increase, so the current amplification factor h FE (=I C / I B ) is likely to decrease, which may result in a decrease in the performance of the bipolar transistor and a decrease in the performance of the semiconductor device.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] In one embodiment, a semiconductor device includes a semiconductor substrate, a first impurity region of a first conductivity type formed in the semiconductor substrate, a first well region of a second conductivity type formed in the first impurity region, an emitter region of the first conductivity type formed in the first well region, a base region of the second conductivity type formed in the first well region, and a collector region of the first conductivity type formed in the first impurity region. Let Wb1 be the distance from a first junction between a lower surface of the emitter region and the first well region to a second junction between the lower surface of the first well region and the first impurity region, Na1 be the impurity concentration of a portion of the first well region located below the first junction, Wb2 be the distance from a third junction between a side surface of the emitter region and the first well region to the base region, and Na2 be the impurity concentration of a portion of the first well region located between the third junction and the base region. The relationship (Na1×Wb1)≦(Na2×Wb2) is satisfied.

[0009] In one embodiment, a method for manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate including a first impurity region of a first conductivity type; forming a first well region of a second conductivity type in the first impurity region; forming a base region of the second conductivity type in the first well region; and forming an emitter region of the first conductivity type in the first well region and a collector region of the first conductivity type in the first impurity region. Let Wb1 be the distance from a first junction between a lower surface of the emitter region and the first well region to a second junction between the lower surface of the first well region and the first impurity region, Na1 be the impurity concentration of a portion of the first well region located below the first junction, Wb2 be the distance from a third junction between a side surface of the emitter region and the first well region to the base region, and Na2 be the impurity concentration of a portion of the first well region located between the third junction and the base region. The relationship (Na1×Wb1)≦(Na2×Wb2) is satisfied. [Effects of the Invention]

[0010] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a diagram showing an impurity profile of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is an equivalent circuit diagram showing the current mirror circuit according to the first embodiment. [Figure 5] FIG. 5 is an enlarged cross-sectional view of a main part of a bipolar transistor in the study example. [Figure 6] FIG. 6 is an enlarged cross-sectional view of a main part of the bipolar transistor according to the first embodiment. [Figure 7]FIG. 7 is an explanatory diagram for explaining main features of the bipolar transistor according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing data obtained from an experiment conducted by the inventors of the present invention. [Figure 9] FIG. 9 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 12] 12A to 12C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 13] 13A to 13C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 14] 14A to 14C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 15] 15A to 15C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 16] 16A to 16C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 17] FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 18] FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 19] FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 20] FIG. 20 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 21] FIG. 21 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 22] FIG. 22 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 23] 23A to 23C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to that shown in FIG. [Figure 24]FIG. 24 is an enlarged cross-sectional view of a main part of a bipolar transistor according to the first modification. [Figure 25] FIG. 25 is an enlarged cross-sectional view of a main part of a bipolar transistor according to the second modification. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, depth, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that a surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) <Bipolar transistor structure> The semiconductor device according to the first embodiment includes an NPN bipolar transistor BJT. The structure of the bipolar transistor BJT will be described below with reference to Figures 1 and 2. Figure 1 is a plan view showing the bipolar transistor BJT. Figure 2 is a cross-sectional view taken along line AA in Figure 1.

[0015] As shown in Figures 1 and 2, the bipolar transistor BJT includes an n-type impurity region NEP, an n-type well region (impurity region) NW1, an n-type collector region (impurity region) NC, a p-type well region (impurity region) PW1, a p-type base region (impurity region) PB, and an n-type emitter region (impurity region) NE.

[0016] The impurity region NEP, well region NW1, and collector region NC function as the collector of the bipolar transistor BJT, the well region PW1 and base region PB function as the base of the bipolar transistor BJT, and the emitter region NE function as the emitter of the bipolar transistor BJT.

[0017] As shown in FIG. 1, the well region PW1 and the well region NW1 are separated from each other in a plan view and are surrounded by the impurity region NEP in a plan view. The emitter region NE, the base region PB, and the collector region NC are separated from each other in a plan view. The emitter region NE and the base region PB are surrounded by the well region PW1 in a plan view. The collector region NC is surrounded by the well region NW1 in a plan view. In FIG. 1, the well region PW1 is formed inside the dashed line, and the well region NW1 is formed outside the dashed line.

[0018] As shown in FIG. 2, the semiconductor device includes a semiconductor substrate SUB. An impurity region NEP is formed in the semiconductor substrate SUB. The semiconductor substrate SUB of the first embodiment includes, for example, a support substrate SS made of a p-type silicon substrate, and an n-type impurity region NEP formed on the support substrate SS. The impurity region NEP is an n-type silicon layer formed on the support substrate SS by epitaxial growth. An n-type buried region (impurity region) NBL is formed across the support substrate SS and the silicon layer.

[0019] The semiconductor substrate SUB having a stacked structure including the support substrate SS and the silicon layer is an example, and the semiconductor substrate SUB may be a single-layer p-type silicon substrate. In this case, the impurity region NEP and the buried region NBL are formed in the p-type silicon substrate.

[0020] The semiconductor substrate SUB has an upper surface TS and a lower surface BS. The impurity region NEP is formed to a predetermined depth from the upper surface TS of the semiconductor substrate SUB. A well region PW1 and a well region NW1 are formed in the impurity region NEP. The well region PW1 and the well region NW1 are each formed from the upper surface TS of the semiconductor substrate SUB to a position shallower than the depth of the impurity region NEP.

[0021] A base region PB and an emitter region NE are formed in the well region PW1. A collector region NC is formed in the well region NW1. The emitter region NE, the base region PB, and the collector region NC are each disposed on the upper surface TS of the semiconductor substrate SUB. Specifically, the emitter region NE, the base region PB, and the collector region NC are each formed from the upper surface TS of the semiconductor substrate SUB to a position shallower than the depth of the well region PW1 and the depth of the well region NW1.

[0022] The base region PB has a higher impurity concentration than the well region PW1. The well region NW1 has a higher impurity concentration than the impurity region NEP. The emitter region NE and the collector region NC have higher impurity concentrations than the impurity concentration of the well region NW1.

[0023] Although the collector region NC is formed in the well region NW1, if the well region NW1 is not formed, the collector region NC may be formed in the impurity region NEP.

[0024] Also, an element isolation portion STI is formed in the semiconductor substrate SUB. The element isolation portion STI includes a trench formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB, and an insulating film buried inside the trench. The insulating film is, for example, a silicon oxide film.

[0025] In the bipolar transistor BJT, an element isolation portion STI is formed in a portion of the semiconductor substrate SUB located between the base region PB and the collector region NC (between the well region PW1 and the well region NW1). Note that an insulating film such as the element isolation portion STI is not formed in a portion of the well region PW1 located between the emitter region NE and the base region PB. In other words, the emitter region NE and the base region PB are arranged so that no insulating film is formed between the emitter region NE and the base region PB.

[0026] An insulating film IF1 is selectively formed on a portion of the upper surface TS of the semiconductor substrate SUB. The insulating film IF1 is formed on a portion of the emitter region NE, on the well region PW1, and on a portion of the base region PB so as to cover the boundary between the emitter region NE and the well region PW1 and also to cover the boundary between the well region PW1 and the base region PB. The insulating film IF1 is, for example, a silicon oxide film.

[0027] A silicide film SI is formed on an upper surface TS of the semiconductor substrate SUB that is not covered with the insulating film IF1. That is, the silicide film SI is formed on the base region PB, the emitter region NE, and the collector region NC that are exposed from the insulating film IF1 and the element isolation part STI. The silicide film SI is, for example, a cobalt silicide (CoSi2) film, a nickel silicide (NiSi) film, or a nickel platinum silicide (NiPtSi) film.

[0028] 3 is a diagram showing an impurity profile of the semiconductor device along the depth direction Pro1 shown in FIG. 2 from the upper surface TS of the semiconductor substrate SUB. In the first embodiment, the well region PW1 is formed by multiple ion implantations with different implantation energies. Therefore, as shown in FIG. 3, the concentration in the shallow part of the well region PW1 is reduced and the concentration in the deep part of the well region PW1 is increased. By increasing the concentration in the deep part of the well region PW1, punch-through can be prevented and the breakdown voltage between the collector and the base can be ensured.

[0029] However, due to the reduction in the shallow concentration of the well region PW1, the base current I B tends to increase, and there is a risk that the current amplification factor h B which is the ratio of the base current I C to the collector current I FE (=I C / I B ) tends to decrease. This issue will be specifically explained below using FIGS. 4 and 5.

[0030] FIG. 4 shows a current mirror circuit composed of two bipolar transistors BJT as an example of an analog circuit included in a semiconductor device.

[0031] The current mirror circuit is used to supply an appropriate bias current to a transistor in a later stage than the current mirror circuit and cause the transistor in the later stage to perform a desired operation. Therefore, two bipolar transistors BJT having equal characteristics and sizes are used, and the currents I1 and I2 flowing through the two bipolar transistors BJT are designed to be equal.

[0032] For example, in the bipolar transistor BJT through which the current I1 flows, the voltage V C1 between the base and the emitter is determined so that the current I1 and the collector current I C1 are substantially equal (I1≈I BE1 ) and stabilize.<00002??>

[0033] However, precisely speaking, the current I1 is the value obtained by subtracting the two base currents I C1 from the collector current I B1 , I B2 (I1 = I C1 - I B1 - I B2 ), and an error due to the base currents I B1 , I B2 occurs. In normal circuit design, a method of correcting the error due to the base current I C is adopted after determining the collector current I B first. Therefore, the current amplification factor h FE It should be noted that there seems to be an error in the original text where "図4は、半導体装置に含まれるアナログ回路の一例として、2つのバイポーラトランジスタBJTを用いて構成されたカレントミラー回路を示している。" is followed by some tags with incorrect numbering (e.g., etc.). Also, in the translation, the tag in the original has been translated as <00002??> as it seems incorrect in the original. Please check and correct the original text for a more accurate translation.(=I C / I B ) the base current I B1 , I B2 An increase in is not desirable.

[0034] The electron current component of a bipolar transistor BJT is the collector current I C and the base current I B 5 and 6 show the collector current I C Electron current and base current I contributing to B 5 shows a bipolar transistor of an example studied by the inventors of the present application, and FIG. 6 shows the bipolar transistor BJT of the first embodiment.

[0035] 5 and 6, the shallow portion of the well region PW1 is shown as a low-concentration region PW1b, and the deep portion of the well region PW1 located below the low-concentration region PW1b is shown as a high-concentration region PW1a. The emitter region NE and the base region PB are formed in the low-concentration region PW1b.

[0036] Since the impurity concentration of the low-concentration region PW1b is lower than the impurity concentration of the high-concentration region PW1a, the collector current I C Some of the electrons contributing to the electron transport are easily injected in the direction toward the base region PB.

[0037] As shown in Figure 5, in the study example, the electron current from the emitter region NE reaches the base region PB, and the base current I B increases, and the current amplification factor h FE As shown in Fig. 6, in the first embodiment, the electron current from the emitter region NE is prevented from reaching the base region PB.

[0038] For example, if the impurity concentration of the low concentration region PW1b in FIG. 5 is the same as the impurity concentration of the low concentration region PW1b in FIG. 6, the distance between the emitter region NE and the base region PB in FIG. 6 is designed to be longer than the distance between the emitter region NE and the base region PB in FIG. 5. In FIG. 6, electrons injected from the corner of the emitter region NE travel a certain distance toward the base region PB, but then recombine in the low concentration region PW1b located between the emitter region NE and the base region PB. Therefore, the base current I B The increase in the current gain h FE The decrease in

[0039] In addition, Figure 6 shows the base current I B This is an example of a method to suppress the increase in base current I B The condition for suppressing the increase in the base current I is not limited to the distance between the emitter region NE and the base region PB. B The conditions under which the increase can be suppressed will be explained.

[0040] The electron current Jn is calculated by the following formula: "Na" is the impurity concentration of the well region PW1. "Wb" is the distance of the well region PW1. "q" is the elementary charge. "Dn" is the diffusion coefficient of electrons. "n i " is the intrinsic carrier concentration. "k" is the Boltzmann constant. "T" is the absolute temperature.

number

[0041] The electron current Jn is inversely proportional to the impurity concentration (Na × Wb) of the well region PW1 per unit area. C When calculating the electron current component contributing to the above, the distance from the junction JC1 between the lower surface of the emitter region NE and the well region PW1 to the junction JC2 between the lower surface of the well region PW1 and the impurity region NEP is defined as Wb1, and the impurity concentration of the well region PW1 located below the junction JC1 is defined as Na1.

[0042] Base current I B When calculating the electron current component contributing to the above, the distance from the junction JC3 between the side surface of the emitter region NE and the well region PW1 to the base region PB is defined as Wb2, and the impurity concentration of the well region PW1 located between the junction JC3 and the base region PB is defined as Na2.

[0043] The smaller the value of Na1×Wb1, the greater the collector current I C The larger the value of Na2 × Wb2, the larger the base current I B Therefore, the base current I B and the current amplification factor h FE In order to increase Wb1, it is preferable to satisfy the relationship (Na1×Wb1)≦(Na2×Wb2), as shown in the "Condition" in Figure 7. This can improve the performance of the bipolar transistor BJT, and therefore the performance of the semiconductor device.

[0044] For example, in the case of a well region PW1 including a high-concentration region PW1a and a low-concentration region PW1b as in embodiment 1, since the impurity concentration Na2 is lower than the impurity concentration Na1, it is preferable that the distance Wb2 be longer than the distance Wb1 so as to satisfy the relationship (Na1 × Wb1) ≦ (Na2 × Wb2).

[0045] FIG. 8 shows the results of an experiment conducted by the inventors of the present invention, and shows the relationship between the distance Wb2 and the current amplification factor h FE 8 also shows the relationship between the distance Wb2 and the variation (3σ) in the impurity concentration contained in the low-concentration region PW1b. Note that FIG. 8 shows data when the relationship (Na2 / Na1) = (0.33 / 1.00) is satisfied.

[0046] As shown in Fig. 8, when the value of Na2 / Na1 is constant, the current amplification factor h FEIn the first embodiment, the variation (3σ) of the impurity concentration is almost unchanged with respect to the change in the distance Wb2, but in the first and second modifications described below, the variation (3σ) of the impurity concentration is improved with respect to the change in the distance Wb2.

[0047] <Structures of low-voltage MISFET and high-voltage MISFET> The structures of the n-type low breakdown voltage MISFET 1Q and the p-type high breakdown voltage MISFET 2Q provided in the semiconductor device will be described below with reference to FIG.

[0048] 2 and 9, the semiconductor device includes a region 1A in which a bipolar transistor BJT is formed, a region 2A in which a low-voltage MISFET 1Q is formed, and a region 3A in which a high-voltage MISFET 2Q is formed. The low-voltage MISFET 1Q is used in, for example, a logic circuit. The high-voltage MISFET 2Q has a higher breakdown voltage than the low-voltage MISFET 1Q, is called an LDMOS (Laterally Diffused Metal Oxide Semiconductor), and is used in, for example, analog circuits or I / O circuits.

[0049] 9, an n-type buried region NBL and a p-type buried region (impurity region) PBL are formed in the semiconductor substrate SUB. A p-type isolation region (impurity region) PISO is formed in the semiconductor substrate SUB and is located above the buried region PBL. The buried region NBL, the buried region PBL, and the isolation region PISO electrically isolate semiconductor elements such as the bipolar transistor BJT, the low-breakdown-voltage MISFET1Q, and the high-breakdown-voltage MISFET2Q from each other and from the p-type support substrate SS.

[0050] First, the structure of the low-breakdown-voltage MISFET 1Q in the region 2A will be described.

[0051] The low-voltage MISFET 1Q includes a p-type well region (impurity region) PW2, an n-type extension region (impurity region) NEX, an n-type high-concentration diffusion region (impurity region) NR, a gate insulating film GI1, a gate electrode GE1, a sidewall spacer SW, and a silicide film SI.

[0052] A well region PW2 is formed in a portion of the semiconductor substrate SUB located in region 2A. An n-type source region and an n-type drain region are formed in the well region PW2. The n-type source region and the n-type drain region each include an extension region NEX and a heavily doped diffusion region NR formed in the well region PW2. The heavily doped diffusion region NR has an impurity concentration higher than the impurity concentration of the extension region NEX.

[0053] A gate insulating film GI1 is formed on the well region PW2. The gate insulating film GI1 is, for example, a silicon oxide film. A gate electrode GE1 is formed on the gate insulating film GI1. The gate electrode GE1 is, for example, an n-type polycrystalline silicon film.

[0054] Sidewall spacers SW are formed on the side surfaces of the gate electrode GE1. The sidewall spacers SW include, for example, a silicon oxide film and a silicon nitride film formed on the silicon oxide film. The extension regions NEX are covered with the sidewall spacers SW. A silicide film SI is formed on the upper surfaces of the gate electrode GE1 and the high-concentration diffusion regions NR exposed from the sidewall spacers SW and the element isolation parts STI.

[0055] The gate electrode GE1 is formed on a portion of the semiconductor substrate SUB located between the two extension regions NEX in the X direction. A portion of the well region PW2 located between the pair of extension regions NEX and below the gate electrode GE1 functions as a channel region of the low-voltage MISFET 1Q.

[0056] Furthermore, the well region PW1 of the bipolar transistor BJT and the well region PW2 of the low-voltage MISFET 1Q are formed in the same process. Therefore, the impurity profile of the well region PW2 is the same as the impurity profile of the well region PW1 shown in FIG. 3. Note that "the same impurity profile" means that the impurity profiles are the same within a range that includes errors due to manufacturing variations. That is, the deep portion of the well region PW2 is a high-concentration region similar to the high-concentration region PW1a of the well region PW1, and the shallow portion of the well region PW2 is a low-concentration region similar to the low-concentration region PW1b. The impurity concentration of the high-concentration region of the well region PW2 is higher than the impurity concentration of the low-concentration region of the well region PW2.

[0057] In the low-voltage MISFET 1Q, the impurity concentration in the shallow portion of the well region PW2 is lower than the impurity concentration in the deep portion of the well region PW2, thereby suppressing latch-up. Therefore, the reliability of the low-voltage MISFET 1Q can be ensured, and the reliability of the semiconductor device can be ensured. Furthermore, the well regions PW1 and PW2 can be formed in the same process, thereby simplifying the manufacturing process and suppressing increases in manufacturing costs.

[0058] Next, the structure of the high-voltage MISFET 2Q in the region 3A will be described.

[0059] The high-voltage MISFET 2Q includes a p-type well region (impurity region) PW3, an n-type well region (impurity region) NW2, a p-type low-concentration diffusion region (impurity region) PLD, a p-type high-concentration diffusion region (impurity region) PR, a gate insulating film GI2, a gate electrode GE2, a sidewall spacer SW, and a silicide film SI.

[0060] A well region PW3 and a well region NW2 are formed in a portion of the semiconductor substrate SUB located in the region 3A. A high-concentration diffusion region PR is formed in the well region PW3. The drain region of the high-voltage MISFET 2Q includes the well region PW3 and the high-concentration diffusion region PR.

[0061] A p-type source region is formed in the well region NW2. The p-type source region includes a lightly doped diffusion region PLD formed in the well region NW2 and a heavily doped diffusion region PR formed in the lightly doped diffusion region PLD. The lightly doped diffusion region PLD has an impurity concentration higher than that of the well region PW3 and lower than that of the heavily doped diffusion region PR.

[0062] A gate insulating film GI2 is formed on the well region PW3 and the well region NW2. The gate insulating film GI2 is, for example, a silicon oxide film and has a thickness greater than that of the gate insulating film GI1. A gate electrode GE2 is formed on the gate insulating film GI2. The gate electrode GE2 is, for example, a p-type polycrystalline silicon film.

[0063] Furthermore, an element isolation portion STI is formed in the well region PW3. The well region PW3 is formed to a position deeper than the depth of the element isolation portion STI. Of both side surfaces of the gate electrode GE2, the side surface facing the high-concentration diffusion region PR constituting the drain region is located on the element isolation portion STI.

[0064] Sidewall spacers SW are formed on the side surfaces of the gate electrode GE2. A silicide film SI is formed on the upper surfaces of the gate electrode GE2 and the heavily doped diffusion region PR exposed from the sidewall spacers SW and the element isolation part STI.

[0065] Of the well region NW2, a portion located between the lightly doped diffusion region PLD and the well region PW3 and located below the gate electrode GE2 functions as a channel region of the high-voltage MISFET 2Q.

[0066] <Method of manufacturing a semiconductor device> Each manufacturing step included in the method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to Figures 10 to 23. Figures 10, 12, 14, 16, 18, 20, and 22 correspond to cross-sectional views taken along line AA in Figure 1.

[0067] 10 and 11, first, a support substrate SS made of p-type silicon is prepared. Next, an n-type buried region NBL and a p-type buried region PBL are selectively formed in the support substrate SS by photolithography and ion implantation. Note that after forming an impurity region NEP on the support substrate SS, the buried regions NBL and PBL may be formed by photolithography and ion implantation.

[0068] Next, the impurities contained in the buried regions NBL and PBL are diffused by heat treatment in an inert gas atmosphere, for example, at a temperature of 950°C to 1250°C for 60 minutes to 120 minutes.

[0069] 12 and 13, first, an n-type impurity region NEP, which is a silicon layer, is formed on a support substrate SS by epitaxial growth, thereby preparing a semiconductor substrate SUB including the support substrate SS and the impurity region NEP.

[0070] The semiconductor substrate SUB may be a single-layer p-type silicon substrate. In this case, after preparing a p-type silicon substrate, the buried region PBL, the buried region NBL, and the impurity region NEP are sequentially formed in the p-type silicon substrate by photolithography and ion implantation. In this manner, the semiconductor substrate SUB including the impurity region NEP may be prepared.

[0071] Next, a p-type isolation region PISO is selectively formed in the impurity region NEP and above the buried region PBL by photolithography and ion implantation. Then, a heat treatment is performed to diffuse the impurities contained in the isolation region PISO. This heat treatment is performed in an inert gas atmosphere, for example, at a temperature ranging from 950°C to 1250°C for 60 minutes to 120 minutes.

[0072] As shown in FIGS. 14 and 15, an element isolation part STI, an n-type well region NW1, an n-type well region NW2, and a p-type well region PW3 are formed in a semiconductor substrate SUB.

[0073] First, a trench is formed in the semiconductor substrate SUB by photolithography and anisotropic etching, reaching a predetermined depth from the top surface of the semiconductor substrate SUB. Next, an insulating film, such as a silicon oxide film, is formed on the semiconductor substrate SUB so as to fill the trench. Next, the insulating film located outside the trench is removed by polishing using a CMP method, so that the insulating film filled in the trench remains. In this manner, an element isolation portion STI including the trench and the insulating film is formed.

[0074] Next, by photolithography and ion implantation, a well region NW1 is selectively formed in the impurity region NEP in the region 1A, and a well region NW2 and a well region PW3 are sequentially and selectively formed in the impurity region NEP in the region 3A.

[0075] As shown in FIGS. 16 and 17, a p-type well region PW1 and a p-type well region PW2 are formed in a semiconductor substrate SUB.

[0076] First, a resist pattern RP1 is formed on the upper surface TS of the semiconductor substrate SUB, selectively opening portions of the impurity region NEP located in region 1A and region 2A. Next, ion implantation is performed using the resist pattern RP1 as a mask to form a well region PW1 in the impurity region NEP located in region 1A and a well region PW2 in the impurity region NEP located in region 2A. Next, the resist pattern RP1 is removed by ashing.

[0077] The well regions PW1 and PW2 are formed by multiple ion implantations with different implantation energies, and therefore have the impurity profiles shown in FIG.

[0078] Furthermore, any one of the steps of forming the well regions PW1 and PW2, the step of forming the well region PW3, the step of forming the well region NW1, and the step of forming the well region NW2 may be performed first.

[0079] Next, heat treatment is performed to activate the impurities contained in well regions PW1, PW2, PW3, NW1, and NW2 in an inert gas atmosphere at a temperature of 900° C. to 1000° C. for 10 seconds to 60 seconds.

[0080] Furthermore, since this heat treatment is performed for a shorter time than the heat treatment for diffusing the impurities contained in the above-mentioned buried region NBL, buried region PBL, and isolation region PISO, the impurity profiles of each of well region PW1, well region PW2, well region PW3, well region NW1, and well region NW2 do not change much and are almost the same as those at the time of ion implantation.

[0081] As shown in FIGS. 18 and 19, a gate insulating film GI1, a gate insulating film GI2, a gate electrode GE1 and a gate electrode GE2 are formed on an upper surface TS of a semiconductor substrate SUB, and an n-type extension region NEX is formed in the semiconductor substrate SUB.

[0082] First, in regions 1A, 2A, and 3A, a gate insulating film GI2 is formed by, for example, thermal oxidation on the upper surface TS of the semiconductor substrate SUB exposed from the element isolation portions STI. Next, the gate insulating film GI2 located in regions 1A and 2A is selectively removed by photolithography and isotropic etching. As a result, in region 3A, the gate insulating film GI2 remains on the well regions NW2 and PW3.

[0083] Next, in regions 1A and 2A, a gate insulating film GI1 is formed by, for example, thermal oxidation on the upper surface TS of the semiconductor substrate SUB exposed from the element isolation portions STI. Next, polycrystalline silicon films are formed on the gate insulating films GI1 and GI2 by, for example, a film formation process using a CVD method. Next, n-type impurities are selectively introduced into the polycrystalline silicon film located in region 2A by photolithography and ion implantation, and p-type impurities are selectively introduced into the polycrystalline silicon film located in region 3A.

[0084] Next, the polycrystalline silicon film is patterned by photolithography and anisotropic etching. As a result, the polycrystalline silicon film located in region 1A is removed, a gate electrode GE1 is formed from the n-type polycrystalline silicon film located in region 2A, and a gate electrode GE2 is formed from the p-type polycrystalline silicon film located in region 3A. Next, the gate insulating films GI1 and GI2 exposed from the gate electrodes GE1 and GE2 may be removed by isotropic etching.

[0085] In this way, in region 2A, gate insulating film GI1 is formed on well region PW2, and gate electrode GE1 is formed on gate insulating film GI1. Also, in region 3A, gate insulating film GI2 is formed on well region NW2 and well region PW3, and gate electrode GE2 is formed on gate insulating film GI2.

[0086] Next, an n-type extension region NEX is selectively formed in the well region PW2 by photolithography and ion implantation.

[0087] As shown in FIGS. 20 and 21, a p-type lightly doped diffusion region PLD is formed in a semiconductor substrate SUB.

[0088] First, a resist pattern RP2 is formed on the upper surface TS of the semiconductor substrate SUB and on the gate electrode GE2, selectively opening the well region NW2. Next, ion implantation is performed using the resist pattern RP2 as a mask to form a low-concentration diffusion region PLD in the well region NW2 exposed from the gate electrode GE2 in region 3A. Next, the resist pattern RP2 is removed by ashing.

[0089] Either the step of forming the extension region NEX or the step of forming the lightly doped diffusion region PLD may be performed first.

[0090] 22 and 23, sidewall spacers SW are formed on the side surfaces of the gate electrodes GE1 and GE2. A p-type heavily doped diffusion region PR and a p-type base region PB are formed in the semiconductor substrate SUB in the same process, and an n-type heavily doped diffusion region NR, an n-type emitter region NE, and an n-type collector region NC are formed in the semiconductor substrate SUB in the same process.

[0091] First, a stacked film including, for example, a silicon oxide film and a silicon nitride film is formed on the semiconductor substrate SUB by a film formation process using, for example, a CVD method so as to cover the gate electrodes GE1 and GE2. Next, the stacked film is anisotropically etched to form sidewall spacers SW from the stacked film remaining on each side surface of the gate electrodes GE1 and GE2.

[0092] Next, by using photolithography technology and ion implantation, a base region PB is selectively formed in the well region PW1 in region 1A, a high-concentration diffusion region PR is selectively formed in the well region NW3 and the low-concentration diffusion region PLD in region 3A, and a high-concentration diffusion region PR is selectively formed in the isolation region PISO.

[0093] Next, using photolithography and ion implantation techniques, an emitter region NE is selectively formed in well region PW1 in region 1A, a collector region NC is selectively formed in well region NW1 in region 1A, and a high-concentration diffusion region NR is selectively formed in well region PW2 in region 2A.

[0094] Either the step of forming the heavily doped diffusion region PR and the base region PB or the step of forming the heavily doped diffusion region NR, the emitter region NE and the collector region NC may be performed first.

[0095] Next, a heat treatment is performed to activate the impurities contained in the lightly doped diffusion region PLD, the heavily doped diffusion region PR, the base region PB, the extension region NEX, the heavily doped diffusion region NR, the emitter region NE, and the collector region NC. This heat treatment is performed in an inert gas atmosphere, for example, at a temperature ranging from 900°C to 1000°C for 10 seconds to 60 seconds.

[0096] Thereafter, the semiconductor device shown in FIGS. 2 and 9 is manufactured through the following steps.

[0097] First, an insulating film IF1 is formed on the upper surface TS of the semiconductor substrate SUB by a film formation process using, for example, a CVD method so as to cover the gate electrodes GE1, GE2, and the sidewall spacers SW. Next, the insulating film IF1 is patterned by photolithography and anisotropic etching. As a result, the insulating film IF1 is left on a part of the emitter region NE, the well region PW1, and a part of the base region PB so as to cover the boundary between the emitter region NE and the well region PW1 and the boundary between the well region PW1 and the base region PB.

[0098] Next, by salicide technology, a silicide film SI is formed on the base region PB, the emitter region NE, the collector region NC, the gate electrode GE1, the gate electrode GE2, the high-concentration diffusion region PR, and the high-concentration diffusion region NR, which are exposed from the insulating film IF1 and the element isolation portion STI.

[0099] (Variation 1) A semiconductor device according to Modification 1 of Embodiment 1 will be described below with reference to Fig. 24. In the following description, differences from Embodiment 1 will be mainly described, and descriptions of points that overlap with Embodiment 1 will be omitted.

[0100] 24, in Modification 1, a lightly doped diffusion region PLD is formed in the well region PW1. The lightly doped diffusion region PLD of the bipolar transistor BJT and the lightly doped diffusion region PLD of the high-breakdown-voltage MISFET 2Q are formed in the same process. To achieve this, an opening is formed in the resist pattern RP2 formed in the region 1A in FIG. 20, so as to expose a part of the well region PW1.

[0101] The impurity profile of the lightly doped diffusion region PLD located in region 1A is the same as the impurity profile of the lightly doped diffusion region PLD located in region 3A. The lightly doped diffusion region PLD located in region 1A has an impurity concentration higher than that of the well region PW1 and lower than that of the base region PB. The base region PB is formed in the lightly doped diffusion region PLD. In addition, in a plan view, the lightly doped diffusion region PLD located in region 1A, the emitter region NE, and the collector region NC are separated from each other.

[0102] The impurity concentration Na2 in the first modification includes the impurity concentration of the lightly doped diffusion region PLD located between the junction JC3 and the base region PB. Therefore, the impurity concentration Na2 in the first modification is higher than the impurity concentration Na2 in the first embodiment, so that the relationship (Na1×Wb1)≦(Na2×Wb2) is more easily satisfied. Therefore, in the first modification, the base current I B It is easy to reduce the current gain h FE It is easy to increase.

[0103] As shown in FIG. 8, when the value of Na2 / Na1 is constant, the current amplification factor h FE In addition, in the first modification, the low-concentration diffusion region PLD is formed also in the well region PW1, and thus the variation (3σ) in the impurity concentration contained in the low-concentration region PW1b is improved with respect to the change in the distance Wb2.

[0104] Furthermore, in Modification 1, since the impurity concentration Na2 is high, the distance Wb2 can be shortened within a range that satisfies the relationship (Na1×Wb1)≦(Na2×Wb2). In this case, the plane area of ​​the bipolar transistor BJT can be reduced, thereby enabling the miniaturization of the semiconductor device.

[0105] Furthermore, since the lightly doped diffusion region PLD located in the region 1A and the lightly doped diffusion region PLD located in the region 3A can be formed in the same process, the manufacturing process can be simplified and an increase in manufacturing costs can be suppressed.

[0106] (Variation 2) A semiconductor device according to Modification 2 of Embodiment 1 will be described below with reference to Fig. 25. In the following description, differences from Modification 1 will be mainly described, and descriptions of points that overlap with Modification 1 will be omitted.

[0107] 24, in the second modification, not only the lightly doped diffusion region PLD but also the well region PW3 is formed in the well region PW1. The well region PW3 of the bipolar transistor BJT and the well region PW3 of the high voltage MISFET 2Q are formed in the same process.

[0108] The impurity profile of the well region PW3 located in region 1A is the same as the impurity profile of the well region PW3 located in region 3A. The well region PW3 located in region 1A has an impurity concentration lower than the impurity concentration of the lightly doped diffusion region PLD and the impurity concentration of the base region PB. The base region PB and the lightly doped diffusion region PLD are formed in the well region PW3. In addition, in a plan view, the well region PW3, the emitter region NE, and the collector region NC located in region 1A are separated from each other.

[0109] The impurity concentration Na2 in the second modification includes the impurity concentration of the lightly doped diffusion region PLD located between the junction JC3 and the base region PB and the impurity concentration of the well region PW3. Therefore, the impurity concentration Na2 in the second modification is higher than the impurity concentration Na2 in the first embodiment, so that the relationship (Na1×Wb1)≦(Na2×Wb2) is more easily satisfied. Therefore, in the second modification, the base current I B It is easy to reduce the current gain h FE It is easy to increase.

[0110] As shown in FIG. 8, when the value of Na2 / Na1 is constant, the current amplification factor h FEIn addition, in the second modification, the low concentration diffusion region PLD and the well region PW3 are formed in the well region PW1, and thus the variation (3σ) in the impurity concentration is improved with respect to the change in the distance Wb2.

[0111] In the second modification, as in the first modification, the impurity concentration Na2 is high, so the distance Wb2 can be shortened within the range that satisfies the relationship (Na1×Wb1)≦(Na2×Wb2). In this case, the planar area of ​​the bipolar transistor BJT can be reduced, thereby enabling the miniaturization of the semiconductor device.

[0112] Furthermore, since the well region PW3 located in the region 1A and the well region PW3 located in the region 3A can be formed in the same manufacturing process, the manufacturing process can be simplified and an increase in manufacturing costs can be suppressed.

[0113] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to these embodiments and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0114] 1A, 2A, 3A area 1Q Low-voltage MISFET 2Q high voltage MISFET BJT Bipolar Transistor BS Bottom surface of semiconductor substrate GE1, GE2 gate electrodes GI1, GI2 gate insulating film IF1 insulating film JC1, JC2, JC3 joint surface NBL n-type buried region (impurity region) NC n-type collector region (impurity region) NE n-type emitter region (impurity region) NEP n-type impurity region NEX n-type extension region (impurity region) NR n-type high concentration diffusion region (impurity region) NW1, NW2 n-type well region (impurity region) PB p-type base region (impurity region) PBL p-type buried region (impurity region) PISO p-type isolation region (impurity region) PLD p-type low concentration diffusion region (impurity region) PR p-type high concentration diffusion region (impurity region) PW1, PW2, PW3 p-type well regions (impurity regions) PW1a High concentration area PW1b Low concentration area RP1, RP2 resist patterns SI silicide film SS support board STI element isolation section SUB Semiconductor substrate SW Sidewall Spacer TS Top surface of semiconductor substrate

Claims

1. a semiconductor substrate; a first impurity region of a first conductivity type formed in the semiconductor substrate; a first well region of a second conductivity type opposite to the first conductivity type formed in the first impurity region; an emitter region of the first conductivity type formed in the first well region; a base region of the second conductivity type formed in the first well region and having an impurity concentration higher than an impurity concentration of the first well region; a collector region of the first conductivity type formed in the first impurity region and having an impurity concentration higher than an impurity concentration of the first impurity region; Equipped with the emitter region, the base region, and the collector region are spaced apart from one another in a plan view, a semiconductor device in which the relationship (Na1×Wb1)≦(Na2×Wb2) is satisfied, where Wb1 is the distance from a first junction surface between a lower surface of the emitter region and the first well region to a second junction surface between the lower surface of the first well region and the first impurity region, Na1 is the impurity concentration of a portion of the first well region located below the first junction surface, Wb2 is the distance from a third junction surface between a side surface of the emitter region and the first well region to the base region, and Na2 is the impurity concentration of a portion of the first well region located between the third junction surface and the base region.

2. 2. The semiconductor device according to claim 1, the first well region includes a low concentration region and a high concentration region located below the low concentration region; The semiconductor device, wherein the impurity concentration of the high concentration region is higher than the impurity concentration of the low concentration region.

3. 3. The semiconductor device according to claim 2, The semiconductor device, wherein the emitter region and the base region are formed in the low concentration region.

4. 3. The semiconductor device according to claim 2, The impurity concentration Na2 is lower than the impurity concentration Na1, The semiconductor device, wherein the distance Wb2 is longer than the distance Wb1.

5. 3. The semiconductor device according to claim 2, a second well region of the second conductivity type formed in the semiconductor substrate; a first gate insulating film formed on the second well region; a first gate electrode formed on the first gate insulating film; Further provided with the first impurity region, the first well region, the emitter region, the base region, and the collector region constitute a bipolar transistor; the second well region, the first gate insulating film, and the first gate electrode constitute a first MISFET; The semiconductor device, wherein the impurity profile of the first well region is the same as the impurity profile of the second well region.

6. 2. The semiconductor device according to claim 1, a second impurity region of the second conductivity type formed in the first well region and having an impurity concentration higher than an impurity concentration of the first well region and lower than an impurity concentration of the base region; the emitter region, the second impurity region, and the collector region are spaced apart from one another in a plan view; the base region is formed in the second impurity region; The impurity concentration Na2 includes the impurity concentration of the second impurity region located between the third junction surface and the base region.

7. 7. The semiconductor device according to claim 6, a third well region of the first conductivity type formed in the semiconductor substrate; a third impurity region of the second conductivity type formed in the third well region; a fourth impurity region of the second conductivity type formed in the third impurity region and having an impurity concentration higher than that of the third impurity region; a second gate insulating film formed on the third well region; a second gate electrode formed on the second gate insulating film; Further provided with the first impurity region, the first well region, the emitter region, the base region, and the collector region constitute a bipolar transistor; the third well region, the third impurity region, the fourth impurity region, the second gate insulating film, and the second gate electrode constitute a second MISFET, an impurity profile of the second impurity region being the same as an impurity profile of the third impurity region;

8. 2. The semiconductor device according to claim 1, a first well region having a first insulating film formed therein and a second insulating film formed therein; a second insulating film formed in the first well region;

9. 2. The semiconductor device according to claim 1, the first conductivity type is n-type, The second conductivity type is p-type.

10. 2. The semiconductor device according to claim 1, the base region surrounds the emitter region in a plan view, The collector region surrounds the base region and the emitter region in a plan view.

11. (a) providing a semiconductor substrate including a first impurity region of a first conductivity type; (b) forming a first well region of a second conductivity type opposite to the first conductivity type in the first impurity region; (c) forming a base region of the second conductivity type in the first well region, the base region having an impurity concentration higher than an impurity concentration of the first well region; (d) forming an emitter region of the first conductivity type in the first well region, and forming a collector region of the first conductivity type in the first impurity region, the collector region having an impurity concentration higher than an impurity concentration of the first impurity region; Equipped with the emitter region, the base region, and the collector region are spaced apart from one another in a plan view, a distance from a first junction surface between a lower surface of the emitter region and the first well region to a second junction surface between the lower surface of the first well region and the first impurity region being defined as Wb1, an impurity concentration of a portion of the first well region located below the first junction surface being defined as Na1, a distance from a third junction surface between a side surface of the emitter region and the first well region to the base region being defined as Wb2, and an impurity concentration of a portion of the first well region located between the third junction surface and the base region being Na2, wherein the relationship (Na1×Wb1)≦(Na2×Wb2) is satisfied.

12. 12. The method for manufacturing a semiconductor device according to claim 11, the first well region is formed by a plurality of ion implantations with different implantation energies; the first well region includes a low concentration region and a high concentration region located below the low concentration region; The method for manufacturing a semiconductor device, wherein the impurity concentration of the high concentration region is higher than the impurity concentration of the low concentration region.

13. 13. The method for manufacturing a semiconductor device according to claim 12, The method for manufacturing a semiconductor device, wherein the emitter region and the base region are formed in the low concentration region.

14. 13. The method for manufacturing a semiconductor device according to claim 12, The impurity concentration Na2 is lower than the impurity concentration Na1, A method for manufacturing a semiconductor device, wherein the distance Wb2 is longer than the distance Wb1.

15. 13. The method for manufacturing a semiconductor device according to claim 12, (e) forming a second well region of the second conductivity type in the semiconductor substrate; (f) forming a first gate insulating film on the second well region; (g) forming a first gate electrode on the first gate insulating film; Further provided with the first impurity region, the first well region, the emitter region, the base region, and the collector region constitute a bipolar transistor; the second well region, the first gate insulating film, and the first gate electrode constitute a first MISFET; The method for manufacturing a semiconductor device, wherein the step (b) and the step (e) are performed as a single step.

16. 12. The method for manufacturing a semiconductor device according to claim 11, (h) forming a second impurity region of the second conductivity type in the first well region between the steps (b) and (c); Further provided with the base region is formed in the second impurity region; the second impurity region has an impurity concentration higher than the impurity concentration of the first well region and lower than the impurity concentration of the base region; the emitter region, the second impurity region, and the collector region are spaced apart from one another in a plan view; The impurity concentration Na2 includes the impurity concentration of the second impurity region located between the third junction surface and the base region.

17. 17. The method for manufacturing a semiconductor device according to claim 16, (i) forming a third well region of the first conductivity type in the semiconductor substrate; (j) forming a third impurity region of the second conductivity type in the third well region; (k) forming a fourth impurity region of the second conductivity type in the third impurity region, the fourth impurity region having an impurity concentration higher than that of the third impurity region; (l) forming a second gate insulating film on the third well region; (m) forming a second gate electrode on the second gate insulating film; Further provided with the first impurity region, the first well region, the emitter region, the base region, and the collector region constitute a bipolar transistor; the third well region, the third impurity region, the fourth impurity region, the second gate insulating film, and the second gate electrode constitute a second MISFET, The method for manufacturing a semiconductor device, wherein the step (h) and the step (j) are performed as a single step.

18. 12. The method for manufacturing a semiconductor device according to claim 11, a first well region formed on the first insulating film and having a first insulating film formed on the first well region; a second well region formed on the first insulating film and having a second insulating film formed on the first well region;

19. 12. The method for manufacturing a semiconductor device according to claim 11, the first conductivity type is n-type, The second conductivity type is p-type.

20. 12. The method for manufacturing a semiconductor device according to claim 11, the base region surrounds the emitter region in a plan view, The method for manufacturing a semiconductor device, wherein the collector region surrounds the base region and the emitter region in a plan view.

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