Semiconductor device and power semiconductor system including the same

Abstract

To provide a semiconductor device including a high electron mobility transistor with improved reliability.SOLUTION: A semiconductor device according to the present invention includes: a high electron mobility transistor; a short circuit detection circuit that outputs a short circuit protection voltage based on gate and drain voltages of the high electron mobility transistor; and a protection circuit that reduces a gate voltage of the high electron mobility transistor based on the short circuit protection voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a power semiconductor system including the same. [Background technology]

[0002] In modern society, semiconductor devices are closely related to daily life. In particular, the importance of power semiconductor devices, which are used in various fields such as transportation (e.g., electric vehicles, railways, and electric trams), renewable energy systems (e.g., solar power generation and wind power generation), and mobile devices, is gradually increasing. Power semiconductor devices are semiconductor devices used to handle high voltages and high currents, and perform functions such as power conversion and control in large power systems and high-power electronic devices. Power semiconductor devices have the ability and durability to handle high power, handle large amounts of current, and withstand high voltages. For example, power semiconductor devices can handle voltages from hundreds to thousands of volts and currents from tens to thousands of amperes. Power semiconductor devices can minimize power loss and improve electrical energy efficiency. Furthermore, power semiconductor devices can operate stably even in high-temperature environments.

[0003] These power semiconductor devices can be categorized by material, such as SiC power semiconductor devices and GaN power semiconductor devices. By manufacturing power semiconductor devices using SiC or GaN instead of existing silicon wafers (Si wafers), it is possible to compensate for the disadvantage of silicon, which has unstable properties at high temperatures. SiC power semiconductor devices are resistant to high temperatures and have low power loss, making them suitable for electric vehicles and renewable energy systems. GaN power semiconductor devices are expensive but are efficient in terms of speed, making them suitable for fast charging of mobile devices. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device including a high electron mobility transistor with improved reliability. [Means for solving the problem]

[0005] In order to achieve the above object, one aspect of the present invention provides a semiconductor device comprising: a high electron mobility transistor; a short circuit detection circuit that outputs a short circuit protection voltage based on a gate voltage of the high electron mobility transistor and a drain voltage of the high electron mobility transistor; and a protection circuit that reduces the gate voltage of the high electron mobility transistor based on the short circuit protection voltage.

[0006] In order to achieve the above object, according to another aspect of the present invention, a semiconductor device includes a high electron mobility transistor, a first transistor connected between a gate electrode of the high electron mobility transistor and a second power supply voltage, the first transistor having a gate electrode connected to a first node, a second transistor connected between a drain electrode of the high electron mobility transistor and the first node, the second transistor having a gate electrode connected to the gate electrode of the high electron mobility transistor, and a first resistor connected between the first node and the second power supply voltage.

[0007] In order to achieve the above object, one aspect of the present invention provides a power semiconductor system including a high electron mobility transistor, a gate driver that outputs a gate voltage (VG) to a gate electrode of the high electron mobility transistor, and a short circuit protection device connected to the gate electrode of the high electron mobility transistor, wherein the short circuit protection device includes a short circuit detection circuit that outputs a short circuit protection voltage based on the gate voltage and a drain voltage of the high electron mobility transistor, and a protection circuit that reduces the gate voltage of the high electron mobility transistor based on the short circuit protection voltage. [Effects of the Invention]

[0008] According to the present invention, even if a short circuit occurs in a specific circuit within a semiconductor device, it is possible to prevent destruction of a high electron mobility transistor due to a short circuit current, thereby making it possible to provide a semiconductor device including a high electron mobility transistor with improved reliability. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram illustrating a power semiconductor system according to an embodiment; [Figure 2] FIG. 2 is a block diagram for specifically explaining a gate driver and a semiconductor device. [Figure 3] FIG. 2 is a block diagram for explaining the configuration and operation of a gate driver and a semiconductor device according to an embodiment. [Figure 4] FIG. 2 is a block diagram for specifically explaining the configuration and operation of a gate driver and a semiconductor device according to an embodiment. [Figure 5] 1 is a graph showing the current and voltage characteristics of a high electron mobility transistor (H1) in a normal state and a short-circuit state. [Figure 6] FIG. 1 is a circuit diagram showing a configuration of a gate driver and a semiconductor device according to an embodiment. [Figure 7] 10 is a flowchart illustrating an operation of the detection circuit according to the embodiment. [Figure 8] 10 is a flowchart illustrating the operation of the gate driver according to the embodiment. [Figure 9] FIG. 1 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment. [Figure 10] FIG. 1 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment. [Figure 11] FIG. 1 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment. [Figure 12] FIG. 1 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment. [Figure 13] FIG. 1 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment. [Figure 14]FIG. 1 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment. [Figure 15] FIG. 1 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment. [Figure 16] FIG. 1 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment. [Figure 17] FIG. 1 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement various embodiments of the present invention. The present invention may be embodied in various different forms and is not limited to the examples described herein.

[0011] In order to clearly describe the present invention, parts that are not relevant to the description will be omitted and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0012] Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, thicknesses are exaggerated to clearly show multiple layers and regions. In the drawings, thicknesses of some layers and regions are exaggerated for the convenience of explanation.

[0013] Furthermore, when a layer, film, region, plate, or other part is said to be "on" or "above" another part, this includes not only the case where it is "directly above" that part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" or "above" the opposite direction of gravity.

[0014] Furthermore, throughout the specification, when a part "comprises" a certain element, it does not mean that it excludes other elements, but that it may further include other elements, unless otherwise specified.

[0015] Also, throughout this specification, "on a plane" means when the target part is viewed from above, and "on a cross section" means when the target part is cut vertically and viewed from the side.

[0016] FIG. 1 is a block diagram that schematically illustrates a power semiconductor system.

[0017] Referring to FIG. 1, a power semiconductor system 10 includes a gate driver 20 and a semiconductor device (or power device) 30.

[0018] 1 , a power semiconductor system 10 is a system that outputs electric power, and includes, for example, transportation systems such as electric vehicles, railways, and electric trams, renewable energy systems such as solar power generation and wind power generation, mobile devices, and home electronic devices. In an embodiment, the power semiconductor system 10 includes a semiconductor device 30 and a gate driver 20 that provides an electrical signal to the semiconductor device 30.

[0019] The gate driver 20 receives a control signal (CS) from an external device. The gate driver 20 generates a gate voltage (VG) based on the control signal (CS) and supplies the gate voltage (VG) to the semiconductor device 30. The control signal (CS) is a signal for controlling the gate driver 20. The control signal (CS) is a signal output from a control unit located outside the power semiconductor system 10. For example, the control signal (CS) is a signal output from a microprocessor such as a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP). Unlike the example shown in FIG. 1, the control signal (CS) may also be output from an integrated circuit included in the power semiconductor system 10. In an embodiment, the control signal (CS) includes a pulse width modulation (PWM) signal. In an embodiment, the gate driver 20 generates a gate voltage (VG) having a target magnitude or waveform based on information included in the control signal (CS) and outputs the gate voltage (VG) to the outside. The information contained in the control signal (CS) is, for example, the duty ratio of the PWM signal.

[0020] The gate voltage (VG) is a signal for controlling a discrete semiconductor device included in the semiconductor device 30. Specifically, the gate voltage (VG) is an electrical signal provided to a terminal of the discrete semiconductor device included in the semiconductor device 30. In one embodiment, the gate voltage (VG) has a value greater than that of the control signal (CS). The gate driver 20 converts an electrical signal received from the outside into an appropriate signal for controlling the discrete semiconductor device included in the semiconductor device 30 and provides the converted signal to the semiconductor device 30. In one embodiment, the gate driver 20 operates as a signal amplifier for processing rapid on / off switching of the discrete semiconductor device included in the semiconductor device 30.

[0021] The semiconductor device 30 includes at least one or more components for converting, controlling, or distributing power. As an example, the semiconductor device 30 includes components such as an inverter, a converter, a power management IC (PMIC), and / or a power distribution unit (PDU). The components (e.g., inverter, converter, PMIC, PDU) included in the semiconductor device 30 include various discrete semiconductor elements therein to perform the function of converting, controlling, or distributing power. For example, the semiconductor device 30 includes discrete semiconductor elements such as a transistor, such as an IGBT or a MOSFET, a diode, or a thyristor.

[0022] In the embodiment, the semiconductor device 30 includes a discrete semiconductor element that performs a switching operation. That is, the semiconductor device 30 according to the embodiment includes a discrete semiconductor element that performs an on / off operation according to the level of the gate voltage (VG), and by controlling the on / off operation of the discrete semiconductor element, the supply power can be controlled or converted.

[0023] FIG. 2 is a block diagram for specifically explaining the gate driver and the semiconductor device.

[0024] 2, the gate driver 20 includes a signal generator 21 and an amplifier 22, and the semiconductor device 30 includes unit blocks (or power blocks) 31, 32, and 33. The unit blocks 31, 32, and 33 are individual semiconductor elements that perform one unit function, or are a collection of individual semiconductor elements and / or passive elements configured to perform one unit function.

[0025] The signal generator 21 generates an output control signal (OCS) based on a control signal (CS) received from the outside. The output control signal (OCS) is a signal for controlling the output of the gate voltage (VG) output from the amplifier 22. The signal generator 21 generates the output control signal (OCS) based on the control signal (CS) and then provides it to the amplifier 22.

[0026] The amplifier 22 outputs a gate voltage (VG) to the outside in response to an output control signal (OCS) received from the signal generator 21. A signal directly output from an external microprocessor or an internal integrated circuit, such as the control signal (CS) shown in FIG. 2, has a relatively low power and may be insufficient to drive a high-power element such as a power semiconductor element. The gate driver 20 according to the embodiment receives the control signal (CS), which is a low-power input signal, and then outputs a gate voltage (VG) signal having a high power to the outside via the amplifier 22 based on the control signal (CS). In the embodiment, the amplifier 22 outputs a gate voltage (VG) of a level that turns on or off a switching element included in the semiconductor device 30 based on the output control signal (OCS).

[0027] The unit blocks 31, 32, and 33 are discrete semiconductor elements that perform a single unit function, or are a collection of discrete semiconductor elements and / or passive elements configured to perform a single unit function. One unit function is, for example, a switching operation or a rectification operation. However, the function performed by each of the unit blocks 31, 32, and 33 is not limited to switching and rectification. That is, each of the unit blocks 31, 32, and 33 can be designed to perform various operations performed by various known discrete semiconductor elements, in addition to switching and rectification. The unit blocks 31, 32, and 33 are included in the semiconductor device 30, and together with other unit blocks 31, 32, and 33 in the semiconductor device 30, perform functions of power conversion and control, such as an inverter, converter, and PMIC.

[0028] FIG. 3 is a block diagram for explaining the configuration and operation of the gate driver and semiconductor device according to the embodiment.

[0029] Referring to FIG. 3, a semiconductor device 30 according to an embodiment includes a high electron mobility transistor (H1) and a short circuit protection device 100.

[0030] In this embodiment, the high electron mobility transistor (H1) is a switching element included in any of the unit blocks 31, 32, and 33 described with reference to FIG. 2. The high electron mobility transistor (H1) includes a drain electrode and a source electrode. Although not explicitly shown in FIG. 3, the drain electrode of the high electron mobility transistor (H1) is connected to a separate circuit including at least one passive and / or active element and connected to an external power source. The source electrode of the high electron mobility transistor (H1) is connected to a separate circuit including at least one passive and / or active element. In FIG. 3, the drain voltage (VD) is the voltage of the drain electrode of the high electron mobility transistor (H1), and the source voltage (VS) is the voltage of the source electrode of the high electron mobility transistor (H1).

[0031] The gate electrode of the high electron mobility transistor H1 is connected to the output terminal of the gate driver 20. The high electron mobility transistor H1 receives a gate voltage VG from the output terminal of the gate driver 20. The high electron mobility transistor H1 turns on or off depending on the level of the gate voltage VG provided by the gate driver 20. For example, when the potential difference between the gate voltage VG and the drain electrode of the high electron mobility transistor H1 is equal to or higher than the threshold voltage of the high electron mobility transistor H1, the high electron mobility transistor H1 turns on. For example, when the potential difference between the gate voltage VG and the drain electrode of the high electron mobility transistor H1 is lower than the threshold voltage of the high electron mobility transistor H1, the high electron mobility transistor H1 turns off.

[0032] The short circuit protection device 100 is configured to prevent breakdown of the high electron mobility transistor H1 when a short circuit occurs in a specific circuit within the semiconductor device 30. A short circuit may occur in a specific circuit within the semiconductor device 30 if the gate driver 20 malfunctions or if a specific load included in the semiconductor device 30 malfunctions. As an example, although not clearly shown in FIG. 3 , a short circuit may occur around a circuit connected to the drain electrode of the high electron mobility transistor H1. At this time, a very large amount of short circuit current may instantaneously flow between the drain and source electrodes of the high electron mobility transistor H1. The short circuit protection device 100 prevents breakdown of the high electron mobility transistor H1 due to the short circuit current flowing between the drain and source electrodes of the high electron mobility transistor H1 when a short circuit occurs.

[0033] The short circuit protection device 100 is connected to the output terminal of the gate driver 20 or the gate electrode of the high electron mobility transistor H1 and receives a gate voltage VG. The short circuit protection device 100 is connected to the drain electrode of the high electron mobility transistor H1 and receives a drain voltage VD. In one embodiment, the short circuit protection device 100 detects a short circuit in the high electron mobility transistor H1 based on the voltage levels of the gate voltage VG and the drain voltage VD of the high electron mobility transistor H1. In one embodiment, the short circuit protection device 100 outputs a short circuit protection signal SPS to turn off the high electron mobility transistor H1 if both the voltage levels of the gate voltage VG and the drain voltage VD of the high electron mobility transistor H1 are high. The short circuit protection device 100 provides the short circuit protection signal SPS to the gate driver 20. In one embodiment, the short circuit protection signal SPS is a voltage signal. The gate driver 20 outputs a gate voltage (VG) that turns on or off the high electron mobility transistor (H1) based on the voltage level of the short circuit protection signal (SPS) provided from the short circuit protection device 100. For example, the gate driver 20 outputs the gate voltage (VG) based on the voltage level of the control signal (CS) and the voltage level of the short circuit protection signal (SPS).

[0034] In the embodiment, the number of short circuit protection devices 100 is equal to the number of high electron mobility transistors H1 included in the semiconductor device 30. For example, the semiconductor device 30 may include a plurality of high electron mobility transistors H1 and a short circuit protection device 100 connected to the gate electrodes of each of the high electron mobility transistors H1. However, without being limited thereto, the semiconductor device 30 may have one short circuit protection device 100 per one unit block 31 to 33 (see FIG. 2). That is, each of the unit blocks 31, 32, and 33 described with reference to FIG. 2 includes a plurality of high electron mobility transistors H1, and the plurality of high electron mobility transistors H1 included in each unit block 31, 32, and 33 are commonly connected to one short circuit protection device 100. The short circuit protection device 100 outputs a short circuit protection signal SPS to turn off the plurality of high electron mobility transistors H1 when a short circuit occurs in the peripheral circuit of at least one of the plurality of high electron mobility transistors H1. In this case, all of the high electron mobility transistors (H1) may be turned off, or only the high electron mobility transistors (H1) located around the circuit where the short circuit has occurred may be turned off.

[0035] FIG. 4 is a block diagram for specifically explaining the configuration and operation of the gate driver and semiconductor device according to the embodiment.

[0036] Referring to FIG. 4, the short circuit protection device 100 includes a detection circuit 110 and a protection circuit 120 .

[0037] The detection circuit 110 detects a short circuit state within the semiconductor device 30. The detection circuit 110 generates a short circuit protection signal (SPS) and outputs the short circuit protection signal (SPS) to the gate driver 20 and the protection circuit 120. In this embodiment, the short circuit protection signal (SPS) is a voltage signal. In this embodiment, the detection circuit 110 outputs the short circuit protection signal (SPS) having different levels to the outside based on the level of the gate voltage (VG) and the level of the drain voltage (VD). The drain voltage (VD) refers to the voltage of the drain electrode of the high electron mobility transistor (H1). For example, if the peripheral circuit of the high electron mobility transistor (H1) is short-circuited, the detection circuit 110 outputs the short circuit protection signal (SPS) having a first level to the outside. If the high electron mobility transistor (H1) is not short-circuited, the detection circuit 110 outputs the short circuit protection signal (SPS) having a second level different from the first level to the outside. In this embodiment, the gate driver 20 determines whether the high electron mobility transistor (H1) is short-circuited based on the voltage level of the short circuit protection signal (SPS). When a short circuit occurs, the gate driver 20 outputs a gate voltage (VG) that turns off the high electron mobility transistor (H1).

[0038] The protection circuit 120 reduces the level of the gate voltage (VG) based on the short circuit protection signal (SPS). The protection circuit 120 protects the high electron mobility transistor (H1) from damage due to a short circuit current by using the gate voltage (VG) that turns off the high electron mobility transistor (H1) immediately after a short circuit occurs until the high electron mobility transistor (H1) is completely turned off. After receiving the short circuit protection signal (SPS) from the detection circuit 110, the protection circuit 120 reduces the gate voltage (VG) based on the voltage level of the short circuit protection signal (SPS). This turns off the high electron mobility transistor (H1) or reduces the magnitude of the short circuit current flowing between the drain electrode and the source electrode of the high electron mobility transistor (H1). In this embodiment, the time from immediately after a short circuit occurs until the protection circuit 120 reduces the gate voltage (VG) is shorter than the short circuit withstand time (SCWT) of the high electron mobility transistor (H1).

[0039] After receiving the control signal (CS) and the short circuit protection signal (SPS), the gate driver 20 outputs a gate voltage (VG) that turns on or off the high electron mobility transistor (H1) based on the control signal (CS) and the short circuit protection signal (SPS). When the peripheral circuit of the high electron mobility transistor (H1) is in a short circuit state, the gate driver 20 outputs a gate voltage (VG) that turns off the high electron mobility transistor (H1), completely turning off the high electron mobility transistor (H1). In this way, the gate driver 20 protects the high electron mobility transistor (H1) from damage due to short circuit current.

[0040] According to this embodiment, when a short circuit occurs, two steps are taken to prevent the high electron mobility transistor H1 from being destroyed, thereby effectively protecting the high electron mobility transistor H1 in a short circuit situation. When a short circuit occurs around the high electron mobility transistor H1, in a first step, the protection circuit 120 reduces the gate voltage V within the short circuit withstand time (SCWT) of the high electron mobility transistor H1 to reduce the magnitude of the short circuit current flowing between the drain and source electrodes of the high electron mobility transistor H1. In a second step, the gate driver 20 outputs a gate voltage V that turns off the high electron mobility transistor H1, completely turning off the high electron mobility transistor H1.

[0041] A semiconductor device according to an embodiment includes a short circuit detection circuit that detects a short circuit state, and a protection circuit that reduces a gate voltage within a short circuit withstand time (SCWT) based on a short circuit protection voltage output from the short circuit detection circuit. According to the embodiment, by reducing the gate voltage of the high electron mobility transistor within the short circuit withstand time in a short circuit state, it is possible to prevent damage to the high electron mobility transistor due to a short circuit current, thereby improving the reliability of the high electron mobility transistor.

[0042] 5 is a graph showing the current and voltage characteristics of the high electron mobility transistor (H1) in a normal state and a short circuit state. Specifically, FIG. 5 is a graph showing the magnitudes of VGS, VDS, and IDS over time in a normal state and a short circuit state. VGS is the voltage between the gate electrode and drain electrode of the high electron mobility transistor (H1), VDS is the voltage between the drain electrode and source electrode of the high electron mobility transistor (H1), and IDS indicates the magnitude of the current flowing between the drain electrode and source electrode of the high electron mobility transistor (H1).

[0043] In a normal state, the turn-on gate voltage (VG) is applied to the gate electrode of the high electron mobility transistor (H1) from the gate driver 20 described with reference to Figure 3. The gate-source voltage difference (VGS) gradually increases and remains constant for a predetermined time (t2 to t3) due to the Miller effect, and then reaches a maximum value (VGS MAX ) The drain-source voltage difference (VDS) reaches a maximum value (VDS MAX ), which maintains a constant value for a predetermined period (t0 to t2), decreases from t2, and reaches the lowest value (VDS MIN ) The drain-source current (IDS) begins to increase when the gate-source voltage difference (VGS) exceeds the threshold voltage (VTH) of the high electron mobility transistor (H1), and saturates at t2. The high electron mobility transistor (H1) is designed to operate in the linear region under normal conditions.

[0044] In a short circuit state, a very high level voltage is applied between the drain and source electrodes of the high electron mobility transistor H1. For example, if a short circuit occurs in the vicinity of the circuit connected to the drain electrode of the high electron mobility transistor H1, a very high level voltage is applied between the drain and source electrodes of the high electron mobility transistor H1 due to the short circuit current flowing through the drain electrode of the high electron mobility transistor H1. In this case, the high electron mobility transistor H1 operates in the saturation region.

[0045] In a short circuit state, the gate driver 20 described with reference to Figure 3 applies a turn-on gate voltage (VG) to the gate electrode of the high electron mobility transistor (H1). The gate-source voltage difference (VGS) gradually increases and reaches a maximum value (VGS MAX ) in this case, unlike the normal state, there is no period (t2 to t3) where the gate-source voltage difference (VGS) maintains a constant value. In the short circuit state, unlike the normal state, even if the high electron mobility transistor (H1) is turned on, the drain-source voltage difference (VDS) does not decrease and reaches the maximum value (VDS MAX Specifically, the drain-source voltage difference (VDS) decreases over a predetermined period and then reaches the maximum value (VDS MAX ) (t2~t3).

[0046] That is, when a turn-on gate voltage (VG) is applied to the gate electrode of the high electron mobility transistor (H1) in a short circuit state, the gate-source voltage difference (VGS) and the drain-source voltage difference (VDS) all have maximum values.

[0047] In a short circuit state, the high electron mobility transistor (H1) operates in the saturation region, so the drain-source current (IDS) gradually increases and the gate-source voltage difference (VGS) reaches a maximum value (VGSMAX ) (T5), the saturation current (IDS SAT ) is reached. SAT ) and the drain-source voltage difference (VDS) is the maximum value (VDS MAX ), a very high power loss continues to occur across the high electron mobility transistor H1 due to P (power) = V (voltage) × I (current), which may cause the high electron mobility transistor H1 to break down after a predetermined time t6 has elapsed. At this time, the short circuit withstand time (SCWT) of the high electron mobility transistor H1 is t6 - t0.

[0048] 6 to 8 are diagrams specifically illustrating the operation of the gate driver and the short-circuit protection device according to the embodiment.

[0049] FIG. 6 is a circuit diagram showing the configuration of a gate driver and a semiconductor device according to an embodiment. Referring to FIG. 6, the gate driver 20 includes a pull-up transistor (UT), a pull-down transistor (DT) connected in series with the pull-up transistor (UT), and a first capacitor (C1) connected in parallel with the pull-up transistor (UT) and the pull-down transistor (DT). The drain of the pull-up transistor (UT) and a first electrode of the first capacitor (C1) are connected to a second power supply voltage (VDD). The source of the pull-down transistor (DT) and a second electrode of the first capacitor (C1) are connected to a first power supply voltage (VSS). In some embodiments, the first power supply voltage (VSS) has a lower level than the second power supply voltage (VDD). However, this is not limiting, and in some other embodiments, the first power supply voltage (VSS) may have a higher level than the second power supply voltage (VDD). 6, in some embodiments, the first power supply voltage (VSS) may be coupled to the source electrode (VS) of the high electron mobility transistor (H1). The source electrode of the pull-up transistor (UT), the drain electrode of the pull-down transistor (DT), and the gate electrode of the first high electron mobility transistor (H1) are coupled to the output node (NO). In some embodiments, the pull-up transistor (UT) and the pull-down transistor (DT) are NMOS transistors. However, without limitation, in other embodiments, either the pull-up transistor (UT) or the pull-down transistor (DT) may be a PMOS transistor.

[0050] When the first high electron mobility transistor (H1) is turned on, a first level pull-up signal (GU) is applied to the gate electrode of the pull-up transistor (UT). The first level is a voltage that turns on the pull-up transistor (UT), and in this embodiment, the potential difference between the first level of the pull-up signal (GU) and the output node (NO) is higher than the threshold voltage of the pull-up transistor (UT). When the first high electron mobility transistor (H1) is turned on, a second level pull-down signal (GD) is applied to the gate electrode of the pull-down transistor (DT). The second level is a voltage that turns off the pull-down transistor (DT). With the pull-up transistor (UT) turned on and the pull-down transistor (DT) turned off, the second power supply voltage (VDD) is applied to the gate electrode of the first high electron mobility transistor (H1). A second power supply voltage (VDD) having a voltage level higher than the threshold voltage of the first high electron mobility transistor (H1) is applied to the gate electrode of the first high electron mobility transistor (H1), thereby turning on the first high electron mobility transistor (H1).

[0051] When the first high electron mobility transistor (H1) is turned off, a first level pull-down signal (GD) is applied to the gate of the pull-down transistor (DT). The first level is a voltage that turns on the pull-down transistor (DT). In this embodiment, the potential difference between the first level of the pull-down signal (GD) and the first power supply voltage (VSS) is higher than the threshold voltage of the pull-down transistor (DT). When the first high electron mobility transistor (H1) is turned off, a second level pull-up signal (GU) is applied to the gate of the pull-up transistor (UT). The second level is a voltage that turns off the pull-up transistor (UT). When the pull-up transistor (UT) is turned off and the pull-down transistor (DT) is turned on, the charge stored in the gate of the first high electron mobility transistor (H1) is released to the outside via the first power supply voltage (VSS), and the first high electron mobility transistor (H1) is turned off.

[0052] The first capacitor C1 is a decoupling capacitor. For example, when the first high electron mobility transistor H1 is turned off, the voltage of the gate electrode of the first high electron mobility transistor H1 drops sharply to the same level as the first power supply voltage VSS. At this time, the voltage of the drain electrode of the pull-up transistor UT is not affected by the voltage of the gate electrode of the first high electron mobility transistor H1 and is maintained at the same level as the second power supply voltage VSS due to the first capacitor C1.

[0053] 6, the detection circuit 110 includes a logic gate (AG), and the protection circuit 120 includes a first transistor (T1). The logic gate (AG) receives a gate voltage (VG) and a drain voltage (VD) as input signals and outputs a short-circuit protection voltage (VP). The short-circuit protection voltage (VP) is the short-circuit protection signal (SPS) described with reference to FIG. 3. In this embodiment, the logic gate (AG) is an AND gate.

[0054] The logic gate (AG) compares the drain voltage (VD) and gate voltage (VG) with first and second reference voltages (VREF1, VREF2), respectively, and outputs different levels of short circuit protection voltages (VP) based on the comparison. In some embodiments, the reference voltages (VREF1, VREF2) are reference voltages that determine whether a signal input to the logic gate (AG) is logic high or logic low. In some embodiments, the first reference voltage (VREF1) is the maximum value of VDS (VDS) in the graph of VDS described with reference to FIG. 5. MAX ) and the minimum value (VDS MIN ) is set to have a level greater than the gate voltage (VG) that turns on the high electron mobility transistor (H1). In some embodiments, the second reference voltage (VREF2) is set to have a level less than the gate voltage (VG) that turns on the high electron mobility transistor (H1) and greater than the gate voltage (VG) that turns off the high electron mobility transistor (H1). In some embodiments, the first reference voltage (VREF1) and the second reference voltage (VREF2) may have substantially the same level.

[0055] In this embodiment, the detection circuit 110 determines that the peripheral circuit of the high electron mobility transistor H1 is in a short circuit state when both the gate voltage (VG) and the drain voltage (VD) are high. In this case, the detection circuit 110 outputs a short circuit protection voltage (VP) to protect the high electron mobility transistor H1. Specifically, the logic gate AG outputs a first level short circuit protection voltage (VP) when the drain voltage (VD) is equal to or higher than the first reference voltage (VREF1) and the gate voltage (VG) is equal to or higher than the second reference voltage (VREF2). The first level short circuit protection voltage (VP) has a voltage level that turns on the first transistor T1. For example, the first level has a voltage level greater than or equal to the threshold voltage of the first transistor T1. When the first transistor (T1) is turned on, the second power supply voltage (VDD) is distributed across both ends of the two transistors (UT and T1) according to the ratio of the drain-source resistances (Rdson) of the pull-up transistor (UT) and the first transistor (T1). In this case, a lower gate voltage (VG) is applied to the gate electrode of the first high electron mobility transistor (H1) compared to when the first transistor (T1) is turned off. As a result, when a short circuit occurs, the first high electron mobility transistor (H1) is turned off, or the magnitude of the short circuit current flowing between the drain electrode and source electrode of the first high electron mobility transistor (H1) is reduced.

[0056] The gate driver 20 receives a short-circuit protection voltage (VP) and outputs a gate voltage (VG) that turns off the high electron mobility transistor (H1). In one embodiment, the gate driver 20 receives a control signal (CS) that turns on the pull-up transistor (UT) and the pull-down transistor (DT) and a first-level short-circuit protection voltage (VP). When the first-level short-circuit protection voltage (VP) is applied, the gate driver 20 generates a pull-up signal (GU) of a second level that turns off the pull-up transistor (UT) and a pull-down signal (GD) of a first level that turns on the pull-down transistor (DT), even if it receives the control signal (CS) that turns on the pull-up transistor (UT) and the pull-down transistor (DT). Therefore, the gate driver 20 outputs a gate voltage (VG) at the level of the first power supply voltage (VSS).

[0057] FIG. 7 is a flowchart illustrating the operation of the detection circuit according to the embodiment.

[0058] 7, in step S701, the detection circuit 110 receives a drain voltage (VD) and a gate voltage (VG). The detection circuit 110 determines whether a short circuit exists in the peripheral circuit based on the drain voltage (VD) and the gate voltage (VG), and then outputs a short protection voltage (VP) based on the determination.

[0059] In step S703, the detection circuit 110 compares the levels of the drain voltage (VD) and the gate voltage (VG) with the levels of the first reference voltage (VREF1) and the second reference voltage (VREF2), respectively. The detection circuit 110 determines whether the drain voltage (VD) is greater than or equal to the first reference voltage (VREF1) and whether the gate voltage (VG) is greater than or equal to the second reference voltage (VREF2).

[0060] If the drain voltage (VD) is equal to or greater than the first reference voltage (VREF1) and the gate voltage (VG) is equal to or greater than the second reference voltage (VREF2), the detection circuit 110 outputs a first-level short-circuit protection voltage (VP) (S705). The first-level short-circuit protection voltage (VP) has a voltage level that turns on the first transistor (T1) described with reference to FIG. 5. When the first transistor (T1) is turned on, the gate voltage (VG) of the high electron mobility transistor (H1, see FIG. 5) decreases.

[0061] The detection circuit 110 outputs a second-level short-circuit protection voltage (VP) when either the drain voltage (VD) or the gate voltage (VG) is smaller than the reference voltages (VREF1, VREF2) (S707). For example, when the drain voltage (VD) is smaller than the first reference voltage (VREF1), when the gate voltage (VG) is smaller than the second reference voltage (VREF2), or when the drain voltage (VD) is smaller than the first reference voltage (VREF1) and the gate voltage (VG) is smaller than the second reference voltage (VREF2), the detection circuit 110 outputs the second-level short-circuit protection voltage (VP). The second-level short-circuit protection voltage (VP) has a voltage level that turns off the first transistor (T1) described with reference to FIG. 5.

[0062] FIG. 8 is a flowchart for explaining the operation of the gate driver 20 according to the embodiment.

[0063] In step S801, the gate driver 20 receives a control signal (CS) from the outside and a short circuit protection voltage (VP) from the detection circuit 110. The control signal (CS) is a signal for controlling the gate driver 20. For example, the control signal (CS) is a turn-on control signal for turning on the high electron mobility transistor (H1) or a turn-off control signal for turning off the high electron mobility transistor (H1). The gate driver 20 outputs a gate voltage (VG) for turning on the high electron mobility transistor (H1) or a gate voltage (VG) for turning off the high electron mobility transistor (H1) based on the control signal (CS).

[0064] In step S803, the gate driver 20 determines whether the control signal (CS) is a turn-on control signal or a turn-off control signal.

[0065] If the control signal (CS) is not a turn-on control signal, the gate driver 20 outputs a third-level gate voltage (VG) (S805). The third level is a voltage level that turns off the high electron mobility transistor (H1). For example, the third level has a voltage level lower than the threshold voltage of the high electron mobility transistor (H1). When the third-level gate voltage is applied to the gate electrode of the high electron mobility transistor (H1), the high electron mobility transistor (H1) turns off.

[0066] If the control signal (CS) is a turn-on control signal, the gate driver 20 determines whether the short-circuit protection voltage (VP) has a first level (S807). The first level is a voltage level that turns on the first transistor (T1) described with reference to FIG. 6. If the short-circuit protection voltage (VP) has the first level, the gate driver 20 outputs a gate voltage (VG) of a third level (S805).

[0067] When the short circuit protection voltage (VP) is not at the first level, the gate driver 20 outputs a gate voltage (VG) at a fourth level. The fourth level is a voltage level that turns on the high electron mobility transistor (H1). For example, the fourth level is a voltage level higher than the threshold voltage of the high electron mobility transistor (H1). When the gate voltage at the fourth level is applied to the gate electrode of the high electron mobility transistor (H1), the high electron mobility transistor (H1) turns on.

[0068] 9 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment, specifically, a circuit diagram showing the logic gate (AG) described with reference to FIG.

[0069] 9, the logic gate AG includes a second transistor T2 connected between a drain electrode of a high electron mobility transistor H1 and a first node N1, and a first resistor R1 connected between a first power supply voltage VSS and the first node N1. The gate electrode of the second transistor T2 is connected to the output terminal of the gate driver 20 or the gate electrode of the high electron mobility transistor H1.

[0070] In this embodiment, the second transistor T2 and the first resistor R1 operate together as an AND gate. The gate electrode and drain electrode of the second transistor T2 function as two inputs of the AND gate, respectively. Referring to FIG. 9, the gate electrode of the second transistor T2 receives a gate voltage VG output from the gate driver 20. The drain electrode of the second transistor T2 receives a drain voltage VD of the high electron mobility transistor H1. The first node N1 is the output node of the AND gate. When a high gate voltage VG, for example, the fourth level gate voltage described with reference to FIG. 8, is input to the gate electrode of the second transistor T2, the second transistor T2 is turned on and outputs a short circuit protection voltage VP (see FIG. 6) via the first node N1. The voltage level of the short circuit protection voltage VP can be adjusted depending on the resistance value of the first resistor R1. In this embodiment, the resistance value of the first resistor (R1) is selected so that when a high voltage is input to both the gate electrode and the drain electrode of the second transistor (T2), a short circuit protection voltage (VP) higher than the threshold voltage of the first transistor (T1) is output from the first node (N1).

[0071] 10 and 11 are circuit diagrams showing a gate driver and a semiconductor device according to an embodiment. The gate driver 20 and the semiconductor device 30 shown in FIGS. 10 and 11 correspond to the same parts as those in the previously described embodiment, so a description thereof will be omitted and the following description will focus on the differences. The semiconductor device 30 according to the embodiment differs from the previously described embodiment in that it further includes a first voltage regulator 201. Referring to FIGS. 10 and 11, the detection circuit 110 according to the embodiment further includes a first voltage regulator 201 located between the logic gate AG and the drain electrode of the high electron mobility transistor H1.

[0072] The first voltage regulator 201 includes a clipper circuit. For example, the first voltage regulator 201 adjusts the voltage level of the drain voltage (VD) input to the input terminal of the logic gate (AG). When a short circuit occurs, a very high drain voltage (VD) is applied to the drain electrode of the high electron mobility transistor (H1). The first voltage regulator 201 adjusts the drain voltage (VD) to an appropriate level (e.g., a voltage lower than the drain voltage (VD)) and then provides it to the input terminal of the logic gate (AG).

[0073] 11, the first voltage regulator 201 includes a third transistor T3 connected between the drain electrode of the high electron mobility transistor H1 and the second transistor T2, and a second resistor R2 connected between a second node N2 between the second transistor T2 and the third transistor T3 and a first power supply voltage VSS. A second power supply voltage VDD is applied to the gate electrode of the third transistor T3. The third transistor T3 is turned on by the second power supply voltage VDD and adjusts the voltage level of the drain voltage VD and outputs it to the second node N2. In this embodiment, the voltage level at the second node N2 is lower than the drain voltage VD. The voltage at the second node N2 can be adjusted according to the resistance value of the second resistor R2.

[0074] 12 and 13 are circuit diagrams showing a gate driver and a semiconductor device according to an embodiment. The gate driver 20 and the semiconductor device 30 shown in FIGS. 12 and 13 correspond to the same parts as those in the previously described embodiment, so a description thereof will be omitted and the following description will focus on the differences. The semiconductor device 30 according to the embodiment differs from the previously described embodiment in that it further includes a second voltage regulator 203. Referring to FIGS. 12 and 13, the detection circuit 110 according to the embodiment further includes a second voltage regulator 203 located between the logic gate AG and the gate electrode of the high electron mobility transistor H1.

[0075] The second voltage regulator 203 further includes a voltage divider. For example, the second voltage regulator 203 may adjust the voltage level of the gate voltage VG input to the input terminal of the logic gate AG. The second voltage regulator 203 adjusts the gate voltage VG to an appropriate level and then provides it to the input terminal of the logic gate AG.

[0076] 13, the second voltage regulator 203 includes a fourth transistor T4 connected between the gate electrode of the high electron mobility transistor H1 and the gate electrode of the second transistor T2, and a third resistor R3 connected between a third node N3 between the gate electrodes of the fourth transistor T4 and the second transistor T2 and the first power supply voltage VSS. The gate electrode of the fourth transistor T4 is connected to the drain electrode of the fourth transistor T4. The fourth transistor T4 is turned on when the gate voltage VG is a high voltage, for example, the fourth level gate voltage described with reference to FIG. 8. At this time, the voltage at the third node N3 can be adjusted according to the resistance value of the third resistor R3.

[0077] 14 to 16 are circuit diagrams showing a gate driver and a semiconductor device according to an embodiment. The gate driver 20 and the semiconductor device 30 shown in FIGS. 14 to 16 correspond to the same parts as those of the previously described embodiment, so a description thereof will be omitted and the following description will focus on the differences. The semiconductor device 30 according to the embodiment differs from the previous embodiment in that it further includes a third voltage regulator 205. Referring to FIGS. 14 to 16, the detection circuit 110 according to the embodiment further includes a third voltage regulator 205 located between the output terminal of the logic gate AG and the gate electrode of the first transistor T1.

[0078] The third voltage regulator 205 includes a digitizer circuit that converts an analog signal into a digital signal. The third voltage regulator 205 converts the voltage signal output from the output terminal of the logic gate (AG) into a digital signal and outputs it to the outside as a short circuit protection voltage (VP).

[0079] 15, the third voltage regulator 205 includes two inverter circuits (NG1, NG2) connected in series. The first inverter circuit (NG1) is connected between the output terminal of the logic gate (AG) and the input terminal of the second inverter circuit (NG2). The second inverter circuit is connected between the output terminal of the first inverter circuit (NG1) and the gate electrode of the first transistor (T1). In this embodiment, the first inverter circuit (NG1) converts the voltage signal output from the logic gate (AG) into a digital signal and outputs it. In this embodiment, the second inverter circuit (NG2) inverts the digital signal output from the first inverter circuit (NG1) and outputs it to the outside as a short circuit protection voltage (VP).

[0080] 16, the third voltage regulator 205 includes a fifth transistor T5 connected between a fourth node N4 and a first power supply voltage VSS and having a gate electrode connected to the first node N1, and a fourth resistor R4 connected between the fourth node N4 and a second power supply voltage VDD. The fifth transistor T5 and the fourth resistor R4 together operate as a first inverter circuit NG1.

[0081] The third voltage regulator 205 further includes a sixth transistor T6 connected between a fifth node N5 and the first power supply voltage VSS and having its gate electrode connected to the fourth node N4, and a fifth resistor R5 connected between the fifth node N5 and the second power supply voltage VDD. The fifth node N5 is connected to the gate electrode of the first transistor T1 and the gate driver 20. The sixth transistor T6 and the fifth resistor R5 together operate as a second inverter circuit NG2.

[0082] In FIG. 16, when the potential difference between the voltage of the first node N1 and the first power supply voltage VSS is a high voltage, for example, a voltage higher than the threshold voltage of the fifth transistor T5, the fifth transistor T5 turns on. At this time, the first power supply voltage VSS is applied to the fourth node N4. When the voltage of the fourth node N4 is the first power supply voltage VSS, the sixth transistor T6 turns off. At this time, the second power supply voltage VDD is applied to the fifth node N5. In this embodiment, the potential difference between the second power supply voltage VDD and the first power supply voltage VSS is higher than the threshold voltage of the first transistor T1. As a result, the first transistor T1 turns on.

[0083] When the potential difference between the voltage of the first node N1 and the first power supply voltage VSS is a low voltage, e.g., lower than the threshold voltage of the fifth transistor T5, the fifth transistor T5 turns off. At this time, the second power supply voltage VDD is applied to the fourth node N4. When the voltage of the fourth node N4 is the second power supply voltage VDD, the sixth transistor T6 turns on. At this time, the first power supply voltage VSS is applied to the fifth node N5. As a result, the first transistor T1 turns off.

[0084] FIG. 17 is a circuit diagram showing a gate driver and a semiconductor device according to an embodiment.

[0085] 17 are the same as those in the previously described embodiment, so a description thereof will be omitted and the following description will focus on the differences. The semiconductor device 30 according to this embodiment differs from the previously described embodiment in that the third voltage regulator 205 further includes a voltage divider.

[0086] 17, the third voltage regulator 205 according to the embodiment includes an inverter circuit 205a and a voltage adjustment circuit 205b connected between the inverter circuit 205a and a logic gate AG. The voltage adjustment circuit 205b is a voltage divider. For example, the voltage adjustment circuit 205b adjusts the voltage level of a voltage input to an input terminal (e.g., a gate electrode of a fifth transistor T5) of the first inverter circuit NG1. The voltage adjustment circuit 205b adjusts the voltage output from the output terminal (e.g., a first node N1) of the logic gate AG to an appropriate level and then provides the adjusted voltage to the input terminal (e.g., a gate electrode of a fifth transistor T5) of the first inverter circuit NG1.

[0087] The voltage adjustment circuit 205b includes a seventh transistor T7 connected between the first node N1 and the gate electrode of the fifth transistor T5, and a sixth resistor R6 connected between a sixth node N6 between the gate electrode of the fifth transistor T5 and the seventh transistor T7 and the first power supply voltage VSS. The gate electrode of the seventh transistor T7 is connected to the drain electrode of the seventh transistor T7. The seventh transistor T7 turns on when the voltage output from the first node N1 is high. At this time, the voltage at the sixth node N6 is adjusted according to the resistance value of the sixth resistor R6.

[0088] Although the embodiments of the present invention have been described in detail above, the technical scope of the present invention is not limited to these, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention also fall within the technical scope of the present invention. [Explanation of symbols]

[0089] CS control signal VG Gate voltage VD drain voltage VS Source Voltage VDD Second power supply voltage VSS First power supply voltage VP Short circuit protection voltage H1 high electron mobility transistor OCS output control signal SPS Short Circuit Protection Signal 10 Power Semiconductor Systems 20 Gate Driver 21 Signal generator 22 Amplifier 30 Semiconductor devices (power devices) 100 Short-circuit protection device 110 Detection circuit 120 Protection circuit 201 First voltage regulator 203 Second voltage regulator 205 Third voltage regulator

Claims

1. a high electron mobility transistor (H1); a short circuit detection circuit (110) that outputs a short circuit protection voltage based on a gate voltage (VG) of the high electron mobility transistor and a drain voltage of the high electron mobility transistor; a protection circuit (120) that reduces a gate voltage of the high electron mobility transistor based on the short circuit protection voltage.

2. 2. The semiconductor device of claim 1, wherein the protection circuit comprises a first transistor (T1) having a gate electrode connected between the gate electrode of the high electron mobility transistor and a first power supply voltage (VSS) and receiving the short circuit protection voltage.

3. The short circuit detection circuit 3. The semiconductor device according to claim 2, further comprising an AND gate circuit including a first input terminal that receives an input of a gate voltage of the high electron mobility transistor, a second input terminal that receives an input of a drain voltage of the high electron mobility transistor, and an output terminal that outputs the short circuit protection voltage.

4. the AND gate circuit outputs a first level short circuit protection voltage when the drain voltage of the high electron mobility transistor and the gate voltage of the high electron mobility transistor have a level higher than a reference voltage; outputting a short circuit protection voltage of a second level lower than the first level when at least one of the drain voltage of the high electron mobility transistor and the gate voltage of the high electron mobility transistor has a level lower than the reference voltage; the first level is greater than or equal to a threshold voltage of the first transistor, and the second level is less than a threshold voltage of the first transistor; 4. The semiconductor device according to claim 3, wherein the second level is lower than the first level.

5. The AND gate circuit is a second transistor connected between the drain electrode of the high electron mobility transistor and a first node connected to the gate electrode of the first transistor, the second transistor having a gate electrode connected to the gate electrode of the high electron mobility transistor; 4. The semiconductor device according to claim 3, further comprising: a first resistor (R1) connected between the first power supply voltage and the first node.

6. The high electron mobility transistor further includes a first voltage regulator (201) connected between the drain electrode of the high electron mobility transistor and the second input terminal; The first voltage regulator a third transistor (T3) connected between the drain electrode of the high electron mobility transistor and the second transistor, the gate electrode of which is connected to a second power supply voltage (VDD); 6. The semiconductor device of claim 5, further comprising: a second resistor (R2) connected between the third transistor and the first power supply voltage (VSS).

7. a second voltage regulator (203) connected between the gate electrode of the high electron mobility transistor and the first input terminal of the AND gate circuit; The second voltage regulator a fourth transistor connected between the gate electrode of the high electron mobility transistor and the gate electrode of the second transistor; a third resistor connected between the fourth transistor and the first power supply voltage; 6. The semiconductor device according to claim 5, wherein the fourth transistor has a source electrode and a gate electrode connected to each other.

8. a third voltage regulator (205) connected between the output terminal of the AND gate circuit and the gate electrode of the first transistor; 6. The semiconductor device of claim 5, wherein the third voltage regulator comprises an even number of inverter circuits connected in series with each other.

9. a third voltage regulator (205) coupled between the first node and the gate electrode of the first transistor; The third voltage regulator (205) a fifth transistor (T5) connected between a second node and the first power supply voltage (VSS) and having a gate electrode connected to the first node; a fourth resistor R4 connected between the second node and a second power supply voltage VDD; a sixth transistor (T6) connected between a third node and the first power supply voltage (VSS) and having a gate electrode connected to the second node; a fifth resistor (R5) connected between the third node and the second power supply voltage (VDD); 6. The semiconductor device according to claim 5, wherein a gate electrode of the first transistor is connected to the third node.

10. The third voltage regulator a seventh transistor connected between a fourth node and the first node; a sixth resistor (R6) connected between the fourth node and the first power supply voltage (VSS), a gate electrode of the fifth transistor is connected to the fourth node; 10. The semiconductor device of claim 9, wherein a gate electrode of the seventh transistor is connected to a source electrode of the seventh transistor.

11. a high electron mobility transistor (H1); a first transistor (T1) connected between a gate electrode of the high electron mobility transistor and a second power supply voltage, the gate electrode of the first transistor being connected to a first node; a second transistor (T2) connected between the drain electrode of the high electron mobility transistor and the first node, the second transistor (T2) having a gate electrode connected to the gate electrode of the high electron mobility transistor; a first resistor (R1) connected between the first node and the second power supply voltage.

12. a third transistor (T3) connected between the drain electrode of the high electron mobility transistor and the second transistor, the gate electrode of which is connected to a second power supply voltage (VDD); 12. The semiconductor device of claim 11, further comprising: a second resistor (R2) connected between the third transistor and a first power supply voltage.

13. a fourth transistor connected between the gate electrode of the high electron mobility transistor and the gate electrode of the second transistor; a third resistor connected between the fourth transistor and the first power supply voltage; The semiconductor device of claim 11, wherein the fourth transistor has a source electrode and a gate electrode connected to each other.

14. a fifth transistor (T5) connected between a second node and the first power supply voltage (VSS) and having a gate electrode connected to the first node; a fourth resistor (R4) connected between the second node and the second power supply voltage (VDD); a sixth transistor (T6) connected between a third node and the first power supply voltage (VSS) and having a gate electrode connected to the second node; a fifth resistor (R5) connected between the third node and the second power supply voltage (VDD); 12. The semiconductor device of claim 11, wherein a gate electrode of the first transistor is connected to the third node.

15. a seventh transistor connected between a fourth node and the first node; a sixth resistor R6 connected between the fourth node and the first power supply voltage; a gate electrode of the fifth transistor is connected to the fourth node; 15. The semiconductor device of claim 14, wherein a gate electrode of the seventh transistor is connected to a source electrode of the seventh transistor.

16. a high electron mobility transistor (H1); a gate driver (20) that outputs a gate voltage (VG) to the gate electrode of the high electron mobility transistor; a short circuit protection device (100) coupled to the gate electrode of the high electron mobility transistor; The short circuit protection device (100) a short circuit detection circuit that outputs a short circuit protection voltage based on the gate voltage and the drain voltage of the high electron mobility transistor; a protection circuit that reduces a gate voltage of the high electron mobility transistor based on the short circuit protection voltage.

17. 17. The power semiconductor system of claim 16, wherein the protection circuit comprises a first transistor having a gate electrode connected between a gate electrode of the high electron mobility transistor and a first power supply voltage (VSS), the first transistor receiving the short circuit protection voltage.

18. The short circuit detection circuit an AND gate circuit including a first input terminal for receiving the gate voltage, a second input terminal for receiving the drain voltage of the high electron mobility transistor, and an output terminal for outputting the short circuit protection voltage; the AND gate circuit outputs a first level short circuit protection voltage when the drain voltage of the high electron mobility transistor and the gate voltage have a level higher than a reference voltage; outputting a short circuit protection voltage of a second level lower than the first level when at least one of the drain voltage and the gate voltage of the high electron mobility transistor has a level lower than the reference voltage; the first level is greater than or equal to a threshold voltage of the first transistor, and the second level is less than a threshold voltage of the first transistor; 17. The power semiconductor system of claim 16, wherein the second level is less than the first level.

19. The gate driver outputting a third level gate voltage for turning on the high electron mobility transistor or a fourth level gate voltage for turning off the high electron mobility transistor based on a control signal (CS) received from an external device and the short circuit protection voltage; 20. The power semiconductor system of claim 18, wherein when the short circuit protection voltage has the first level, a gate voltage of a third level is output to turn off the high electron mobility transistor.

20. The gate driver a pull-up transistor connected between an output node to which the gate voltage is output and a second power supply voltage, and a pull-down transistor connected between the output node and a first power supply voltage (VSS); 20. The power semiconductor system of claim 18, wherein when the short circuit protection voltage has the first level, the pull-up transistor is turned off and the pull-down transistor is turned on.

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