Laminate parametric measurement unit test circuit

Abstract

To provide a test circuit for improving efficiency, reliability and safety of a battery pack.SOLUTION: A test circuit 100 may comprise a laminate precision parametric measurement unit (PMU) including a precision voltage source 114 series connected to a common-mode (CM) power source 112. A common-mode voltage source may include a voltage source configured to supply voltage in a relatively wide range (for example, -100 V to 100 V) suitable for testing a DUT 130 including a battery management system integrated circuit (BMSIC). In contrast, a precision voltage source may include a voltage source that supplies and measures voltage over a relatively small range (for example, -2 V to 6 V to the common-mode voltage source) with higher accuracy (for example, voltage step in 30 to 300 uV).SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. patent application Ser. No. 19 / 076,762, filed Mar. 11, 2025, entitled "STACKED PARAMETRIC MEASUREMENT UNIT TEST CIRCUIT," which in turn claims priority to and the benefit of U.S. provisional patent application Ser. No. 63 / 571,994, filed Mar. 29, 2024, entitled "STACKED PARAMETRIC MEASUREMENT UNIT TEST CIRCUIT," which is incorporated herein by reference in its entirety.

[0002] Electric vehicles (EVs) of all types (including hybrids) are becoming more popular as consumers increasingly adopt sustainable energy-based technologies. Relatedly, the installation of solar panels and stationary battery energy storage systems (BESS) is increasing as homeowners and businesses increase their use of renewable solar energy. The above-referenced trends in EVs and BESS are being accelerated by government mandates worldwide.

[0003] A key component of EVs and BESSs is the battery pack. Battery packs typically include a matrix of interconnected lithium-ion cells. A particular battery pack can include multiple battery modules, each including multiple lithium-ion batteries stacked in series. The battery modules may be connected to each other, for example, via electrical bus bars. Modern battery packs in EVs and BESSs can be quite large. For example, an exemplary battery pack may include four battery modules, each including a matrix of cells connected in series and / or parallel. For example, an exemplary battery module may include 6 to 30 cells in series and 50 to 80 cells in parallel, providing a total of 300 to 2400 cells.

[0004] The present disclosure, in accordance with one or more various examples, will now be described in detail with reference to the following figures, which are provided for illustrative purposes only and are merely exemplary. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 2 illustrates an exemplary test circuit in accordance with various examples of the techniques of this disclosure. [Figure 2] FIG. 1 illustrates another exemplary test circuit in accordance with various examples of the techniques of this disclosure. [Figure 3] FIG. 1 illustrates another exemplary test circuit in accordance with various examples of the techniques of this disclosure. [Figure 4] 4 illustrates an expanded view of an example parametric measurement unit (PMU) from the test circuit of FIG. 3, in accordance with various examples of the techniques of this disclosure. [Figure 5] 4 illustrates an expanded view of an exemplary isolated power supply from the test circuit of FIG. 3, in accordance with various examples of the techniques of this disclosure. [Figure 6] 4A-4C are diagrams illustrating expanded views of example common-mode voltage sources from the test circuit of FIG. 3, in accordance with various examples of the techniques of this disclosure. [Figure 7] 4A-4C illustrate expanded views of example configuration switches from the test circuit of FIG. 3, in accordance with various examples of the techniques of this disclosure. [Figure 8] FIG. 1 illustrates another exemplary test circuit in accordance with various examples of the techniques of this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] The drawings are not exhaustive and are not intended to limit the disclosure to the precise form disclosed.

[0007] While battery-based EVs and BESSs can reduce reliance on fossil fuels, the use of lithium-ion batteries and other cell technologies brings new safety, long-term reliability, and efficiency challenges that can be addressed by specially designed battery management systems (BMS).

[0008] An exemplary BMS may include a BMS controller and a set of BMS integrated circuits (BMS ICs). The BMS ICs, typically one per battery module, can measure various parameters (e.g., voltage, current, temperature, etc.) at several locations in the battery pack. These measured parameters can be provided to algorithms running on the BMS controller, such as a battery fuel gauge algorithm and an optimal charging algorithm. Utilizing these algorithms, the BMS controller can optimize (or improve) battery pack system-level metrics such as state of charge (SOC) and state of health (SOH). The BMS controller can also balance electric and thermal cells to improve the efficiency, reliability, and safety of the battery pack.

[0009] Many BMSs are designed to meet stringent electrical specifications to improve and optimize performance and reliability. For example, the BMS's analog front end (AFE) and analog-to-digital converter (ADC), which digitize cell and busbar voltages, are often designed to have microvolt (uV) accuracy and precision. This is because a typical cell's discharge curve is relatively flat, which means that cell voltages should be measured with fine granularity to predict cell SOC. As another example, the BMS's voltage sensing circuitry is often designed to draw very low currents, typically in the microampere (uA) range, to reduce the amount the BMS discharges battery pack cells (here, discharging by the BMS is undesirable because charging resources are used to power EV and BESS systems). BMS charge balancing circuits are also often designed to meet stringent terminal input impedance specifications.

[0010] While a BMS can play an important role in improving the safety, long-term reliability, and efficiency of EVs and BESSs, a BMS is often only as reliable as it can be tested. Therefore, the circuitry used to test a BMS (BMS test circuitry) may also play an important role in improving the safety, long-term reliability, and efficiency of battery-based products, including EVs and BESSs.

[0011] However, designing BMS test circuits can be a serious challenge, due in part to (a) the stringent electrical specifications to which BMSs are designed and (b) the increasing size of battery packs (e.g., a single stack may contain anywhere from 6 to as many as 30 cells interconnected in series).

[0012] For example, BMS test circuits (often implemented using ICs) generally should be as accurate / precise as the BMS device under test (DUT). Therefore, BMS test circuits are often designed to measure and source voltages with uV granularity (e.g., steps of approximately 30 to 300 uV granularity). Similarly, BMS test circuits are often designed to measure and source low currents, on the order of approximately 300 nA to 1 uA, with a high level of precision. Further complicating the above challenges is the fact that, as battery pack sizes increase, these tests are often performed at high voltages to emulate the top cell of a series-connected stack. Generally, voltage sources that provide high voltages with high accuracy / granularity are expensive and have large form factors. This can be problematic when chip space is already at a premium for BMS test circuits due to the increasingly large number of cells contained in modern battery modules. For example, BMS test circuits are often designed to emulate battery modules. For example, if a battery module includes 16 cells, a conventional BMS test circuit would typically require 16 channels just to emulate the voltage supplied by those 16 cells. Thus, the high channel density (i.e., the density of channels) on many BMS test circuits can limit the size available for circuit components such as large form factor voltage sources.

[0013] Embodiments of the disclosed technology may be implemented to provide a new, compact circuit architecture designed to measure and source high voltages with high precision / granularity. Such a design is well suited for BMS test circuits and other applications requiring compact circuits for measuring and sourcing high voltages with high precision / granularity. Such a circuit architecture can also source and measure low currents with high precision, another feature that makes it well suited for BMS test circuits and many other applications.

[0014] For example, a test circuit of the disclosed technology may include a "stacked precision parametric measurement unit (PMU)" that includes a precision PMU connected in series with a common-mode (CM) voltage source / power supply. The common-mode voltage source may be configured to supply a relatively wide range of voltages (e.g., -100 V to 100 V) that may be suitable for testing BMS ICs. In contrast, a precision PMU may include a voltage source that sources / measures voltages with high precision and granularity (e.g., in uV steps, such as 30 to 300 uV voltage steps) over a relatively small range (e.g., -2 V to 6 V relative to the common-mode voltage source). Because the precision PMU can source / measure finer-grained voltage steps, the common-mode voltage source can be a lower-precision voltage source. Thus, the common-mode voltage source may have a smaller form factor (and lower cost) than alternative voltage sources that offer higher precision over a comparable voltage range. Relatedly (and as described in more detail below), connecting the precision PMU return line above a terminal at the output of the common-mode voltage source can help eliminate / reduce noise generated by the high-voltage common-mode voltage source by canceling the noise through the use of a floating ground and differential signaling. Thus, a higher noise and more power-efficient voltage source (e.g., an SMPS voltage source) can be used for the common-mode voltage source.

[0015] In some embodiments, the test circuitry may include a demultiplexer for connecting the output from the "stacked" PMU to the cell voltage (CV) and cell balance (CB) terminals of the device under test (DUT). In this manner, the test circuitry can support multiple DUT CV and CB terminals. The demultiplexer may be separate to support more flexibility, or may be integrated (e.g., an IC) with the PMU to reduce area on the device interface board (DIB). Exemplary demultiplexers may include transistor-based switches and circuits and / or include a microelectromechanical systems (MEMS) switching matrix.

[0016] Digital-to-analog converters (DACs) may also be used with "stacked" PMUs to drive DUT terminals in force-voltage (FV) or force-current (FI) modes, for example. Various types of DACs are possible, including DACs with various resolutions (e.g., 16-bit DACs) and various architectures (e.g., delta-sigma or Nyquist). The DACs can be integrated within the "stacked" PMU IC or provided externally as part of a separate IC and / or on a circuit board. Regardless of the drive mode, the "stacked" PMU's high-dynamic-range analog front-end can measure the response of DUT terminal voltages (e.g., between +25 V and -25 V) to uV accuracy in measure voltage (MV) mode. Similarly, the "stacked" PMU's high-dynamic-range analog front-end can measure DUT currents (e.g., between 2 uA and 1 A) in measure current (MI) mode.

[0017] As alluded to above, the "stacked" PMU can operate in any one or combination of force-voltage (FV) mode, force-current (FI) mode, measure-voltage (MV) mode, and measure-current (MI) mode. In FV mode, the channels of the "stacked" PMU may support output of a relatively wide range of voltages (e.g., from -100 V to 100 V) with fine accuracy (e.g., plus or minus 100 μV). In FI mode, the "stacked" PMU may be configured to provide current over a relatively wide range (e.g., from 1 μA to 1 A or more). These capabilities may enable the "stacked" PMU to test BMS ICs under several battery pack conditions and EV / BESS operating modes. In some implementations, by adjusting the "offset" of the voltage and / or current applied by the "stacked" PMU, the "stacked" PMU may be floated over a large + / - 100 V compliance range.

[0018] In certain embodiments, the "stacked" PMU may include one or more integrated clamp circuits to limit the voltage and / or current applied to the DUT, thereby protecting the DUT from overstress conditions outside its designed operating regime. Additionally, the precision PMU's channels may be equipped with alarm functions to detect temperature, voltage, current, and force / sense Kelvin faults. Monitor analog outputs may be included for connection to external components. Window comparators may be used to quickly compare measured parameters with predetermined thresholds.

[0019] In some embodiments, the "stacked" PMU may be configurable to use both internally generated precision signals (e.g., via one or more DACs) or external analog or digital test signals. In addition to setting static values, patterns may be programmed into embedded memory and output from the "stacked" PMU. The "stacked" PMU may include an embedded serial peripheral interface (SPI) peripheral that allows the "stacked" PMU to be controlled by embedded SPI controllers in various field programmable gate arrays (FPGAs), microprocessors, or other test equipment systems and / or circuits.

[0020] Exemplary embodiments are described in more detail below. It should be understood that various features, aspects, and functions described in one or more of the individual embodiments are not limited in their applicability to the particular embodiment described. Instead, they may be applied alone or in various combinations to one or more other embodiments, regardless of whether such an embodiment is described and whether such features are presented as part of the described embodiment. Therefore, the breadth and scope of the present application should not be limited by any of the exemplary embodiments described above.

[0021] FIG. 1 illustrates an exemplary test circuit 100 in accordance with various examples of the techniques of this disclosure.

[0022] As shown, test circuit 100 can be used to test DUT 130. In various examples, DUT 130 may, but need not, include a BMS IC.

[0023] In the example of FIG. 1, test circuit 100 includes stacked PMU 110 and demultiplexer 120 .

[0024] As shown, the exemplary stacked PMU 110 includes a common-mode voltage source 112 and a precision voltage source 114 electrically connected in series (e.g., “stacked”) with each other. The common-mode voltage source 112 may be connected between ground (e.g., a global ground or a true ground) and a “low-side” (i.e., lower voltage side) terminal of the precision voltage source 114, which can be used to apply a differential voltage to terminals (e.g., VC1, VC2) of the DUT 130.

[0025] In certain embodiments, the stacked PMU 110 may also include an ammeter 116 electrically connected in series with the precision voltage source 114. As shown, in some of these embodiments, the ammeter 116 may be electrically connected to a terminal of the precision voltage source 114 that is on the “high side” (i.e., the higher voltage side) of the precision voltage source 114. The combination of the precision voltage source 114 and the ammeter 116 may be referred to as a precision PMU. However, it should be understood that this is only one exemplary implementation / example of a precision PMU operating mode, which may also be referred to as a force-voltage measured current (FVMI) operating mode. Other exemplary implementations / exemplary operating modes may include (a) force-current measured voltage (FIMV), (b) force-current measured current (FIMI), and (c) force-voltage measured voltage (FVMV), which may be implemented using a current source connected in parallel with a voltmeter.

[0026] The stacked PMU 110 may also include a supply / high-pass 119 and a return / low-pass 118. The supply / high-pass 119 connects the high-side terminal of the precision voltage source 114 to the supply / high terminal 119(t). As described in more detail below, the demultiplexer 120 can connect the supply / high terminal 119(t) to the high-side (i.e., higher voltage side) of a differential voltage applied to a terminal of the DUT 130 (e.g., the positive voltage of the differential signal is applied to the cell voltage terminal VC1). The return / low-pass 118 connects the low-side terminal of the precision voltage source 114 to the return / low terminal 118(t). As described in more detail below, the demultiplexer 120 can connect the return / low terminal 118(t) to the low-side (i.e., lower voltage side) terminal of a differential (e.g., negative) voltage applied to a terminal of the DUT 130 (e.g., the cell voltage terminal VC2).

[0027] As shown, return / low pass 118 may connect to the low-side terminal of precision voltage source 114 above the output terminal of common-mode voltage source 112. With this design, return / low pass 118 can provide a differential signal and a floating ground that allows for the rejection of noise generated by common-mode voltage source 112. Accordingly, embodiments of the present disclosure enable test circuits to use noisier voltage sources (e.g., switched-mode power supply (SMPS) voltage sources) for common-mode voltage source 112, thereby reducing power consumption and implementation costs and size for stacked PMU 110 (and thus increasing the possible density of test circuits). However, it should be understood that various types of voltage sources may be used for common-mode voltage source 112, including other types of SMPS and non-SMPS voltage sources. For example, in some implementations, common-mode voltage source 112 may include an SMPS voltage source whose output is connected to a linear regulator, such as a low-dropout regulator (LDO). In other implementations, common-mode voltage source 112 may comprise an LDO alone, or the like.

[0028] Referring again to common-mode voltage source 112, common-mode voltage source 112 may be configured to supply a relatively wide range of voltages suitable for testing BMS ICs (e.g., −100 V to 100 V). Because precision voltage source 114 can supply / measure precision voltage steps (e.g., voltage steps of 30 to 300 μV), common-mode voltage source 112 may be a lower-precision voltage source. Therefore, common-mode voltage source 112 may have a smaller form factor (and less cost) than alternative voltage sources that must provide higher precision over the same / similar voltage range. Relatedly (and as discussed above), return / low-pass 118 is connected to the low-side terminal of precision voltage source 114 above the output terminal of common-mode voltage source 112, so that return / low-pass 118 provides a differential signal and a floating ground that can help reject noise generated by common-mode voltage source 112. Therefore, a higher noise voltage source (eg, an SMPS voltage source) can be used for common-mode voltage source 112 with lower power consumption and less cost.

[0029] Referring now to precision voltage source 114, precision voltage source 114 may be configured to source and measure a relatively low voltage range with relatively high accuracy (e.g., compared to common-mode voltage source 112). For example, precision voltage source 114 may source / measure a range of −2 V to 6 V (relative to common-mode voltage source 112) in fine steps, such as approximately 30 to 300 uV steps, or any step size that may be required for purposes of testing the DUT.

[0030] As described above, the exemplary stacked PMU 110 can operate in any one or combination of force-voltage (FV) mode, force-current (FI) mode, measure-voltage (MV) mode, and measure-current (MI) mode. In FV mode, the channels of the stacked PMU 110 may support output voltages ranging from, for example, −100 V to 100 V with a high level of accuracy, such as 100 μV. In FI mode, the stacked PMU 110 may be configured to provide currents ranging from, for example, approximately 1 μA to 1 A. These capabilities can advantageously enable the stacked PMU 110 to test the DUT 130 under multiple battery pack conditions and EV / BESS operating modes. In some implementations, by adjusting the “offset” of the voltages and currents applied by the stacked PMU 110, they can be floated over a large (e.g., + / −100 V) compliance range.

[0031] In certain embodiments, the stacked PMU 110 may include one or more integrated circuits or external clamp circuits (not shown) that limit and / or control the voltage and current conditions applied to the DUT 130, thereby protecting the DUT 130 from overstress conditions outside its designed operating regime and preventing possible damage or failure. Additionally, channels of the stacked PMU 110 may be equipped with alarm functions capable of detecting temperature, voltage, current, and force / sensing Kelvin faults. Monitor analog outputs may be included for connection to external components, such as analog-to-digital converters (ADCs) or associated analog front-end amplifiers or filters. A window comparator may be used to quickly compare measured parameters with predetermined thresholds. In certain embodiments, the window comparator may be implemented / embedded in the stacked PMU 110. The output of the window comparator may be a binary high / low signal that can be connected to an external field-programmable gate array (FPGA), microprocessor, or microcontroller within a larger test system.

[0032] In some embodiments, the stacked PMU 110 may be configurable to use both internally generated precision signals (e.g., via one or more DACs that may have an appropriate resolution, e.g., 20 bits) or external or internal analog test signals. In addition to set (e.g., static) values, patterns may be programmed into and output from the stacked PMU 110's embedded memory. In particular embodiments, the stacked PMU 110 may include an embedded serial peripheral interface (SPI) peripheral (not shown) that allows the stacked PMU 110 to be controlled in various ways by an embedded SPI controller, such as, for example, a field programmable gate array (FPGA), microprocessor, or other test equipment system and / or circuitry.

[0033] Referring again to the demultiplexer 120, the demultiplexer 120 can selectively connect (1) its supply / high terminal 119(t) to the high-side terminal (i.e., higher voltage side) of a source providing the positive differential voltage signal being applied to the DUT 130, and (2) its return / low terminal 118(t) to the low-side terminal (i.e., lower voltage side) of a source providing the negative differential voltage signal being applied to the DUT 130. For example, in a first mode / setting of the demultiplexer 120, the demultiplexer 120 can connect the supply / high terminal 119(t) to the cell voltage terminal VC1 and the return / low terminal 118(t) to the cell voltage terminal VC2 of the DUT 130. Thus, the stacked PMU 110 can test / measure the voltage difference between the cell voltage terminal VC1 and the cell voltage terminal VC2. In a second mode / setting of the demultiplexer 120, the demultiplexer 120 can connect the supply / high terminal 119(t) to the cell voltage terminal VCN-1 and the return / low terminal 118(t) to the cell voltage terminal VCN of the DUT 130.

[0034] In some embodiments, the demultiplexer 120 may include a MEMS switching matrix, although in other implementations other demultiplexers / devices may be used, and the demultiplexer may be external to the stacked PMU 110 (e.g., as a separate IC or component) or integrated therein.

[0035] As alluded to above, the DUT 130 may include various types of devices, including a BMS IC. Although only cell voltage terminals are shown in the particular example of FIG. 1 (i.e., cell voltage terminals VCl-VCN), in various implementations, the DUT 130 may include other terminals to be tested, such as cell balancing terminals or other types of terminals.

[0036] FIG. 2 illustrates an exemplary test circuit 200 in accordance with various examples of the techniques of this disclosure.

[0037] Unlike test circuit 100, example test circuit 200 may omit a demultiplexer. Instead, test circuit 200 may include a stacked PMU 210 having a “common mode voltage source precision PMU stack” for each channel of DUT 230.

[0038] For example, a first common-mode voltage source precision PMU stack may be connected to cell voltage terminal VC1 of DUT 230 via terminal 217(t)(i) of test circuit 200. The first common-mode voltage source precision PMU stack may include (a) common-mode voltage source 212(i), (b) precision voltage source 214(i) connected in series with common-mode voltage source 212(i), and / or (c) ammeter 216(i).

[0039] Similarly, a second common-mode voltage source precision PMU stack may be connected to cell voltage terminal VC2 of DUT 230 via terminal 217(t)(ii) of test circuit 200. The second common-mode voltage source precision PMU stack may include (a) common-mode voltage source 212(ii), (b) precision voltage source 214(ii) connected in series with common-mode voltage source 212(ii), and / or (c) ammeter 216(ii).

[0040] Although not shown, stacked PMU 210 may include, for example, an additional common mode voltage source precision PMU stack for each channel of DUT 230 .

[0041] Precision voltage source 214(i) and precision voltage source 214(ii) may be the same as or similar to precision voltage source 114 of test circuit 100. Similarly, ammeter 216(i) and ammeter 216(ii) may be the same as or similar to ammeter 116 of test circuit 100. Therefore, the combination of precision voltage source 214(i) and ammeter 216(i) may be referred to as a first precision PMU. Similarly, the combination of precision voltage source 214(ii) and ammeter 216(ii) may be referred to as a second precision PMU.

[0042] Common-mode voltage source 212(i) and common-mode voltage source 212(ii) may also be similar to common-mode voltage source 112 of test circuit 100. However, because common-mode voltage source 212(i) and common-mode voltage source 212(ii) are channel-specific, they may not need to provide as wide a range of voltages as common-mode voltage source 112.

[0043] A potential advantage of test circuit 200 over test circuit 100 is that it can simultaneously test more channels (potentially all channels) of DUT 230. In contrast, test circuit 100 may test only a single voltage difference at a time. Thus, test circuit 200 may facilitate faster and larger-scale testing than test circuit 100.

[0044] However, test circuit 100 may offer certain advantages over test circuit 200, including, for example, a smaller / more compact form factor and fewer electrical components. In this regard, because stacked PMU 110 includes a return / low line 118 (e.g., a floating ground) connected above common-mode voltage source 112, such a return line can help eliminate / reduce noise generated by common-mode voltage source 112 from reaching precision DUT 130. In contrast, in embodiments where test circuit 200 lacks such a return line to its constituent precision voltage sources, stacked PMU 210 may need to address noise through other mechanisms. In other embodiments, stacked PMU 210 may use one or more floating grounds and differential voltages / signals, or a combination of single-ended and differential voltages / signals.

[0045] FIG. 3 illustrates another test circuit 300 in accordance with various examples of the techniques of this disclosure.

[0046] As shown, the test circuit 300 includes: The DUT 360 includes a series-connected stack of floating-ground PMUs (e.g., PMUs 316, 315, 314, 313, and in some implementations, additional PMUs connected in series below PMU 313) connected to the DUT 360 and configured to test whether the cell voltage (CV) and cell balance (CB) terminal characteristics of the DUT 360 meet applicable specifications. This floating-ground-based topology can meet common-mode and uV / uA accuracy requirements, for example, as described herein. Each PMU may have an isolated power supply (e.g., isolated power supply 336 for PMU 316, isolated power supply 335 for PMU 315, isolated power supply 334 for PMU 314, and isolated power supply 333 for PMU 313) to galvanically isolate the PMU circuitry from the system input power supply 350, for example. In this configuration, a DAC (e.g., a 20-bit or other resolution DAC) integrated into each PMU drives the CV and CB terminals (e.g., terminals 366, 365, 364, and 363) of the DUT 360 in force-voltage (FV) or force-current (FI) mode, or a combination thereof, and the DUT's measured current (MI) and measured voltage (MV) responses can be used to verify the DUT's battery cell measurements, input current, and on-resistance capabilities of the CB switch transistor. Each PMU FV or FI stimulus can be independently programmed using test equipment software, thereby enabling the emulation of any battery cell state. Particular embodiments can extend the testable DUT voltage range up to its maximum rating by connecting each PMU in series with an in-phase, efficient switched-mode power supply (SMPS) (e.g., common-mode voltage source 326 for PMU 316, common-mode voltage source 325 for PMU 315, common-mode voltage source 324 for PMU 314, etc.). Test circuit 300 may be reconfigurable between a first high-precision topology and a second extended voltage range topology using a switching matrix (e.g., a switching matrix including switch 346 that selectively connects PMU 316 in series with PMU 315, switch 345 that selectively connects PMU 315 in series with PMU 314, switch 344 that selectively connects PMU 314 in series with PMU 313, etc.).These switching matrices / switches may be separate to support greater flexibility, or may be integrated with or within the respective PMUs, for example, as co-packaged microelectromechanical systems (MEMS) switches. At the circuit level, one or more integrated clamp circuits within each PMU can limit the voltage and current across the DUT 360. In some cases, the clamps may be external to the respective PMU. Additionally, each PMU may have alarm capabilities to detect temperature, voltage, current, and force / sense Kelvin faults, etc.

[0047] Referring again to Figure 3, as shown, each PMU may be powered by an isolated power supply. Power supply isolation allows the PMUs to be electrically connected in series while maintaining their supply voltage low relative to that of the total series voltage.

[0048] FIG. 4 shows an expanded view of PMU 315 from test circuit 300 of FIG. 3, in accordance with various examples of the techniques of this disclosure.

[0049] 4, GND may refer to the ground terminal of the power supply of PMU 315. PWR may refer to the positive terminal of the power supply of PMU 315. OUT may refer to the output terminal of PMU 315. LS may refer to the low sense terminal of PMU 315.

[0050] FIG. 5 shows an expanded view of the isolated power supply 335 from the test circuit 300 of FIG. 3, in accordance with various examples of the techniques of this disclosure.

[0051] 5, VINP may refer to the positive terminal of the input power supply of isolated power supply 335. GNDIN may refer to the ground terminal of the input power supply of isolated power supply 335. VOUTP may refer to the positive terminal of the output power supply of isolated power supply 335. GNDOUT may refer to the ground terminal of the output power supply of isolated power supply 335. The isolation barrier may refer to a transformer or other electrical isolation incorporated into isolated power supply 335.

[0052] 6 shows an expanded view of common-mode voltage source 325 from test circuit 300 of FIG. 3, in accordance with various examples of the techniques of this disclosure. As an example, common-mode voltage source 325 may provide a voltage between −100V and 100V.

[0053] FIG. 7 shows an expanded view of switch 345 from test circuit 300 of FIG. 3, in accordance with various examples of the techniques of this disclosure.

[0054] As shown in FIG. 7 , switch 345 can configure test circuit 300 between (a) a normal voltage high precision mode in which the pole of switch 345 is connected to contact 1 of switch 345, thereby connecting the low sense terminal of PMU 315 to the output terminal of PMU 314, and (b) an extended voltage low precision mode in which the pole of switch 345 is connected to contact 2 of switch 345, thereby connecting the low sense terminal of PMU 315 to common mode power supply 325.

[0055] FIG. 8 illustrates another test circuit 800 in accordance with various examples of the techniques of this disclosure.

[0056] As shown, test circuit 800 may include a series-connected stack of floating-ground PMUs (e.g., PMUs 816, 815, 814, 813, and in some implementations, an additional PMU connected in series below PMU 813) connected to a DUT 870. The PMUs are configured to test whether the cell voltage (CV) terminal characteristics and cell balance (CB) terminal characteristics of DUT 870 meet applicable specifications. Each PMU may have, for example, an isolated power supply (e.g., isolated power supply 836 for PMU 816, isolated power supply 835 for PMU 815, isolated power supply 834 for PMU 814, isolated power supply 833 for PMU 813) to galvanically isolate the PMU circuitry from the system input power supply 850. Each PMU may be connected in series with a common-mode voltage source (e.g., common-mode voltage source 826 for PMU 816, common-mode voltage source 825 for PMU 815, common-mode voltage source 824 for PMU 814, etc.). 8, each PMU is connected to a dedicated / separate common-mode voltage source, in one or more embodiments, the PMUs may be connected to the same common-mode voltage source. However, connecting each PMU to a dedicated / separate common-mode voltage source can facilitate independent control benefits, such as when a common-mode voltage source connected to a first PMU needs to provide a different voltage output than a common-mode voltage source connected to a second PMU.

[0057] As shown in FIG. 8, the bidirectional switch of FIG. 3 can be replaced by a three-way switch (i.e., switches 846, 845, 844, and in some implementations, an additional switch connected below switch 844 of FIG. 8).

[0058] For example, switch 846, in its first configuration, can connect low sense terminal PMU 816 to the output terminal of PMU 815. Relatedly, switch 845, in its first configuration, can connect low sense terminal PMU 815 to the output terminal of PMU 814. Similarly, switch 844, in its first configuration, can connect low sense terminal PMU 814 to the output terminal of PMU 813. Thus, in the first configuration of the switches, the PMUs of test circuit 800 can be connected in series to emulate a battery stack to be managed by DUT 870 (which, as described above, may be a battery management system (BMS)). Thus, in this first configuration of the switches, test circuit 800 can test the ability of DUT 870 (e.g., a BMS) to measure individual terminal voltages of the battery stack being emulated by test circuit 800.

[0059] In the second configuration, switch 846 can connect low sense terminal PMU 816 to ground 866. In this regard, switch 845 can connect low sense terminal PMU 815 to ground 865 in its second configuration. Similarly, switch 844 can connect low sense terminal PMU 814 to ground 864 in its second configuration. Thus, in the second configuration of the switches, test circuit 800 can be configured to test low-voltage characteristics of DUT 870 (e.g., characteristics of DUT 870 that are tested at a relatively low voltage, such as 0 to 5 volts). Non-limiting examples of low-voltage characteristics can include (a) differential voltage between successive terminals of DUT 870, (b) battery cell ADC resolution of DUT 870, and (c) other characteristics of DUT 870 that are tested at a relatively low voltage (e.g., 0 to 5 volts).

[0060] In its third configuration, switch 846 can connect low sense terminal PMU 816 to common-mode voltage source 826. Relatedly, switch 845 can connect low sense terminal PMU 815 to common-mode voltage source 825 in its third configuration. Similarly, switch 844 can connect low sense terminal PMU 814 to common-mode voltage source 824 in its third configuration. Thus, in the third configuration of the switches, test circuit 800 can be configured to test high-voltage characteristics of DUT 870 (e.g., characteristics of DUT 870 that are tested at a relatively high voltage, such as 60 to 100 volts). Non-limiting examples of high-voltage characteristics may include (a) the absolute maximum voltage rating of the cell voltage terminals of DUT 870, (b) leakage current from the cell voltage terminals of DUT 870 when the maximum rated voltage is applied, and (c) other characteristics of DUT 870 that are tested at a relatively high voltage (e.g., 60 to 100 volts).

[0061] In one or more embodiments, the PMU may connect directly to the input power supply 850. This may allow for an embodiment that does not include a galvanic isolation module, which may allow for lower cost and higher efficiency with less power loss.

[0062] Terms and phrases used in this document, and variations thereof, unless expressly stated otherwise, should be construed as open-ended rather than limiting. As an example of the foregoing, the term "including" should be read to mean "including, without limitation," etc. The term "example" is used to provide illustrative examples of the items under discussion, rather than an exhaustive or limiting list thereof. The terms "a" or "an" should be read to mean "at least one," "one or more," etc., and adjectives such as "conventional," "traditional," "usual," "standard," and "known." Terms of similar import should not be construed to limit the described items to items available during a given period or at a given time. Instead, they should be read to encompass conventional, traditional, usual, or standard technology that may be available or known now or at any time in the future. When this document refers to technology that would be apparent or known to those skilled in the art, such technology encompasses technology that would be apparent or known to those skilled in the art at any time now or in the future.

[0063] The presence of broad words and phrases such as "one or more," "at least," "but not limited to," or other similar phrases should not be construed to imply that a narrower case is intended or required in some cases where such broad phrase is not present. The use of the term "component" does not imply that aspects or functionality described or claimed as part of a component are all configured within a common package. Indeed, any or all of the various aspects of a component, whether control logic or other components, may be combined into a single package or maintained separately, and may further be distributed across multiple groups or packages or locations.

[0064] Furthermore, various embodiments described herein are described with reference to exemplary block diagrams, flow charts, and other diagrams. As will become apparent to one of ordinary skill in the art after reading this document, the illustrated embodiments and their various alternatives can be practiced without being limited to the illustrated examples. For example, block diagrams and their accompanying description should not be construed as mandating a particular arrangement or configuration.

Claims

1. In the test circuit, a first parametric measurement unit (PMU), a first power source; an output terminal for connecting the first power supply to a first terminal of a device under test (DUT); a first parametric measurement unit (PMU) comprising: a second PMU, a second power source; a second PMU having an output terminal for connecting the second power supply to a second terminal of the DUT; a common-mode voltage source configured to provide a wider range of voltages in less precise steps than the first power supply and the second power supply; A switch, a first configuration in which the switch connects the low sense terminal of the first PMU to the output terminal of the second PMU; a switch having a configuration in a second configuration in which the switch connects the low sense terminal of the first PMU to the common mode voltage source.

2. a third PMU, a third power source; and a third PM having an output terminal for connecting the third power supply to a third terminal of the DUT; a second common-mode voltage source configured to provide a wider range of voltages with lower precision steps than the first power supply, the second power supply, and the third power supply; a second switch; the second PMU further comprises a low sense terminal; The second switch has a configuration of: a first configuration in which the second switch connects the low sense terminal of the second PMU to the output terminal of the third PMU; 2. The test circuit of claim 1, wherein the second switch is in a second configuration connecting the low sense terminal of the second PMU to the second common mode voltage source.

3. a first isolated power supply electrically connected to provide a first voltage to the first PMU; a second isolated power supply electrically connected to provide a second voltage to the second PMU; 2. The test circuit of claim 1, wherein the first voltage and the second voltage have a higher accuracy than the common-mode voltage source.

4. the first isolated power supply comprising a voltage input terminal, a voltage output terminal connected to the first PMU, and a first galvanic isolation barrier separating the voltage input terminal from the voltage output terminal; the second isolated power supply comprising a voltage input terminal, a voltage output terminal connected to the second PMU, and a second galvanic isolation barrier separating the voltage input terminal of the second isolated power supply from the voltage output terminal of the second isolated power supply; 4. The test circuit according to claim 3, wherein the voltage input terminal of the first isolated power supply and the voltage input terminal of the second isolated power supply are connected to a common input power supply.

5. 2. The test circuit of claim 1, wherein the first power supply comprises one or more digital-to-analog converters (DACs) and an amplifier that drives the first terminal of the DUT in a force-voltage (FV) mode, a force-current (FI) mode, or a combination thereof.

6. The first power source is a first precision voltage source for driving the first terminal of the DUT in FV mode; or 2. The test circuit of claim 1, including at least one first precision current source for driving the first terminal of the DUT in FI mode.

7. the DUT comprises a battery management system (BMS); 2. The test circuit of claim 1, wherein the first terminal of the DUT comprises a cell voltage terminal and the second terminal of the DUT comprises a cell balance terminal.

8. In the test circuit, a first parametric measurement unit (PMU), a first power source; an output terminal for connecting the first power supply to a first terminal of a device under test (DUT); a first parametric measurement unit (PMU) having a low sense terminal; a second PMU, a second power source; a second PMU having an output terminal for connecting the second power supply to a second terminal of the DUT; a common-mode voltage source configured to provide a wider range of voltages in less precise steps than the first power supply and the second power supply; A switch, a first configuration in which the switch connects the low sense terminal of the first PMU to the output terminal of the second PMU; a second configuration in which the switch connects the low sense terminal of the first PMU to ground; a switch having a configuration including a third configuration in which the switch connects the low sense terminal of the first PMU to the common mode voltage source.

9. the DUT comprises a battery management system (BMS); In the first configuration of the switch, the first PMU and the second PMU are connected in series to emulate a battery stack to be managed by the BMS; In the second configuration of the switch, the first PMU is configured to test low voltage characteristics of the BMS; 9. The test circuit of claim 8, wherein in the third configuration of the switch, the first PMU is configured to test high voltage characteristics of the BMS.

10. 10. The test circuit of claim 9, wherein in the first configuration of the switch, the test circuit is configured to test the ability of the BMS to measure individual terminal voltages of a battery stack.

11. a third PMU, a third power source; and a third PM having an output terminal for connecting the third power supply to a third terminal of the DUT; a second common-mode voltage source configured to provide a wider range of voltages with lower precision steps than the first power supply, the second power supply, and the third power supply; a second switch, the second PMU further comprises a low sense terminal; The second switch has a configuration of: a first configuration in which the second switch connects the low sense terminal of the second PMU to the output terminal of the third PMU; a second configuration in which the second switch connects the low sense terminal of the second PMU to ground; a third configuration in which the second switch connects the low sense terminal of the second PMU to the second common mode voltage source; 9. The test circuit of claim 8.

12. a first isolated power supply electrically connected to provide a first voltage to the first PMU; a second isolated power supply electrically connected to provide a second voltage to the second PMU; 9. The test circuit of claim 8, wherein the first voltage and the second voltage are more accurate than the common-mode voltage source.

13. the first isolated power supply comprising a voltage input terminal, a voltage output terminal connected to the first PMU, and a first galvanic isolation barrier separating the voltage input terminal from the voltage output terminal; the second isolated power supply comprising a voltage input terminal, a voltage output terminal connected to the second PMU, and a second galvanic isolation barrier separating the voltage input terminal of the second isolated power supply from the voltage output terminal of the second isolated power supply; 13. The test circuit of claim 12, wherein the voltage input terminal of the first isolated power supply and the voltage input terminal of the second isolated power supply are connected to a common input power supply.

14. 9. The test circuit of claim 8, wherein the first power supply comprises one or more digital-to-analog converters (DACs) and amplifiers that drive terminals of the DUT in a force-voltage (FV) mode, a force-current (FI) mode, or a combination thereof.

15. In the test circuit, a first parametric measurement unit (PMU), a first power source; an output terminal for connecting the first power supply to a first terminal of a device under test (DUT); a first parametric measurement unit (PMU) having a low sense terminal; a second PMU, a second power source; a second PMU having an output terminal for connecting the second power supply to a second terminal of the DUT; a common-mode voltage source configured to provide a wider range of voltages in less precise steps than the first power supply and the second power supply; A switch, a first configuration in which the switch connects the low sense terminal of the first PMU to the output terminal of the second PMU; a switch having a configuration including a first configuration in which the switch connects the low sense terminal of the first PMU to the common mode voltage source; and a second configuration in which the switch connects the low sense terminal of the first PMU to the common mode voltage source.

16. 16. The test circuit of claim 15, wherein the configurations of the switch consist of the first configuration and the second configuration.

17. the DUT comprises a battery management system (BMS); the configurations for the switch further include a third configuration in which the switch connects the low sense terminal of the first PMU to ground; In the first configuration of the switch, the first PMU and the second PMU are connected in series to emulate a battery stack to be managed by the BMS; In the second configuration of the switch, the first PMU is configured to test high voltage characteristics of the BMS; 16. The test circuit of claim 15, wherein in the third configuration of the switch, the first PMU is configured to test low voltage characteristics of the BMS.

18. 20. The test circuit of claim 17, wherein in the first configuration of the switch, the test circuit is configured to test the ability of the BMS to measure individual terminal voltages of a battery stack.

19. 18. The test circuit of claim 17, wherein the test circuit further comprises "M" number of PMUs, and wherein in the first configuration of the switch, the test circuit is configured to emulate the battery stack comprising "M+2" number of battery modules, wherein the number "M" includes four or more.

20. 18. The test circuit of claim 17, wherein the test circuit further comprises "N" number of PMUs, and wherein in the first configuration of the switch, the test circuit is configured to emulate the battery stack comprising "N+2" number of battery modules, the "N+2" number comprising an integer multiple of four.

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