Semiconductor device

Abstract

To provide a semiconductor device capable of reading data with high accuracy.SOLUTION: A semiconductor device has first and second memory cells and a switch. The first memory cell has first and second transistors and a first capacitor, and the second memory cell has third and fourth transistors and a second capacitor. The first and second capacitors has a ferroelectric layer between a pair of electrodes. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and the gate of the second transistor is electrically connected to one of electrodes of the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor, and the gate of the fourth transistor is electrically connected to one of electrodes of the second capacitor. The other one of the source and the drain of the first transistor is electrically connected to the other one of the source and the drain of the third transistor via the switch.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a driving method thereof, or the like. Another embodiment of the present invention relates to an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, imaging devices, display devices, light-emitting devices, power storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and driving methods thereof or manufacturing methods thereof. Note that a semiconductor device generally refers to a device that utilizes semiconductor characteristics, and a memory device is a semiconductor device. [Background technology]

[0003] Metal oxides have been attracting attention as semiconductors applicable to transistors. Indium-gallium-zinc oxide, also known as "IGZO," is a representative multi-component metal oxide. Research on IGZO has revealed that it has a c-axis aligned crystalline (CAAC) structure and a nanocrystalline (nc) structure, which are neither single crystal nor amorphous (see, for example, Non-Patent Document 1).

[0004] It has been reported that a transistor having a metal oxide semiconductor in a channel formation region (hereinafter also referred to as an "oxide semiconductor transistor" or an "OS transistor") has an extremely small off-state current (for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4).

[0005] Furthermore, a memory (sometimes referred to as OS memory) utilizing the extremely small off-state current of OS transistors has been proposed. For example, Patent Document 1 discloses a circuit configuration of NOSRAM. Note that "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM." NOSRAM refers to a memory in which the cells are two-transistor (2T) or three-transistor (3T) gain cells and the access transistors are OS transistors. The current that flows between the source and drain in the off state, i.e., the leakage current, is extremely small. NOSRAM can be used as a nonvolatile memory by utilizing its extremely small leakage current characteristic to retain charge corresponding to data within the cell. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2011 / 0176348 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-patent document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-patent document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0008] In order to read data with high accuracy in memories such as NOSRAM, it is important that the potential output from a memory cell differs greatly when different data is read from the memory cell. For example, when binary data is stored in a memory cell, it is preferable that the difference between the potential output from the memory cell when reading data with a value of "0" and the potential output from the memory cell when reading data with a value of "1" is large.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device that can read data with high accuracy and a driving method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a driving method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility and a driving method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device that can store a large amount of data and a driving method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed and a driving method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device that consumes low power and a driving method thereof. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a driving method thereof.

[0010] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and / or other problems. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device comprising a first memory cell, a second memory cell, and a switch, wherein the first memory cell comprises a first transistor, a second transistor, and a first capacitor, and the second memory cell comprises a third transistor, a fourth transistor, and a second capacitor, wherein the first capacitor and the second capacitor have a ferroelectric layer between a pair of electrodes, wherein one of a source or a drain of the first transistor is electrically connected to a gate of the second transistor, the gate of the second transistor is electrically connected to one electrode of the first capacitor, one of a source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, the gate of the fourth transistor is electrically connected to one electrode of the second capacitor, and the other of the source or the drain of the first transistor is electrically connected to the other of the source or the drain of the third transistor via a switch.

[0012] Alternatively, in the above aspect, the memory cell may have a first drive circuit, which has a function of turning on the first transistor when reading data from the first memory cell, and which has a function of turning on the third transistor when reading data from the second memory cell.

[0013] Alternatively, in the above aspect, the memory cell may have a second drive circuit, which has a function of reading data from the first memory cell based on the potential of either the source or the drain of the second transistor, and the second drive circuit may have a function of reading data from the second memory cell based on the potential of either the source or the drain of the fourth transistor.

[0014] Alternatively, in the above embodiment, the first to fourth transistors may have a metal oxide in a channel formation region.

[0015] Alternatively, in the above aspect, the first memory cell may have a fifth transistor, the second memory cell may have a sixth transistor, one of the source or drain of the fifth transistor may be electrically connected to one of the source or drain of the second transistor, and one of the source or drain of the sixth transistor may be electrically connected to one of the source or drain of the fourth transistor.

[0016] Alternatively, in the above aspect, the memory cell may have a third driving circuit, which has a function of turning on the fifth transistor when reading data from the first memory cell, and the third driving circuit may have a function of turning on the sixth transistor when reading data from the second memory cell.

[0017] Alternatively, in the above aspect, the fifth transistor and the sixth transistor may have a metal oxide in the channel formation region.

[0018] Alternatively, one embodiment of the present invention is a semiconductor device including a memory cell, a first driver circuit, and a switch, wherein the memory cell includes a first transistor, a second transistor, and a capacitor, the capacitor having a ferroelectric layer between a pair of electrodes, one of a source or a drain of the first transistor being electrically connected to a gate of the second transistor, the gate of the second transistor being electrically connected to one electrode of the capacitor, and the other of the source or the drain of the first transistor being electrically connected to a first driver circuit via the switch, and the first driver circuit having a function of generating data to be written to the memory cell.

[0019] Alternatively, in the above aspect, a second driving circuit may be provided, and the second driving circuit may have a function of turning on the first transistor when reading data from the memory cell.

[0020] Alternatively, the above aspect may include a third driver circuit, and the third driver circuit may have a function of reading data from the memory cell based on the potential of one of the source and drain of the second transistor.

[0021] Alternatively, in the above aspect, the first transistor and the second transistor may have a metal oxide in a channel formation region.

[0022] Alternatively, in the above aspect, the memory cell may have a third transistor, and one of the source or drain of the third transistor may be electrically connected to one of the source or drain of the second transistor.

[0023] Alternatively, in the above aspect, a fourth drive circuit may be provided, and the fourth drive circuit may have a function of turning on the third transistor when reading data from the memory cell.

[0024] Alternatively, in the above aspect, the third transistor may have a metal oxide in a channel formation region.

[0025] Alternatively, one aspect of the present invention includes a first layer and a second layer having a region overlapping with the first layer, the first layer including a first memory cell, a second memory cell, and a switch, the first memory cell including a first transistor, a second transistor, and a first capacitance, the second memory cell including a third transistor, a fourth transistor, and a second capacitance, the first capacitance and the second capacitance including a ferroelectric layer between a pair of electrodes, the second layer including a first calculation unit and a second calculation unit, and one of a source or a drain of the first transistor is connected to a gate of the second transistor. the gate of the second transistor is electrically connected to one electrode of the first capacitance, one of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor, the gate of the fourth transistor is electrically connected to one electrode of the second capacitance, the other of the source or drain of the first transistor and the other of the source or drain of the third transistor are electrically connected via a switch, the first calculation unit is electrically connected to a first power supply line, and the second calculation unit is electrically connected to a second power supply line.

[0026] Alternatively, in the above aspect, the first power supply line may not be electrically connected to the second power supply line.

[0027] Alternatively, in the above aspect, the semiconductor memory device may have a third layer, the third layer having an area overlapping with the first layer and the second layer, the third layer having a first driving circuit, the first driving circuit having a function of turning on the first transistor when reading data from the first memory cell, and the first driving circuit having a function of turning on the third transistor when reading data from the second memory cell.

[0028] Alternatively, in the above aspect, the third layer may have a second drive circuit, and the second drive circuit may have a function of reading data from the first memory cell based on the potential of either the source or the drain of the second transistor, and the second drive circuit may have a function of reading data from the second memory cell based on the potential of either the source or the drain of the fourth transistor.

[0029] Alternatively, in the above embodiment, the ferroelectric layer may include hafnium oxide and / or zirconium oxide.

[0030] An electronic device including the semiconductor device of one embodiment of the present invention and a housing is also one embodiment of the present invention. [Effects of the Invention]

[0031] According to one embodiment of the present invention, a semiconductor device capable of reading data with high accuracy and a driving method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device and a driving method thereof can be provided. According to one embodiment of the present invention, a semiconductor device with high design flexibility and a driving method thereof can be provided. According to one embodiment of the present invention, a semiconductor device capable of storing a large amount of data and a driving method thereof can be provided. According to one embodiment of the present invention, a semiconductor device that operates at high speed and a driving method thereof can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption and a driving method thereof can be provided. According to one embodiment of the present invention, a novel semiconductor device and a driving method thereof can be provided.

[0032] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0033] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of the semiconductor device. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 4] Fig. 4A is a circuit diagram showing an example of the configuration of a memory cell, Fig. 4B is a schematic diagram showing an example of the configuration of a capacitor, and Fig. 4C is a graph showing the hysteresis characteristics of a ferroelectric material. [Figure 5] Fig. 5A is a timing chart showing an example of a method for driving a semiconductor device, and Figs. 5B to 5E are circuit diagrams showing an example of a method for driving a semiconductor device. [Figure 6] FIG. 6 is a timing chart showing an example of a method for driving a semiconductor device. [Figure 7] 7A to 7C are circuit diagrams showing an example of a method for driving a semiconductor device. [Figure 8] Fig. 8A is a timing chart showing an example of a method for driving a semiconductor device, and Fig. 8B and Fig. 8C are circuit diagrams showing an example of a method for driving a semiconductor device. [Figure 9] 9A and 9B are circuit diagrams showing examples of the configuration of a memory cell. [Figure 10] 10A and 10B are perspective views showing configuration examples of a semiconductor device. [Figure 11] FIG. 11 is a perspective view showing a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a diagram showing an example of a layout of a semiconductor device. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 14] 14A to 14C are cross-sectional views showing examples of the structure of a transistor. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 16] 16A and 16B are cross-sectional views showing examples of the structure of a transistor. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a configuration example of a transistor. [Figure 18] 18A to 18C are cross-sectional views showing examples of the structure of a transistor. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a configuration example of a transistor. [Figure 20] 20A and 20B are cross-sectional views showing examples of the structure of a transistor. [Figure 21] 21A and 21B are cross-sectional views showing examples of the structure of a transistor. [Figure 22] Fig. 22A is a diagram explaining the classification of IGZO crystal structures, Fig. 22B is a diagram explaining the XRD spectrum of crystalline IGZO, and Fig. 22C is a diagram explaining the micro-electron beam diffraction pattern of crystalline IGZO. [Figure 23] Fig. 23A is a perspective view showing an example of a semiconductor wafer, Fig. 23B is a perspective view showing an example of a chip, Fig. 23C and Fig. 23D are perspective views showing an example of an electronic component. [Figure 24] 24A to 24J are diagrams showing an example of an electronic device. [Figure 25] 25A to 25E are diagrams showing an example of an electronic device. [Figure 26] 26A to 26C are diagrams showing an example of an electronic device. [Figure 27] 27A to 27F are diagrams showing the measurement results of Id-Vg characteristics according to the example. [Figure 28] 28A to 28F are diagrams showing the results of a drain breakdown voltage test according to the example. [Figure 29] 29A to 29F are diagrams showing the results of a drain breakdown voltage test according to the example. [Figure 30] Fig. 30A is a circuit diagram illustrating an outline of an off-state current measuring TEG, and Fig. 30B is a graph showing the temperature dependence of leakage current. [Figure 31] Fig. 31A is a schematic diagram showing the structure of the prototype transistor, and Fig. 31B and Fig. 31C are cross-sectional STEM images of the prototype transistor. [Figure 32] 32A and 32B show the top gate voltage-drain current characteristics of the fabricated transistor. [Figure 33] FIG. 33 is a diagram showing the maximum current gain in the prototype transistor. DETAILED DESCRIPTION OF THE INVENTION

[0034] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0035] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated explanations thereof may be omitted.

[0037] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “[ ]”, “< >”, or “_” may be added to the symbol.

[0038] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when the term "OS FET" or "OS transistor" is used, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0039] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a driving method thereof will be described.

[0040] One embodiment of the present invention relates to a semiconductor device having a cell. The cell includes a first transistor, a second transistor, and a capacitor. One of the source and drain of the first transistor is electrically connected to the gate of the second transistor. The gate of the second transistor is electrically connected to one electrode of the capacitor. In a cell having such a configuration, data can be stored by the capacitor. Therefore, the cell can be called a memory cell, and the semiconductor device can be called a memory device.

[0041] The capacitor has a structure in which a ferroelectric layer is provided between a pair of electrodes. In this case, data written to the memory cell can be retained by polarization of the ferroelectric layer. When reading data from a memory cell with such a structure, one electrode of the capacitor is electrically floating, and the potential of the other electrode of the capacitor is varied. This causes the potential of the one electrode of the capacitor to vary due to capacitive coupling. The fluctuation range of the potential of the one electrode of the capacitor can be determined by the ratio of the capacitance value of the capacitor to the parasitic capacitance of the node to which the one electrode of the capacitor is electrically connected.

[0042] When the data stored in the memory cell is different, the amount of polarization of the ferroelectric layer is different. This results in a different capacitance value of the capacitor. Therefore, by changing the potential of the other electrode of the capacitor, the potential of one electrode of the capacitor can be changed depending on the data stored in the memory cell. Data can be read from the memory cell based on this difference.

[0043] Here, when different data is read from a memory cell, if the potential of one electrode of the capacitor is significantly different, the data can be read with high accuracy. For example, when binary data is stored in a memory cell, if there is a large difference between the potential output from the memory cell when reading data value "0" and the potential output from the memory cell when reading data value "1", the data can be read with high accuracy. To achieve this, it is important to appropriately control the parasitic capacitance of the node to which one electrode of the capacitor is electrically connected.

[0044] In a semiconductor device according to one embodiment of the present invention, when data is read from a memory cell, the parasitic capacitance of a node to which one electrode of a capacitor is electrically connected can be controlled, thereby enabling data to be read from the memory cell with high accuracy.

[0045] 1 is a block diagram showing a configuration example of a semiconductor device 10 according to one embodiment of the present invention, which includes a memory unit MU, a driver circuit WWD, a driver circuit RWD, a driver circuit WBD, and a driver circuit RBD.

[0046] 2 is a circuit diagram showing an example of the configuration of the memory unit MU, which also shows the drive circuit WBD.

[0047] The memory unit MU includes a memory cell array MCA <1> Memory cell array MCA <k>(k is an integer greater than or equal to 1) and a switch array SWA <0> Switch array SWA <k-1>and,

[0048] For example, switch array SWA <0> The drive circuit WBD and the memory cell array MCA <1> The switch array SWA is also provided between the <1> is a memory cell array MCA <1> and the memory cell array MCA <2> Furthermore, the switch array SWA <k-1>is a memory cell array MCA <k-1>and the memory cell array MCA <k>In other words, the memory unit MU is provided with the switch arrays SWA and the memory cell arrays MCA alternately. <k-1>is not shown.

[0049] The switch array SWA has switches SW arranged therein. Specifically, for example, the switch array SWA <0> Switch SW <0> are arranged in multiple rows, and the switch array SWA <1> Switch SW <1> are arranged in multiple rows, and the switch array SWA <2> Switch SW <2> are arranged in multiple rows, and the switch array SWA <k-1>Switch SW <k-1>The switches SW may be, for example, transistors.

[0050] For example, switch SW <0> One terminal of the switch SW <0> The other terminal of the memory cell array MCA <1> Also, the switch SW <1> One terminal of the memory cell array MCA <1> and is electrically connected to the switch SW <1> The other terminal of the memory cell array MCA <2> Furthermore, the switch SW <k-1>One terminal of the memory cell array MCA <k-1>and is electrically connected to the switch SW <k-1>The other terminal of the memory cell array MCA <k>That is, the drive circuit WBD is electrically connected to the memory cell array MCA via the switch SW. Also, the memory cell arrays MCA are electrically connected to each other via the switch SW.

[0051] Specifically, the drive circuit WBD is <1> Memory cell array MCA <k>The driver circuit WBD is electrically connected to the wiring WBL via the switch SW. <0> via the memory cell array MCA <1> and is electrically connected to the switch SW <0> , and switch SW <1> via the memory cell array MCA <2> and is electrically connected to the switch SW <0> or switch SW <k-1>via the memory cell array MCA <k>and electrically connected to each other.

[0052] The wiring WBL has a capacitance C1, which is a parasitic capacitance. <0> The other terminal and the switch SW <1> The capacitance C1 of the wiring WBL between one terminal of <1> Also, for example, switch SW <1> The other terminal and the switch SW <2> The capacitance C1 of the wiring WBL between one terminal of <2> Also, the switch SW <k-2>The other terminal and the switch SW <k-1>The capacitance C1 of the wiring WBL between one terminal of <k-1>Furthermore, the switch SW <k-1>The other terminal of the memory cell array MCA <k>The parasitic capacitance of the wiring WBL between <k>In addition, in Fig. 2, the switch array SWA <k-2>, and switch SW <k-2>is not shown. Here, the memory cell array MCA <1> Memory cell array MCA <k>In the case where the wiring length of the wiring WBL in each memory cell array MCA is the same, the capacitance C1 <1> 〜Capacity C1 <k>The capacitance values ​​of the two can be considered to be the same. In Figure 2, the parasitic capacitance is shown by a dashed line. Similar notations may be used in other figures.

[0053] Fig. 3 is a block diagram showing a configuration example of the semiconductor device 10. Fig. 3 shows a specific configuration example of the memory cell array MCA, in which the memory unit MU has the configuration shown in Fig. 2. In the memory cell array MCA, memory cells MC are arranged in a matrix.

[0054] The drive circuit WWD is electrically connected to the memory cells MC by wiring WWL. The drive circuit RWD is electrically connected to the memory cells MC by wiring RWL. The drive circuit WWD and the drive circuit RWD are electrically connected to the memory cells MC by wiring PL. The drive circuit RBD is electrically connected to the memory cells MC by wiring RBL. As described above, the drive circuit WBD is electrically connected to the memory cells MC by wiring WBL via the switch SW. Here, for example, memory cells MC in the same row can be electrically connected by the same wiring WWL, wiring PL, and wiring RWL. Furthermore, memory cells MC in the same column can be electrically connected by the same wiring WBL and wiring RBL. Furthermore, the switch array SWA can be provided with a switch SW for each column of memory cells MC.

[0055] The drive circuit WWD has a function of generating a signal for controlling the selection of the memory cell MC to which data is written. The drive circuit WWD has a function of generating a signal to be applied to the wiring WWL, and also has a function of generating a signal to be applied to the wiring PL. The drive circuit WWD can generate a signal for the desired selection control using a decoder circuit, a shift register circuit, or the like.

[0056] The drive circuit RWD has a function of generating a signal for controlling the selection of the memory cell MC from which data is read. The drive circuit RWD has a function of generating a signal to be provided to the wiring RWL and a function of generating a signal to be provided to the wiring PL. The drive circuit RWD can generate a signal for desired selection control using a decoder circuit, a shift register circuit, or the like.

[0057] Here, the signal applied to the wiring PL can be generated by the driver circuit WWD when writing data to the memory cell MC, and by the driver circuit RWD when reading data from the memory cell MC.

[0058] The driver circuit WBD has a function of outputting a data signal to be written to the memory cell MC. The driver circuit WBD has a function of outputting a data signal to be given to the wiring WBL. The driver circuit WBD has a decoder circuit and a plurality of latch circuits. The driver circuit WBD has a function of outputting the data signal held in the latch circuits at the timing when data is written to the memory cell MC.

[0059] The driver circuit RBD has a function of reading data from the memory cell MC. Specifically, the driver circuit RBD has a function of determining the data read from the memory cell MC based on the potential output from the memory cell MC when data is read from the memory cell MC. For example, when binary data is read from the memory cell MC, the driver circuit RBD has a function of determining whether the value of the data read from the memory cell MC is "0" or "1" based on the potential output from the memory cell MC. The driver circuit RBD has a function of determining the data read from the memory cell MC, for example, by comparing the magnitude relationship between the potential of the wiring RBL and a reference potential. The driver circuit RBD also has a function of outputting a potential representing the data read from the memory cell MC, for example, to the outside of the semiconductor device 10. For example, the driver circuit RBD can generate a desired potential to be output to the outside based on the potential output from the memory cell MC using an amplifier circuit, a comparator circuit, or the like. The driver circuit RBD can also have a precharge circuit. In this case, the driver circuit RBD can output a precharge potential to the wiring RBL.

[0060] Here, the wiring WWL can be referred to as a write word line or simply as a word line, and the drive circuit WWD can be referred to as a write word line drive circuit or simply as a word line drive circuit. The wiring RWL can be referred to as a read word line or simply as a word line, and the drive circuit RWD can be referred to as a read word line drive circuit or simply as a word line drive circuit. Furthermore, the wiring PL can be referred to as a plate line.

[0061] The wiring WBL can be referred to as a write bit line or simply as a bit line, the driver circuit WBD can be referred to as a write bit line driver circuit or simply as a bit line driver circuit, the wiring RBL can be referred to as a read bit line or simply as a bit line, and the driver circuit RBD can be referred to as a read bit line driver circuit or simply as a bit line driver circuit.

[0062] 4 is a circuit diagram showing an example configuration of a memory cell MC. The memory cell MC has a transistor M1, a transistor M2, a transistor M3, and a capacitor C2. The capacitor C2 is a ferroelectric capacitor with a ferroelectric layer between a pair of electrodes. The capacitor C2, which is a ferroelectric capacitor with a ferroelectric layer, is indicated by a circuit symbol different from that of a capacitor without a ferroelectric layer.

[0063] In the following description, each transistor in the memory cell MC shown in FIG. 4A is an n-channel transistor. For example, if the transistor M1 is an n-channel transistor, the transistor M1 can be turned on by setting the wiring WWL to a high potential (also referred to as an H-level potential or H level). The same applies to the transistor M3. Note that the following description can be applied even if some or all of the transistors in the memory cell MC are p-channel transistors by appropriately reversing the magnitude relationship of the potentials, for example.

[0064] One of the source or drain of transistor M1 is electrically connected to the gate of transistor M2. The gate of transistor M2 is electrically connected to one electrode of capacitor C2. One of the source or drain of transistor M2 is electrically connected to one of the source or drain of transistor M3. Here, the node electrically connecting one of the source or drain of transistor M1, the gate of transistor M2, and one electrode of capacitor C2 is referred to as node SN.

[0065] The other of the source and drain of transistor M1 is electrically connected to a terminal for transmitting a signal of wiring WBL. The gate of transistor M1 is electrically connected to a terminal for transmitting a signal of wiring WWL. The other of the source and drain of transistor M2 is electrically connected to a terminal for transmitting a signal of wiring SL. The other of the source and drain of transistor M3 is electrically connected to a terminal for transmitting a signal of wiring RBL. The gate of transistor M3 is electrically connected to a terminal for transmitting a signal of wiring RWL. The other electrode of capacitor C2 is electrically connected to a terminal for transmitting a signal of wiring PL.

[0066] The wiring SL is a wiring to which a constant potential is applied for reading data from the memory cell MC. When reading data from the memory cell MC, a current can be passed between the wiring RBL and the wiring SL according to the data stored in the memory cell MC.

[0067] The transistors M1 to M3 can be transistors whose channel formation regions include silicon (hereinafter referred to as Si transistors) and / or transistors whose channel formation regions include an oxide semiconductor (hereinafter referred to as OS transistors).

[0068] Silicon used for the channel formation region of a Si transistor can be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single-crystal silicon, etc. As the transistors M1 to M3, in addition to OS transistors and Si transistors, transistors whose channel formation region contains Ge or the like, transistors whose channel formation region contains a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe, transistors whose channel formation region contains carbon nanotubes, transistors whose channel formation region contains an organic semiconductor, etc. can be used.

[0069] OS transistors can be easily integrated because they can be freely arranged by stacking them on circuits using Si transistors, etc. Furthermore, OS transistors can be fabricated at low cost because they can be fabricated using the same manufacturing equipment as Si transistors.

[0070] Furthermore, OS transistors have better electrical characteristics than Si transistors in high-temperature environments. Specifically, they have a large ratio of on-current to off-current even at high temperatures of 100° C. to 200° C., preferably 125° C. to 150° C., and therefore can perform good switching operations.

[0071] 4B is a schematic diagram showing an example of the configuration of the capacitor C2. The capacitor C2 has a ferroelectric layer FE between the electrode UE and the electrode LE. Such a capacitor C2 having a ferroelectric layer is sometimes called a ferroelectric capacitor or a ferroelectric capacitor.

[0072] When a voltage (electric field or electric field) is applied between the electrodes UE and LE in the capacitor C2 equipped with a ferroelectric layer, the direction and amount of polarization of the ferroelectric layer FE change depending on the direction and amount of the applied voltage. A signal (data) is retained (written) between the electrodes UE and LE by utilizing the change in the polarization state of the ferroelectric layer FE. In the capacitor C2, polarization remains in the ferroelectric layer FE even if the voltage between the electrodes UE and LE is set to zero. To rewrite the polarization, a voltage to reverse the polarization (polarization reversal voltage) is applied.

[0073] 4C is a graph showing the magnitude of polarization of the ferroelectric layer FE in response to the electric field applied to the ferroelectric layer FE. In FIG. 4C, the horizontal axis represents the electric field E applied to the ferroelectric layer FE, and the vertical axis represents the polarization P of the ferroelectric layer FE.

[0074] When the electric field applied to the ferroelectric layer FE is increased, the polarization of the ferroelectric layer FE increases. H After applying the electric field E to the ferroelectric layer FE, if the electric field applied to the ferroelectric layer FE is lowered, negative charges will be biased to one electrode side of the capacitance C2 and positive charges will be biased to the other electrode side of the capacitance C2, so that positive polarization will remain when the electric field becomes 0. L After applying the electric field E to the ferroelectric layer FE, if the electric field applied to the ferroelectric layer FE is increased, the positive charges will be biased to one electrode side of the capacitance C2 and the negative charges will be biased to the other electrode side of the capacitance C2, so that when the electric field becomes 0, a negative polarization will remain. H and electric field E L The voltage for applying this can be called a polarization inversion voltage. By applying the polarization inversion voltage to the capacitor C2, data can be written to the memory cell MC.

[0075] Materials that can be used for the ferroelectric layer FE and have ferroelectric properties include hafnium oxide, zirconium oxide, HfZrO X Examples of materials that can have ferroelectricity include metal oxides such as J1 (wherein X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 is added (here, element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.). The atomic ratio of hafnium atoms to element J1 can be appropriately set; for example, the atomic ratio of hafnium atoms to element J1 may be 1:1 or close to that. Ferroelectric materials include zirconium oxide to which element J2 is added (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.). The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to that ratio. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0076] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b (where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1.)) and metal nitrides such as Al-Ga-Sc nitride or Ga-Sc nitride. Ferroelectric materials include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum (Al), gallium (Ga), indium (In), etc. Element M2 is one or more elements selected from boron (B), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), neodymium (Nd), europium (Eu), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Examples of materials that may exhibit ferroelectricity include materials obtained by adding element M3 to the above-mentioned metal nitrides. The element M3 is one or more elements selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. The ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set. Since the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, which is a Group 15 element, these metal nitrides are sometimes referred to as Group 3-5 ferroelectrics or Group 3 nitride ferroelectrics.

[0077] Furthermore, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N or BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0078] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal nitride oxides in which oxygen is added to the above metal nitrides, etc. may also be used.

[0079] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the ferroelectric layer FE can have a laminated structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity. Furthermore, the term "ferroelectric" is intended to include not only materials that exhibit ferroelectricity but also materials capable of exhibiting ferroelectricity.

[0080] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferred as a material capable of exhibiting ferroelectricity, since it can be processed into a thin film of a few nanometers and still retain ferroelectricity. The film thickness of the ferroelectric layer FE can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, a film thickness of 8 nm to 12 nm is preferred. By using a ferroelectric layer that can be thinned, the capacitor C2 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. Note that, in this specification, a layer of a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification.

[0081] In addition, HfZrO is a material that can have ferroelectric properties. X When using a ferroelectric material, it is preferable to form the film using atomic layer deposition (ALD), particularly thermal ALD. Furthermore, when using thermal ALD to form a film of a material that can have ferroelectricity, it is preferable to use a material that does not contain hydrocarbons (also referred to as Hydro Carbon, HC) as a precursor. If the material that can have ferroelectricity contains either or both of hydrogen and carbon, this may inhibit the crystallization of the material that can have ferroelectricity. Therefore, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Furthermore, as a material that can have ferroelectricity, a material containing hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as the precursor.

[0082] When a film is formed using a material that can have ferroelectricity, impurities in the film, in this case at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed, thereby forming a film having high-purity intrinsic ferroelectricity. The film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high compatibility in manufacturing processes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0083] In addition, HfZrO is a material that can have ferroelectric properties. X When using hafnium oxide and zirconium oxide, it is preferable to use a thermal ALD method to alternately form films of hafnium oxide and zirconium oxide in a 1:1 ratio.

[0084] Furthermore, when a film of a material that may have ferroelectricity is formed using a thermal ALD method, HO or O can be used as the oxidizing agent. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O, O, N, NO, HO, and HO.

[0085] The crystal structure of the material capable of exhibiting ferroelectricity is not particularly limited. For example, the crystal structure of the material capable of exhibiting ferroelectricity may be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, and monoclinic. In particular, the material capable of exhibiting ferroelectricity preferably has an orthorhombic crystal structure, since ferroelectricity is exhibited. Alternatively, the material capable of exhibiting ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.

[0086] Data is written to the memory cell MC according to the direction of the electric field applied to the ferroelectric layer of the capacitor C2, which is determined by the potential of the node SN and the potential of the wiring PL. As will be described in detail later, data is written to the memory cell MC by applying a polarization inversion voltage to the capacitor C2. The ferroelectric layer of the capacitor C2 can take on different polarization states depending on the data to be written to the memory cell MC. Therefore, the data written to the memory cell MC can be retained by the polarization state of the ferroelectric layer of the capacitor C2. The difference in polarization state is maintained even if, for example, the electric field applied to the capacitor C2 is zero. Therefore, data can continue to be retained in the memory cell MC even if, for example, the electric field applied to the capacitor C2 is zero.

[0087] Data is read from the memory cell MC by utilizing capacitive coupling at the capacitor C2 when the potential of the wiring PL is changed. When the potential of the wiring PL is changed, the node SN is placed in an electrically floating state, which causes capacitive coupling at the capacitor C2. Therefore, the potential of the node SN changes in response to changes in the potential of the wiring PL. The change in the potential of the node SN depends on the capacitance value of the capacitor C2, which in turn depends on the polarization state of the ferroelectric layer of the capacitor C2. Therefore, the potential of the gate of the transistor M2 can be changed depending on the data stored. Different gate potentials of the transistor M2 result in different amounts of current flowing between the source and drain of the transistor M2. This results in different potentials of the wiring RBL. Data can be read from the memory cell MC by changing the potential of the wiring RBL.

[0088] 5A is a timing chart showing the operation of writing data to the memory cell MC. In FIG. 5A, the potentials of the wiring WWL, the wiring WBL, the wiring PL, the node SN, the wiring RBL, the wiring RWL, and the wiring SL are shown. Also, in FIG. 5A, the potentials of the switch SW <0> or switch SW <k-1>5A shows the state of "data1" and "data0" as data to be written to the memory cell MC. "data1" is shown as a high potential signal, and "data0" is shown as a low potential signal.

[0089] In Fig. 5A, high potential is indicated by "H" and low potential is indicated by "L." This is the same in the other figures.

[0090] Before time T01, the potentials of the wirings WWL, WBL, PL, node SN, RBL, RWL, and SL are all low.

[0091] Between time T01 and time T02, the switch SW <0> or switch SW <k-1>is turned on (ON). In this state, the driver circuit WBD applies a signal potential corresponding to data "data1" or "data0" to be written to the memory cell MC to the wiring WBL. The potential of the wiring WWL is set to high. As a result, the potential of the wiring WBL is applied to the node SN. The potential of the wiring PL is set to high from time T01 to time T02.

[0092] Between time T01 and time T02, when the wiring PL is at a high potential and the node SN is at a high potential, the potential shown in FIG. 5B is applied to the electrodes of the capacitor C2. As shown in FIG. 5B, since the electrodes of the capacitor C2 are both at a high potential and at the same potential, a voltage exceeding the inversion polarization voltage is not applied, and no electric field is generated in the ferroelectric layer. On the other hand, between time T01 and time T02, when the wiring PL is at a high potential and the node SN is at a low potential, the potential shown in FIG. 5C is applied to the electrodes of the capacitor C2. In this case, for example, an inversion polarization voltage is applied to the capacitor C2, and an electric field E L As a result, a polarization state corresponding to "data0" is written to the capacitor C2.

[0093] When a voltage exceeding the inversion polarization voltage is applied to the capacitor C2, the transistors M1 to M3 are preferably transistors that can withstand high voltages (voltage resistance). For example, the transistors M1 to M3 are preferably OS transistors. OS transistors have higher voltage resistance than Si transistors.

[0094] Between time T02 and time T03, the potential of the wiring PL is set to a low potential. When the potential of the node SN is set to a high potential, the potential shown in FIG. 5D is applied to the electrode of the capacitor C2. As shown in FIG. 5D, a reverse polarization voltage opposite to the reverse polarization voltage shown in FIG. 5C is applied to the capacitor C2, and an electric field E H As a result, a polarization state corresponding to "data1" is written to the capacitor C2. Meanwhile, from time T02 to time T03, when the potential of the node SN is low, the potential shown in FIG. 5E is applied to the electrodes of the capacitor C2. As shown in FIG. 5E, since both electrodes of the capacitor C2 are at low potential and equipotential, a voltage exceeding the inversion polarization voltage is not applied, and no electric field is generated in the ferroelectric layer.

[0095] As described above, when data0 is written to the memory cell MC, data0 is written to the memory cell MC from time T01 to time T02. On the other hand, when data1 is written to the memory cell MC, data1 is written to the memory cell MC from time T02 to time T03.

[0096] Between time T03 and time T04, the potential of the wiring WBL is set to a low potential. This causes the potential of the node SN to become low. Here, since the potential of the wiring PL is also low, a voltage exceeding the inversion polarization voltage is not applied to the ferroelectric layer of the capacitor C2. Therefore, the polarization state of the ferroelectric layer is maintained. Therefore, the data written to the memory cell MC between time T01 and time T03 is maintained.

[0097] After time T04, the potential of the wire WWL is set to a low potential, and the switch SW <0> or switch SW <k-1>is turned off, thereby completing the operation of writing data to the memory cell MC.

[0098] 6 is a timing chart showing the operation of reading data from the memory cell MC. In FIG. 6, similarly to FIG. 5A, the potentials of the wiring WWL, the wiring WBL, the wiring PL, the node SN, the wiring RBL, the wiring RWL, and the wiring SL are shown. In addition, the switch SW <0> or switch SW <k-1>6 shows the state of "data1" and "data0" as data to be written to the memory cell MC. In FIG. 6, "data1" and "data0" correspond to data held as the polarization state of the ferroelectric layer of the capacitor C2 during the data write operation.

[0099] Before time T11, the potentials of the wirings WWL, WBL, PL, node SN, RBL, RWL, and SL are all low.

[0100] Between time T11 and time T12, the switch SW <0> is turned off. This cuts off the electrical connection between the driver circuit WBD and the memory cell MC, and for example, the signal generated by the driver circuit WBD is no longer applied to the memory cell MC. After that, the potential of the wiring WWL is set to a high potential. This turns on the transistor M1, and the node SN and the wiring WBL become conductive. Here, since the electrical connection between the driver circuit WBD and the memory cell MC is cut off, even if the node SN and the wiring WBL become conductive, the node SN becomes electrically floating. In addition, the potential of the wiring RBL is precharged to, for example, a high potential. Furthermore, the switch SW <1> or switch SW <k-1>are set to ON or OFF, respectively. The method for determining which switch SW to turn on will be described later.

[0101] The potential of the wiring PL is set to a high potential from time T12 to time T13. As described above, the node SN is in an electrically floating state. Therefore, the potential of the node SN fluctuates due to the capacitance C2 and capacitive coupling at the node SN.

[0102] 7A is a circuit diagram in which parasitic capacitances and the like are added to the memory cell MC shown in FIG. 4A. As shown in FIG. 7A, the node SN has a capacitance C3, which is a parasitic capacitance caused by the gate capacitance of the transistor M2 and the like. In addition, as described above, the wiring WBL has a capacitance C1, which is a parasitic capacitance.

[0103] Between time T12 and time T13, the node SN and the wiring WBL are in a conductive state. SN is the capacitance value C of capacitor C2 FE and the capacitance value C of the parasitic capacitance C3 S and the capacitance value C due to the capacitance C1, which is the parasitic capacitance of the wiring WBL. WBL If the fluctuation range of the potential of the wiring PL is ΔVPL, then ΔV SN can be expressed by equation (1).

[0104]

number

[0105] Capacitance value C of capacitor C2 FE is determined by the polarization state of the ferroelectric layer of the capacitor C2. This polarization state differs depending on whether the data stored in the memory cell MC is "data1" or "data0". Therefore, the fluctuation width ΔV of the potential of the node SN varies depending on the data stored in the memory cell. SN Therefore, the potential V of the node SN can be SN can be made different.

[0106] From time T13 to time T14, the potential of the wiring RWL is set to a high potential, which turns on the transistor M3 and causes a current corresponding to the potential of the node SN to flow between the drain and source of the transistor M2.

[0107] 7B is a diagram showing the potential of the node SN and the current flowing between the drain and source of the transistor M2 when the potential of the wiring PL is changed from a low potential to a high potential when "data0" is held in the memory cell MC. In the case shown in FIG. 7B, the potential of the node SN is set to potential Vdata0, and the current flowing between the drain and source of the transistor M2 is set to current Idata0.

[0108] 7C is a diagram showing the potential of node SN and the current flowing between the drain and source of transistor M2 when the potential of wiring PL is changed from low to high when "data1" is held in memory cell MC. In the case shown in FIG. 7C, the potential of node SN is assumed to be potential Vdata1, and the current flowing between the drain and source of transistor M2 is assumed to be current Idata1. Current Idata1 is assumed to be larger than current Idata0.

[0109] The current Idata1 is greater than the current Idata0. Therefore, if the potential of the wiring RBL is higher than the potential of the wiring SL, the potential of the wiring RBL when "data1" is stored in the memory cell MC is lower than the potential of the wiring RBL when "data0" is stored in the memory cell MC. Therefore, data can be read from the memory cell MC based on the potential of the wiring RBL.

[0110] Here, the capacitance value of the capacitance C2 when the data held in the memory cell MC is “data1” is expressed as capacitance value C FE1 When the data stored in the memory cell MC is "data0", the capacitance value of the capacitance C2 is set to C FE0 If the difference between the potential Vdata1 and the potential Vdata0 is ΔVdata, ΔVdata can be expressed by equation (2).

[0111]

number

[0112] The larger ΔVdata is, the more accurate the data stored in the memory cell MC can be read, which is preferable. s +C WBL The value of "Cmax" is calculated by converting equation (2) into "C s +C WBL " is the value at which the derivative obtained by partial differentiation with respect to " becomes 0, and can be expressed by equation (3).

[0113]

number

[0114] Therefore, "C s +C WBL " is √(C FE1 C FE0 ) so that C WBL By adjusting the value of ΔVdata, it is possible to increase it.

[0115] Here, by controlling the on / off of the switch SW, the capacitance value C WBL For example, the switch SW <1> or switch SW <k-1>When all of the switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW12, SW13, SW14, SW15, SW26, SW27, SW28, SW30, SW41, SW52, SW63, SW74, SW85, SW96, SW16, SW17, SW18, SW19, SW20, SW21, SW22, SW23 <1> or switch SW <k-1>When one of the switches SW electrically connected to the memory cell from which data is to be read is turned on, two capacitors C1 are electrically connected to the node SN. <1> or switch SW <k-1>When all the capacitance values ​​C WBL By increasing the number of switches SW that are turned on, the capacitance C WBL can be made even larger.

[0116] Capacitance value C FE1 , and capacitance value C FE0 When the capacitance value C FE1 , and capacitance value C FE0 In this case, adjust the number of switches SW to be turned on and WBL By adjusting the value of ΔVdata, it is possible to prevent ΔVdata from becoming small, and therefore the semiconductor device 10 can be made a highly reliable semiconductor device.

[0117] From time T14 to time T15, the potentials of the wiring PL and the wiring RWL are set to low. After time T15, the potential of the wiring WWL is set to low. This completes the reading of data from the memory cell MC.

[0118] A semiconductor device according to one embodiment of the present invention includes a plurality of memory cell arrays MCA, a switch array SWA is provided between the memory cell arrays MCA, and a write bit line driver circuit is electrically connected to each of the plurality of memory cell arrays MCA by a write bit line via a switch SW provided in the switch array SWA.

[0119] In the semiconductor device of one embodiment of the present invention, when data is read from a memory cell MC in the memory cell array MCA, a high potential is applied to the wiring WWL, which is a write word line, to turn on the transistor M1. When the data held in the memory cell MC is "data1", the capacitance value C FE1 and the capacitance value C of the capacitor C2 when the data stored in the memory cell MC is “data0” FE0 The on / off of the switch SW is controlled based on the above. This makes it possible to increase the difference between the potential of the wiring RBL when "data0" is read from the memory cell MC and the potential of the wiring RBL when "data1" is read from the memory cell MC. Therefore, data can be read from the memory cell MC with high accuracy.

[0120] 8A is a timing chart showing a data read operation in the memory cell MC, which is a modification of the operation method shown in FIG. 6. In the operation method shown in FIG. 8A, the potential of the wiring SL is set to a high potential. In addition, from time T11 to time T12, the potential of the wiring RBL is precharged to a low potential.

[0121] 8B and 8C are diagrams showing the current flowing between the drain and source of the transistor M2 from time T13 to time T14, which are modifications of FIGS. 7B and 7C, respectively. When the memory cell MC is driven by the method shown in FIG. 8A, a current Idata0 corresponding to the potential Vdata0 or a current Idata1 corresponding to the potential Vdata1 flows from the wiring SL to the wiring RBL from time T13 to time T14, as shown in FIGS.

[0122] 9A and 9B are circuit diagrams showing an example of the configuration of a memory cell MC, which is a modified example of the memory cell MC shown in FIG. 4A. The memory cell MCa shown in FIG. 9A differs from the memory cell MC shown in FIG. 4A in that the transistors M1 to M3 have back gate electrodes. The back gates of the transistors M1 to M3 are supplied with a back gate voltage V BG is applied. In the memory cell MCa, the on-current of each transistor can be increased.

[0123] The memory cell MCb shown in Figure 9B differs from the memory cell MC shown in Figure 4A in that it omits the transistor M3 and the line RWL is electrically connected to the back gate of the transistor M2. In the memory cell MCb, the threshold voltage of the transistor M2 can be controlled by a selection signal applied to the line RWL. This allows control of whether or not a current flows between the line RBL and the line SL.

[0124] FIG. 10A is a perspective view showing an example of the configuration of semiconductor device 10. Semiconductor device 10 shown in FIG. 10A has layer 11 and layer 13. Layer 11 and layer 13 are stacked so as to have an overlapping region. Note that in FIG. 10A, layer 11 and layer 13 are shown separately to make it easier to understand the configuration of semiconductor device 10. Similar descriptions are used in other figures.

[0125] For example, the layer 11 may be provided with a driving circuit WWD, a driving circuit RWD, a driving circuit WBD, and a driving circuit RBD, and the layer 13 may be provided with a memory unit MU. Therefore, the semiconductor device 10 may be designed to have an area where the memory unit MU and the driving circuits overlap.

[0126] 10A, the drive circuit and the memory cells provided in the memory unit MU can be configured with transistors having different electrical characteristics. For example, the drive circuit can be configured with Si transistors, and the memory cells provided in the memory unit MU can be configured with OS transistors. This increases the design flexibility of the semiconductor device 10.

[0127] Fig. 10B is a perspective view showing a configuration example of the semiconductor device 10, which is a modification of the semiconductor device 10 shown in Fig. 10A. The semiconductor device 10 shown in Fig. 10B has a plurality of layers 13. Fig. 10B shows an example in which k layers 13 are provided.

[0128] In the semiconductor device 10 shown in FIG. 10B, for example, the layer 13 <1> The memory cell array MCA <1> and switch array SWA <0> Also, layer 13 <2> The memory cell array MCA <2> and switch array SWA <1> Furthermore, a layer 13 is provided. <k>The memory cell array MCA <k>and switch array SWA <k-1>and are provided.

[0129] By providing a plurality of layers 13, it is possible to increase the total area of ​​the memory unit MU while preventing the semiconductor device 10 from becoming large in size, and therefore the semiconductor device 10 can be a semiconductor device capable of storing a large amount of data.

[0130] FIG. 11 is a perspective view showing a configuration example of semiconductor device 10, which is a modification of semiconductor device 10 shown in FIG. 10A. Semiconductor device 10 shown in FIG. 11 differs from semiconductor device 10 shown in FIG. 10A in that layer 15 is provided. Layer 15 is provided by stacking layers 11 and 13 so as to have overlapping regions. Note that in FIG. 11, layers 11, 13, and 15 are shown separately to make the configuration of semiconductor device 10 easier to understand.

[0131] The layer 15 has a processing unit PU. The processing unit PU has a function of performing calculations to add functions to the semiconductor device 10. The processing unit PU has a function of performing, for example, a product-sum calculation, such as a product-sum calculation of a neural network. When the processing unit PU has a function of performing a product-sum calculation, the memory unit MU can hold, for example, data corresponding to weight parameters used in the product-sum calculation (weight data) and data corresponding to bias values ​​(bias data).

[0132] The processing unit PU is electrically connected to a power supply line 25. A power supply potential required for driving the processing unit PU is applied to the processing unit PU via the power supply line 25.

[0133] 11 , the layer 13 in which the memory unit MU is provided is preferably provided between the layer 15 in which the processing unit PU is provided and the layer 11 in which a drive circuit for driving the memory cells provided in the memory unit MU is provided. This allows the wiring distance from the processing unit PU to the memory unit MU to be shorter than, for example, when the layer 11 is provided between the layer 15 and the layer 13. This allows the communication speed when the processing unit PU reads data held in the memory unit MU to be increased, thereby increasing the drive speed of the semiconductor device 10. Furthermore, by shortening the wiring distance from the processing unit PU to the memory unit MU, the power consumption of the semiconductor device 10 can be reduced.

[0134] It is also preferable to provide a plurality of arithmetic units PU in the layer 15. Fig. 11 shows an example in which arithmetic units PU_1 to PU_4 are provided in the layer 15 as the arithmetic units PU. Different power supply lines 25 can be electrically connected to the arithmetic units PU_1 to PU_4, respectively. Fig. 11 shows a configuration example in which the arithmetic unit PU_1 is electrically connected to the power supply line 25_1, the arithmetic unit PU_2 is electrically connected to the power supply line 25_2, the arithmetic unit PU_3 is electrically connected to the power supply line 25_3, and the arithmetic unit PU_4 is electrically connected to the power supply line 25_4. For example, the power supply lines 25_1 to 25_4 may be configured not to be electrically connected to each other.

[0135] By providing multiple processing units PU and electrically connecting each to a different power supply line 25, even if some of the processing units PU stop operating normally, the remaining processing units PU can continue to operate, allowing the processing units PU to continue performing operations. This increases the reliability of the semiconductor device 10 compared to a configuration in which only one processing unit PU is provided. Note that each processing unit PU may have a driving circuit in layer 11. For example, in the example shown in FIG. 11, four driving circuits WWD, four driving circuits RWD, four driving circuits WBD, and four driving circuits RBD may be provided in layer 11.

[0136] Fig. 12 is a diagram showing an example of the layout of layer 15. Fig. 12 was drawn using "SX-Meister," an EDA system for semiconductor design manufactured by Jedat Co., Ltd. As shown in Fig. 12, calculation units PU_1 to PU_4 can be provided on layer 15.

[0137] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0138] (Embodiment 2) In this embodiment, a structural example of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. By using this structure, the degree of freedom in designing a semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of a semiconductor device can be increased.

[0139] <Configuration example of semiconductor device> 13 shows, as an example, the semiconductor device described in the above embodiment, which includes a transistor 300, a transistor 500, and a capacitor 600. Fig. 14A shows a cross-sectional view of the transistor 500 in the channel length direction, Fig. 14B shows a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 14C shows a cross-sectional view of the transistor 300 in the channel width direction.

[0140] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has characteristics of a small off-state current and a field-effect mobility that does not change easily even at high temperatures. By applying the transistor 500 to a semiconductor device, such as the OS transistor described in the above embodiment, a semiconductor device whose operating capability is not easily degraded even at high temperatures can be realized.

[0141] The transistor 500 is provided above the transistor 300, for example, and the capacitor 600 is provided above the transistors 300 and 500, for example. Note that the capacitor 600 can be any of the capacitors described in the above embodiments.

[0142] The transistor 300 is provided over a substrate 310 and includes an isolation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 can be applied to, for example, the Si transistor described in the above embodiment. As an example, FIG. 13 illustrates a configuration in which the gate of the transistor 300 is electrically connected to one of the source and drain of the transistor 500 via a pair of electrodes of a capacitor 600.

[0143] The substrate 310 is preferably a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0144] 14C , the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width can be increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0145] The transistor 300 may be either a p-channel type or an n-channel type.

[0146] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that will be one of the source and drain regions, and the low-resistance region 314b that will be the other of the source and drain regions, preferably contain a semiconductor such as a silicon-based semiconductor, and more preferably single-crystal silicon. Alternatively, they may be formed of a material such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or GaN (gallium nitride). A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a high electron mobility transistor (HEMT) by using GaAs and GaAlAs, etc.

[0147] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0148] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material.

[0149] Note that the work function is determined by the material of the conductor, and therefore the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked layer, and tungsten is particularly preferable in terms of heat resistance.

[0150] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed using, for example, a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or a mesa isolation method.

[0151] The transistor 300 illustrated in FIG. 13 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration, a driving method, or the like. For example, the transistor 300 may have a planar structure instead of the FIN structure illustrated in FIG. 14C. For example, when the semiconductor device is a unipolar circuit including only OS transistors, the structure of the transistor 300 may be the same as that of the transistor 500 including an oxide semiconductor, as illustrated in FIG. 15. The details of the transistor 500 will be described later. In this specification and the like, a unipolar circuit refers to a circuit including transistors of only one polarity, that is, an n-channel transistor or a p-channel transistor.

[0152] In FIG. 15 , the transistor 300 is provided on a substrate 310A. However, in this case, the substrate 310A may be a semiconductor substrate similar to the substrate 310 of the semiconductor device in FIG. 13 . Examples of the substrate 310A that can be used include an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE), as well as synthetic resins such as acrylic. Alternatively, there are polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, etc. Alternatively, there are polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, paper, etc.

[0153] In the transistor 300 shown in FIG. 13, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0154] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0155] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0156] The insulator 322 may function as a planarizing film that flattens steps caused by, for example, the transistor 300. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0157] The insulator 324 is preferably a film having a barrier property that prevents hydrogen, impurities, or the like from diffusing from the substrate 310 or the transistor 300 to a region where the transistor 500 is provided.

[0158] An example of a film having a barrier property against hydrogen is silicon nitride formed by a chemical vapor deposition (CVD) method. Here, diffusion of hydrogen into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0159] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorbed hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0160] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0161] Furthermore, the insulators 320, 322, 324, and 326 are embedded with the capacitor 600 or the conductors 328 and 330 connected to the transistor 500. The conductors 328 and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, the same reference numeral may be used to denote multiple structures. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0162] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0163] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 13 , the insulator 350, the insulator 352, and the insulator 354 are stacked in this order over the insulator 326 and the conductor 330. The conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0164] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against impurities such as hydrogen or water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably made of an insulator having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The conductor 356 preferably includes a conductor having a barrier property against impurities such as hydrogen or water. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, thereby suppressing diffusion of hydrogen from the transistor 300 to the transistor 500.

[0165] Note that, for example, tantalum nitride is preferably used as the conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0166] Furthermore, on the insulator 354 and the conductor 356, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order.

[0167] The insulator 360 is preferably an insulator having barrier properties against impurities such as water or hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0168] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, it is preferable to use an insulator that has a barrier property against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 362 and / or the insulator 364 can be made of a material that can be used for the insulator 324.

[0169] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0170] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 364 and the conductor 366. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen and hydrogen.

[0171] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 310 or a region where the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0172] As described above, silicon nitride formed by a CVD method can be used as a film having a barrier property against hydrogen. Also, as a film having a barrier property against hydrogen, for example, metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide are preferably used for the insulators 510 and 514.

[0173] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0174] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0175] A conductor 518 and a conductor constituting the transistor 500 (for example, the conductor 503 shown in FIGS. 14A and 14B ) are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a capacitor 600 or a plug or wiring connected to the transistor 300. The conductor 518 can be formed using a material similar to that of the conductors 328 and 330.

[0176] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0177] Above the insulator 516 is the transistor 500 .

[0178] As shown in FIGS. 14A and 14B, the transistor 500 includes an insulator 516 on an insulator 514, a conductor 503 (conductors 503a and 503b) disposed so as to be embedded in the insulators 514 and 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and an oxide 572a on the oxide 572b. conductor 542b on oxide 530b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping with part of oxide 530b, and insulator 544 arranged on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 571b. 14A and 14B, the insulator 552 is in contact with the upper surface of the insulator 522, the side surface of the insulator 524, the side surface of the oxide 530a, the side surface and upper surface of the oxide 530b, the side surface of the conductor 542, the side surface of the insulator 571, the side surface of the insulator 544, the side surface of the insulator 580, and the lower surface of the insulator 550. The upper surface of the conductor 560 is disposed so as to be at approximately the same height as the upper surfaces of the insulators 554, 550, 552, and 580. The insulator 574 is in contact with at least a portion of the upper surface of the conductor 560, the upper surface of the insulator 552, the upper surface of the insulator 550, the upper surface of the insulator 554, and the upper surface of the insulator 580. Note that the conductors 542a and 542b are collectively referred to as conductors 542, and the insulators 571a and 571b are collectively referred to as insulators 571.

[0179] Openings reaching the oxide 530b are provided in the insulator 580 and the insulator 544. The insulator 552, the insulator 550, the insulator 554, and the conductor 560 are disposed in the openings. In addition, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b in the channel length direction of the transistor 500. The insulator 554 has a region in contact with a side surface of the conductor 560 and a region in contact with a bottom surface of the conductor 560.

[0180] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b.

[0181] Note that although the transistor 500 has a structure in which the oxide 530 has two layers, the oxide 530a and the oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0182] The conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode. The insulators 552, 550, and 554 function as first gate insulators, and the insulators 522 and 524 function as second gate insulators. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 542a functions as one of a source and a drain, and the conductor 542b functions as the other. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0183] FIG. 16A shows an enlarged view of the vicinity of the channel formation region in FIG. 14A. Supply of oxygen to the oxide 530b forms a channel formation region in a region between the conductor 542a and the conductor 542b. Thus, as shown in FIG. 16A, the oxide 530b includes a region 530bc that functions as a channel formation region of the transistor 500, and regions 530ba and 530bb that are provided on either side of the region 530bc and function as source and drain regions. At least a portion of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is located in a region between the conductor 542a and the conductor 542b. The region 530ba overlaps with the conductor 542a, and the region 530bb overlaps with the conductor 542b.

[0184] The region 530bc, which functions as a channel formation region, has a smaller oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V) than the regions 530ba and 530bb. O Since the region 530bc has a low impurity concentration or a low oxygen vacancy, it is a high-resistance region with a low carrier concentration. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.

[0185] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereinafter referred to as V O H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible.

[0186] The regions 530ba and 530bb that function as source and drain regions have oxygen vacancies (V O ) or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, resulting in an increased carrier concentration and low resistance. That is, the regions 530ba and 530bb are n-type regions with a higher carrier concentration and lower resistance than the region 530bc.

[0187] Here, the carrier concentration of the region 530bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 530bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0188] Furthermore, a region having a carrier concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc may be formed between region 530bc and regions 530ba or 530bb. That is, this region functions as a junction region between region 530bc and regions 530ba or 530bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 530ba and 530bb and equal to or higher than those of region 530bc.

[0189] 16A illustrates an example in which the regions 530ba, 530bb, and 530bc are formed in the oxide 530b, but the present invention is not limited to this. For example, each of the regions may be formed not only in the oxide 530b but also in the oxide 530a.

[0190] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0191] In the transistor 500, the oxide 530 including the channel formation region (the oxide 530a and the oxide 530b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0192] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0193] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0194] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0195] In this way, by disposing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a into the oxide 530b.

[0196] Furthermore, since the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Since the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0197] The oxide 530b preferably has crystallinity, and in particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 530b.

[0198] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., oxygen vacancies (V O In particular, the CAAC-OS can be made to have a dense structure with higher crystallinity by performing heat treatment at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide is not polycrystallized after formation of the metal oxide. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0199] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0200] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy is formed as a defect where hydrogen enters the oxygen vacancy (hereinafter referred to as V O H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0201] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This supplies oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device having the transistor.

[0202] Therefore, in the oxide semiconductor, the region 530bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 530ba and 530bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 530ba and 530bb.

[0203] Therefore, in this embodiment, in a state where the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 530bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0204] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 530bc. The V of the region 530bc can be activated by the action of the plasma or microwaves. O H is split off, hydrogen H is removed from the region 530bc, and oxygen vacancy V O can be compensated with oxygen. O H → H + V O This reaction occurs, and the hydrogen concentration in the region 530bc can be reduced. O H can be reduced to lower the carrier concentration.

[0205] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 542a and 542b and do not reach the regions 530ba and 530bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 571 and 580 that cover the oxide 530b and the conductor 542. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0206] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this manner, oxygen can be efficiently injected into the region 530bc. Furthermore, by arranging the insulator 552 to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, injection of more oxygen than necessary into the region 530bc can be suppressed, and oxidation of the side surface of the conductor 542 can be suppressed. Furthermore, oxidation of the side surface of the conductor 542 during formation of the insulating film that becomes the insulator 550 can be suppressed.

[0207] The oxygen implanted into the region 530bc can be in various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 530bc preferably takes one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 552 and the insulator 550 can be improved, thereby improving the reliability of the transistor 500.

[0208] In this way, oxygen vacancies and V O By removing H, the region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 530ba and 530bb, which function as source and drain regions, can be suppressed, thereby maintaining conductivity. This suppresses fluctuations in the electrical characteristics of the transistor 500 and reduces variations in the electrical characteristics of the transistor 500 within the substrate surface.

[0209] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0210] 14B, in a cross-sectional view of the transistor 500 in the channel width direction, the oxide 530b may have a curved surface between the side surface and the top surface of the oxide 530b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0211] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 530b with the insulators 552, 550, and 554, and the conductor 560.

[0212] The oxide 530 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0213] The oxide 530b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies) and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 530b. This can reduce the extraction of oxygen from the oxide 530b even during heat treatment, making the transistor 500 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0214] Here, the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0215] Specifically, when the oxide 530a and the oxide 530b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-M-Zn oxide, the oxide 530a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0216] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 530b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0217] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0218] 14B and other figures, providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530 can cause indium in the oxide 530 to be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. This results in an atomic ratio near the surface of the oxide 530 that is close to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 530, particularly the oxide 530b, can improve the field-effect mobility of the transistor 500.

[0219] The oxide 530a and the oxide 530b have the above structure, which can reduce the defect state density at the interface between the oxide 530a and the oxide 530b. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve high on-state current and high frequency characteristics.

[0220] At least one of the insulators 512, 514, 544, 571, 574, 576, and 581 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 is preferably made of an insulating material that suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, or NO), or copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that suppresses diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., through which the above oxygen is less likely to permeate).

[0221] Note that in this specification, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the barrier property refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0222] The insulators 512, 514, 544, 571, 574, 576, and 581 are preferably insulators that have a function of suppressing diffusion of oxygen and impurities such as water and hydrogen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like can be used. For example, silicon nitride or the like, which has a high hydrogen barrier property, is preferably used for the insulators 512, 544, and 576. Furthermore, for example, aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen, is preferably used for the insulators 514, 571, 574, and 581. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Alternatively, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film or the like disposed outside the insulator 581 toward the transistor 500. Alternatively, oxygen contained in the insulator 524 or the like can be prevented from diffusing toward the substrate through the insulators 512 and 514. Alternatively, oxygen contained in the insulator 580 or the like can be prevented from diffusing upward from the transistor 500 through the insulator 574. In this way, the transistor 500 is preferably surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of preventing the diffusion of impurities such as water and hydrogen and oxygen.

[0223] Here, it is preferable to use an oxide having an amorphous structure as the insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a highly reliable transistor 500 and a semiconductor device can be manufactured that have excellent characteristics.

[0224] Furthermore, the insulators 512, 514, 544, 571, 574, 576, and 581 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0225] The insulators 512, 514, 544, 571, 574, 576, and 581 can be formed by, for example, a sputtering method. Sputtering does not require the use of molecules containing hydrogen in a film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 512, 514, 544, 571, 574, 576, and 581. Note that the film formation method is not limited to sputtering, and a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like may also be used as appropriate.

[0226] It may also be preferable to reduce the resistivity of the insulators 512, 544, and 576. For example, it may be preferable to reduce the resistivity of the insulators 512, 544, and 576 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 512, 544, and 576 may be able to reduce charge-up of the conductors 503, 542, 560, and the like in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0227] The insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 516, 580, and 581.

[0228] For example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarizing film, or the like.

[0229] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Here, the conductor 503 is preferably embedded in an opening formed in the insulator 516. In some cases, part of the conductor 503 is embedded in the insulator 514.

[0230] The conductor 503 includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and sidewall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the top of the conductor 503b is approximately the same as the height of the top of the conductor 503a and the height of the top of the insulator 516.

[0231] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0232] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 503a may be a single layer or a multilayer structure of the above conductive materials. For example, the conductor 503a may be made of titanium nitride.

[0233] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0234] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the Vth of the transistor 500 and reduce the off-state current compared to when a negative potential is not applied to the conductor 503. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to when a negative potential is not applied.

[0235] Note that if the oxide 530 is highly pure and intrinsic, and impurities are removed from the oxide 530 as much as possible, it may be possible to make the transistor 500 normally off (to make the threshold voltage of the transistor 500 higher than 0 V) ​​without applying a potential to the conductor 503 and / or the conductor 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that the same potential is applied to them.

[0236] The electrical resistivity of the conductor 503 is designed taking into consideration the potential to be applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby suppressing the diffusion of the impurities into the oxide 530.

[0237] Note that the conductor 503 is preferably larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in FIG. 14B , the conductor 503 preferably extends to an area outside the channel width direction ends of the oxide 530a and the oxide 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, the conductor 503 and the conductor 560 preferably overlap with each other through an insulator. With this structure, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560 functioning as the first gate electrode and the electric field of the conductor 503 functioning as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is referred to as a surrounded channel (s-channel) structure.

[0238] In this specification and the like, a transistor with an s-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The s-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. The adoption of the s-channel structure can enhance resistance to the short-channel effect, in other words, can provide a transistor that is less susceptible to the short-channel effect.

[0239] By configuring the transistor 500 as a normally-off transistor and having the above-described S-channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 500 can also be considered to have a GAA (gate all around) structure or an LGAA (lateral gate all around) structure. By configuring the transistor 500 as an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulating film can be the entire bulk of the oxide 530. In other words, by configuring the transistor 500 as an S-channel structure, a GAA structure, or an LGAA structure, the transistor 500 can be a so-called bulk-flow type transistor, in which the entire bulk is used as a carrier path. The bulk-flow type transistor structure can increase the current density flowing through the transistor, which is expected to improve the on-state current or field-effect mobility of the transistor.

[0240] 14B, the conductor 503 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 503. Furthermore, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0241] Note that although the conductor 503 in the transistor 500 has a stacked structure of the conductor 503a and the conductor 503b, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0242] The insulator 522 and the insulator 524 function as gate insulators.

[0243] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). The insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0244] The insulator 522 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 to the substrate and diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, the insulator 522 can suppress diffusion of impurities such as hydrogen into the transistor 500 and suppress generation of oxygen vacancies in the oxide 530. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0245] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 522 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0246] The insulator 522 may be a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the insulator functioning as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 522 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0247] The insulator 524 in contact with the oxide 530 can be formed using, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0248] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0249] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0250] The insulators 522 and 524 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 524 may be formed in an island shape overlapping the oxide 530a. In this case, the insulator 544 is in contact with the side surface of the insulator 524 and the top surface of the insulator 522.

[0251] The conductor 542a and the conductor 542b are provided in contact with the top surface of the oxide 530b. The conductor 542a and the conductor 542b function as a source electrode and a drain electrode of the transistor 500, respectively.

[0252] As the conductor 542 (conductor 542a and conductor 542b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.

[0253] Note that hydrogen contained in the oxide 530b and the like may diffuse into the conductor 542a or the conductor 542b. In particular, when a nitride containing tantalum is used for the conductor 542a and the conductor 542b, hydrogen contained in the oxide 530b and the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen may bond with nitrogen contained in the conductor 542a or the conductor 542b. In other words, hydrogen contained in the oxide 530b and the like may be absorbed by the conductor 542a or the conductor 542b.

[0254] Furthermore, it is preferable that no curved surface be formed between the side surface of the conductor 542 and the top surface of the conductor 542. The conductor 542 without such a curved surface can increase the cross-sectional area of ​​the conductor 542 in the cross section in the channel width direction. This can increase the conductivity of the conductor 542 and the on-state current of the transistor 500.

[0255] The insulator 571a is provided in contact with the top surface of the conductor 542a, and the insulator 571b is provided in contact with the top surface of the conductor 542b. The insulator 571 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing oxygen diffusion. For example, the insulator 571 preferably has a function of suppressing oxygen diffusion more than the insulator 580. The insulator 571 may be, for example, a nitride containing silicon, such as silicon nitride. The insulator 571 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 571 may be an insulator such as a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 is preferable because hydrogen can be more effectively captured or fixed. This enables the manufacture of a highly reliable transistor 500 and a semiconductor device with favorable characteristics.

[0256] The insulator 544 is provided to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 544 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 544 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0257] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulators 524 and 580 can be prevented from diffusing into the conductor 542. This can prevent the conductor 542 from being directly oxidized by the oxygen contained in the insulators 524 and 580, which increases the resistivity and reduces the on-state current.

[0258] The insulator 552 functions as part of the gate insulator. The insulator 552 is preferably a barrier insulating film against oxygen. Any of the insulators that can be used for the insulator 574 may be used as the insulator 552. An insulator containing one or both of an oxide of aluminum and hafnium may be used as the insulator 552. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), and the like. In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 contains at least oxygen and aluminum.

[0259] As shown in FIG. 14B, the insulator 552 is provided in contact with the top surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the top surface of the insulator 522. That is, the regions of the oxide 530a, the oxide 530b, and the insulator 524 that overlap with the conductor 560 are covered with the insulator 552 in the cross section in the channel width direction. This allows the insulator 552, which has oxygen barrier properties, to block oxygen from being released from the oxides 530a and 530b during heat treatment or the like. This reduces the formation of oxygen vacancies (Vo) in the oxides 530a and 530b. This reduces the oxygen vacancies (Vo) and V formed in the region 530bc shown in FIG. 16A. O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be improved.

[0260] Conversely, even if the insulator 580, the insulator 550, or the like contains excessive oxygen, the oxygen can be prevented from being excessively supplied to the oxide 530a and the oxide 530b. Therefore, the region 530bc shown in FIG. 16A can prevent the regions 530ba and 530bb from being excessively oxidized, which would result in a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0261] 14A, the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 571, the insulator 544, and the insulator 580. This reduces the oxidation of the side surfaces of the conductor 542 and the formation of an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0262] The insulator 552, together with the insulator 554, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 552 preferably has a small thickness. The thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 552 only needs to have at least a region with the above-described thickness. The thickness of the insulator 552 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 552 only needs to have at least a region with a thickness thinner than the insulator 550.

[0263] To form the insulator 552 into a thin film as described above, it is preferable to form the film by the ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD method in which a plasma excited reactant is used. The PEALD method may be preferable because it can form the film at a lower temperature by using plasma.

[0264] The ALD method utilizes the self-regulating property of atoms and can deposit atoms layer by layer, which has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, and the formation of films at low temperatures, etc. Therefore, the insulator 552 can be formed with good coverage on the side surfaces of openings formed in the insulator 580 or the like and with the thin film thickness as described above.

[0265] Some precursors used in the ALD method contain carbon and other impurities. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0266] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. The insulator 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 550 is an insulator containing at least oxygen and silicon.

[0267] Like the insulator 524, the insulator 550 preferably has a reduced concentration of impurities such as water or hydrogen. The thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15 nm or less, or 20 nm or less. Note that the above-mentioned lower and upper limits can be combined. In this case, the insulator 550 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0268] 14A and 14B, the insulator 550 is shown as a single layer, but the present invention is not limited to this and may have a laminated structure of two or more layers. For example, as shown in Fig. 16B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0269] As shown in FIG. 16B , when the insulator 550 has a two-layer structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator that suppresses oxygen diffusion. Such a structure can suppress the diffusion of oxygen contained in the insulator 550a into the conductor 560. That is, a decrease in the amount of oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the oxygen contained in the insulator 550a can be suppressed. For example, the insulator 550a may be formed using any of the materials that can be used for the insulator 550, and the insulator 550b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b contains at least oxygen and hafnium. The thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned thickness in at least a portion.

[0270] When silicon oxide, silicon oxynitride, or the like is used for the insulator 550a, the insulator 550b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a stacked structure of the insulators 550a and 550b, a thermally stable stacked structure with a high dielectric constant can be achieved. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. Therefore, the dielectric strength of the insulator 550 can be increased.

[0271] The insulator 554 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 554. This can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. The insulator 554 can be any of the insulators that can be used for the insulator 576. For example, silicon nitride formed by a PEALD method can be used as the insulator 554. In this case, the insulator 554 contains at least nitrogen and silicon.

[0272] The insulator 554 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 550 from diffusing into the conductor 560.

[0273] The insulator 554, together with the insulator 552, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 554 preferably has a small thickness. The thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 554 only needs to have at least a region with the above-described thickness. The thickness of the insulator 554 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 554 only needs to have at least a region with a thickness thinner than the insulator 550.

[0274] The conductor 560 functions as a first gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed over the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. As shown in FIGS. 14A and 14B, the height of the top of the conductor 560 roughly coincides with the height of the top of the insulator 550. Note that although the conductor 560 is shown as having a two-layer structure of the conductor 560a and the conductor 560b in FIGS. 14A and 14B, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers, other than the two-layer structure.

[0275] The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, or copper atoms, or that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0276] Furthermore, since the conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 560b caused by oxygen contained in the insulator 550. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0277] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b can have a layered structure. Specifically, for example, the conductor 560b can have a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0278] Furthermore, in the transistor 500, the conductor 560 is formed in a self-aligned manner so as to fill an opening formed in the insulator 580, etc. By forming the conductor 560 in this manner, the conductor 560 can be reliably placed in the region between the conductor 542a and the conductor 542b without alignment.

[0279] 14B , in the channel width direction of the transistor 500, the height of the bottom surface of the conductor 560 in a region where the conductor 560 does not overlap with the oxide 530b is preferably lower than the height of the bottom surface of the oxide 530b when the bottom surface of the insulator 522 is used as the reference. When the conductor 560, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can be easily applied to the entire channel formation region of the oxide 530b. Therefore, the on-state current of the transistor 500 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 560 and the height of the bottom surface of the oxide 530b in the region where the oxides 530a and 530b do not overlap with the conductor 560, relative to the bottom surface of the insulator 522, is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and is preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0280] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are provided. The top surface of the insulator 580 may be planarized.

[0281] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 580 is preferably formed using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0282] The insulator 580 preferably has a reduced concentration of impurities such as water or hydrogen. For example, the insulator 580 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0283] The insulator 574 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water or hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. The insulator 574 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 574 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 574 contains at least oxygen and aluminum. By providing the insulator 574, which is in contact with the insulator 580 and has a function of capturing impurities such as hydrogen, in the region between the insulators 512 and 581, the insulator 574 can capture impurities such as hydrogen contained in the insulator 580 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 574 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 500 and semiconductor device with favorable characteristics.

[0284] The insulator 576 functions as a barrier insulating film that suppresses diffusion of impurities such as water or hydrogen from above into the insulator 580. The insulator 576 is disposed over the insulator 574. The insulator 576 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 576 may be a silicon nitride film formed by a sputtering method. A high-density silicon nitride film can be formed by forming the insulator 576 by a sputtering method. Alternatively, the insulator 576 may be formed by stacking a silicon nitride film formed by a PEALD method or a CVD method on the silicon nitride film formed by a sputtering method.

[0285] One of the first and second terminals of the transistor 500 is electrically connected to a conductor 540a functioning as a plug, and the other of the first and second terminals of the transistor 500 is electrically connected to a conductor 540b. Note that in this specification and the like, the conductors 540a and 540b are collectively referred to as conductors 540.

[0286] For example, the conductor 540a is provided in a region overlapping with the conductor 542a. Specifically, in the region overlapping with the conductor 542a, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 14A and insulators 582 and 586 shown in FIG. 13, and the conductor 540a is provided inside the openings. For example, the conductor 540b is provided in a region overlapping with the conductor 542b. Specifically, in the region overlapping with the conductor 542b, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Fig. 14A and insulators 582 and 586 shown in Fig. 13, and the conductor 540b is provided inside the openings. The insulators 582 and 586 will be described later.

[0287] 14A, an insulator 541a may be provided as an insulator having a barrier property against impurities between the conductor 540a and a side surface of the opening in a region overlapping with the conductor 542a. Similarly, an insulator 541b may be provided as an insulator having a barrier property against impurities between the conductor 540b and a side surface of the opening in a region overlapping with the conductor 542b. Note that in this specification and the like, the insulators 541a and 541b are collectively referred to as the insulator 541.

[0288] The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0289] Furthermore, when the conductor 540 has a layered structure, it is preferable to use a conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen for the insulators 574, 576, 581, 580, 544, and the first conductor disposed near the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 576 from being mixed into the oxide 530 through the conductors 540a and 540b.

[0290] The insulators 541a and 541b may be a barrier insulating film that can be used for the insulator 544 or the like. For example, the insulators 541a and 541b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 541a and 541b are provided in contact with the insulators 574, 576, and 571, and thus can prevent impurities such as water and hydrogen contained in the insulator 580 or the like from being mixed into the oxide 530 through the conductors 540a and 540b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0291] When the insulators 541a and 541b are formed into a layered structure as shown in FIG. 14A, it is preferable that the first insulator in contact with the inner wall of the opening of the insulator 580 or the like and the second insulator inside it are formed by combining a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0292] For example, aluminum oxide formed by the ALD method can be used as the first insulator, and silicon nitride formed by the PEALD method can be used as the second insulator. With this structure, oxidation of the conductor 540 can be suppressed, and furthermore, hydrogen contamination of the conductor 540 can be reduced.

[0293] Although the transistor 500 has a stacked structure of the first insulator of the insulator 541 and the second conductor of the insulator 541, the present invention is not limited to this. For example, the insulator 541 may have a single layer or a stacked structure of three or more layers. Furthermore, the transistor 500 has a stacked structure of the first conductor of the conductor 540 and the second conductor of the conductor 540, but the present invention is not limited to this. For example, the conductor 540 may have a single layer or a stacked structure of three or more layers.

[0294] 13, conductors 610 and 612, which function as wiring and are in contact with the upper portions of conductors 540a and 540b, may be disposed. Conductor 610 and conductor 612 are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors may also have a layered structure. Specifically, for example, the conductors may be a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductors may be formed so as to be embedded in openings provided in an insulator.

[0295] Note that the structure of the transistor included in the semiconductor device of one embodiment of the present invention is not limited to the transistor 500 illustrated in Figures 13, 14A, 14B, and 15. The structure of the transistor included in the semiconductor device of one embodiment of the present invention may be changed depending on the situation.

[0296] For example, the transistor 500 illustrated in FIGS. 13, 14A, 14B, and 15 may have the structure illustrated in FIG. 17. The transistor in FIG. 17 differs from the transistor 500 illustrated in FIGS. 13, 14A, 14B, and 15 in that it includes an oxide 543a and an oxide 543b. Note that in this specification and the like, the oxide 543a and the oxide 543b are collectively referred to as the oxide 543. The cross-sectional structure of the transistor in FIG. 17 in the channel width direction can be similar to that of the cross-section of the transistor 500 illustrated in FIG. 14B.

[0297] The oxide 543a is provided between the oxide 530b and the conductor 542a, and the oxide 543b is provided between the oxide 530b and the conductor 542b. Here, the oxide 543a is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542a. The oxide 543b is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542b.

[0298] The oxide 543 preferably has a function of suppressing oxygen permeation. Placing the oxide 543, which has a function of suppressing oxygen permeation, between the conductor 542 functioning as a source or drain electrode and the oxide 530b is preferable because the electrical resistance between the conductor 542 and the oxide 530b can be reduced. Such a structure can improve the electrical characteristics, field-effect mobility, and reliability of the transistor 500 in some cases.

[0299] Alternatively, a metal oxide containing element M may be used as oxide 543. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 543 has a higher concentration of element M than oxide 530b. Alternatively, oxide 543 may be gallium oxide. Alternatively, oxide 543 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the film thickness of oxide 543 is preferably 0.5 nm or more, or 1 nm or more, and is preferably 2 nm or less, 3 nm or less, or 5 nm or less. The above-described lower and upper limits may be combined. Preferably, oxide 543 is crystalline. When oxide 543 is crystalline, oxygen release from oxide 530 can be effectively suppressed. For example, if the oxide 543 has a crystalline structure such as a hexagonal crystal structure, the release of oxygen from the oxide 530 may be suppressed.

[0300] An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.

[0301] The insulator 582 is preferably made of a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0302] The insulator 586 can be made of a material similar to that of the insulator 320. The use of a material with a relatively low dielectric constant for these insulators can reduce parasitic capacitance between wirings. For example, the insulator 586 can be made of a silicon oxide film, a silicon oxynitride film, or the like.

[0303] Next, a description will be given of the capacitor 600 and its peripheral wiring or plugs included in the semiconductor device shown in Figures 13 and 15. Note that the capacitor 600, wiring, and / or plugs are provided above the transistor 500 shown in Figures 13 and 15.

[0304] The capacitor 600 includes, for example, a conductor 610 , a conductor 620 , and an insulator 630 .

[0305] A conductor 610 is provided over one of the conductors 540a and 540b, the conductor 546, and the insulator 586. The conductor 610 functions as one of a pair of electrodes of a capacitor 600.

[0306] A conductor 612 is provided over the other of the conductor 540a and the conductor 540b and over the insulator 586. The conductor 612 functions as a plug, a wiring, a terminal, or the like that electrically connects the transistor 500 to a circuit element, a wiring, or the like arranged above it.

[0307] The conductor 612 and the conductor 610 may be formed at the same time.

[0308] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0309] 13, the conductor 612 and the conductor 610 have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0310] An insulator 630 is provided on the insulator 586 and the conductor 610. The insulator 630 functions as a dielectric sandwiched between the pair of electrodes of the capacitor 600.

[0311] The insulator 630 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or zirconium oxide. The insulator 630 can be formed as a stacked layer or a single layer using any of the above materials.

[0312] Furthermore, for example, a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material may be used for the insulator 630. With this configuration, the capacitor 600 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the insulator with high dielectric strength improves the dielectric strength, thereby suppressing electrostatic breakdown of the capacitor 600.

[0313] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0314] Alternatively, the insulator 630 may be a single layer or a multilayer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). Alternatively, the insulator 630 may be a compound containing hafnium and zirconium. As semiconductor devices become smaller and more highly integrated, thinning of the gate insulator and dielectrics used in capacitors can cause problems such as leakage current in transistors and capacitors. Using a high-k material for the insulators that function as the gate insulator and dielectrics used in capacitors can reduce the gate potential during transistor operation and ensure capacitance while maintaining the physical film thickness.

[0315] The conductor 620 is provided to overlap with the conductor 610 with the insulator 630 placed therebetween. The conductor 610 functions as one of a pair of electrodes of the capacitor 600.

[0316] The conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other structures such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used. For example, the conductor 620 can be made of a material that can be used for the conductor 610. The conductor 620 may have a laminated structure of two or more layers, rather than a single-layer structure.

[0317] An insulator 640 is provided over the conductor 620 and the insulator 630. For the insulator 640, for example, a film having a barrier property that prevents diffusion of hydrogen, impurities, or the like into a region where the transistor 500 is provided is preferably used. Therefore, a material similar to that of the insulator 324 can be used.

[0318] An insulator 650 is provided over the insulator 640. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape below it. Therefore, the insulator 650 can be made of, for example, a material that can be used for the insulator 324.

[0319] 13 and 15 is a planar type, the shape of the capacitor is not limited to this. The capacitor 600 may be, for example, a cylindrical type instead of a planar type.

[0320] 13, an insulator 411, an insulator 412, an insulator 413, and an insulator 414 are provided in this order above an insulator 650. A conductor 416 functioning as a plug or a wiring is provided in the insulators 411, 412, and 413. For example, the conductor 416 can be provided in a region overlapping with a conductor 660 described later.

[0321] Furthermore, openings are provided in the insulators 630, 640, and 650 in regions overlapping with the conductor 612, and the conductor 660 is provided to fill the openings. The conductor 660 functions as a plug or wiring electrically connected to the conductor 416 included in the above-described wiring layer.

[0322] The insulators 411 and 414 are preferably made of an insulator that has barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulators 411 and 414 can be made of a material that can be used for the insulator 324, for example.

[0323] For the insulators 412 and 413, similar to the insulator 326, it is preferable to use an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings.

[0324] Furthermore, the conductor 612 and the conductor 416 can be formed using, for example, the same material as the conductor 328 and the conductor 330 .

[0325] <Example of a configuration of a transistor and a ferroelectric capacitor> Next, a configuration will be described in which a dielectric that may have ferroelectricity is provided in and around a transistor 500 that includes a metal oxide in a channel formation region.

[0326] FIG. 18A shows an example of the configuration of a transistor in which a dielectric that may have ferroelectricity is provided in the configuration of the transistor 500 shown in FIG. 13, FIG. 14A, etc.

[0327] 18A has a configuration in which the insulator 522 functioning as the second gate insulator is replaced with an insulator 520. As one example, the insulator 520 can be a dielectric material that may have ferroelectricity.

[0328] 18A can have a ferroelectric capacitor between the conductor 503, which functions as the second gate electrode, and the oxide 530. In other words, the transistor of FIG. 18A can be an FeFET (Ferroelectric FET) in which a dielectric that may have ferroelectricity is provided in a part of the second gate insulator.

[0329] Although insulator 520 is illustrated as a single layer in FIG. 18A, insulator 520 may be an insulating film of two or more layers including a dielectric material that may have ferroelectricity. A specific example of such a transistor is shown in FIG. 18B. In FIG. 18B, insulator 520 includes insulator 520a and insulator 520b, for example. Insulator 520a is provided on the top surface of insulator 516 and conductor 503, and insulator 520b is provided on the top surface of insulator 520a.

[0330] For example, a dielectric material that may have ferroelectricity may be used as the insulator 520a. For example, silicon oxide may be used as the insulator 520b. Alternatively, for example, silicon oxide may be used as the insulator 520a and a dielectric material that may have ferroelectricity may be used as the insulator 520b.

[0331] As shown in Figure 18B, by using two layers of insulator 520, with one layer being a dielectric that may have ferroelectricity and the other layer being silicon oxide, it is possible to suppress current leakage between conductor 503, which functions as a gate electrode, and oxide 530.

[0332] 18C shows an example of the configuration of a transistor in which the insulator 520 has three layers. In Fig. 18C, the insulator 520 includes, for example, an insulator 520a, an insulator 520b, and an insulator 520c. The insulator 520c is provided on the top surface of the insulator 516 and the conductor 503, the insulator 520a is provided on the top surface of the insulator 520c, and the insulator 520b is provided on the top surface of the insulator 520a.

[0333] The insulator 520a may be made of, for example, a dielectric material that may have ferroelectricity, and the insulators 520b and 520c may be made of, for example, silicon oxide.

[0334] The respective configurations of the transistors and ferroelectric capacitors shown in FIGS. 18A and 18B can be applied to, for example, the transistors FM1 to FM3 described in the first embodiment.

[0335] FIG. 19 shows an example of a transistor configuration in which a dielectric that may have ferroelectric properties is provided in the configuration of the transistor 500 shown in FIGS. 13 and 14A, etc., which is different from the transistors in FIGS. 18A to 18C.

[0336] The transistor shown in Figure 19 shows an example of a transistor configuration in which a dielectric that may have ferroelectric properties is provided above insulators 552, 550, and 554 that function as first gate insulators, conductor 560 that functions as a first gate electrode, and a partial region of insulator 580.

[0337] Specifically, insulator 561 is provided so as to be in contact with insulator 552, insulator 550, insulator 554, conductor 560, and partial regions of insulator 580. As an example, insulator 561 can be made of a dielectric material that can have ferroelectricity and can be applied to insulator 520 in FIG. 18A.

[0338] A conductor 562 is provided to be in contact with an upper portion of the insulator 561. The conductor 562 can be provided using, for example, the same material as the conductors 328 and 330.

[0339] Therefore, with the configuration of the transistor in FIG. 19, a ferroelectric capacitor can be provided between the conductor 503 functioning as the first gate electrode and the conductor 562.

[0340] Note that the insulator 561 may have a stacked structure of two or more layers, similar to the insulator 520 shown in FIGS. 18B and 18C.

[0341] Furthermore, the respective configurations of the transistor and ferroelectric capacitor shown in FIG. 19 can be applied to, for example, the transistor M1 and capacitor C2 explained in the first embodiment.

[0342] FIG. 20A shows an example of a transistor configuration in which a dielectric that may have ferroelectric properties is provided in the configuration of transistor 500 of FIGS. 13, 14A, etc., which is different from the transistors of FIGS. 18A to 18C and 19.

[0343] 20A , an insulator 602 is provided in an opening that overlaps with the conductor 542b and is provided in the insulators 544, 571b, 580, 574, 576, and 581. Specifically, in the opening, an insulator 541b is provided on a side surface of the opening, a conductor 540b is provided over the insulator 541b and over the conductor 542b that is at the bottom of the opening, an insulator 602 is provided in a portion of the insulator 581 and over the conductor 540b, and a conductor 613 is provided over the insulator 602 to fill the remaining opening.

[0344] As another specific configuration example, within the opening, an insulator 541b is provided on the side of the opening, a conductor 540b is provided on the insulator 541b, an insulator 602 is provided in a portion of the insulator 581, on the conductor 540b, and on the conductor 542b at the bottom of the opening, and a conductor 613 is provided on the insulator 602 so as to fill the remaining opening.

[0345] For example, the insulator 602 may be a dielectric material that may have ferroelectric properties, which may be applicable to the insulator 520 in FIG. 18A.

[0346] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferable as a dielectric that can have ferroelectricity because it can maintain ferroelectricity even when processed into a thin film of a few nanometers. Here, the film thickness of the insulator 602 can be 100 nm or less, preferably 50 nm or less, and more preferably 10 nm or less. By thinning the insulator 602, it can be combined with a miniaturized transistor to form a semiconductor device.

[0347] The insulator 602 is a material containing hafnium oxide and zirconium oxide (HfZrO x When using the above-mentioned film, it is preferable to form the film by using a thermal ALD method.

[0348] Furthermore, when the insulator 602 is formed by the thermal ALD method, it is preferable to use a material that does not contain hydrocarbons (also referred to as Hydro Carbon, HC) as a precursor. If the insulator 602 contains either or both of hydrogen and carbon, crystallization of the insulator 602 may be hindered. For this reason, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the insulator 602. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Note that the insulator 602 may be formed using a material containing hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as the precursor.

[0349] Furthermore, when forming the insulator 602 using a thermal ALD method, the oxidizing agent can be H2O or O3. Note that using O3 as the oxidizing agent for the thermal ALD method is more preferable than using H2O because it can reduce the hydrogen concentration in the film. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0350] The conductor 613 can be formed using, for example, a material similar to that of the conductors 328 and 330 .

[0351] The conductor 613 can be formed by ALD, CVD, or the like. For example, titanium nitride can be formed by thermal ALD. Here, the conductor 613 is preferably formed by a method in which the substrate is heated, as in the thermal ALD method. For example, the substrate temperature may be set to room temperature or higher, preferably 300°C or higher, more preferably 325°C or higher, and even more preferably 350°C or higher. Alternatively, the substrate temperature may be set to 500°C or lower, preferably 450°C or lower. For example, the substrate temperature may be set to about 400°C.

[0352] By forming the conductor 613 within the temperature range described above, it is possible to impart ferroelectricity to the insulator 602 without performing a high-temperature bake treatment (for example, a bake treatment at a heat treatment temperature of 400°C or higher or 500°C or higher) after forming the conductor 613. Furthermore, by forming the conductor 613 using the ALD method, which causes relatively little damage to the base, as described above, it is possible to prevent the crystal structure of the insulator 602 from being excessively destroyed, thereby enhancing the ferroelectricity of the insulator 602.

[0353] For example, when the conductor 613 is formed by sputtering, there is a possibility that damage may occur in the underlayer, in this case the insulator 602. For example, when the insulator 602 is made of a material containing hafnium oxide and zirconium oxide (HfZrO x When the conductor 613 is formed by sputtering, the HfZrO x Damage occurs to HfZrO x The crystal structure (typically a cubic crystal structure) of HfZrO may be destroyed by heat treatment. x There are also methods to repair the damage to the crystal structure of HfZrO formed by sputtering. x Damage in, e.g., HfZrO x Dangling bonds in (e.g., O * ) and HfZrO x The hydrogen contained in the x In some cases, damage in the crystal structure of the material cannot be repaired.

[0354] Therefore, HfZrO used as the insulator 602 x It is preferable to use a material that does not contain hydrogen or has an extremely low hydrogen content for the insulator 602. By using a material that does not contain hydrogen or has an extremely low hydrogen content for the insulator 602, the crystallinity of the insulator 602 can be improved, resulting in a structure with high ferroelectricity.

[0355] As described above, in one embodiment of the present invention, for example, a ferroelectric material is formed as the insulator 602 by a thermal ALD method using a hydrocarbon-free precursor (typically a chlorine-based precursor) and an oxidizer (typically O). Thereafter, the conductor 613 is formed by a thermal ALD method (typically at 400° C. or higher). This allows the crystallinity or ferroelectricity of the insulator 602 to be improved without annealing after the formation of the conductor 613, in other words, by utilizing the temperature during the formation of the conductor 613. Note that improving the crystallinity or ferroelectricity of the insulator 602 by utilizing the temperature during the formation of the conductor 613 without annealing after the formation of the conductor 613 is sometimes referred to as self-annealing.

[0356] The configuration of the transistor in FIG. 20A allows a ferroelectric capacitor to be provided between the conductor 540b and the conductor 613 in the opening included in the region overlapping with the conductor 542b.

[0357] The insulator 602 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 18B and 18C.

[0358] FIG. 20B shows an example of a transistor configuration in which a dielectric that may have ferroelectric properties is provided in the configuration of transistor 500 of FIGS. 13, 14A, etc., which is different from the transistors of FIGS. 18A to 18C, 19, and 20A.

[0359] 20B has a structure in which the insulators 552, 550, and 554 functioning as the first gate insulator are replaced with an insulator 553. For example, the insulator 553 can be a dielectric that can have ferroelectricity and can be used for the insulator 520 in FIG. 18A.

[0360] Therefore, the transistor of Figure 20B can have a ferroelectric capacitor between the conductor 560, which functions as the first gate electrode, and the oxide 530. In other words, the transistor of Figure 20B can be an FeFET in which a dielectric that may have ferroelectric properties is provided in a portion of the first gate insulator.

[0361] Note that the insulator 553 may have a stacked structure of two or more layers, similar to the insulator 520 shown in FIGS. 18B and 18C.

[0362] In addition, in FIG. 20B, the insulator 552, the insulator 550, and the insulator 554 are replaced with the insulator 553. However, as another example of the configuration, at least one of the insulators 552, 550, and 554 may be replaced with the insulator 553, and the remaining insulator and the insulator 553 may form a layered structure.

[0363] Furthermore, the respective configurations of the transistor and ferroelectric capacitor shown in FIGS. 20A and 20B can be applied to, for example, the transistor M1 and capacitor C2 described in the first embodiment.

[0364] FIG. 21A shows an example of the configuration of a transistor 500 and a capacitor, in which a capacitor including a dielectric material that may have ferroelectricity is provided around the transistor 500.

[0365] 21A , for example, a plurality of openings are formed in the insulators 544, 571b, 580, 574, 576, and 581 in a region overlapping with the conductor 542b. A conductor 540c functioning as a plug is provided inside one of the openings, and an insulator 541c serving as an insulator with a barrier property against impurities is provided between a side surface of the opening and the conductor 540c. A conductor 540d functioning as a plug is provided inside another of the openings, and an insulator 541d serving as an insulator with a barrier property against impurities is provided between a side surface of the opening and the conductor 540d. The conductor 540c and the conductor 540d can be made of, for example, a material that can be used for the conductor 540a and the conductor 540b, and the insulator 541c and the insulator 541d can be made of, for example, a material that can be used for the insulator 541a and the insulator 541b.

[0366] An insulator 601 is provided on the upper part of the conductor 540c and the conductor 540d so as to be in contact with them. As an example, the insulator 601 can be made of a dielectric material that can have ferroelectricity and can be used for the insulator 520 in FIG. 18A.

[0367] A conductor 611 is provided to be in contact with an upper portion of the insulator 601. The conductor 611 can be provided using, for example, the same material as the conductors 328 and 330.

[0368] Therefore, with the configuration shown in FIG. 21A, a ferroelectric capacitor can be provided between the conductor 540c and the conductor 540d that function as plugs and the conductor 611.

[0369] The insulator 601 may have a laminated structure of two or more layers, similar to the insulator 520 shown in FIGS. 18B and 18C.

[0370] 14A, the number of plugs in contact with insulator 601 is two (conductor 540c and conductor 540d), but the number of plugs may be one or three or more. In other words, while FIG. 15 illustrates an example in which two openings having conductors as plugs are provided in the region overlapping with insulator 601, the number of openings provided in the region overlapping with insulator 601 may be one or three or more.

[0371] FIG. 21B shows an example of a configuration of a transistor 500 and a capacitor, which is different from that of FIG. 21A, in which a capacitor including a dielectric material that may have ferroelectricity is provided around the transistor 500.

[0372] 21B, an insulator 631 is provided on the upper surface of a portion of the conductor 610 located on the conductor 540b functioning as a plug and the insulator 581. As an example, the insulator 631 can be a dielectric material that can have ferroelectricity and can be used for the insulator 520 in FIG.

[0373] In addition, a conductor 620 is provided on the upper surface of insulator 631, and an insulator 640 and an insulator 650 are provided in order on the upper surfaces of insulator 581, conductor 612, conductor 620, and a partial region of insulator 631.

[0374] Therefore, with the configuration shown in FIG. 21B, a ferroelectric capacitor can be provided between the conductor 610 and the conductor 620.

[0375] Note that the insulator 631 may have a stacked structure of two or more layers, similar to the insulator 520 shown in FIGS. 18B and 18C.

[0376] Furthermore, the respective configurations of the transistor and ferroelectric capacitor shown in FIGS. 21A and 21B can be applied to, for example, the transistor M1 and capacitor C2 described in the first embodiment.

[0377] By applying the structure described in this embodiment to a semiconductor device including a transistor having an oxide semiconductor, fluctuations in electrical characteristics of the transistor can be suppressed and reliability can be improved. Alternatively, miniaturization or high integration of a semiconductor device including a transistor having an oxide semiconductor can be achieved.

[0378] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0379] (Embodiment 3) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0380] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. Furthermore, it is preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0381] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 22A, which is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0382] As shown in FIG. 22A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous (excluding single crystal and polycrystal). "Crystal" includes single crystal and polycrystal.

[0383] The structure within the bold frame in Figure 22A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0384] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 22B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." In Figure 22B, the horizontal axis represents 2θ [deg.], and the vertical axis represents intensity [au]. The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 22B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 22B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 22B is 500 nm.

[0385] As shown in Figure 22B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected at or near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 22B, the peak at or near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0386] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 22C. Figure 22C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 22C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0387] As shown in FIG. 22C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0388] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from those shown in FIG. 22A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), and amorphous oxide semiconductors.

[0389] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0390] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. Considering an atomic arrangement as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0391] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0392] In an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0393] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type or composition of the metal elements constituting the CAAC-OS.

[0394] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0395] When the crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal or heptagonal lattice arrangement. In the CAAC-OS, no clear grain boundaries can be identified even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0396] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current or field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in a transistor semiconductor layer. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0397] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the formation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0398] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0399] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0400] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0401] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that, hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0402] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0403] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0404] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0405] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0406] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0407] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0408] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0409] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0410] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0411] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0412] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0413] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0414] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0415] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0416] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0417] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0418] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0419] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0420] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0421] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0422] (Fourth embodiment) In this embodiment mode, an example of a semiconductor wafer on which the semiconductor device or the like described in the above embodiment mode is formed and an example of an electronic component in which the semiconductor device is incorporated will be described.

[0423] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device is formed will be described with reference to FIG. 23A.

[0424] 23A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0425] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process can reduce warping of the wafer 4801, for example, and enable miniaturization of the component.

[0426] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0427] By performing a dicing process, chips 4800a as shown in FIG. 23B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0428] 23A 。 Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 23A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the device for manufacturing the element.

[0429] <Electronic components> 23C is a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 23C includes a chip 4800a in a mold 4711. The chip 4800a can be, for example, a memory device according to one embodiment of the present invention.

[0430] 23C omits some parts to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0431] 23D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0432] The semiconductor device 4710 can be, for example, a chip 4800a, the semiconductor device described in the above embodiment, or a high bandwidth memory (HBM). The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0433] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0434] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0435] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0436] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0437] Furthermore, in SiP or MCM using a silicon interposer, a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.

[0438] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0439] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. Fig. 23D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0440] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0441] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0442] (Embodiment 5) In this embodiment, application examples of a semiconductor device according to one embodiment of the present invention will be described.

[0443] The semiconductor device according to one embodiment of the present invention can be applied to, for example, memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, and the like). It can also be used in image sensors, IoT (Internet of Things) devices, healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0444] 24A to 24J and 25A to 25E illustrate examples of electronic devices including an electronic component 4700 or an electronic component 4730 including the semiconductor device according to one embodiment of the present invention.

[0445] [mobile phone] 24A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0446] By applying the semiconductor device according to one embodiment of the present invention, the information terminal 5500 can hold a temporary file (for example, a cache when using a web browser) generated when an application is executed.

[0447] [Wearable devices] 24B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0448] Like the above-described information terminal 5500, the wearable terminal can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0449] [Information terminal] 24C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0450] Like the above-described information terminal 5500, the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0451] 24A to 24C are taken as examples of electronic devices, and are illustrated in Figures 24A to 24C, respectively. However, information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0452] [electric appliances] 24D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. Electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, and a freezer compartment door 5803. For example, electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0453] The semiconductor device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information about food items stored in the electric refrigerator-freezer 5800 or information about expiration dates of the food items to and from an information terminal or the like via the Internet, for example. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the semiconductor device.

[0454] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0455] [Game consoles] 24E illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0456] FIG. 24F further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 24F, the controller 7522 can include a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a sliding knob, or the like. The shape of the controller 7522 is not limited to the shape shown in FIG. 24F, and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0457] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0458] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the semiconductor device described in the above embodiments to the portable game machine 5200 or the stationary game machine 7500. Furthermore, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0459] Furthermore, by applying the semiconductor device described in the above embodiments to the portable game console 5200 or the stationary game console 7500, temporary files and the like necessary for calculations occurring during game execution can be stored.

[0460] The electronic device of one embodiment of the present invention is not limited to a portable game machine or a stationary game machine, but may be, for example, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park) or a pitching machine for batting practice installed in a sports facility.

[0461] [Moving object] The semiconductor device described in the above embodiment mode can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0462] FIG. 24G illustrates an automobile 5700 as an example of a moving object.

[0463] An instrument panel that provides various information by displaying a speedometer or tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0464] In particular, the display device can compensate for, for example, a field of view blocked by a pillar or a blind spot of the driver's seat, thereby improving safety, by displaying an image from an imaging device (not shown) provided on the automobile 5700. In other words, by displaying an image from an imaging device provided outside the automobile 5700, blind spots can be compensated for and safety can be improved.

[0465] The semiconductor device described in the above embodiment can temporarily store data. Therefore, the semiconductor device can be used to store necessary temporary data in an automatic driving system for the automobile 5700, a system that provides road guidance, hazard prediction, or the like. The display device may be configured to display temporary data such as road guidance or hazard prediction. Furthermore, the display device may be configured to store video data from a driving recorder installed in the automobile 5700.

[0466] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, the moving body may be a train, a monorail, a ship, or an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, or rocket).

[0467] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0468] 24H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0469] A low-power digital camera 6240 can be realized by applying the semiconductor device described in the above embodiment modes to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0470] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0471] 24I illustrates a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. An image on the display unit 6303 may be switched depending on the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0472] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the semiconductor device described above, the video camera 6300 can store temporary files generated during encoding.

[0473] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0474] 24J is a cross-sectional schematic diagram showing an example of an ICD. ICD main body 5400 has at least battery 5401, electronic components 4700, a regulator, a control circuit, antenna 5404, wire 5402 to the right atrium, and wire 5403 to the right ventricle.

[0475] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0476] The ICD main unit 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing and rapid ventricular tachycardia or ventricular fibrillation persists, treatment with an electric shock is performed.

[0477] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store, in the electronic component 4700, data on the heart rate acquired by the sensor, the number of times pacing therapy has been performed, or the duration of the therapy, for example.

[0478] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 can also function as an auxiliary power source.

[0479] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, or body temperature can be confirmed on an external monitor device.

[0480] [PC expansion device] The semiconductor device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) or an expansion device for an information terminal.

[0481] Figure 25A shows an example of such an expansion device: a portable expansion device 6100 that is external to a PC and equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC via USB (Universal Serial Bus), for example. Note that while Figure 25A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan.

[0482] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with a circuit for driving the semiconductor device described in the above embodiment, for example. For example, an electronic component 4700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0483] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card which can be attached to an electronic device such as an information terminal or a digital camera.

[0484] FIG. 25B is a schematic diagram of the external appearance of an SD card, and FIG. 25C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. A semiconductor device and a circuit for driving the semiconductor device are provided on the substrate 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0485] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and allows reading and writing of data from and to the electronic component 4700.

[0486] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0487] FIG. 25D is a schematic diagram of the external appearance of an SSD, and FIG. 25E is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. A semiconductor device and a circuit for driving the semiconductor device are provided on the substrate 5153. For example, the substrate 5153 is equipped with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the substrate 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, or the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0488] [Calculator] 26A is an example of a large-scale computer. The computer 5600 has a rack 5610 in which a plurality of rack-mounted computers 5620 are stored.

[0489] Computer 5620 can have the configuration shown in the perspective view in Fig. 26B, for example. In Fig. 26B, computer 5620 has motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

[0490] PC card 5621 shown in FIG. 26C is an example of a processing board equipped with a CPU, a GPU, a semiconductor device, or the like. PC card 5621 includes board 5622. Board 5622 includes connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 26C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0491] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0492] Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to or inputting signals to PC card 5621. Connection terminals 5623, 5624, and 5625 can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0493] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0494] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0495] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. The semiconductor device 5628 can be, for example, a memory device. The electronic component 4700 can be used as the semiconductor device 5628.

[0496] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0497] By using the semiconductor device of one embodiment of the present invention in the various electronic devices, the reliability of the electronic devices can be improved.

[0498] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Example]

[0499] In this example, a transistor having a channel formation region including an oxide semiconductor (referred to as an OS transistor) was fabricated and evaluated assuming high-voltage operation. Note that the OS transistor fabricated in this example corresponds to the transistor 500 shown in FIGS. 14A and 14B , and therefore the configuration and the like of the OS transistor fabricated in this example can be referred to in the above embodiment.

[0500] In this example, OS transistors (Samples 800A to 800D) with different design values ​​of channel length (L) and channel width (W) were prepared. Specifically, Sample 800A is an OS transistor with L / W = 30 nm / 30 nm, Sample 800B is an OS transistor with L / W = 40 nm / 40 nm, Sample 800C is an OS transistor with L / W = 50 nm / 50 nm, and Sample 800D is an OS transistor with L / W = 60 nm / 60 nm. Note that in the following, the values ​​of L and W represent design values.

[0501] Samples 800A to 800D will be described below.

[0502] The oxide 530a was formed from an In-Ga-Zn oxide film deposited by sputtering using a target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide 530b was formed from an In-Ga-Zn oxide film deposited by sputtering using a target with an atomic ratio of In:Ga:Zn=1:1:2. The films that became the oxides 530a and 530b were formed by successive film deposition.

[0503] The conductor 542a and the conductor 542b were formed using a tantalum nitride film. The insulator 552 was formed using a silicon oxide film. The insulator 550 was formed using a hafnium oxide film. The insulator 554 was formed using a silicon nitride film. The film thicknesses of the insulators 552, 550, and 554 were adjusted so that the equivalent oxide thickness (EOT) of the gate insulator was 4.4 nm.

[0504] The conductor 560a was formed using a titanium nitride film. Also, the conductor 560b was formed using a tungsten film. Note that the film that becomes the conductor 560a and the film that becomes the conductor 560b were formed by continuous film formation.

[0505] The above is the description of Samples 800A to 800D. Note that the gate length (Lg) of Sample 800A was 22 nm as a result of length measurement.

[0506] Also, as a comparative example, a transistor having silicon in the channel formation region (referred to as a Si transistor) was prepared. In this embodiment, n-channel and p-channel Si transistors were fabricated. Hereinafter, the n-channel Si transistor is referred to as Sample 800E, and the p-channel Si transistor is referred to as Sample 800F. Note that Samples 800E and 800F have an EOT of 2.6 nm and an L / W of 60 nm / 120 nm.

[0507] <Id-Vg characteristics> First, for Samples 800A to 800F, the drain current (Id)-gate voltage (Vg) characteristics were measured using a semiconductor parameter analyzer manufactured by Keysight Technologies. The measurement of the Id-Vg characteristics was performed with the drain voltage (Vd) set to 0.1 V or 1.2 V, the back-gate voltage (Vbg) set to 0 V, and the gate voltage swept from -4.0 V to 4.0 V in 0.1 V steps.

[0508] Figures 27A to 27F show the measurement results of the Id-Vg characteristics of each sample. Figure 27A is a graph of the Id-Vg characteristics of Sample 800A, Figure 27B is a graph of the Id-Vg characteristics of Sample 800B, Figure 27C is a graph of the Id-Vg characteristics of Sample 800C, Figure 27D is a graph of the Id-Vg characteristics of Sample 800D, Figure 27E is a graph of the Id-Vg characteristics of Sample 800E, and Figure 27F is a graph of the Id-Vg characteristics of Sample 800F. In Figures 27A to 27F, the horizontal axis represents the gate voltage (Vg) [V], and the vertical axis represents the drain current (Id) [A]. Also, the drain current at Vd = 0.1 V is shown by a solid line, and the drain current at Vd = 1.2 V is shown by a dashed line.

[0509] As shown in FIGS. 27A to 27D, the OS transistors (Samples 800A to 800D) exhibited favorable electrical characteristics.

[0510] <Drain withstand voltage test> Next, a drain breakdown voltage test was carried out on each of the samples 800A to 800F.

[0511] In the drain breakdown voltage test, the gate voltage (Vg) was set to 0 V or +3.3 V. For Samples 800A to 800E, the source voltage (Vs) and back gate voltage (Vbg) were set to 0 V, and for Sample 800F, the source voltage (Vs) and back gate voltage (Vbg) were set to +1.2 V. The drain current (Id) was measured while increasing the drain voltage (Vd) from 0 V. The Vd at which the drain current (Id) suddenly decreased, i.e., the transistor was destroyed, was defined as the drain breakdown voltage (Vds breakdown voltage). The maximum Vd voltage was +10 V. The measurements were performed at room temperature.

[0512] Figures 28A to 29F show the results of a drain breakdown voltage test for each sample. Figures 28A to 28F are graphs of the Id-Vd characteristics of each sample when the gate voltage (Vg) was set to 0 V. Figures 29A to 29F are graphs of the Id-Vd characteristics of each sample when the gate voltage (Vg) was set to +3.3 V. In Figures 28A to 29F, the horizontal axis represents the drain voltage (Vd) [V], and the vertical axis represents the drain current (Id) [A].

[0513] Fig. 28A is a graph of the Id-Vd characteristics of sample 800A, Fig. 28B is a graph of the Id-Vd characteristics of sample 800B, Fig. 28C is a graph of the Id-Vd characteristics of sample 800C, Fig. 28D is a graph of the Id-Vd characteristics of sample 800D, Fig. 28E is a graph of the Id-Vd characteristics of sample 800E, and Fig. 28F is a graph of the Id-Vd characteristics of sample 800F. From Fig. 28A to Fig. 28F, it was found that the Vds breakdown voltage of sample 800A was 7.75V, the Vds breakdown voltage of sample 800B was 8.0V, the Vds breakdown voltage of sample 800C was 9.0V, and the Vds breakdown voltage of sample 800D was 9.0V. It was also found that the Vds breakdown voltage of sample 800E was 3.75V, and the Vds breakdown voltage of sample 800F was 5.0V.

[0514] Fig. 29A is a graph of the Id-Vd characteristics of sample 800A, Fig. 29B is a graph of the Id-Vd characteristics of sample 800B, Fig. 29C is a graph of the Id-Vd characteristics of sample 800C, Fig. 29D is a graph of the Id-Vd characteristics of sample 800D, Fig. 29E is a graph of the Id-Vd characteristics of sample 800E, and Fig. 29F is a graph of the Id-Vd characteristics of sample 800F. From Fig. 29A to Fig. 29F, it was found that the Vds breakdown voltage of sample 800A was 6.5V, the Vds breakdown voltage of sample 800B was 6.25V, the Vds breakdown voltage of sample 800C was 6.25V, and the Vds breakdown voltage of sample 800D was 7.0V. It was also found that the Vds breakdown voltage of sample 800E was 3.25V, and the Vds breakdown voltage of sample 800F was 4.75V.

[0515] 28A to 29F show that the OS transistor has a higher drain breakdown voltage than the Si transistor. Also, Fig. 28A shows that the sample 800A can operate even at a drain voltage (Vd) of 4.5 V. Also, Fig. 29A shows that the sample 800A is resistant to hot carrier injection (HCI) at room temperature.

[0516] <Temperature dependence of off-state current> Next, we evaluated the temperature dependence of the on-state current of an OS transistor by fabricating a TEG for measuring the off-state current, which has a sample of 800A.

[0517] 30A shows a circuit diagram outlining the off-current measuring TEG. The off-current measuring TEG has terminals A to E, a transistor M1, a transistor M2, and a read circuit RC.

[0518] One of the source and the drain of the transistor M1 is electrically connected to terminal A. The other of the source and the drain of the transistor M1 is electrically connected to node ND. The gate of the transistor M1 is electrically connected to terminal B. One of the source and the drain of the transistor M2 is electrically connected to node ND. The other of the source and the drain of the transistor M2 is electrically connected to terminal D. The gate of the transistor M2 is electrically connected to terminal C. The back gate of the transistor M2 is electrically connected to terminal E. The read circuit RC is electrically connected to node ND.

[0519] Transistor M1 is a write transistor that applies a potential to node ND. Transistor M2 is the transistor whose off-state current is measured. 20,000 800A samples of transistor M2 are connected in parallel. In other words, transistor M2 has a design value of a channel length of 30 nm and a channel width of 0.6 mm (= 30 nm × 20,000 pieces). Read circuit RC can constantly read the potential of node ND.

[0520] Next, a method for measuring the off-state current will be described. First, a potential V11 that turns on the transistor M1 is applied to the terminal B to turn on the transistor M1. Next, a potential V12 is applied to the terminal A until the potential of the node ND reaches V12. In this embodiment, V12 is set to 1.2 V. Next, a potential V13 that turns off the transistor M1 is applied to the terminal B to turn off the transistor M1. Note that the transistor M2 is always in the off state when a potential of −2 V is applied to the terminal C, a potential of −3 V is applied to the terminal E, and a potential of 0 V is applied to the terminal D.

[0521] In this way, the change in the potential of the node ND over time from when the transistor M1 is turned off is read by the read circuit RC, and the leakage current, i.e., the off-current of the transistor M2 can be calculated. off , the capacity of node ND is C ND , the potential change at node ND is ΔV ND , the elapsed time is t, and the off-state current is I off =C ND ×ΔV ND / t. Note that the design value of the channel width of the transistor M1 is much smaller than the channel width of the transistor M2, so the off-state current of the transistor M1 can be ignored.

[0522] In the measurement environment at a temperature of 150°C and the measurement environment at a temperature of 125°C, the potential change ΔV of the node ND after 1 hour ND In addition, in a measurement environment with a temperature of 100°C, the potential change ΔV of the node ND over a 2-hour period ND It was read as follows.

[0523] FIG. 30B shows a graph of the temperature dependence of the off-current of the transistor M2. The horizontal axis of FIG. 30B represents 1000 times the reciprocal of the absolute temperature T [K], and the vertical axis represents the off-current (I off ) [A / μm]. The off-state current of the transistor M2 at each temperature is plotted by a diamond in FIG. 30B. At a temperature of 150°C, it is 1.3×10 -18 A off-state current, 3.0 x 10 at 125°C -19 A off-state current, 7.1 x 10 at 100°C -20 The off-state current of 1×10 A was obtained for each sample. The approximate straight line is shown as a solid line. When the approximate straight line is extrapolated to room temperature (27°C), the off-state current is 1×10 A at room temperature. -21 It was estimated that the off-state current was less than A / μm. Therefore, it was found that the sample 800A constituting the transistor M2 had a very small off-state current.

[0524] Based on the above, OS transistors are expected to be used as high-voltage miniaturized devices.

[0525] This embodiment can be appropriately combined with other embodiment modes shown in this specification. [Example]

[0526] In this example, a transistor that can be used as a transistor included in a memory cell MC was fabricated.

[0527] FIG. 31A is a schematic diagram illustrating the structure of a prototype transistor. The prototype transistor is an OS transistor. Specifically, the prototype transistor has a configuration similar to that of the transistor 500 described in the above embodiment, including a top gate electrode, a gate insulating layer on the top gate electrode side, a back gate electrode, and electrodes functioning as a source or drain. The transistor was designed to have a channel length and a channel width of 30 nm. The EOT of the gate insulating layer on the top gate electrode side was set to 4.4 nm. The prototype transistor includes an In-Ga-Zn oxide (CAAC-IGZO) having a CAAC structure in the channel formation region.

[0528] Figure 31B is a cross-sectional STEM (Scanning Transmission Electron Microscope) image of the fabricated transistor in the channel length direction. Figure 31B shows that the measured gate length of the fabricated transistor was 21.5 nm, and the measured channel length was 31.5 nm.

[0529] Figure 31C is a cross-sectional STEM image of the fabricated transistor in the channel width direction. Figure 31C shows that the measured gate width of the fabricated transistor was 31.7 nm, and therefore the measured channel width of the fabricated transistor was confirmed to be 31.7 nm.

[0530] 31B and 31C, it was confirmed that a transistor having the configuration shown in Fig. 31A could be fabricated. As described above, the designed values ​​of the channel length and channel width were each 30 nm, and the measured values ​​of the channel length and channel width were 31.5 nm and 31.7 nm, respectively, confirming that the transistor could be fabricated as designed.

[0531] This embodiment can be appropriately combined with other embodiment modes shown in this specification. [Example]

[0532] In this example, a transistor having a channel formation region including an oxide semiconductor (referred to as an OS transistor) was fabricated, and the electrical characteristics of the fabricated transistor were measured. Note that the OS transistor fabricated in this example corresponds to the transistor 500 shown in FIGS. 14A and 14B , and therefore the contents described in the previous embodiment can be referred to for the structure and the like of the OS transistor fabricated in this example.

[0533] 32A and 32B show the top gate voltage (Vgs) vs. drain current (Id) characteristics of a prototype transistor with a gate length of 22 nm. The vertical axis in Fig. 32A shows Id in logarithm, and the vertical axis in Fig. 32B shows Id in linear.

[0534] The top gate voltage-drain current characteristics shown in FIG. 32A were measured when the drain voltage relative to the source was 1.2 V, the back gate voltage relative to the source was 0 V, and the measurement temperatures were −40° C., 27° C., 85° C., and 125° C.

[0535] The top gate voltage-drain current characteristics shown in FIG. 32A show that the off-state current is below the lower measurement limit of the measurement equipment (1×10 -13 A) It was less than that.

[0536] Furthermore, as shown in FIG. 32B, the drive current of the prototype transistor did not decrease even when the temperature of the measurement environment was increased.

[0537] FIG. 33 is a diagram showing the maximum current gain of a prototype transistor fabricated with a gate length of 13 nm.

[0538] Figure 33 shows the current gain versus the input frequency (indicated as "Input frequency" in the figure), and is the result of measurements taken when the drain voltage relative to the source is 2.5V, the top gate voltage is 2.5V, the back gate voltage relative to the source is 0V, and the temperature of the measurement environment is 27°C. From Figure 33, it is clear that the cutoff frequency (indicated as "f T ") is 60GHz.

[0539] This embodiment can be appropriately combined with other embodiment modes shown in this specification.

[0540] (Notes regarding the present specification) The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0541] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0542] In addition, the content (or even a part of the content) described in one embodiment can be applied, combined, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0543] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0544] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0545] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0546] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0547] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is referred to as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and drain of a transistor can be appropriately changed to source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0548] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0549] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and depending on the reference potential, the potential applied to wiring, for example, may be changed.

[0550] In this specification and the like, the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0551] In this specification, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows, or a device that has a function of selecting and switching a path for a current to flow.

[0552] In this specification, the channel length refers to, for example, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap in a top view of a transistor, or a distance between a source and a drain in a region where a channel is formed.

[0553] In this specification and the like, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0554] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, it enables the exchange of electrical signals between A and B. [Explanation of symbols]

[0555] 10: semiconductor device, 11: layer, 13: layer, 15: layer, 25: power line, 25_1: power line, 25_2: power line, 25_3: power line, 25_4: power line, 300: transistor, 310: substrate, 310A: substrate, 312: element isolation layer, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364 : insulator, 366: conductor, 411: insulator, 412: insulator, 413: insulator, 414: insulator, 416: conductor, 500: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 514: insulator, 516: insulator, 518: conductor, 520: insulator, 520a: insulator, 520b: insulator, 520c: insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 530ba: region, 530bb: region, 530bc: region, 540: conductor, 540a: conductor , 540b: conductor, 540c: conductor, 540d: conductor, 541: insulator, 541a: insulator, 541b: insulator, 541c: insulator, 541d: insulator, 542: conductor, 542a: conductor, 542b: conductor, 543: oxide, 543a: oxide, 543b: oxide, 544: insulator, 546: conductor, 550: insulator, 550a: insulator, 550b: insulator, 552: insulator, 553: insulator, 554: insulator, 560: conductor, 560a: conductor, 560b: conductor, 561: insulator, 562: conductor, 571: insulator, 571a: insulator, 5 71b: insulator, 574: insulator, 576: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 600: capacitor, 601: insulator, 602: insulator, 610: conductor, 611: conductor, 612: conductor, 613: conductor, 620: conductor, 630: insulator, 631: insulator, 640: insulator, 650: insulator, 660: conductor, 4700: electronic component, 4702: printed circuit board, 4704: mounting board, 4710: semiconductor device, 4711: mold, 4712: land, 4713: electrode pad, 4714: wire, 4730: electronic component,4731: Interposer, 4732: Package substrate, 4733: Electrode, 4735: Semiconductor device, 4800: Semiconductor wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit section, 4803: Spacing, 4803a: Spacing, 5110: SD card, 5111: Housing, 5112: Connector, 5113: Substrate, 5115: Controller chip, 5150: SSD, 5151: Housing, 5152: Connector, 5153: Substrate, 5155: Memory chip, 5156: Controller chip, 5200: portable game console, 5201: housing, 5202: display unit, 5203: button, 5300: desktop information terminal, 5301: main body, 5302: display unit, 5303: keyboard, 5400: ICD main body, 5401: battery, 5402: wire, 5403: wire, 5404: antenna, 5405: subclavian vein, 5406: superior vena cava, 5500: information terminal, 5510: housing, 5511: display unit, 5600: calculator, 5610: rack, 5620: calculator, 5621: PC Card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 5700: automobile, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator compartment door, 5803: freezer compartment door, 5900: information terminal, 5901: housing, 5902: display unit, 5903: operation switch, 5904: operation switch, 5905: band, 6100 : Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 6104: Board, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: Housing, 6302: Housing, 6303: Display unit, 6304: Operation switch, 6305: Lens, 6306: Connection unit, 7500: Type game console, 7520: Main unit, 7522: Controller, < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

[Claim 1] a memory cell, a switch, a first drive circuit, a second drive circuit, and a third drive circuit; the memory cell includes a first transistor, a second transistor, and a capacitor; the first transistor and the second transistor have indium oxide in a channel formation region; the capacitor has a ferroelectric layer between a pair of electrodes, one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; a gate of the second transistor electrically connected to one electrode of the capacitor; the other of the source and the drain of the first transistor is electrically connected to the first drive circuit via the switch; the first driving circuit has a function of generating data to be written to the memory cell; the second driving circuit has a function of turning on the first transistor when reading data from the memory cell; The third driver circuit has a function of reading data from the memory cell based on the potential of one of the source and drain of the second transistor.

Images