Substrate, manufacturing method thereof, substrate for semiconductor package and semiconductor device

Abstract

To provide a technique with which, even if the formation density of through holes on a substrate is uneven, the effects of the uneven formation density of the through holes are sufficiently mitigated so that a homogeneous plating layer is formed.SOLUTION: A manufacturing method of a substrate includes: a first step of selecting a first through hole group 171 where through holes are approximately evenly arranged, from through hole formation positions in a first area with a high formation density of the through holes; a second step of drilling holes at formation positions of the first through hole group 171 and at formation positions of a through hole group 172 in a second area 32 with a lower formation density of the through holes than that of the first area and performing plating treatment; a third step of selecting a second through hole group 172 other than the first through hole group 171, from the through hole formation positions in the first area; and a fourth step of drilling holes at the formation positions of the second through hole group 172 and a part of the through hole formation positions in the second area and performing plating treatment.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present invention relates to a substrate, a method for manufacturing the same, a substrate for a semiconductor package, and a semiconductor device. [Background technology]

[0002] In recent years, the number and density of plated through holes (PTH) in FC-BGA substrates have tended to increase, resulting in areas with large variations in PTH density within the substrate surface. When PTH density varies within a substrate surface, differences in the thickness of the plating applied to the substrate surface occur when plating through holes (TH), affecting the finished product and mounting. In other words, in areas with high PTH density, the plating thickness applied to the substrate surface is thin, while in areas with low PTH density, the plating thickness applied to the substrate surface is thick. For this reason, when there is a difference in density of PTH, a method has been devised in which the formation of through holes in areas with a high density of through holes is divided into two steps to suppress the difference in the thickness of the plating that adheres to the substrate surface.

[0003] Patent Document 1 discloses the following as a manufacturing method for forming uniform plating even when there is a deviation in the through-hole arrangement density. "A plurality of first through holes 4-1 are formed at a first pitch in a double-sided copper-clad laminate, a first plating film is formed on a first copper foil 2-1, a second plating film is formed on a second copper foil 2-2, and cylindrical first through-hole conductors 5-3 are formed, a first filling resin 6-1 is filled in the first through-hole conductors, a plurality of second through holes 4-2 are formed at a second pitch relative to adjacent first through holes, a third plating film and a fourth plating film are formed, and cylindrical second through-hole conductors 5-6 are formed on the side walls of the plurality of second through holes, and a second filling resin 6-2 is filled in the second through-hole conductors, and the surfaces of the first copper foil and second copper foil are made flush with the surfaces of the filling resin by polishing, and then a first conductive circuit 8-1 and a second conductive circuit 8-2 are formed from a fifth plating film 7-1 and a sixth plating film 7-2 formed on both surfaces. do." [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-93811 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, even if there is a bias in the arrangement density of the through holes, the effects of the difference in density of the through holes are mitigated by dividing the through hole formation, plating treatment, and through hole filling into two steps. However, there is a limit to the extent to which the effects of the bias in the density of the through holes can be mitigated by simply dividing the process into two steps. For this reason, in Patent Document 1, the surfaces of the first copper foil and the second copper foil and the surface of the filling resin are finally made flush with each other by polishing. This requires a step to make them flush, leaving room for improvement in terms of the manufacturing process and manufacturing costs. Furthermore, if the effects of differences in density of through holes cannot be sufficiently mitigated, even if a process is adopted to form a flush surface by polishing or the like, there is a risk that missing wiring patterns will occur in areas where the plating process is insufficient. Therefore, an object of the present invention is to provide a technique for sufficiently mitigating the influence of unevenness in the formation density of through holes, even when the formation density of through holes is uneven. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, one representative method for manufacturing a substrate of the present invention includes a first step of selecting a first group of through holes that are approximately uniformly arranged from through hole formation positions in a first region where the through hole formation density is high; a second step of drilling holes at the formation positions of the first group of through holes and at the formation positions of through hole groups in a second region where the through hole formation density is lower than that of the first region, and then performing a plating process; a third step of selecting a second through hole group other than the first through hole group from through hole formation positions in the first region; The method includes a fourth step of drilling holes in the positions where the second through-hole group is to be formed and in part of the positions where the through-holes in the second region are to be formed, and plating the holes.

[0007] In order to solve the above problems, one representative substrate of the present invention is: A substrate having a plurality of through holes formed therein, A first plating layer and a second plating layer are laminated on the hole wall of the through hole and the surface of the substrate. [Effects of the Invention]

[0008] According to the present invention, even if there is a bias in the density of through-holes formed, it is possible to provide a technique for mitigating the influence of the bias in the density of through-holes formed. Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiments of the invention. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view and a cross-sectional view of a substrate in which a through-hole is formed. [Figure 2] FIG. 2 is a cross-sectional view of a substrate used in the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view of the upper half of the substrate shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view of the upper half of the substrate after the first drilling process. [Figure 5] FIG. 5 is a cross-sectional view of the upper half of the substrate after the through-holes have been filled. [Figure 6] FIG. 6 is a cross-sectional view of the upper half of the substrate after the second drilling process. [Figure 7] FIG. 7 is a cross-sectional view of the upper half of the substrate after the through-holes have been filled. [Figure 8] FIG. 8 is a cross-sectional view of the top half of the substrate after two plating processes. [Figure 9] FIG. 9 is a cross-sectional view of the upper half of the substrate on which the etching resist is formed. [Figure 10] FIG. 10 is a cross-sectional view of the upper half of the etched substrate. [Figure 11] FIG. 11 is a cross-sectional view of the upper half of the substrate from which the etching resist has been stripped. [Figure 12] FIG. 12 is a cross-sectional view of the detailed structure of the wiring layer. [Figure 13] FIG. 13 is a cross-sectional view of the substrate for a semiconductor package according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view of the first drilling process in the second embodiment. [Figure 16] FIG. 16 is a cross-sectional view of the second drilling process in the second embodiment. [Figure 17] FIG. 17 is a plan view showing a through hole in the fourth embodiment. [Figure 18] FIG. 18 is a plan view showing a through hole in the fourth embodiment. [Figure 19] FIG. 19 is a plan view showing a through hole in the fourth embodiment. [Figure 20] FIG. 20 is a plan view showing a through hole in the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, in the description of the drawings, the same parts are designated by the same reference numerals. When there are multiple components with the same or similar functions, they may be described using the same reference numeral with different subscripts. When there is no need to distinguish between these multiple components, the subscripts may be omitted. Furthermore, although terms such as "first," "second," and "third" may be used to describe various elements or components in this disclosure, it will be understood that these elements or components should not be limited by these terms. These terms are used only to distinguish one element or component from another. Thus, a first element or component discussed below could also be referred to as a second element or component without departing from the teachings of the inventive concept.

[0011] In this disclosure, "upward" refers to the vertically upward direction. Furthermore, "upward" and its opposite, "downward," are sometimes referred to as the "positive z-axis direction" and the "negative z-axis direction," and the horizontal direction is sometimes referred to as the "x-axis direction" and the "y-axis direction." Furthermore, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings. For example, the thickness of the copper plating formed on the front and back surfaces of the substrate may be exaggerated compared to the copper plating formed on the wall of the through hole in order to facilitate understanding of the invention.

[0012] In addition, in this disclosure, the "density of through holes" refers to the number of through holes per unit area of ​​the substrate to be processed or treated in one processing or treatment such as drilling or plating.

[0013] (substrate) First, with reference to FIG. 1, a substrate and a through hole provided therein according to an embodiment of the present disclosure will be described. Fig. 1(a) is a plan view of a substrate 10, and Fig. 1(b) is a cross-sectional view taken along line XX in Fig. 1(a). A large number of through holes 30 are formed in the substrate 10, but in a first region 12 near the center of the substrate, the pitch between the through holes is narrower than in other regions, making it a region where the through holes are formed at a higher density. On the other hand, in the region surrounding 12, the pitch between the through holes is wider, making it a region where the through holes are formed at a lower density. Generally, when a semiconductor element is mounted on the surface of substrate 10, the pitch between the connection terminals of the semiconductor element is narrow, and therefore the through holes are often formed narrow in the substrate in the region where the semiconductor element is mounted. The pitch ratio between the pitch P1 between the through holes in first region 12 near the center of the substrate and the pitch P2 between the through holes in the peripheral region may differ by approximately 1.5 to 3.0.

[0014] Therefore, when plating is performed on areas where there are large differences in the density of through holes, the thickness of the plating layer formed on the surface of the substrate in areas with a high density of through holes will be thinner than in other areas, and in some cases this may lead to poor formation of the wiring pattern on the surface of the substrate. When plating through holes (through-hole plating), the plating speed inside the through holes is faster than on the surface of the board, and a thick plating layer is formed on the wall of the through holes. Therefore, if there are a large number of through holes per surface of the board, plating material is taken up by the plating inside the through holes, and the amount of plating deposited on the surface of the board decreases.

[0015] [First embodiment] To correct this variation in the thickness of the plating layer on the substrate surface, it is necessary to ensure that the through holes in the substrate are distributed approximately evenly throughout the substrate when plating is performed. For this reason, in the first embodiment, as described below, the distribution of the through holes in the substrate is made approximately uniform each time a plating process is performed. In other words, each time a plating process is performed, the through holes to be plated are selected so that the through holes are always distributed evenly. For this reason, even through holes that have already been plated once are re-formed and plated again.

[0016] Hereinafter, the method for manufacturing a substrate in the first embodiment will be described with reference to FIGS. FIG. 2 is a cross-sectional view of the substrate 10 used in the first embodiment. A general insulating substrate can be used as the substrate 10. In the first embodiment, a copper clad laminate (CCL) having copper foil 22 formed on both sides of the substrate 10 will be used for explanation. The core layer 21 of the substrate 10 is formed of a single-phase or multiple-layer (four-layer) insulating resin, and examples of the insulating resin include glass-cloth epoxy resin and BT (bismaleimide triazine) resin. The thickness of the core layer 21 is approximately 0.4 mm to 1.6 mm, and the substrate size is generally 500 × 600 mm.

[0017] <Position of through-hole> 3 is a cross-sectional view of the upper half of the substrate 10 shown in FIG. 2, with through-hole formation positions 30a to 30f indicated by hatching. In the example shown in FIG. 3, four through-holes (30a to 30e) are formed on the right side, with region 31 being a region with a high through-hole formation density. On the other hand, two through-holes (30e, 30f) are formed on the left side of FIG. 3, with region 32 being a region with a low through-hole formation density. In other words, region 31 corresponds to the first region 12 shown in FIG. 1, and region 32 corresponds to the second region surrounding first region 12.

[0018] <First drilling process> Next, the first drilling process will be described with reference to FIG. 4. FIG. 4 is a cross-sectional view of the upper half of the substrate 10 after the first drilling process. In the first drilling process, of the through-hole formation positions 30a to 30f, only 30a, 30c, 30e, and 30f are drilled. That is, in region 31 where the through-hole formation density is high, the through-hole formation positions are selected so that the intervals between the through-holes are approximately equal to those in the second region. In region 32, all of the through-hole formation positions are selected, and drilling is performed. That is, in the first drilling process, the drilling positions are selected so that the density of the through-holes is approximately equal across the entire substrate. In the drilling process, through-holes are formed in the substrate by drilling or laser irradiation, and after the through-holes are formed, electroless plating is performed.

[0019] <First plating process and hole filling process> Next, the electrolytic plating process and the hole filling process will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view of the upper half of a substrate that has been subjected to electroless plating, electrolytic plating, and then hole filling of the through holes. By performing electrolytic plating (through-hole plating) on ​​the substrate that has undergone electroless plating, plating layers 51 are formed on the walls of the through holes, and plating layers 50 are formed on the front and back surfaces of the substrate 10 (only the upper half of the substrate is shown in Figure 5). Thereafter, the gaps in the through holes are filled with resist paste, and a hardening process is carried out to form hole-filling resist 52. In the first drilling process in the first embodiment, in the region 31 where the density of through holes is high, the drilling locations are selected so that the density of through holes is approximately uniform, so that a plating layer 50 with little variation in thickness can be obtained on the front and back surfaces of the substrate.

[0020] <Second drilling process> Next, the second drilling process will be described with reference to FIG. 6. FIG. 6 is a cross-sectional view of the upper half of the substrate 10 after the second drilling process. In the second drilling process, holes are drilled at 30b, 30d, 30e, and 30f among the through-hole formation positions 30a to 30f. That is, in the second drilling process, new holes are drilled at 30b and 30d, which were not drilled at the first drilling process, in the region 31 where the through-hole formation density is high, to form through holes. However, if only 30b and 30d are drilled and then plated, an excessively large plating layer will be formed in the region 32. For this reason, in the first embodiment, holes 30e and 30f, which have already been drilled, are also drilled again. In this way, in the second drilling process, the drilling locations are also selected so that the density of through holes is approximately uniform over the entire substrate.

[0021] When drilling a second hole in the same location as the first, the diameter of the hole in the second drilling may be larger than the first, or may be the same as the first. Also, the center of the second drilling may be slightly offset from the center of the first drilling. By increasing the diameter of the second hole, it is possible to reduce the thickness of the plating layer formed on the substrate surface around the large diameter hole.

[0022] After the second drilling process is performed to form the through holes, electroless plating is performed in the same manner as in the first drilling process.

[0023] <Second plating process and hole filling process> Next, the second electrolytic plating process and hole filling process will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view of the upper half of a substrate that has been subjected to electroless plating, electrolytic plating, and then hole filling of the through holes. By performing electrolytic plating (through-hole plating) on ​​the substrate described in Figure 6, a plating layer 71 is formed on the hole walls of the through holes 30b, 30d, 30e, and 30f, and a plating layer 70 is further formed on the plating layer 50 on the front and back surfaces of the substrate 10. Thereafter, the gaps in the through holes are filled with resist paste, and a hardening process is carried out to form hole-filling resist 72. In the second drilling process in the first embodiment, the drilling locations are also selected in the region 31 where the through-hole formation density is high so that the density of through-holes is approximately uniform across the entire substrate. Therefore, plating layer 70 with little variation in thickness can be obtained on the front and back surfaces of the substrate. As a result, by the first plating process and the second plating process, plating layers consisting of plating layer 50 and plating layer 70 with little variation in thickness can be obtained on both surfaces of substrate 10, i.e., the front and back surfaces of the substrate.

[0024] <Cross-sectional structure of plating layer> Next, the cross-sectional structure of the upper half of the substrate that has been plated twice will be described with reference to Fig. 8. Fig. 8(a) is a cross-sectional view of the first embodiment when a copper clad laminate (CCL) having copper foil formed on both sides of the substrate is used, and Fig. 8(b) is a cross-sectional view of the first embodiment when a laminate having no copper foil formed thereon is used as the substrate. 8(a), copper foil 22 is formed on the upper surface of core layer 21 constituting substrate 10, and plating layer 50 by the first plating process is formed on the upper surface of copper foil 22, sandwiching boundary line 80. Furthermore, plating layer 70 by the second plating process is formed, sandwiching boundary line 81. In Figure 8(b), a plating layer 50 is formed by a first plating process on the upper surface of the core layer 21 that constitutes the substrate 10, and a plating layer 70 is further formed by a second plating process across a boundary line 81. The boundary line 80 and the boundary line 81 are the boundary lines between the first plating process and the second plating process. This intermittent process causes discontinuity in the crystal structure at the boundary surface, resulting in visible stripe-like boundaries.

[0025] <Etching resist pattern> Next, the formation of an etching resist pattern will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view of a substrate in which an etching resist pattern 90 has been formed on the plating layer 70 after the second plating process. The etching resist pattern 90 can be formed into a desired pattern for forming a wiring pattern by a known method. In addition, it can be formed around the through holes as a resist pattern for forming through-hole lands, which are part of the wiring pattern.

[0026] <Copper etching> Next, copper etching will be described with reference to Fig. 10. The plating layer 70 and the plating layer 50 can be etched using the resist pattern 90 described in Fig. 9 to form a desired wiring layer pattern. Note that a known copper etching technique can be used for the etching.

[0027] <Core layer> Next, with reference to Fig. 11, the substrate 10 on which the etching resist has been stripped and a wiring layer has been formed will be described. Fig. 11 is a cross-sectional view of the upper half of the substrate 10 from which the etching resist has been stripped. As shown in Fig. 11, the surface of the substrate 10 is provided with plating layers 70 and 50, and wiring layers with a substantially uniform film thickness are formed in regions 31 and 32.

[0028] Next, the structure of the wiring layer explained in Fig. 11 will be described in detail with reference to Fig. 12. Fig. 12 is a diagram showing a cross section of the wiring layer shown in Fig. 11. FIG. 12(a) is a cross-sectional view of the first embodiment when a copper clad laminate (CCL) having copper foil formed on both sides of the substrate is used, and FIG. 12(b) is a cross-sectional view of the first embodiment when a laminate having no copper foil formed thereon is used as the substrate. In Figure 12(a), a wiring pattern is also formed on the upper surface of the core layer 21 constituting the substrate 10, and a plating layer 50 by the first plating process is formed on the upper surface of the copper foil 22, sandwiching a boundary line 80 therebetween, and a plating layer 70 by the second plating process is further formed as a wiring pattern, sandwiching a boundary line 81 therebetween. In Figure 12(b), a plating layer 50 is formed by the first plating process on the upper surface of the core layer 21 that constitutes the substrate 10, and further, plating layers 70 by the second plating process are formed as wiring patterns on either side of the boundary line 81. In other words, in a substrate having a plating layer formed on the surface of a core layer, the wiring layer formed on the surface of the core layer has a structure in which a second plating layer formed by a second plating process is laminated on top of a first plating layer formed by a first plating process.

[0029] <Substrate for semiconductor packages> Next, with reference to FIG. 13 , a semiconductor package substrate in which buildup layers are formed on the core layer 21 on which the wiring layer described in FIG. 12 is formed will be described. FIG. 13 is a cross-sectional view of a semiconductor package substrate in which three buildup layers 134 are formed on the top and bottom surfaces of the core layer 21. Through holes 30 are formed in the core layer 21, and patterned wiring layers 131 are connected to the through holes 30. An interlayer insulating layer 133 is formed on the wiring layer 131, and vias 132 connecting the wiring layers are formed in the interlayer insulating layer 133. Pads 137 are formed as output electrodes on the top layer of the buildup layers. Solder balls 138 are formed on the pads 137 at the connection points with the semiconductor elements, and a solder resist layer 135 is laid in the other areas. The buildup layers 134 below the core layer 21 have a similar configuration, but the bottom buildup layer has large-area pads 137 arranged on it, assuming that it will be connected to another wiring board with a larger spacing between connection electrodes than the semiconductor elements. However, the configuration of the semiconductor package substrate is not limited to the above, and various other configurations can be adopted.

[0030] <Semiconductor device> Next, with reference to FIG. 14, a semiconductor device 14 in which semiconductor elements and other electronic components 142 are mounted on the semiconductor package substrate 13 described with reference to FIG. 13 will be described. 14 is a cross-sectional view of a semiconductor device 14 in which a semiconductor element 141 or other electronic components 142 are mounted on a semiconductor package substrate 13. The cross-sectional view shows the semiconductor package substrate. Underfill may be injected between the semiconductor element 141 or electronic components 142 and the semiconductor package substrate 13 to make the mounting more secure.

[0031] [Second embodiment] <First drilling process> In the first embodiment, in the first drilling process, the formation positions of the through holes in region 31 where the formation density of the through holes is high are selected so that the intervals between the through holes in the second region are approximately equal. However, in the second embodiment, the formation positions of the first through hole group in region 31 where the formation density of the through holes is high are selected so that the formation density of the through holes is higher than the formation density of the through holes in the second region, which is different from the first embodiment. In the following description, the same or equivalent components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be simplified or omitted. Also, the description of the same steps will be simplified or omitted.

[0032] <Second drilling process> 15, in region 31 where the through holes are formed at a high density, positions 30a, 30c, and 30d are selected as the positions where the through holes are formed so that the formation density is higher than the spacing between the through holes in region 32. Then, in the second drilling process, as shown in FIG. 16, in region 31, holes are drilled in 30b which was not drilled in the first drilling process, and in 30e and 30f in region 32.

[0033] The second embodiment is the same as the first embodiment except for the positions of the first and second drilling processes. Therefore, in the second embodiment, the thickness of the plating layer 50 formed in the region 31 by the first plating process after the first drilling process is thinner than the thickness of the plating layer 50 formed in the region 32. However, the thickness of the plating layer 70 formed in the region 31 by the second plating process is thicker than the thickness of the plating layer 70 formed in the region 32. Furthermore, the thicknesses of the plating layer 50 and the plating layer 70 formed in the region 32 are approximately equal. As a result, the total thickness of the plating layer 50 and the plating layer 70 formed on both sides of the core layer 21 can be made approximately equal on both sides of the core layer 21.

[0034] In other words, in the second embodiment, the density of the through holes formed in the first drilling process and the density of the through holes formed in the second drilling process in region 31 are set to be larger and smaller, based on the density of the through holes in region 32, thereby making it possible to make the thickness of the plating layer that is finally formed uniform on the front surface of the core layer.

[0035] [Third embodiment] <First drilling process> In the second embodiment, in region 31 where the through holes are formed at a high density, the positions where the first through hole groups are formed are spaced apart so that the density of the through holes is higher than the density of the through holes in the second region. However, the third embodiment differs from the second embodiment in that in the region 31 where the density of through holes is high, the formation positions of the first through hole groups are spaced apart so that the density is lower than the density of through holes in the second region. In the following description, the same or equivalent components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be simplified or omitted. Also, the description of the same steps will be simplified or omitted.

[0036] That is, in the third embodiment, the first drilling process is performed as shown in Figure 16 (the second drilling process in the second embodiment), and the second drilling process is performed as shown in Figure 15 (the first drilling process in the second embodiment). In the third embodiment, the thickness of the plating layer 50 formed in the region 31 is thicker than the thickness of the plating layer 50 formed in the region 32 due to the first plating process after the first drilling. However, due to the second plating process after the second drilling, the thickness of the plating layer 70 formed in the region 31 is thinner than the thickness of the plating layer 70 formed in the region 32. Furthermore, the thicknesses of the plating layer 50 and the plating layer 70 formed in the region 32 are approximately equal. As a result, the total thickness of the plating layer 50 and the plating layer 70 formed on both sides of the core layer 21 can be made approximately equal on both sides of the core layer 21.

[0037] In other words, in the third embodiment, the density of the through holes formed in the first drilling process in region 31 is made smaller than the density of the through holes in region 32, and the density of the through holes formed in the second drilling process is made larger than the density of the through holes in region 32, thereby making it possible to make the thickness of the plating layer that is finally formed uniform over the entire surface of the core layer.

[0038] [Fourth embodiment] <Three-time drilling process> In the first to third embodiments, the through holes included in a first region having a high through hole formation density were divided into a first through hole group and a second through hole group. Then, as a first drilling process, drilling was performed on the through hole formation positions of the first through hole group and the second region. Furthermore, as a second drilling process, drilling was performed on the through hole formation positions of the first second through hole group and the second region. However, in the fourth embodiment, the through holes included in the first region having a high through hole formation density are divided into first to third through hole groups, and in the first drilling process, drilling is performed on the first through hole group and some of the through hole formation positions in the second region.The second drilling process then drills the second through hole group and some of the through hole formation positions in the second region, and in the third drilling process, drills the third through hole group and some of the through hole formation positions in the second region, which is different from the first to third embodiments. In the following description, the same or equivalent components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be simplified or omitted. Also, the description of the same steps will be simplified or omitted.

[0039] <First to third through hole groups> First, with reference to Figure 17, the through holes included in the first region 12 where the through hole formation density is high will be described as first to third through hole groups and the through hole formation positions in the second region. Figure 17 is a plan view of the substrate 10 as seen from above, and the through holes included in the first region 12 where the through hole formation density is high are divided into a first through hole group 171 marked with vertical lines, a second through hole group 172 marked with diagonal lines, and a third through hole group 173 marked with grid lines. Note that the through hole formation positions 174 of the second region are arranged around the periphery of the first region 12, and their density is approximately one-third that of the first region 12.

[0040] <1st to 3rd drilling steps> Next, the first to third drilling processes will be described with reference to Figures 18 to 20. The through holes to be drilled in the first round are the first through hole group 171 included in the first region 12 and some of the through holes in the second region, as shown in Figure 18. The through holes to be drilled in the second round are the second through hole group 172 included in the first region 12 and some of the through holes in the second region, as shown in Figure 19. The through holes to be drilled in the third round are the third through hole group 173 included in the first region 12 and some of the through holes in the second region, as shown in Figure 20.

[0041] In the first to third drilling processes, most of the through holes in the second region are drilled three times, followed by plating and hole-filling processes three times. However, as in the first embodiment, the density of the through holes in each plating process is approximately uniform over the entire surface of the core layer, so that the variation in the thickness of the plating layer formed on the core layer can be suppressed. It should be noted that for the through holes in the second region, it is not necessary to perform the drilling, plating, and hole-filling processes three times for all of the through holes present in the second region. In order to make the density of the through holes when plating uniform across the entire surface of the core layer, it is sufficient to perform the drilling, plating, and hole-filling processes at 80% to 90% or more of the through hole formation positions in the second region in the first to third processes, and in order to make the density of the through holes uniform across the entire surface of the core layer, it is also possible to thin out some of the through holes present in the second region before performing the processes.

[0042] [Fifth embodiment] In the fourth embodiment, the densities of the through holes in the first region and the second region are set to be approximately equal in the first to third drilling processes. However, the fifth embodiment differs from the fourth embodiment in that, like the second and third embodiments, the densities of the through holes in the first region during the first to third drilling processes may be set to be greater or smaller than the density of the through holes in the second region. In the following description, the same or equivalent components as those in the fourth embodiment will be denoted by the same reference numerals, and the description thereof will be simplified or omitted. Also, the description of the same steps will be simplified or omitted.

[0043] For example, in the first to third drilling processes, the drilling density in the first region in one of the drilling processes can be set to be greater than the drilling density in the second region, and in the other drilling processes, the drilling density can be set to be smaller than the drilling density in the second region, so that the thickness of the plating layer that is finally formed can be made uniform over the entire surface of the core layer 21.

[0044] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present invention. The present disclosure includes the following aspects.

[0045] (Aspect 1) A method of manufacturing a substrate, comprising forming a through hole in a substrate and forming a plating layer on a hole wall of the through hole and on both surfaces of the substrate, a first step of selecting a first group of through holes arranged approximately uniformly from through hole formation positions in a first region where the through holes are formed at a high density; a second step of performing a drilling process at positions where the first through hole group is formed and at positions where a through hole group in a second region where the through holes are formed at a lower density than in the first region is formed, and then performing a plating process; a third step of selecting a second through hole group other than the first through hole group from through hole formation positions in the first region; a fourth step of drilling holes at the positions where the second through hole group is to be formed and at some of the positions where the through holes in the second region are to be formed, and then plating the holes; A method for manufacturing a substrate comprising:

[0046] (Aspect 2) In the method for producing a substrate according to aspect 1, The formation density of the through holes in the first through hole group is approximately the same as the formation density of the through holes in the second region. A method for manufacturing a substrate.

[0047] (Aspect 3) In the method for producing a substrate according to aspect 1, The formation density of the through holes in the first through hole group is greater than the formation density of the through holes in the second region. A method for manufacturing a substrate.

[0048] (Aspect 4) In the method for producing a substrate according to aspect 1, The formation density of the through holes in the first through hole group is lower than the formation density of the through holes in the second region. A method for manufacturing a substrate.

[0049] (Aspect 5) 5. The method for manufacturing a substrate according to claim 1, The part of the through-hole formation position in the second region in the fourth step is 80% or more of the through-hole formation position in the second region. A method for manufacturing a substrate.

[0050] (Aspect 6) A substrate having a plurality of through holes formed therein, The substrate is characterized in that a first plating layer and a second plating layer are laminated on the hole walls of the through holes and the surface of the substrate.

[0051] (Aspect 7) In the substrate according to embodiment 6, 1. A substrate, comprising: a first region having a high density of through holes; a first plating layer and a second plating layer having substantially the same thickness;

[0052] (Aspect 8) In the substrate according to embodiment 6 or embodiment 7, The substrate is a copper clad laminate (CCL), A substrate characterized in that the first plating layer and the second plating layer are laminated on both sides of the copper-clad laminate.

[0053] (Aspect 9) The substrate of any one of embodiments 6 to 8, The substrate is characterized in that the through-hole has a plating layer formed on the hole wall and the center of the through-hole is filled with a hole-filling resin.

[0054] (Aspect 10) The substrate of any one of embodiments 6 to 9, A substrate for semiconductor package, in which a build-up layer is formed on the substrate.

[0055] (Aspect 11) A semiconductor device in which a semiconductor element is mounted on the substrate for semiconductor package according to aspect 10. [Explanation of symbols]

[0056] 10: Circuit board 13: Substrate for semiconductor package 14: Semiconductor device 12: First Area 21: Core layer 22: Copper foil 30:Through hole 31: Area 32: Area 50: Plating layer 70: Plating layer 71: Plating layer (hole wall) 72: Hole filling resist 80: Borderline 81: Borderline 90: Etching resist pattern 131: Wiring layer 132: Beer 133: Interlayer insulating layer 134: Build-up layer 135: Solder resist layer 136: Viapad 137: Ball pad 138: Solder ball 141: Semiconductor element 142: Electronic parts 171: First through-hole group 172: Second through-hole group 173: Third through-hole group 174: Position where through-holes are formed in the second region

Claims

1. A method of manufacturing a substrate, comprising forming a through hole in a substrate and forming a plating layer on a hole wall of the through hole and on both surfaces of the substrate, a first step of selecting a first group of through holes arranged substantially uniformly from through hole formation positions in a first region where the through holes are formed at a high density; a second step of performing a drilling process at positions where the first through hole group is formed and at positions where a through hole group in a second region where the through holes are formed at a lower density than in the first region is formed, and then performing a plating process; a third step of selecting a second through hole group other than the first through hole group from through hole formation positions in the first region; a fourth step of drilling holes at the positions where the second through-hole group is to be formed and at some of the positions where the through-holes in the second region are to be formed, and then plating the holes; A method for manufacturing a substrate comprising:

2. 2. The method for manufacturing a substrate according to claim 1, A method for manufacturing a substrate, wherein the formation density of the through holes in the first through hole group is approximately the same as the formation density of the through holes in the second region.

3. 2. The method for manufacturing a substrate according to claim 1, A method for manufacturing a substrate, wherein the formation density of the through holes in the first through hole group is greater than the formation density of the through holes in the second region.

4. 2. The method for manufacturing a substrate according to claim 1, A method for manufacturing a substrate, wherein the formation density of the through holes in the first through hole group is lower than the formation density of the through holes in the second region.

5. 5. The method for manufacturing a substrate according to claim 1, A method for manufacturing a substrate, wherein the part of the through-hole formation position in the second region in the fourth step is 80% or more of the through-hole formation position in the second region.

6. A substrate having a plurality of through holes formed therein, A substrate characterized in that a first plating layer and a second plating layer are laminated on the wall of the through hole and the surface of the substrate.

7. The substrate according to claim 6, A substrate, characterized in that in a first region where the density of through holes is high, the thicknesses of the first plating layer and the second plating layer are approximately equal.

8. The substrate according to claim 6, The substrate is a copper clad laminate (CCL), A substrate characterized in that the first plating layer and the second plating layer are laminated on both sides of the copper-clad laminate.

9. The substrate according to any one of claims 6 to 8, The substrate is characterized in that the through-hole has a plating layer formed on the hole wall and the center of the through-hole is filled with a hole-filling resin.

10. The substrate according to any one of claims 6 to 8, A substrate for semiconductor package, in which a build-up layer is formed on the substrate.

11. A semiconductor device comprising a semiconductor element mounted on the semiconductor package substrate according to claim 10.

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