Semiconductor device and method for manufacturing the same

Abstract

To realize a semiconductor device that does not adversely affect circuit operation even in a fine pixel circuit.SOLUTION: The semiconductor device includes: a first gate electrode; a first gate insulating layer; an oxide semiconductor layer; a second gate insulating layer provided with a first opening and a second opening reaching the oxide semiconductor layer; a second gate electrode extending in a first direction; a first electrode in contact with the oxide semiconductor layer at the first opening; and a second electrode in contact with the oxide semiconductor layer at the second opening. In a first region in plan view, the second gate electrode overlaps the oxide semiconductor layer, and in a second region in plan view, the first electrode contacts the oxide semiconductor layer. In a cross-sectional view, the width of the second gate electrode in a second direction intersecting the first direction is 2 μm or less, and the distance between the first region and the second region in the second direction is 2 μm or less.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Recently, development of transistors using oxide semiconductors for the channel instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been progressing (for example, Patent Documents 1 and 2). Transistors using oxide semiconductors for the channel have a simple structure and are formed by a low-temperature process, similar to transistors using amorphous silicon for the channel. Transistors using oxide semiconductors for the channel are known to have higher mobility and exhibit very low off-current than transistors using amorphous silicon for the channel.

[0003] In recent years, pixel size in display devices has been reduced. Along with this reduction in pixel size, reductions in wiring width and transistor size have been considered. However, there are limits to these reductions, and it is difficult to obtain a sufficient aperture ratio due to the arrangement of metal layers and semiconductor layers that constitute pixel circuits. Therefore, development is underway to use transistors in pixel circuits that use oxide semiconductor layers as channels, which can obtain sufficient characteristics for driving pixel circuits even with small transistor sizes. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-146819 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-159315 Summary of the Invention [Problem to be solved by the invention]

[0005] As transistors become smaller, their manufacturing processes can cause abnormalities in their characteristics. Because it is particularly difficult to achieve both high initial characteristics and high reliability in stress tests, there is often a trade-off between these two factors. For example, in a top-gate transistor using an oxide semiconductor layer as the channel, the initial characteristics and stress test results are affected by the film quality of the insulating layer provided above the gate electrode. Abnormal initial characteristics and characteristic fluctuations in reliability tests of transistors adversely affect the operation of pixel circuits in display devices.

[0006] An object of one embodiment of the present invention is to realize a semiconductor device that does not adversely affect circuit operation even when the pixel circuit is minute. [Means for solving the problem]

[0007] a first gate insulating layer above the first gate electrode; an oxide semiconductor layer above the first gate insulating layer; a second gate insulating layer above the oxide semiconductor layer, the second gate insulating layer having a first opening and a second opening reaching the oxide semiconductor layer; a second gate electrode extending in a first direction above the second gate insulating layer; a first electrode in contact with the oxide semiconductor layer in the first opening; and a second electrode in contact with the oxide semiconductor layer in the second opening, wherein the second gate electrode overlaps with the oxide semiconductor layer in a first region in a planar view and the first electrode in contact with the oxide semiconductor layer in a second region in a planar view; a width of the second gate electrode in a second direction intersecting the first direction is 2 μm or less in a cross-sectional view; and a distance between the first region and the second region in the second direction is 2 μm or less in a cross-sectional view.

[0008] a first gate electrode formed on the first insulating layer, an oxide semiconductor layer formed on the first insulating layer, a second gate insulating layer formed on the oxide semiconductor layer, a second gate electrode extending in a first direction above the second gate insulating layer, an impurity implanted into the oxide semiconductor layer from above the second gate electrode through the second gate insulating layer, a first opening and a second opening formed in the second gate insulating layer, the first opening and the second opening reaching the oxide semiconductor layer, and a first electrode in contact with the oxide semiconductor layer in the first opening and a second electrode in contact with the oxide semiconductor layer in the second opening, wherein the width of the second gate electrode in a second direction intersecting the first direction is 2 μm or less in a cross-sectional view, and the distance between the first region and the second region in the second direction is 2 μm or less in a cross-sectional view. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. [Figure 2] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 3] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 4] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 5] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 6] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 7] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 8] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 9] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 10] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 11] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 12] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 13] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 14] 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention. [Figure 15] FIG. 10 is a diagram showing electrical characteristics of the semiconductor device according to the embodiment of the present invention. [Figure 16] FIG. 10 is a diagram showing electrical characteristics of the semiconductor device according to the embodiment of the present invention. [Figure 17] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 19] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 20] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 21] 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 22] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily arrive at by appropriately modifying the configuration of the embodiments while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part more schematically than the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, configurations similar to those described above with respect to the previous drawings are designated by the same reference numeral followed by an alphabet, and detailed description may be omitted as appropriate.

[0011] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downper." For convenience of explanation, the terms "up" and "downper" are used in the following description. However, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be different from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When a pixel electrode is referred to as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is referred to as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0012] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, although the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer as an example of a display device, the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0013] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0015] [1. First embodiment] [1-1. Configuration of display device 10] The configuration of a display device 10 according to one embodiment of the present invention will be described with reference to Figs. 1 to 13. Fig. 1 is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. Fig. 2 is a plan view showing an overview of a display device according to one embodiment of the present invention. Figs. 3 to 13 are plan views illustrating the layout of each layer in a display device according to one embodiment of the present invention. The cross-sectional view of Fig. 1 is a cross-sectional view for explaining the layer structure of the display device 10, and may not strictly match the plan view of Fig. 2.

[0016] As shown in FIG. 1, the display device 10 is provided above a substrate SUB. The display device 10 has a transistor Tr1, a transistor Tr2 (Tr2-1, Tr2-2), wiring W, a pixel electrode PTCO, a common auxiliary electrode CMTL, and a common electrode CTCO. TCO is an abbreviation for Transparent Conductive Oxide. The transistor Tr1 is a semiconductor device included in a pixel circuit of the display device 10. The transistor Tr2 is a semiconductor device included in a peripheral circuit. As will be described in detail later, the peripheral circuit is a circuit that drives the pixel circuit. In the following description, the "semiconductor device" may include only the configuration of the transistor Tr1, or may include the configurations of both the transistors Tr1 and Tr2.

[0017] [1-2. Configuration of transistor Tr1] The transistor Tr1 has a gate electrode LS (LS1, LS2), gate insulating layers GI2, IL1, oxide semiconductor layers OS (OS1, OS2), gate insulating layer GI1, gate electrode GL1, connection electrode WM, connection electrode ZTCO, and wiring XTCO. The gate electrode LS is provided above the substrate SUB. The gate insulating layers GI2, IL1 are provided above the gate electrode LS. The oxide semiconductor layer OS is provided above the gate insulating layer IL1. The gate insulating layer GI1 is provided above the oxide semiconductor layer OS. The gate electrode GL1 is provided above the gate insulating layer GI1. In this embodiment, a dual-gate transistor in which the gate electrode LS is provided below the oxide semiconductor layer OS and the gate electrode GL1 is provided above the oxide semiconductor layer OS is exemplified, but a top-gate transistor in which only the gate electrode GL1 is provided may also be used.

[0018] In this embodiment, gate electrodes LS1 and LS2 are provided as the gate electrode LS. However, the gate electrode LS may be formed of only the gate electrode LS1 or only the gate electrode LS2. In plan view, the gate electrode LS is provided in a region where the gate electrode GL1 and the oxide semiconductor layer OS overlap. That is, in plan view, the gate electrode LS is provided in a region where the gate electrode LS overlaps with the oxide semiconductor layer OS1. For example, the same voltage as that of the gate electrode GL1 is supplied to the gate electrode LS. However, a voltage different from that of the gate electrode GL1 may be supplied to the gate electrode LS. The gate electrode LS also functions as a light-shielding layer, and prevents light incident from the substrate SUB side from reaching the oxide semiconductor layer OS1.

[0019] In this embodiment, the oxide semiconductor layer OS is in contact with the gate insulating layer IL1, but the present invention is not limited to this configuration. For example, a metal oxide layer may be provided between the oxide semiconductor layer OS and the gate insulating layer IL1. For example, a metal oxide containing aluminum as a main component may be used as the metal oxide layer. Specifically, aluminum oxide may be used as the metal oxide layer. In this case, the metal oxide layer may be provided in the same region as the gate insulating layer IL1 and may be processed into the same pattern as the oxide semiconductor layer OS.

[0020] The oxide semiconductor layer OS includes a polycrystalline structure, an amorphous structure, or a structure in which the polycrystalline structure and the amorphous structure are mixed. The oxide semiconductor layer OS includes oxide semiconductor layers OS1 and OS2. The oxide semiconductor layer OS1 is an oxide semiconductor layer in a region overlapping with the gate electrode GL1 in a planar view. The oxide semiconductor layer OS1 functions as a semiconductor layer and is switched between a conductive state and a non-conductive state depending on the voltage supplied to the gate electrode GL1. In other words, the oxide semiconductor layer OS1 functions as a channel of the transistor Tr1. The oxide semiconductor layer OS2 functions as a conductive layer. The oxide semiconductor layers OS1 and OS2 are layers formed from the same oxide semiconductor layer. For example, the oxide semiconductor layer OS2 is an oxide semiconductor layer having the same physical properties as the oxide semiconductor layer OS1, the resistance of which is reduced by doping impurities into the layer.

[0021] An insulating layer IL2 is provided above the gate electrode GL1. A wiring W1 is provided above the insulating layer IL2. The wiring W1 is connected to the oxide semiconductor layer OS2 via a connection electrode WM provided inside an opening WCON provided in the insulating layer IL2 and the gate insulating layer GI1. The connection electrode WM is in contact with the oxide semiconductor layer OS at the bottom of the opening WCON. The wiring W1 and the connection electrode WM are metal layers and are in the same layer. A data signal related to the gradation of the pixel is transmitted to the wiring W1. An insulating layer IL3 is provided above the insulating layer IL2 and the wiring W1. The connection electrode ZTCO and the wiring XTCO are above the insulating layer IL3 and in contact with the upper surface of the insulating layer IL3.

[0022] The connection electrode ZTCO is connected to the oxide semiconductor layer OS2 through an opening ZCON provided in the insulating layers IL3 and IL2 and the gate insulating layer GI1. The connection electrode ZTCO is in contact with the oxide semiconductor layer OS2 in a contact region CON1 at the bottom of the opening ZCON. The wiring XTCO is connected to the wiring W1 through an opening XCON provided in the insulating layer IL3. The connection electrode ZTCO and the wiring XTCO are transparent conductive layers. As described above, the gate electrode GL1, the wiring W1, the connection electrode WM, the connection electrode ZTCO, and the wiring XTCO are provided above the oxide semiconductor layer OS.

[0023] The wiring XTCO is provided in the same layer as the connection electrode ZTCO and is separated from the connection electrode ZTCO. When the oxide semiconductor layer OS has a polycrystalline structure, the material of the connection electrode ZTCO is the same as the material of the wiring XTCO, but the crystallinity of a portion of the connection electrode ZTCO differs from that of the wiring XTCO. For example, even if the connection electrode ZTCO and the wiring XTCO are both ITO formed using the same process, the crystallinity of a portion of the ITO used as the connection electrode ZTCO differs from that of the ITO used as the wiring XTCO. Different crystallinity includes different crystal structures, as well as different parameters such as lattice constants even if the crystal structures are the same. When transparent conductive layers with different crystallinity are observed with an optical microscope, they have different colors. In other words, the refractive indices of these transparent conductive layers are different.

[0024] The connection electrode ZTCO is divided into a contact region and a non-contact region in plan view. The contact region includes a region where the connection electrode ZTCO is in contact with the oxide semiconductor layer OS. The non-contact region is a region other than the contact region. The crystallinity of the connection electrode ZTCO in the contact region is different from the crystallinity of the connection electrode ZTCO in the non-contact region.

[0025] For example, when a transparent conductive layer such as an ITO layer is formed in contact with a semiconductor layer such as a silicon layer, the surface of the semiconductor layer is oxidized by the process gas and oxygen ions used during ITO film formation. Because the oxide layer formed on the surface of the semiconductor layer has high resistance, the contact resistance between the semiconductor layer and the transparent conductive layer increases. As a result, poor electrical contact occurs between the semiconductor layer and the transparent conductive layer.

[0026] On the other hand, when the connection electrode ZTCO is formed so as to be in contact with the oxide semiconductor layer OS including a polycrystalline structure, the above-described high-resistance oxide layer is not formed on the surface of the oxide semiconductor layer OS.

[0027] The reason for the above is presumed to be as follows. When the connection electrode ZTCO is formed in contact with the oxide semiconductor layer OS as described above, the connection electrode ZTCO formed above the oxide semiconductor layer OS crystallizes immediately after deposition, reflecting the crystalline structure of the oxide semiconductor layer OS. For example, when the connection electrode ZTCO is formed under certain deposition conditions, the connection electrode ZTCO formed in a portion other than the oxide semiconductor layer OS does not crystallize, but the connection electrode ZTCO formed in a region in contact with the oxide semiconductor layer OS crystallizes. In this way, it is thought that the crystallization of the connection electrode ZTCO during deposition reduces the oxide semiconductor layer OS in a region of the surface of the oxide semiconductor layer OS that is in contact with the connection electrode ZTCO. As a result, it is thought that the carrier concentration on the surface of the oxide semiconductor layer OS increases, reducing the contact resistance between the oxide semiconductor layer OS and the connection electrode ZTCO.

[0028] An insulating layer IL4 is provided above the connection electrode ZTCO. The insulating layer IL4 reduces steps formed by structures provided below the insulating layer IL4. The insulating layer IL4 is sometimes called a planarizing film. A pixel electrode PTCO is provided above the insulating layer IL4. The pixel electrode PTCO is connected to the connection electrode ZTCO through an opening PCON provided in the insulating layer IL4. The region where the connection electrode ZTCO and the pixel electrode PTCO contact is called a contact region CON2. In a plan view, the contact region CON2 overlaps with the gate electrode GL1. The pixel electrode PTCO is a transparent conductive layer.

[0029] An insulating layer IL5 is provided above the pixel electrode PTCO. A common auxiliary electrode CMTL and a common electrode CTCO are provided above the insulating layer IL5. That is, the pixel electrode PTCO faces the common electrode CTCO via the insulating layer IL5. The common electrode CTCO is connected to the common auxiliary electrode CMTL at an opening PCON. As will be described in detail later, the common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The electrical resistance of the common auxiliary electrode CMTL is lower than the electrical resistance of the common electrode CTCO. The common auxiliary electrode CMTL also functions as a light-shielding layer. For example, the common auxiliary electrode CMTL blocks light from adjacent pixels, thereby suppressing color mixing. A spacer SP is provided above the common electrode CTCO.

[0030] Spacers SP are provided for some of the pixels. For example, spacers SP may be provided for any one of blue, red, and green pixels. However, spacers SP may also be provided for all pixels. The height of the spacers SP is half the height of the cell gap. Spacers are also provided on the opposing substrate, and the spacers on the opposing substrate and the spacers SP overlap in a planar view.

[0031] In the above configuration, the gate electrode LS may be referred to as the "first gate electrode." The gate insulating layers GI2 and IL1 may be referred to as the "first gate insulating layer." The gate insulating layer GI1 may be referred to as the "second gate insulating layer." The gate electrode GL1 may be referred to as the "second gate electrode." The insulating layer IL2 may be referred to as the "first insulating layer." The insulating layer IL3 may be referred to as the "second insulating layer." The opening WCON may be referred to as the "first opening." The opening ZCON may be referred to as the "second opening." The wiring W1 and the connecting electrode WM may be referred to as the "first electrode." The connecting electrode ZTCO may be referred to as the "second electrode."

[0032] [1-3. Configuration of transistor Tr2] The transistor Tr2 includes a p-type transistor Tr2-1 and an n-type transistor Tr2-2.

[0033] Each of the p-type transistor Tr2-1 and the n-type transistor Tr2-2 has a gate electrode GL2, a gate insulating layer GI2, and a semiconductor layer S (S1 to S3). The gate electrode GL2 faces the semiconductor layer S. The gate insulating layer GI2 is provided between the semiconductor layer S and the gate electrode GL2. In this embodiment, a bottom-gate transistor in which the gate electrode GL2 is provided closer to the substrate SUB than the semiconductor layer S is exemplified, but a top-gate transistor in which the positional relationship between the semiconductor layer S and the gate electrode GL2 is reversed may also be used.

[0034] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. The semiconductor layer S1 is a semiconductor layer in a region that overlaps with the gate electrode GL2 in a planar view. The semiconductor layer S1 functions as a channel of the transistors Tr2-1 and Tr2-2. The semiconductor layer S2 functions as a conductive layer. The semiconductor layer S3 functions as a conductive layer with higher resistance than the semiconductor layer S2. The semiconductor layer S3 suppresses hot carrier degradation by attenuating hot carriers that invade toward the semiconductor layer S1.

[0035] Gate insulating layers IL1 and GI1 are provided above the semiconductor layer S. In the transistor Tr2, the gate insulating layer GI1 simply functions as an interlayer film. A wiring W2 is provided above these insulating layers. The wiring W2 is connected to the semiconductor layer S2 through an opening provided in the gate insulating layers IL1 and GI1. An insulating layer IL2 is provided above the wiring W2. A wiring W1 is provided above the insulating layer IL2. The wiring W1 is connected to the wiring W2 through an opening provided in the insulating layer IL2. An insulating layer IL3 is provided above the wiring W1. A wiring XTCO is provided above the insulating layer IL3. The wiring XTCO is connected to the wiring W1 through an opening provided in the insulating layer IL3.

[0036] The gate electrodes GL2 and LS2 are in the same layer. The wiring W2 and gate electrode GL1 are in the same layer. The term "in the same layer" means that a single layer is patterned to form a plurality of members.

[0037] [1-4. Planar layout of the display device 10] The planar layout of the pixels of the display device 10 will be described with reference to Figures 2 to 13. The pixel electrode PTCO, the common auxiliary electrode CMTL, the common electrode CTCO, and the spacer SP are omitted in Figure 2. The planar layouts of the pixel electrode PTCO, the common auxiliary electrode CMTL, and the common electrode CTCO are shown in Figures 11 to 13, respectively.

[0038] As shown in FIGS. 2 and 3, the gate electrode LS extends in the D1 direction. The shape of the gate electrode LS varies depending on the pixel. In this embodiment, a protrusion PJT protruding in the D2 direction is provided from a part of the gate electrode LS extending in the D1 direction. As shown in FIG. 5, the gate electrode LS is provided in a region including a region where the gate electrode GL1 and the oxide semiconductor layer OS overlap in a plan view. The gate electrode GL1 can also be called a "gate line."

[0039] 2, 4, and 5, the oxide semiconductor layer OS extends in the D2 direction. The gate electrode GL1 extends in the D1 direction so as to intersect with the oxide semiconductor layer OS. The pattern of the gate electrode GL1 is provided inside the pattern of the gate electrode LS. In other words, the oxide semiconductor layer OS is formed in an elongated shape (a shape having a long side) intersecting with the gate electrode GL1.

[0040] 2, 6, and 7, the opening WCON is provided near the upper end of the pattern of the oxide semiconductor layer OS in a region overlapping with the wiring W1 (W1-1, W1-2). A main portion of the pattern of the oxide semiconductor layer OS extends in the D2 direction between adjacent wirings W1 (W1-1, W1-2). The remaining portion of the pattern of the oxide semiconductor layer OS extends from the main portion toward the region of the opening WCON in a direction oblique to the D1 and D2 directions.

[0041] 2 and 7, multiple wirings W1 extend in the D2 direction. When it is necessary to distinguish adjacent wirings W1 from one another, the adjacent wirings W1 are referred to as wirings W1-1 and W1-2. In this case, it can be said that the main portion of the oxide semiconductor layer OS extends in the D2 direction between the wirings W1-1 and W1-2 and intersects with the gate electrode GL1. In other words, the oxide semiconductor layer OS is provided elongated in the D2 direction and is connected to the wiring W1-1 at one longitudinal end of the oxide semiconductor layer OS.

[0042] As shown in FIGS. 2, 8, and 9, the opening ZCON is provided near the bottom end of the pattern of the oxide semiconductor layer OS. The opening ZCON is provided in a region overlapping with the pattern of the oxide semiconductor layer OS but not overlapping with the gate electrode GL1. The opening ZCON is provided in a region overlapping with the connection electrode ZTCO. The connection electrode ZTCO overlaps with the gate electrode GL1 and the oxide semiconductor layer OS between the wiring W1-1 and the wiring W1-2. Therefore, the connection electrode ZTCO contacts the oxide semiconductor layer OS at the opening ZCON that does not overlap with the gate electrode GL1.

[0043] In other words, the oxide semiconductor layer OS is connected to the connection electrode ZTCO at the other end in the longitudinal direction of the oxide semiconductor layer OS. The connection electrode ZTCO is formed in an elongated shape extending in the D2 direction, similar to the oxide semiconductor layer OS. In the D1 direction, the width of the connection electrode ZTCO is smaller than the width of the oxide semiconductor layer OS.

[0044] 2, 7, and 8, the oxide semiconductor layer OS is in contact with the wiring W1 on the opposite side of the gate electrode GL1 from the opening ZCON. The opening ZCON does not overlap with the gate electrode LS.

[0045] As shown in Figures 2, 10, and 11, the opening PCON is provided near the upper end of the pattern of the connection electrode ZTCO. The opening PCON is provided in a region overlapping with the pattern of the gate electrode GL1 and the pattern of the connection electrode ZTCO. The opening PCON is provided in a region overlapping with the pixel electrode PTCO. The pixel electrode PTCO overlaps with the gate electrode GL1, the oxide semiconductor layer OS, and the connection electrode ZTCO between the wiring W1-1 and the wiring W1-2. Therefore, the pixel electrode PTCO contacts the connection electrode ZTCO at the opening PCON that overlaps with the gate electrode GL1.

[0046] The pixel electrode PTCO extends into the light-transmitting region described below. In other words, the pixel electrode PTCO is formed in an elongated shape extending in the D2 direction, similar to the oxide semiconductor layer OS and the wiring W1-1. In the D1 direction, the width of the pixel electrode PTCO in the portion where the opening PCON is provided is larger than the width of the oxide semiconductor layer OS.

[0047] 11, the connection electrode ZTCO is formed in an elongated shape extending along the wiring W1-1. In the direction D1, the width of the opening PCON constituting the contact region CON2 is greater than the width of the connection electrode ZTCO. In plan view, the entire connection electrode ZTCO overlaps with the pixel electrode PTCO.

[0048] As shown in FIG. 11, the pixel electrodes PTCO are arranged in the D2 direction. Of the pixels adjacent to each other in the D2 direction, one pixel may be referred to as the "first pixel" and the other pixel may be referred to as the "second pixel." For example, the first pixel is the pixel corresponding to the upper pixel electrode PTCO among the pixel electrodes PTCO arranged in the D2 direction in FIG. 11, and the second pixel is the pixel corresponding to the lower pixel electrode PTCO among the pixel electrodes PTCO arranged in the D2 direction. In this case, a pixel signal is supplied to the first pixel and the second pixel from the wiring W1-1.

[0049] The pixel electrodes PTCO are arranged in the direction D1. The pixel adjacent to the first pixel in the direction D1 is called the "third pixel," and the pixel adjacent to the second pixel in the direction D1 is called the "fourth pixel." The third pixel and the fourth pixel are adjacent to each other in the direction D2. A pixel signal is supplied to the third pixel and the fourth pixel from the wiring W1-2 adjacent to the wiring W1-1.

[0050] As described above, each of the first, second, third, and fourth pixels includes a transistor Tr1 (pixel transistor), a connection electrode ZTCO, and a pixel electrode PTCO.

[0051] The transistor Tr1 includes an oxide semiconductor layer OS, a gate electrode GL1 facing the oxide semiconductor layer OS, and a gate insulating layer GI1 between the oxide semiconductor layer OS and the gate electrode GL1. The connection electrode ZTCO overlaps with the gate electrode GL1 and the oxide semiconductor layer OS in a plan view, but is in contact with the oxide semiconductor layer OS at an opening ZCON that does not overlap with the gate electrode GL1. The pixel electrode PTCO overlaps with the gate electrode GL1, the oxide semiconductor layer OS, and the connection electrode ZTCO in a plan view, and is connected to the connection electrode ZTCO at an opening PCON that overlaps with the gate electrode GL1.

[0052] 11 overlaps with the oxide semiconductor layer OS of the first pixel and the oxide semiconductor layer OS of the second pixel provided below the first pixel in a plan view. In addition, the pixel electrode PTCO of the first pixel also overlaps with the oxide semiconductor layer OS of the fourth pixel in a plan view.

[0053] As shown in FIG. 12, the common auxiliary electrode CMTL is provided in a lattice pattern so as to surround the periphery of the pixel region. In other words, the common auxiliary electrode CMTL is provided in common to a plurality of pixels. In other words, the common auxiliary electrode CMTL has an opening OP. The opening OP is provided so as to expose the pixel electrode PTCO. The pattern of the opening OP is provided inside the pattern of the pixel electrode PTCO. The area where the opening OP is provided corresponds to the display area. In other words, the opening ZCON is included in the display area. The display area means an area where a user can see light from the pixels. For example, an area that is light-shielded by a metal layer and from which a user cannot see light is not included in the display area. In other words, the above-mentioned display area may be called a "light-transmitting area (or opening area)".

[0054] As shown in Fig. 13, the common electrode CTCO is provided in common to a plurality of pixels. A slit SL is provided in a region corresponding to the opening OP. The slit SL has a curved shape (a vertically long S-shape). The tip of the slit SL has a shape in which the width perpendicular to the extension direction of the tip becomes smaller. With reference to Figs. 1 and 13, the common electrode CTCO has a slit SL at a position opposite to the pixel electrode PTCO.

[0055] [1-5. Configuration of transistor Tr1] The configuration of the transistor Tr1 in FIG. 1 will be described in detail using FIG. 14. For convenience of explanation, the gate electrode LS is shown as a single layer in FIG. 14. The transistor Tr1 in FIG. 14 is the same as the transistor Tr1 in FIG. 1. Therefore, explanations that overlap with those in FIG. 1 will be omitted.

[0056] As shown in FIG. 14, a region where the gate electrode GL1 and the oxide semiconductor layer OS overlap in a planar view is referred to as region R1. A region where the connection electrode WM and the oxide semiconductor layer OS contact in a planar view is referred to as region R2. A region where the gate electrode LS and the oxide semiconductor layer OS overlap in a planar view is referred to as region R3. A region where the connection electrode ZTCO and the oxide semiconductor layer OS contact in a planar view is referred to as region R4. Region R1 may be referred to as the "first region." Region R2 may be referred to as the "second region." Region R3 may be referred to as the "third region." Region R4 may be referred to as the "fourth region." As shown in FIGS. 2 and 14, a direction D1 in which the gate electrode GL1 extends in a planar view may be referred to as the "first direction." A direction D2 intersecting with direction D1 may be referred to as the "second direction."

[0057] The region R1 of the oxide semiconductor layer OS may be referred to as a channel region. In this case, the regions of the oxide semiconductor layer OS other than the channel region may be referred to as a source region or a drain region. That is, in the region where the oxide semiconductor layer OS is provided, the region that overlaps with the gate electrode GL1 in a planar view is the channel region, and the region that does not overlap with the gate electrode GL1 in a planar view is the source region or the drain region. One or both of the source region and the drain region may be referred to as a "low-resistance region." The amount of impurities contained in the oxide semiconductor layer OS in the source region and the drain region is greater than the amount of impurities contained in the oxide semiconductor layer OS in the channel region. As will be described in detail later, the impurities are implanted into the oxide semiconductor layer OS by ion implantation. The amount of impurities contained in the oxide semiconductor layer OS in the source region and the drain region is 5E19 / cm 3 is less than.

[0058] To rephrase the configuration of the transistor Tr1 using the above expressions, the gate electrode GL1 overlaps with the oxide semiconductor layer OS in a first region (region R1) in a planar view. The connection electrode WM contacts with the oxide semiconductor layer OS in a second region (region R2) in a planar view. The gate electrode LS overlaps with the oxide semiconductor layer OS in a third region (region R3) in a planar view. The connection electrode ZTCO contacts with the oxide semiconductor layer OS in a fourth region (region R4) in a planar view.

[0059] The channel length of the transistor Tr1 shown in FIG. 14 is 2 μm or less. In other words, in a cross-sectional view, the width of the gate electrode GL1 in the D2 direction is 2 μm or less. Furthermore, in the D2 direction, the distance between the portion where the connection electrode WM contacts the oxide semiconductor layer OS and the channel region, and the distance between the portion where the connection electrode ZTCO contacts the oxide semiconductor layer OS and the channel region are 2 μm or less. In other words, in a cross-sectional view, the distance between the region R1 and the region R2 in the D2 direction and the distance between the region R1 and the region R4 in the D2 direction are 2 μm or less. The region R2 may be included in the source region and the region R4 may be included in the drain region, or the region R2 may be included in the drain region and the region R4 may be included in the source region. Note that an end of the connection electrode ZTCO is located at the bottom of the opening ZCON, and a portion of the oxide semiconductor layer OS is exposed from the connection electrode ZTCO at the bottom of the opening ZCON.

[0060] As described above, in the transistor Tr1, the length of the source and drain regions in the direction D2 from the channel region to the connection electrode is 2 μm or less. Therefore, even if the resistance of the oxide semiconductor layer OS in the source and drain regions is high, the resistance of the oxide semiconductor layer OS has little effect on the electrical characteristics of the transistor Tr1. Therefore, the amount of impurities (ions) implanted into the oxide semiconductor layer OS can be reduced to reduce the resistance of the oxide semiconductor layer OS in the source and drain regions. During ion implantation, oxygen vacancies are formed in the oxide semiconductor layer OS when impurities are implanted into the oxide semiconductor layer OS or when the impurities penetrate through the oxide semiconductor layer OS. Meanwhile, when impurities are implanted into the gate insulating layers GI1 and IL1 or when the impurities penetrate through the gate insulating layers GI1 and IL1, hydrogen is generated in these insulating layers. The diffusion of this hydrogen into the oxide semiconductor layer OS in the channel region causes a problem of a reduced effective channel length. A smaller amount of impurities ion-implanted reduces the amount of hydrogen generated from the gate insulating layers GI1 and IL1, thereby suppressing the intrusion of hydrogen into the oxide semiconductor layer OS in the channel region during ion implantation and the diffusion of hydrogen due to heat treatment. Therefore, even in a short-channel transistor, the occurrence of abnormal values ​​in the initial characteristics can be suppressed.

[0061] As described above, the gate electrode LS overlaps with the oxide semiconductor layer OS of the source and drain regions in the region R3. In the D2 direction, the gate electrode LS is longer than the gate electrode GL1. Therefore, in the D2 direction, the distance between the region R3 and the region R2 is shorter than the distance between the region R1 and the region R2. Similarly, in the D2 direction, the distance between the region R3 and the region R4 is shorter than the distance between the region R1 and the region R4.

[0062] The gate electrode LS is supplied with the same voltage as the gate electrode GL1. Therefore, when an on-voltage is applied to the gate electrode GL1 to switch the transistor Tr1 from an off state to an on state, the on-voltage is also applied to the gate electrode LS. As a result, carriers are generated by an electric field formed by the gate electrode LS not only in the oxide semiconductor layer OS in the channel region but also in the oxide semiconductor layers OS in the source and drain regions that overlap the gate electrode LS in a plan view.

[0063] Therefore, even if the resistance of the oxide semiconductor layer OS in the source and drain regions is high when no voltage is applied to the gate electrode GL1, the resistance of the oxide semiconductor layer OS in the regions overlapping with the gate electrode LS in plan view decreases when an on-voltage is applied to the gate electrode GL1, thereby reducing the amount of impurities ion-implanted into the oxide semiconductor layer OS.

[0064] [1-6. Short channel length transistor] The amount of excess oxygen contained in an insulating layer (high-temperature insulating layer) formed at a high temperature (e.g., 350°C) is smaller than the amount of excess oxygen contained in an insulating layer (low-temperature insulating layer) formed at a low temperature (e.g., 200°C). Therefore, the amount of oxygen released by heat treatment is smaller in a high-temperature insulating layer than in a low-temperature insulating layer. Therefore, in a top-gate transistor using an oxide semiconductor layer as the channel, if a high-temperature insulating layer is used as a passivation layer (insulating layer IL2 in Figure 1) above the gate electrode, a sufficient amount of oxygen cannot be supplied from the passivation layer to the oxide semiconductor layer. Therefore, oxygen vacancies formed in the oxide semiconductor layer OS during the manufacturing process cannot be repaired, and abnormalities in the initial characteristics are likely to occur. This abnormality in characteristics is more pronounced in transistors with a channel length of 2 μm or less.

[0065] On the other hand, high-temperature insulating layers have higher resistance to stress tests than low-temperature insulating layers. In other words, when a low-temperature insulating layer is used as the passivation layer, the threshold voltage of the transistor will shift significantly in the positive direction, for example, during a PBTS (Positive Bias Temperature Stress) test. On the other hand, when a high-temperature insulating layer is used as the passivation layer, the shift caused by the PBTS test is suppressed. Therefore, it is necessary to realize a transistor that uses a high-temperature insulating layer as the passivation layer and has a gate length of 2 μm or less, and that does not exhibit abnormalities in its initial characteristics.

[0066] [1-7. Dependence of ion implantation dose on short channel length transistors] 15 and 16 show initial characteristics when the above-described high-temperature insulating layer is used as the insulating layer IL2 of the transistor Tr1 shown in FIG. 14. The electrical characteristics shown in FIGS. 15 and 16 are electrical characteristics measured for multiple transistors Tr1 with different ion implantation doses into the oxide semiconductor layer OS. In FIGS. 15 and 16, the upper electrical characteristics are those of a transistor Tr1 with a channel length of 1.5 μm, and the lower electrical characteristics are those of a transistor Tr1 with a channel length of 2 μm.

[0067] The main process conditions in the manufacturing method of the transistor Tr1 are as follows: Oxide semiconductor layer OS thickness: 30nm Gate insulating layer GI1 thickness: 120nm Ion implantation dose: 1E13~5E15 / cm 2 Ion implantation acceleration voltage: 34 keV Insulating layer IL2 deposition temperature: 350℃ Insulating layer IL2 thickness: 400nm The deposition temperature of the insulating layer IL2 is the set temperature within the chamber in which the substrate is placed during deposition.

[0068] The measurement conditions for transistor Tr1 are as follows: The vertical axis of each electrical characteristic is the drain current value (Id [A]), and the horizontal axis is the gate voltage value (Vg [V]). In the following, L means the channel length, and W means the width of the channel region (channel width) in the direction perpendicular to the channel length (direction D1 in Figure 2). Channel area size: W / L = 3 μm / 1.5 μm or 3 μm / 2 μm Source-drain voltage: 0.05V (dotted line), 10.05V (solid line) Gate voltage: -10V~+10V Measurement environment: room temperature, dark room

[0069] As shown in FIG. 15, the ion implantation dose is 1E15 / cm 2 Under the above conditions, abnormalities in the initial characteristics occur. The abnormalities in the characteristics are more pronounced under the condition of L=1.5 μm than under the condition of L=2 μm. In this embodiment, impurity ions are implanted into the oxide semiconductor layer OS using the gate electrode GL1 as a mask, as will be described in detail later. When the ion implantation dose is large, hydrogen generated during the ion implantation finds its way under the gate electrode GL1, or hydrogen diffuses under the gate electrode GL1 due to heat treatment after the ion implantation, thereby reducing the effective channel length. The greater the ion implantation dose, the shorter the effective channel length. Therefore, it is believed that the abnormalities in the characteristics are more pronounced under the condition of L=1.5 μm than under the condition of L=2 μm.

[0070] On the other hand, as shown in FIG. 16, the ion implantation dose was 5E14 / cm 2 under both the conditions of L=2 μm and L=1.5 μm. 2 Under the following conditions, no abnormalities in the initial characteristics occur: 2 Under the following conditions, the phenomenon in which hydrogen generated by ion implantation flows around to below the gate electrode GL1 and the phenomenon in which hydrogen diffuses below the gate electrode GL1 due to heat treatment after ion implantation are suppressed.

[0071] The smaller the amount of impurities implanted by ion implantation, the higher the electrical resistance of the oxide semiconductor layer OS in the source and drain regions. If the electrical resistance is high, the amount of current flowing through the transistor Tr1 is limited by the electrical resistance of the oxide semiconductor layer OS in the source and drain regions. As a result, a problem may occur in the initial characteristics, in which the on-current plateaus (the on-current is saturated).

[0072] However, in the results shown in FIG. 16, the on-current does not peak out in the initial characteristics of the transistor Tr1. One of the reasons for this is thought to be that in the transistor Tr1, the distance from the connection electrodes (connection electrode WM and connection electrode ZTCO) in contact with the oxide semiconductor layer OS to the channel region is 2 μm or less. Furthermore, because the gate electrode LS overlaps the oxide semiconductor layer OS in the source and drain regions in a planar view, when an on-voltage is applied to the gate electrode LS, carriers are generated in the oxide semiconductor layer OS overlapping the gate electrode LS due to an electric field formed by the gate electrode LS. Therefore, the electrical resistance of the oxide semiconductor layer OS overlapping the gate electrode LS in a planar view is reduced, which is thought to be why the on-current did not peak out as described above.

[0073] [1-8. Manufacturing method of transistor Tr1] A method for manufacturing the transistor Tr1 according to this embodiment will be described with reference to Figures 14 and 17. Figure 17 is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0074] As shown in FIGS. 14 and 17, first, a gate electrode LS is formed on a substrate SUB (step S1001; LS formation). Gate insulating layers GI2 and IL1 are formed on the gate electrode LS (step S1002; GI formation), and an oxide semiconductor layer OS is formed on the entire surface thereof (step S1003; OS formation). A pattern of the oxide semiconductor layer OS is formed by photolithography and etching processes on the oxide semiconductor layer OS (step S1004; OS pattern formation). A heat treatment is performed on the patterned oxide semiconductor layer OS (step S1005; OS annealing). This OS annealing crystallizes the oxide semiconductor layer OS. However, the oxide semiconductor layer OS does not necessarily have to be crystallized by the OS annealing.

[0075] Next, a gate insulating layer GI1 is formed on the oxide semiconductor layer OS (step S1006; GI formation). With the gate insulating layer GI1 formed on the entire surface, oxidation annealing is performed on the oxide semiconductor layer OS (step S1007; oxidation annealing). During the process from when the oxide semiconductor layer OS is formed to when the gate insulating layer GI1 is formed on the oxide semiconductor layer OS, many oxygen vacancies are generated on the top and side surfaces of the oxide semiconductor layer OS. Due to the oxidation annealing, oxygen released from, for example, the gate insulating layer IL1 is supplied to the oxide semiconductor layer OS, and the oxygen vacancies are repaired.

[0076] Next, a conductive layer is formed on the gate insulating layer GI1. The conductive layer is formed on the entire surface. A gate electrode GL1 extending in the D1 direction is formed by a photolithography process and an etching process on the conductive layer (step S1008: GL formation). With the gate electrode GL1 formed, impurity ions are implanted into the source region and drain region (regions corresponding to OS2 in FIG. 1) of the oxide semiconductor layer OS (step S1009: impurity implantation).

[0077] Specifically, in step S1009, impurities are implanted into the oxide semiconductor layer OS from the gate electrode GL1 side through the gate insulating layer GI1 by ion implantation. The implantation dose of the impurities by ion implantation is 5E14 / cm 2 2 The following is an example of the ion implantation. For example, at least one element selected from argon (Ar), phosphorus (P), and boron (B) is implanted as an impurity into the oxide semiconductor layer OS. In addition to the above elements, other impurities include hydrogen (H), helium (He), lithium (Li), beryllium (Be), carbon (C), nitrogen (N), neon (Ne), sodium (Na), magnesium (Mg), aluminum (Al), silicon (Si), sulfur (S), potassium (K), calcium (Ca), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), and germanium (Ge). At least one element selected from the group consisting of arsenic (As), selenium (Se), krypton (Kr), xenon (Xe), strontium (Sr), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), silver (Ag), tin (Sn), antimony (Sb), tellurium (Te), cesium (Cs), barium (Ba), hafnium (Hf), tantalum (Ta), tungsten (W), gold (Au), and bismuth (Bi) may be implanted as an impurity into the oxide semiconductor layer OS. Oxygen vacancies are formed in the oxide semiconductor layer OS by the ion implantation, and the oxygen vacancies are bonded with hydrogen by subsequent heat treatment, thereby reducing the resistance of the oxide semiconductor layer OS. Because a gate electrode GL1 is provided above the oxide semiconductor layer OS that functions as a channel region of the transistor Tr1, impurities are not implanted into the oxide semiconductor layer OS in the channel region.

[0078] Next, an insulating layer IL2 is formed on the gate electrode GL1 (step S1010; IL formation). Next, an opening WCON is formed in the insulating layer IL2 and the gate insulating layer GI1 (step S1011; contact opening). A part of the oxide semiconductor layer OS is exposed through the opening WCON formed by the contact opening. A conductive layer is formed on the insulating layer IL2 and inside the contact (step S1012; conductive layer formation).

[0079] Next, a mask is formed in the region where the wiring W1 is to be provided, and the conductive layer formed on the entire surface is etched through the mask (step S1013: conductive layer etching). Following the above steps, steps similar to S1010 to S1013 are repeated to form the insulating layer IL3, the opening ZCON in the insulating layer IL3, and the connection electrode ZTCO, thereby completing the structure shown in FIG.

[0080] [1-9. Materials of each component of the display device 10] The substrate SUB can be a rigid substrate that is light-transmitting and not flexible, such as a glass substrate, a quartz substrate, or a sapphire substrate. On the other hand, if the substrate SUB needs to be flexible, a flexible substrate that contains resin and has flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used as the substrate SUB. Impurities may be introduced into the resin to improve the heat resistance of the substrate SUB.

[0081] Common metal materials can be used for the gate electrodes LS, GL1, and GL2, the wirings W1 and W2, and the common auxiliary electrode CMTL. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), and silver (Ag), or alloys or compounds thereof, can be used for the electrodes. The above materials can be used as single layers or as multilayers for the electrodes.

[0082] For example, a laminated structure of Ti / Al / Ti is used as the gate electrode GL1. In this embodiment, the cross-sectional shape of the pattern end of the gate electrode GL1 having the above-mentioned laminated structure is a forward tapered shape.

[0083] The gate insulating layers GI1, GI2, IL1 and the insulating layers IL2 to IL5 can be made of a general insulating material. For example, the gate insulating layers GI1, GI2, IL1 and the insulating layers IL2, IL3, IL5 can be made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x ) or other inorganic insulating layers can be used. These insulating layers can be insulating layers with few defects. The insulating layer IL4 can be made of an organic insulating material such as a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluororesin, or a siloxane resin. The gate insulating layers GI1, GI2, and IL1 and the insulating layers IL2, IL3, and IL5 can be made of the organic insulating materials described above. The materials described above can be used as components such as the insulating layers in a single layer or in a laminated structure.

[0084] As an example of the insulating layer, a 120 nm thick SiO x The gate insulating layer IL1 is made of SiO 2 having a total thickness of 300 nm to 700 nm. x / SiN x / SiO x The gate insulating layer GI2 is made of SiO 2 with a total thickness of 60 to 150 nm. x / SiN xThe insulating layer IL2 is made of SiO 2 with a total thickness of 300 nm to 500 nm. x The insulating layer IL3 is made of SiO 2 having a total thickness of 200 nm to 500 nm. x (single layer), SiN x The insulating layer IL4 is an organic layer having a thickness of 2 μm to 4 μm. The insulating layer IL5 is a SiN layer having a thickness of 50 nm to 150 nm. x (single layer) is used.

[0085] The above SiO x N y and AlO x N y is a silicon and aluminum compound containing a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).

[0086] The oxide semiconductor layer OS may be formed using a metal oxide having semiconductor properties. For example, the oxide semiconductor layer OS may be formed using an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). For example, the oxide semiconductor layer OS may be formed using an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and an oxide semiconductor having a different composition may be used. For example, an oxide semiconductor layer having a higher In ratio than the above may be used to improve mobility. On the other hand, an oxide semiconductor layer having a higher Ga ratio than the above may be used to increase the band gap and reduce the influence of light irradiation.

[0087] For example, an oxide semiconductor containing two or more metals including indium (In) may be used as the oxide semiconductor layer OS having a higher In ratio than the above. In this case, the ratio of indium to all metal elements in the oxide semiconductor layer OS may be 50% or more in atomic ratio. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanoid may be used as the oxide semiconductor layer OS. Elements other than those mentioned above may also be used as the oxide semiconductor layer OS.

[0088] The oxide semiconductor layer OS may be formed by adding other elements to an oxide semiconductor containing In, Ga, Zn, and O. For example, a metal element such as Al or Sn may be added to the oxide semiconductor. In addition to the above oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn, and Zn (ITZO), an oxide semiconductor containing In and W, or the like may be used as the oxide semiconductor layer OS.

[0089] When the ratio of indium element in the oxide semiconductor layer OS is high, the oxide semiconductor layer OS is likely to crystallize. As described above, by using a material in which the ratio of indium element to all metal elements is 50% or more for the oxide semiconductor layer OS, the oxide semiconductor layer OS can have a polycrystalline structure. It is preferable that the oxide semiconductor layer OS contains gallium as a metal element other than indium. Gallium belongs to the same group 13 as indium. Therefore, the crystallinity of the oxide semiconductor layer OS is not impaired by gallium, and the oxide semiconductor layer OS has a polycrystalline structure.

[0090] Although a detailed manufacturing method of the oxide semiconductor layer OS will be described later, the oxide semiconductor layer OS can be formed by a sputtering method. The composition of the oxide semiconductor layer OS formed by a sputtering method depends on the composition of the sputtering target. Even when the oxide semiconductor layer OS has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer OS are substantially the same. In this case, the composition of the metal elements in the oxide semiconductor layer OS can be determined based on the composition of the metal elements in the sputtering target.

[0091] When the oxide semiconductor layer OS has a polycrystalline structure, the composition of the oxide semiconductor layer may be determined by X-ray diffraction (XRD). Specifically, the composition of the metal elements in the oxide semiconductor layer can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by XRD. Furthermore, the composition of the metal elements in the oxide semiconductor layer OS can also be determined by X-ray fluorescence analysis or electron probe microanalyzer (EPMA) analysis. However, this is not limited to this because the oxygen element contained in the oxide semiconductor layer OS changes depending on the sputtering process conditions, etc.

[0092] As described above, the oxide semiconductor layer OS has a polycrystalline structure. An oxide semiconductor having a polycrystalline structure can be manufactured using a polycrystalline oxide semiconductor (Poly-OS) technique. Hereinafter, an oxide semiconductor having a polycrystalline structure may be referred to as a Poly-OS to distinguish it from an oxide semiconductor having an amorphous structure.

[0093] As described above, the connection electrode ZTCO, the wiring XTCO, the pixel electrode PTCO, and the common electrode CTCO are made of transparent conductive layers. The transparent conductive layers may be made of ITO and a mixture of indium oxide and zinc oxide (IZO). Materials other than those mentioned above may also be used for the transparent conductive layers.

[0094] As described above, when a metal oxide layer is provided between the oxide semiconductor layer OS and the gate insulating layer IL1, a metal oxide containing aluminum as a main component is used as the metal oxide layer. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x ) is used. "A metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0095] As described above, according to the configuration of the transistor Tr1 and the manufacturing method thereof of this embodiment, in the transistor Tr1 in which a high-temperature insulating layer having high resistance to stress tests is used as the insulating layer IL2, it is possible to realize a transistor Tr1 that exhibits good initial characteristics even when the channel length is 2 μm or less.

[0096] Furthermore, in the transistor Tr1 according to this embodiment, electrical continuity between the oxide semiconductor layer OS including a polycrystalline structure and the connection electrode ZTCO, which is a transparent conductive layer, can be ensured by directly contacting them. Therefore, there is no need to provide a metal layer between the oxide semiconductor layer OS and the connection electrode ZTCO. Furthermore, in the transistor Tr1 according to this embodiment, the contact resistance between the oxide semiconductor layer OS and the connection electrode ZTCO can be reduced. Therefore, the process margin can be increased without degrading the electrical characteristics of the transistor Tr1.

[0097] With the above configuration, light is not blocked at the opening ZCON, thereby suppressing a decrease in aperture ratio. The oxide semiconductor layer is light-transmitting. Therefore, in this embodiment, although an oxide semiconductor layer is provided in the opening region of the pixel region, light from the backlight passes through the oxide semiconductor layer. Therefore, a decrease in transmittance of the opening region due to the oxide semiconductor layer being provided in the opening region is suppressed. Because the oxide semiconductor layer OS is light-transmitting, it is less likely to cause unevenness in transmitted light, unlike a silicon layer. By providing the oxide semiconductor layer OS in the display region, the occurrence of display unevenness can be suppressed.

[0098] [1-10. Variations] A modification of the first embodiment will be described with reference to Figures 18 and 19. Figures 18 and 19 are both cross-sectional views showing the structure of a semiconductor device according to a modification of one embodiment of the present invention. Figures 18 and 19 are both views corresponding to Figure 14. The cross-sectional structures shown in Figures 18 and 19 are similar to the cross-sectional structure shown in Figure 14, but the length of the gate electrode LS in the D2 direction is different between Figures 14, 18, and 19.

[0099] 18, the length of the gate electrode LS in the direction D2 is approximately the same as the length of the gate electrode GL1. That is, in the direction D2, the distance between the region R3 and the region R2 is approximately the same as the distance between the region R1 and the region R2. Similarly, in the direction D2, the distance between the region R3 and the region R4 is approximately the same as the distance between the region R1 and the region R4.

[0100] In this way, even when the gate electrode LS does not overlap the source region and the drain region in plan view, the distance from the connection electrodes (connection electrode WM and connection electrode ZTCO) in contact with the oxide semiconductor layer OS to the channel region is 2 μm or less, so that the amount of impurities injected into the oxide semiconductor layer OS is 5E14 / cm 2 Even if the temperature is less than 1000°C, good initial characteristics can be obtained.

[0101] 19, the gate electrode LS is provided in the direction D2 up to a region that reaches the openings WCON and ZCON. In other words, in plan view, the region R3 overlaps with the region R2. Similarly, in plan view, the region R3 overlaps with the region R4. In other words, when an on-voltage is applied to the gate electrode LS, carriers due to the electric field formed by the gate electrode LS are generated in the oxide semiconductor layer OS between the channel region and the connecting electrodes (the connecting electrodes WM and ZTCO). Therefore, even if the amount of impurities implanted into the source region and the drain region is smaller than that described above, good initial characteristics can be obtained.

[0102] [2. Second Embodiment] The overall configuration of the display device described in the first embodiment will be described with reference to FIGS.

[0103] [2-1. Overview of the display device 20] FIG. 20 is a plan view showing an outline of a display device according to one embodiment of the present invention. As shown in FIG. 20, the display device 20 includes an array substrate 300, a seal portion 400, a counter substrate 500, a flexible printed circuit board 600 (FPC 600), and an IC chip 700. The array substrate 300 and the counter substrate 500 are bonded together by the seal portion 400. A plurality of pixel circuits 310 are arranged in a matrix in a liquid crystal region 22 surrounded by the seal portion 400. The liquid crystal region 22 is an area that overlaps with a liquid crystal element 410 (described later) in a planar view. The liquid crystal region 22 is an area that contributes to display. The liquid crystal region 22 may also be referred to as a "display region." The above-mentioned transistor Tr1 is provided in the liquid crystal region 22 (display region).

[0104] The sealing region 24, in which the sealing portion 400 is provided, is the region surrounding the liquid crystal region 22. The FPC 600 is provided in the terminal region 26. The terminal region 26 is the region where the array substrate 300 is exposed from the counter substrate 500, and is provided outside the sealing region 24. Note that the outside of the sealing region 24 means the outside of the region where the sealing portion 400 is provided and the region surrounded by the sealing portion 400. The IC chip 700 is provided on the FPC 600. The IC chip 700 supplies signals to drive each pixel circuit 310. The sealing region 24 or the region combining the sealing region 24 and the terminal region 26 is the region surrounding the liquid crystal region 22 (display region). These regions may be referred to as the "frame region." The above-mentioned transistor Tr2 is provided in the frame region.

[0105] [2-2. Circuit configuration of display device 20] Fig. 21 is a block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. As shown in Fig. 21, a source driver circuit 320 is provided adjacent to the liquid crystal region 22 in which the pixel circuits 310 are arranged in the direction D2 (column direction), and a gate driver circuit 330 is provided adjacent to the liquid crystal region 22 in the direction D1 (row direction). The source driver circuit 320 and the gate driver circuit 330 are provided in the sealing region 24. However, the region in which the source driver circuit 320 and the gate driver circuit 330 are provided is not limited to the sealing region 24, and may be any region outside the region in which the pixel circuits 310 are provided.

[0106] A source line 321 extends from the source driver circuit 320 in the direction D2 and is connected to a plurality of pixel circuits 310 arranged in the direction D2. A gate line 331 extends from the gate driver circuit 330 in the direction D1 and is connected to a plurality of pixel circuits 310 arranged in the direction D1. The source line 321 corresponds to the line W1 in FIG. 2. The gate line 331 corresponds to the gate electrode GL1 in FIG. 2.

[0107] A terminal portion 333 is provided in the terminal region 26. The terminal portion 333 and the source driver circuit 320 are connected by a connection wiring 341. Similarly, the terminal portion 333 and the gate driver circuit 330 are connected by a connection wiring 341. When the FPC 600 is connected to the terminal portion 333, the external device to which the FPC 600 is connected is connected to the display device 20, and each pixel circuit 310 provided in the display device 20 is driven by a signal from the external device.

[0108] The transistor Tr1 shown in the first embodiment is used in the pixel circuit 310. The transistor Tr2 shown in the first embodiment is applied to transistors included in the source driver circuit 320 and the gate driver circuit 330.

[0109] 2-3. Pixel circuit 310 of display device 20 FIG. 22 is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention. As shown in FIG. 22, the pixel circuit 310 includes elements such as a transistor 800, a storage capacitor 890, and a liquid crystal element 410. One electrode of the storage capacitor 890 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. Similarly, one electrode of the liquid crystal element 410 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. The transistor 800 has a first gate electrode 810, a first source electrode 830, and a first drain electrode 840. The first gate electrode 810 is connected to a gate wiring 331. The first source electrode 830 is connected to a source wiring 321. The first drain electrode 840 is connected to the storage capacitor 890 and the liquid crystal element 410. The transistor Tr1 shown in the first embodiment is applied to the transistor 800 shown in FIG. 22. In this embodiment, for convenience of explanation, 830 is referred to as a source electrode and 840 as a drain electrode, but the source and drain functions of these electrodes may be interchanged.

[0110] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies the design, or adds or omits processes or modifies conditions based on the semiconductor device of each embodiment, such combinations are included in the scope of the present invention as long as they include the gist of the present invention.

[0111] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0112] 10, 20: display device, 22: liquid crystal region, 24: sealing region, 26: terminal region, 300: array substrate, 310: pixel circuit, 320: source driver circuit, 321: source wiring, 330: gate driver circuit, 331: gate wiring, 333: terminal section, 341: connection wiring, 400: sealing section, 410: liquid crystal element, 500: opposing substrate, 600: flexible printed circuit board (FPC), 700: IC chip, 800: transistor, 810: first gate electrode, 830: first source electrode, 840: first drain electrode, 890: storage capacitor, CMTL: common auxiliary electrode, CON1, CON2: contact region, CTCO: common electrode, GI1, GI2, IL1: gate insulating layer, GL1, GL2: gate electrode, IL2 to IL5: insulating layer, LS: gate electrode, OP: opening, OS: oxide semiconductor layer, PCON: opening, PJT: protrusion, PTCO: pixel electrode, R1 to R4: region, S: semiconductor layer, SL: slit, SP: spacer, SUB: substrate, Tr1, Tr2: transistor, W1, W2: wiring, WCON, XCON, ZCON: opening, WM: connecting electrode, XTCO: wiring, ZTCO: connecting electrode

Claims

1. a first gate electrode; a first gate insulating layer above the first gate electrode; an oxide semiconductor layer above the first gate insulating layer; a second gate insulating layer above the oxide semiconductor layer, the second gate insulating layer having a first opening and a second opening that reach the oxide semiconductor layer; a second gate electrode extending in a first direction above the second gate insulating layer; a first electrode in contact with the oxide semiconductor layer in the first opening; a second electrode in contact with the oxide semiconductor layer in the second opening; the second gate electrode overlaps with the oxide semiconductor layer in a first region in a plan view; the first electrode is in contact with the oxide semiconductor layer in a second region in a plan view; In a cross-sectional view, the width of the second gate electrode in a second direction intersecting the first direction is 2 μm or less; In a cross-sectional view, the distance between the first region and the second region in the second direction is 2 μm or less.

2. the first gate electrode overlaps with the oxide semiconductor layer in a third region in a plan view; 2. The semiconductor device according to claim 1, wherein, in a cross-sectional view, a distance between the third region and the second region in the second direction is smaller than a distance between the first region and the second region in the second direction.

3. the second electrode is in contact with the oxide semiconductor layer in a fourth region in a plan view; In a cross-sectional view, the distance between the first region and the fourth region in the second direction is 2 μm or less, In a cross-sectional view, a distance between the third region and the fourth region in the second direction is smaller than a distance between the first region and the fourth region in the second direction; the first electrode is a metal layer; The semiconductor device according to claim 2 , wherein the second electrode is a transparent conductive layer.

4. a first insulating layer above the second gate electrode; a second insulating layer above the first insulating layer, the first opening is provided in the second gate insulating layer and the first insulating layer; the second opening is provided in the second gate insulating layer, the first insulating layer, and the second insulating layer; the first electrode is provided between the first insulating layer and the second insulating layer, The semiconductor device according to claim 3 , wherein the second electrode is provided above the second insulating layer.

5. the first gate electrode overlaps with the oxide semiconductor layer in a third region in a plan view; The semiconductor device according to claim 1 , wherein a portion of said third region overlaps with said second region in a plan view.

6. the second electrode is in contact with the oxide semiconductor layer in a fourth region in a plan view; In a cross-sectional view, the distance between the first region and the fourth region in the second direction is 2 μm or less, In a plan view, a part of the third region overlaps with the fourth region, the first electrode is a metal layer; The semiconductor device according to claim 5 , wherein the second electrode is a transparent conductive layer.

7. a first insulating layer above the second gate electrode; a second insulating layer above the first insulating layer, the first opening is provided in the second gate insulating layer and the first insulating layer; the second opening is provided in the second gate insulating layer, the first insulating layer, and the second insulating layer; the first electrode is provided between the first insulating layer and the second insulating layer, The semiconductor device according to claim 6 , wherein the second electrode is provided above the second insulating layer.

8. The oxide semiconductor layer is a channel region overlapping the second gate electrode in a plan view; a low resistance region that does not overlap with the second gate electrode in a plan view, an amount of impurities contained in the oxide semiconductor layer in the low resistance region is greater than an amount of impurities contained in the channel region; The amount of impurities contained in the oxide semiconductor layer in the low resistance region is greater than the amount of impurities contained in the oxide semiconductor layer in the channel region, and is 5E19 / cm ３ The semiconductor device according to claim 1 , wherein the thickness is less than 100 μm.

9. forming a first gate electrode above the substrate; forming a first gate insulating layer above the first gate electrode; forming an oxide semiconductor layer above the first gate insulating layer; forming a second gate insulating layer above the oxide semiconductor layer; forming a second gate electrode extending in a first direction above the second gate insulating layer; impurities are implanted into the oxide semiconductor layer from above the second gate electrode through the second gate insulating layer; forming a first opening and a second opening in the second gate insulating layer, the first opening and the second opening reaching the oxide semiconductor layer; a first electrode in contact with the oxide semiconductor layer in the first opening, and a second electrode in contact with the oxide semiconductor layer in the second opening, In a cross-sectional view, the width of the second gate electrode in a second direction intersecting the first direction is 2 μm or less; In a cross-sectional view, the distance between the first region and the second region in the second direction is 2 μm or less.

10. The dose of the impurity is 5E14 / cm ２ 10. The method for manufacturing a semiconductor device according to claim 9, wherein:

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