Semiconductor device and method for manufacturing the same

Abstract

To realize a semiconductor device that does not adversely affect circuit operation even in a fine pixel circuit.SOLUTION: The semiconductor device includes: a semiconductor layer; a gate electrode facing the semiconductor layer and having a first stepped part; a gate insulating layer between the semiconductor layer and the gate electrode; a first insulating layer on the gate electrode; a conductive layer patterned on the first insulating layer; and a sacrificial layer interposed between the conductive layer and the first insulating layer, the sacrificial layer being made of a material different from that of the first insulating layer. In a region where the conductive layer does not overlap in plan view, the first insulating layer is exposed from the sacrificial layer and the conductive layer.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Recently, development of transistors using oxide semiconductors for the channel instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been progressing (for example, Patent Documents 1 and 2). Transistors using oxide semiconductors for the channel have a simple structure and are formed by a low-temperature process, similar to transistors using amorphous silicon for the channel. Transistors using oxide semiconductors for the channel are known to have higher mobility and a very low off-current than transistors using amorphous silicon for the channel.

[0003] In recent years, pixel sizes of display devices have been reduced. Along with this reduction in pixel size, reductions in wiring width and transistor size have been considered. However, there are limits to these reductions, and the aperture ratio is reduced due to the arrangement of metal layers and semiconductor layers that constitute pixel circuits. Therefore, development is underway to use transistors in pixel circuits that use oxide semiconductor layers as channels, which can provide sufficient characteristics for driving pixel circuits even with small transistor sizes. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-146819 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-159315 Summary of the Invention [Problem to be solved by the invention]

[0005] As transistor sizes are reduced, abnormalities in the transistor structure may occur due to the influence of the transistor manufacturing process. In particular, when an inorganic insulating layer is provided on a structure with a step, the surface of the inorganic insulating layer will have a step shape that reflects the step shape of the structure. When a conductive layer pattern is formed on such an inorganic insulating layer, etching residues of the conductive layer may occur in the step portions of the inorganic insulating layer. As pixel circuits are reduced in size and the distance between adjacent structures becomes smaller, even small amounts of etching residue may cause problems such as short circuits between wiring.

[0006] An object of one embodiment of the present invention is to realize a semiconductor device that does not adversely affect circuit operation even when the pixel circuit is minute. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention includes a semiconductor layer, a gate electrode facing the semiconductor layer and having a first step portion, a gate insulating layer between the semiconductor layer and the gate electrode, a first insulating layer on the gate electrode, a patterned conductive layer on the first insulating layer, a sacrificial layer between the conductive layer and the first insulating layer and made of a material different from that of the first insulating layer, and the first insulating layer is exposed from the sacrificial layer and the conductive layer in an area where it does not overlap with the conductive layer in a planar view.

[0008] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming a semiconductor layer on a substrate, forming a gate insulating layer on the semiconductor layer, forming a gate electrode having a first step portion on the gate insulating layer, forming a first insulating layer on the gate electrode, forming a sacrificial layer made of a material different from that of the first insulating layer on the first insulating layer, depositing a conductive layer on the sacrificial layer, and etching at least a portion of the conductive layer and the sacrificial layer via a mask to form a pattern of the conductive layer. [Brief explanation of the drawings]

[0009] [Figure 1]1 is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. [Figure 2] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 3] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 4] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 5] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 6] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 7] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 8] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 9] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 10] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 11] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 12] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 13] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 14] FIG. 10 is a cross-sectional view showing etching residues generated in a semiconductor device according to a comparative example. [Figure 15] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16]1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 19] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. [Figure 20] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 21] 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 22] 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily arrive at by appropriately modifying the configuration of the embodiments while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part more schematically than the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, configurations similar to those described above with respect to the previous drawings are designated by the same reference numeral followed by an alphabet, and detailed description may be omitted as appropriate.

[0011] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downper." For convenience of explanation, the terms "up" and "downper" are used in the following description. However, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be different from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When a pixel electrode is referred to as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is referred to as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0012] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, although the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer as an example of a display device, the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0013] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0015] [1. First embodiment] [1-1. Configuration of display device 10] The configuration of a display device 10 according to one embodiment of the present invention will be described with reference to Figs. 1 to 13. Fig. 1 is a cross-sectional view showing an overview of a display device according to one embodiment of the present invention. Fig. 2 is a plan view showing an overview of a display device according to one embodiment of the present invention. Figs. 3 to 13 are plan views illustrating the layout of each layer in a display device according to one embodiment of the present invention. The cross-sectional view of Fig. 1 is a cross-sectional view for explaining the layer structure of the display device 10, and may not strictly match the plan view of Fig. 2.

[0016] As shown in FIG. 1, the display device 10 is provided above a substrate SUB. The display device 10 has a transistor Tr1, a transistor Tr2, a wiring W, a pixel electrode PTCO, a common auxiliary electrode CMTL, and a common electrode CTCO. TCO is an abbreviation for Transparent Conductive Oxide. The transistor Tr1 is a semiconductor device included in a pixel circuit of the display device 10. The transistor Tr2 is a semiconductor device included in a peripheral circuit. As will be described in detail later, the peripheral circuit is a circuit that drives the pixel circuit. In the following description, the "semiconductor device" may include only the configuration of the transistor Tr1, or may include the configurations of both the transistors Tr1 and Tr2.

[0017] [1-2. Configuration of transistor Tr1] The transistor Tr1 has an oxide semiconductor layer OS (OS1, OS2), a gate insulating layer GI1, a gate electrode GL1, a connection electrode ZTCO, and a wiring XTCO. The gate electrode GL1 faces the oxide semiconductor layer OS. The gate insulating layer GI1 is provided between the oxide semiconductor layer OS and the gate electrode GL1. In this embodiment, a top-gate transistor in which the oxide semiconductor layer OS is provided closer to the substrate SUB than the gate electrode GL1 is exemplified, but a bottom-gate transistor in which the positional relationship between the gate electrode GL1 and the oxide semiconductor layer OS is reversed may also be used.

[0018] The oxide semiconductor layer OS has a polycrystalline structure. The oxide semiconductor layer OS includes oxide semiconductor layers OS1 and OS2. The oxide semiconductor layer OS1 is an oxide semiconductor layer in a region overlapping with the gate electrode GL1 in a planar view. The oxide semiconductor layer OS1 functions as a semiconductor layer and is switched between a conductive state and a non-conductive state depending on the voltage supplied to the gate electrode GL1. In other words, the oxide semiconductor layer OS1 functions as a channel of the transistor Tr1. The oxide semiconductor layer OS2 functions as a conductive layer. The oxide semiconductor layers OS1 and OS2 are layers formed from the same oxide semiconductor layer. For example, the oxide semiconductor layer OS2 is an oxide semiconductor layer whose resistance is reduced by implanting impurities into a layer having the same physical properties as the oxide semiconductor layer OS1.

[0019] An insulating layer IL2 is provided above the gate electrode GL1. A wiring W1 is provided above the insulating layer IL2. The wiring W1 is connected to the oxide semiconductor layer OS2 via an opening WCON provided in the insulating layer IL2 and the gate insulating layer GI1. The wiring W1 is a metal layer. A data signal related to the gradation of the pixel is transmitted to the wiring W1. An insulating layer IL3 is provided above the insulating layer IL2 and the wiring W1. The connection electrode ZTCO and the wiring XTCO are in contact with the upper surface of the insulating layer IL3 above the insulating layer IL3. In other words, the insulating layer IL3 is in contact with the lower surfaces of the connection electrode ZTCO and the wiring XTCO below the connection electrode ZTCO and the wiring XTCO.

[0020] The connection electrode ZTCO is connected to the oxide semiconductor layer OS2 through an opening ZCON provided in the insulating layers IL3 and IL2 and the gate insulating layer GI1. The connection electrode ZTCO is in contact with the oxide semiconductor layer OS2 at the bottom of the opening ZCON. The wiring XTCO is connected to the wiring W1 through an opening XCON provided in the insulating layer IL3. The connection electrode ZTCO and wiring XTCO are transparent conductive layers. As described above, the gate electrode GL1, the connection electrode ZTCO, and the wiring XTCO are provided above the oxide semiconductor layer OS.

[0021] The wiring XTCO is provided in the same layer as the connection electrode ZTCO and is separated from the connection electrode ZTCO. The material of the connection electrode ZTCO is the same as that of the wiring XTCO, but the crystallinity of a portion of the connection electrode ZTCO differs from that of the wiring XTCO. For example, even if the connection electrode ZTCO and the wiring XTCO are both ITO formed using the same process, the crystallinity of a portion of the ITO used as the connection electrode ZTCO differs from that of the ITO used as the wiring XTCO. Different crystallinity includes different crystal structures, as well as different parameters such as lattice constants even if the crystal structure is the same. When transparent conductive layers with different crystallinity are observed with an optical microscope, they have different colors. In other words, the refractive indices of these transparent conductive layers are different.

[0022] The insulating layer IL2 may be referred to as a “first insulating layer.” The insulating layer IL3 may be referred to as a “sacrificial layer.” As described above, the insulating layer IL2 is provided above the oxide semiconductor layer OS and the gate electrode GL1.

[0023] The connection electrode ZTCO is divided into a first region and a second region in a plan view. The first region includes a region where the connection electrode ZTCO is in contact with the oxide semiconductor layer OS. The second region is a region other than the first region. The crystallinity of the connection electrode ZTCO in the first region is different from the crystallinity of the connection electrode ZTCO in the second region.

[0024] For example, when a transparent conductive layer such as an ITO layer is formed in contact with a semiconductor layer such as a silicon layer, the surface of the semiconductor layer is oxidized by the process gas and oxygen ions used during ITO film formation. Because the oxide layer formed on the surface of the semiconductor layer has high resistance, the contact resistance between the semiconductor layer and the transparent conductive layer increases. As a result, poor electrical contact occurs between the semiconductor layer and the transparent conductive layer.

[0025] On the other hand, when the connection electrode ZTCO is formed so as to be in contact with the oxide semiconductor layer OS including a polycrystalline structure, the above-described high-resistance oxide layer is not formed on the surface of the oxide semiconductor layer OS.

[0026] The reason for the above is presumed to be as follows. When the connection electrode ZTCO is formed in contact with the oxide semiconductor layer OS as described above, the connection electrode ZTCO formed above the oxide semiconductor layer OS crystallizes immediately after deposition, reflecting the crystalline structure of the oxide semiconductor layer OS. For example, when the connection electrode ZTCO is formed under certain deposition conditions, the connection electrode ZTCO formed in a portion other than the oxide semiconductor layer OS does not crystallize, but the connection electrode ZTCO formed in a region in contact with the oxide semiconductor layer OS crystallizes. In this way, it is thought that the crystallization of the connection electrode ZTCO during deposition reduces the oxide semiconductor layer OS in a region of the surface of the oxide semiconductor layer OS that is in contact with the connection electrode ZTCO. As a result, it is thought that the carrier concentration on the surface of the oxide semiconductor layer OS increases, reducing the contact resistance between the oxide semiconductor layer OS and the connection electrode ZTCO.

[0027] An insulating layer IL4 is provided above the connection electrode ZTCO. The insulating layer IL4 reduces steps formed by structures provided below the insulating layer IL4. The insulating layer IL4 is sometimes called a planarizing film. A pixel electrode PTCO is provided above the insulating layer IL4. The pixel electrode PTCO is connected to the connection electrode ZTCO through an opening PCON provided in the insulating layer IL4. The region where the connection electrode ZTCO and the pixel electrode PTCO contact is called a contact region CON2. In a plan view, the contact region CON2 overlaps with the gate electrode GL1. The pixel electrode PTCO is a transparent conductive layer.

[0028] An insulating layer IL5 is provided above the pixel electrode PTCO. A common auxiliary electrode CMTL and a common electrode CTCO are provided above the insulating layer IL5. That is, the pixel electrode PTCO faces the common electrode CTCO via the insulating layer IL5. The common electrode CTCO is connected to the common auxiliary electrode CMTL at an opening PCON. As will be described in detail later, the common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The electrical resistance of the common auxiliary electrode CMTL is lower than the electrical resistance of the common electrode CTCO. The common auxiliary electrode CMTL also functions as a light-shielding layer. For example, the common auxiliary electrode CMTL blocks light from adjacent pixels, thereby suppressing color mixing. A spacer SP is provided above the common electrode CTCO.

[0029] Spacers SP are provided for some of the pixels. For example, spacers SP may be provided for any one of blue, red, and green pixels. However, spacers SP may also be provided for all pixels. The height of the spacers SP is half the height of the cell gap. Spacers are also provided on the opposing substrate, and the spacers on the opposing substrate and the spacers SP overlap in a planar view.

[0030] A light-shielding layer LS is provided between the transistor Tr1 and the substrate SUB. In this embodiment, light-shielding layers LS1 and LS2 are provided as the light-shielding layer LS. However, the light-shielding layer LS may be formed of only the light-shielding layer LS1 or only the light-shielding layer LS2. In plan view, the light-shielding layer LS is provided in a region where the gate electrode GL1 and the oxide semiconductor layer OS overlap. That is, in plan view, the light-shielding layer LS is provided in a region where the light-shielding layer LS overlaps with the oxide semiconductor layer OS1. The light-shielding layer LS prevents light incident from the substrate SUB side from reaching the oxide semiconductor layer OS1. When a conductive layer is used as the light-shielding layer LS, a voltage may be applied to the light-shielding layer LS to control the oxide semiconductor layer OS1. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate electrode GL1 may be connected in a peripheral region of the pixel circuit. In plan view, the contact region CON1 is provided in a region where the light-shielding layer LS does not overlap.

[0031] In this embodiment, the oxide semiconductor layer OS is in contact with the insulating layer IL1, but the present invention is not limited to this configuration. For example, a metal oxide layer may be provided between the oxide semiconductor layer OS and the insulating layer IL1. For example, a metal oxide containing aluminum as a main component may be used as the metal oxide layer. Specifically, aluminum oxide may be used as the metal oxide layer. In this case, the metal oxide layer may be provided in the same region as the insulating layer IL1 and may be processed into the same pattern as the oxide semiconductor layer OS.

[0032] [1-3. Configuration of transistor Tr2] The transistor Tr2 includes a p-type transistor Tr2-1 and an n-type transistor Tr2-2.

[0033] Each of the p-type transistor Tr2-1 and the n-type transistor Tr2-2 has a gate electrode GL2, a gate insulating layer GI2, and a semiconductor layer S (S1 to S3). The gate electrode GL2 faces the semiconductor layer S. The gate insulating layer GI2 is provided between the semiconductor layer S and the gate electrode GL2. In this embodiment, a bottom-gate transistor in which the gate electrode GL2 is provided closer to the substrate SUB than the semiconductor layer S is exemplified, but a top-gate transistor in which the positional relationship between the semiconductor layer S and the gate electrode GL2 is reversed may also be used.

[0034] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. The semiconductor layer S1 is a semiconductor layer in a region that overlaps with the gate electrode GL2 in a planar view. The semiconductor layer S1 functions as a channel of the transistors Tr2-1 and Tr2-2. The semiconductor layer S2 functions as a conductive layer. The semiconductor layer S3 functions as a conductive layer with higher resistance than the semiconductor layer S2. The semiconductor layer S3 suppresses hot carrier degradation by attenuating hot carriers that invade toward the semiconductor layer S1.

[0035] An insulating layer IL1 and a gate insulating layer GI1 are provided above the semiconductor layer S. In the transistor Tr2, the gate insulating layer GI1 simply functions as an interlayer film. A wiring W2 is provided above these insulating layers. The wiring W2 is connected to the semiconductor layer S2 through an opening provided in the insulating layer IL1 and the gate insulating layer GI1. An insulating layer IL2 is provided above the wiring W2. A wiring W1 is provided above the insulating layer IL2. The wiring W1 is connected to the wiring W2 through an opening provided in the insulating layer IL2. An insulating layer IL3 is provided above the wiring W1. A wiring XTCO is provided above the insulating layer IL3. The wiring XTCO is connected to the wiring W1 through an opening provided in the insulating layer IL3.

[0036] The gate electrode GL2 and the light-shielding layer LS2 are in the same layer. The wiring W2 and the gate electrode GL1 are in the same layer. The term "in the same layer" means that a single layer is patterned to form multiple components.

[0037] [1-4. Planar layout of the display device 10] The planar layout of the pixels of the display device 10 will be described with reference to Figures 2 to 13. The pixel electrode PTCO, the common auxiliary electrode CMTL, the common electrode CTCO, and the spacer SP are omitted in Figure 2. The planar layouts of the pixel electrode PTCO, the common auxiliary electrode CMTL, and the common electrode CTCO are shown in Figures 11 to 13, respectively.

[0038] As shown in FIGS. 2 and 3, the light-shielding layer LS extends in the D1 direction. The shape of the light-shielding layer LS differs depending on the pixel. In this embodiment, a protrusion PJT protruding in the D2 direction is provided from a part of the light-shielding layer LS extending in the D1 direction. As shown in FIG. 5, the light-shielding layer LS is provided in a region including a region where the gate electrode GL1 and the oxide semiconductor layer OS overlap in a plan view. The gate electrode GL1 can also be called a "gate line."

[0039] 2, 4, and 5, the oxide semiconductor layer OS extends in the D2 direction. The gate electrode GL1 extends in the D1 direction so as to intersect with the oxide semiconductor layer OS. The pattern of the gate electrode GL1 is provided inside the pattern of the light-shielding layer LS. In other words, the oxide semiconductor layer OS is formed in an elongated shape (a shape having a long side) intersecting with the gate electrode GL1.

[0040] 2, 6, and 7, the opening WCON is provided near the upper end of the pattern of the oxide semiconductor layer OS in a region overlapping with the wiring W1 (W1-1, W1-2). A main portion of the pattern of the oxide semiconductor layer OS extends in the D2 direction between adjacent wirings W1 (W1-1, W1-2). The remaining portion of the pattern of the oxide semiconductor layer OS extends from the main portion toward the region of the opening WCON in a direction oblique to the D1 and D2 directions.

[0041] 2 and 7, multiple wirings W1 extend in the D2 direction. When it is necessary to distinguish adjacent wirings W1 from one another, the adjacent wirings W1 are referred to as wirings W1-1 and W1-2. In this case, it can be said that the main portion of the oxide semiconductor layer OS extends in the D2 direction between the wirings W1-1 and W1-2 and intersects with the gate electrode GL1. In other words, the oxide semiconductor layer OS is provided elongated in the D2 direction and is connected to the wiring W1-1 at one longitudinal end of the oxide semiconductor layer OS.

[0042] As shown in FIGS. 2, 8, and 9, the opening ZCON is provided near the bottom end of the pattern of the oxide semiconductor layer OS. The opening ZCON is provided in a region overlapping with the pattern of the oxide semiconductor layer OS but not overlapping with the gate electrode GL1. The opening ZCON is provided in a region overlapping with the connection electrode ZTCO. The connection electrode ZTCO overlaps with the gate electrode GL1 and the oxide semiconductor layer OS between the wiring W1-1 and the wiring W1-2. Therefore, the connection electrode ZTCO contacts the oxide semiconductor layer OS at the opening ZCON that does not overlap with the gate electrode GL1.

[0043] In other words, the oxide semiconductor layer OS is connected to the connection electrode ZTCO at the other end in the longitudinal direction of the oxide semiconductor layer OS. The connection electrode ZTCO is formed in an elongated shape extending in the D2 direction, similar to the oxide semiconductor layer OS. In the D1 direction, the width of the connection electrode ZTCO is smaller than the width of the oxide semiconductor layer OS.

[0044] 2, 7, and 8, the oxide semiconductor layer OS is in contact with the wiring W1 on the opposite side of the gate electrode GL1 from the opening ZCON. The opening ZCON does not overlap with the light-shielding layer LS.

[0045] As shown in Figures 2, 10, and 11, the opening PCON is provided near the upper end of the pattern of the connection electrode ZTCO. The opening PCON is provided in a region overlapping with the pattern of the gate electrode GL1 and the pattern of the connection electrode ZTCO. The opening PCON is provided in a region overlapping with the pixel electrode PTCO. The pixel electrode PTCO overlaps with the gate electrode GL1, the oxide semiconductor layer OS, and the connection electrode ZTCO between the wiring W1-1 and the wiring W1-2. Therefore, the pixel electrode PTCO contacts the connection electrode ZTCO at the opening PCON that overlaps with the gate electrode GL1.

[0046] The pixel electrode PTCO extends into the light-transmitting region described below. In other words, the pixel electrode PTCO is formed in an elongated shape extending in the D2 direction, similar to the oxide semiconductor layer OS and the wiring W1-1. In the D1 direction, the width of the pixel electrode PTCO in the portion where the opening PCON is provided is larger than the width of the oxide semiconductor layer OS.

[0047] 11, the connection electrode ZTCO is formed in an elongated shape extending along the wiring W1-1. In the direction D1, the width of the opening PCON constituting the contact region CON2 is greater than the width of the connection electrode ZTCO. In plan view, the entire connection electrode ZTCO overlaps with the pixel electrode PTCO.

[0048] As shown in FIG. 11, the pixel electrodes PTCO are arranged in the D2 direction. Of the pixels adjacent to each other in the D2 direction, one pixel may be referred to as the "first pixel" and the other pixel may be referred to as the "second pixel." For example, the first pixel is the pixel corresponding to the upper pixel electrode PTCO among the pixel electrodes PTCO arranged in the D2 direction in FIG. 11, and the second pixel is the pixel corresponding to the lower pixel electrode PTCO among the pixel electrodes PTCO arranged in the D2 direction. In this case, a pixel signal is supplied to the first pixel and the second pixel from the wiring W1-1.

[0049] The pixel electrodes PTCO are arranged in the direction D1. The pixel adjacent to the first pixel in the direction D1 is called the "third pixel," and the pixel adjacent to the second pixel in the direction D1 is called the "fourth pixel." The third pixel and the fourth pixel are adjacent to each other in the direction D2. A pixel signal is supplied to the third pixel and the fourth pixel from the wiring W1-2 adjacent to the wiring W1-1.

[0050] As described above, each of the first, second, third, and fourth pixels includes a transistor Tr1 (pixel transistor), a connection electrode ZTCO, and a pixel electrode PTCO.

[0051] The transistor Tr1 includes an oxide semiconductor layer OS, a gate electrode GL1 facing the oxide semiconductor layer OS, and a gate insulating layer GI1 between the oxide semiconductor layer OS and the gate electrode GL1. The connection electrode ZTCO overlaps with the gate electrode GL1 and the oxide semiconductor layer OS in a plan view, but is in contact with the oxide semiconductor layer OS at an opening ZCON that does not overlap with the gate electrode GL1. The pixel electrode PTCO overlaps with the gate electrode GL1, the oxide semiconductor layer OS, and the connection electrode ZTCO in a plan view, and is connected to the connection electrode ZTCO at an opening PCON that overlaps with the gate electrode GL1.

[0052] 11 overlaps with the oxide semiconductor layer OS of the first pixel and the oxide semiconductor layer OS of the second pixel provided below the first pixel in a plan view. In addition, the pixel electrode PTCO of the first pixel also overlaps with the oxide semiconductor layer OS of the fourth pixel in a plan view.

[0053] As shown in FIG. 12, the common auxiliary electrode CMTL is provided in a lattice pattern so as to surround the periphery of the pixel region. In other words, the common auxiliary electrode CMTL is provided in common to a plurality of pixels. In other words, the common auxiliary electrode CMTL has an opening OP. The opening OP is provided so as to expose the pixel electrode PTCO. The pattern of the opening OP is provided inside the pattern of the pixel electrode PTCO. The area where the opening OP is provided corresponds to the display area. In other words, the opening ZCON is included in the display area. The display area means an area where a user can see light from the pixels. For example, an area that is light-shielded by a metal layer and from which a user cannot see light is not included in the display area. In other words, the above-mentioned display area may be called a "light-transmitting area (or opening area)".

[0054] As shown in Fig. 13, the common electrode CTCO is provided in common to a plurality of pixels. A slit SL is provided in a region corresponding to the opening OP. The slit SL has a curved shape (a vertically long S-shape). The tip of the slit SL has a shape in which the width perpendicular to the extension direction of the tip becomes smaller. With reference to Figs. 1 and 13, the common electrode CTCO has a slit SL at a position opposite to the pixel electrode PTCO.

[0055] [1-5. Etching residue] A problem newly recognized in the process of arriving at the present invention will be described with reference to Fig. 14. It was found that when the size of pixel circuits in display devices is reduced and the spacing between adjacent signal lines (for example, the wiring W1-1 and wiring W1-2 in Fig. 2) becomes 5 µm or less, a problem occurs in which a leak current flows between the signal lines due to slight etching residues of the conductive layer generated between the adjacent signal lines.

[0056] FIG. 14 is a cross-sectional view showing etching residues generated in a semiconductor device according to a comparative example. The cross-sectional view of FIG. 14 shows a transistor Tr1 provided in the pixel circuit of FIG. 1. When an inorganic insulating layer is used as the insulating layer IL2, a step portion ST2 that reflects the shape of the step portion ST1 of the gate electrode GL1 is formed in the insulating layer IL2, as shown in FIG. 14. A gap Cv (or a crack or groove) may be formed from the step portion ST1 to the step portion ST2. Note that a partially enlarged view of the step portion ST2 of the insulating layer IL2 is shown in a dotted circle at the top of FIG. 14.

[0057] The voids Cv affect the surface shape of the insulating layer IL2. Specifically, the voids Cv form an uneven shape on the sidewall of the insulating layer IL2 at the step ST2. Here, when forming the wiring W1, a conductive layer is formed on the entire surface of the insulating layer IL2, and then the conductive layer is etched using a mask that covers the area where the wiring W1 will be formed. The conductive layer formed on the entire surface of the insulating layer IL2 is also formed in the uneven recesses formed on the sidewall of the insulating layer IL2. The conductive layer formed inside the recesses formed on the sidewall is difficult to remove by the above-mentioned etching. Therefore, even after the etching for forming the wiring W1 is completed, the conductive layer formed in the recesses may remain as etching residue Rd.

[0058] 2, the etching residue Rd is generated along the pattern edge of the gate electrode GL1. That is, the generated etching residue Rd is present so as to extend in the direction D1. Therefore, the etching residue Rd present between the wiring W1-1 and the wiring W1-2 generates a leakage current between the wiring W1-1 and the wiring W1-2.

[0059] The amount of etching residue Rd described above is very small, and in pixel circuits where the size of the pixel circuit has not been reduced as in the past, the problem of leakage current between signal lines has not been apparent. However, as described above, it has been found that the problem of leakage current begins to become apparent, particularly when the spacing between adjacent signal lines is 5 μm or less. This problem was newly recognized in the process of arriving at the present invention, and was not a problem that had been recognized previously.

[0060] [1-6. Structure and manufacturing method for eliminating etching residue] 15 to 17, the structure of transistor Tr1 and a manufacturing method thereof for eliminating the etching residue will be described. FIG. 15 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 16 and 17 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 16, the structure differs from that of the comparative example shown in FIG. 14 in that a sacrificial layer Sc is formed between the insulating layer IL2 and the conductive layer W1'. The conductive layer W1' is a conductive layer formed on the entire surface to form the wiring W1.

[0061] As shown in FIGS. 15 and 16, first, a light-shielding layer LS is formed on a substrate SUB (step S1001; LS formation). A gate insulating layer GI2 and an insulating layer IL1 are formed on the light-shielding layer LS, and an oxide semiconductor layer OS is formed on the entire surface thereof (step S1002; OS formation). A pattern of the oxide semiconductor layer OS is formed by photolithography and etching processes on the oxide semiconductor layer OS (step S1003; OS pattern formation). A heat treatment is performed on the patterned oxide semiconductor layer OS (step S1004; OS annealing). This OS annealing crystallizes the oxide semiconductor layer OS. However, the oxide semiconductor layer OS does not necessarily have to be crystallized by the OS annealing.

[0062] Next, a gate insulating layer GI1 is formed on the oxide semiconductor layer OS (step S1005: GI formation). With the gate insulating layer GI1 formed on the entire surface, oxidation annealing is performed on the oxide semiconductor layer OS (step S1006: oxidation annealing). During the process from when the oxide semiconductor layer OS is formed until when the gate insulating layer GI1 is formed on the oxide semiconductor layer OS, many oxygen vacancies are generated on the top and side surfaces of the oxide semiconductor layer OS. Due to the oxidation annealing, oxygen released from, for example, the insulating layer IL1 is supplied to the oxide semiconductor layer OS, and the oxygen vacancies are repaired.

[0063] Next, a conductive layer is formed on the gate insulating layer GI1. The conductive layer is formed on the entire surface. A gate electrode GL1 having a step portion ST1 is formed by a photolithography process and an etching process on the conductive layer (step S1007; GL formation). With the gate electrode GL1 formed, a resistance reduction process is performed on the source region and drain region (regions corresponding to OS1 and OS2 in FIG. 1) of the oxide semiconductor layer OS (step S1008; SD resistance reduction).

[0064] Specifically, in S1008, impurities are implanted into the oxide semiconductor layer OS from the gate electrode GL1 side through the gate insulating layer GI1 by ion implantation. For example, argon (Ar), phosphorus (P), or boron (B) is implanted into the oxide semiconductor layer OS by ion implantation. Oxygen vacancies are formed in the oxide semiconductor layer OS by the ion implantation, and the oxygen vacancies are bonded with hydrogen by subsequent heat treatment, thereby reducing the resistance of the oxide semiconductor layer OS. Because the gate electrode GL1 is provided above the oxide semiconductor layer OS that functions as the channel region of the transistor Tr1, impurities are not implanted into the oxide semiconductor layer OS in the channel region.

[0065] Next, an insulating layer IL2 is formed on the gate electrode GL1 (Step S1009: Form IL). The insulating layer IL2 may be referred to as the "first insulating layer." A sacrificial layer Sc made of a material different from that of the insulating layer IL2 is formed on the insulating layer IL2 (Step S1010: Form Sc). The sacrificial layer Sc may be referred to as the "second insulating layer." As will be described in detail later, an insulating layer containing silicon oxide, for example, is used as the insulating layer IL2. An insulating layer containing silicon nitride, for example, is used as the sacrificial layer Sc. The thickness of the sacrificial layer Sc is 50 nm or more and 300 nm or less. As will be described later, if the thickness of the sacrificial layer Sc is smaller than the lower limit of the above range, etching residues Rd may be generated in the insulating layer IL2. If the thickness of the sacrificial layer Sc is larger than the upper limit of the above range, the in-plane variation in the etching amount of the sacrificial layer Sc, which will be described later, increases, resulting in a large amount of over-etching of the insulating layer IL2.

[0066] In this embodiment, both the insulating layer IL2 and the sacrificial layer Sc are inorganic insulating layers. Therefore, when the insulating layer IL2 is formed on the gate electrode GL1, a step portion ST2 is formed in the insulating layer IL2, reflecting the shape of the step portion ST1 of the gate electrode GL1. Furthermore, when the sacrificial layer Sc is formed on the insulating layer IL2, a step portion ST3 is formed in the sacrificial layer Sc, reflecting the shape of the step portion ST2 of the insulating layer IL2. When the insulating layer IL2 and the sacrificial layer Sc are formed, a void Cv is formed from the step portion ST1 to the step portion ST3, and this void Cv reaches the surface of the sacrificial layer Sc. The step portion ST1 may be referred to as the "first step portion," the step portion ST2 may be referred to as the "second step portion," and the step portion ST3 may be referred to as the "third step portion."

[0067] Next, contacts are formed in the insulating layer IL2 and the sacrificial layer Sc (step S1011; contact opening). The contact opening exposes a portion of the oxide semiconductor layer OS. A conductive layer W1' is formed on the sacrificial layer Sc and inside the contact (step S1012; conductive layer deposition). The conductive layer W1' is deposited so that a portion of it penetrates into the cavity Cv (at a position corresponding to the etching residue Rd). As described above, the cavity Cv is formed in both the insulating layer IL2 and the sacrificial layer Sc. The conductive layer W1' is deposited inside the cavity Cv formed in the sacrificial layer Sc, but the conductive layer W1' is not deposited, or is hardly deposited, in the cavity Cv formed in the insulating layer IL2.

[0068] Next, a mask is formed in the region where the wiring W1 will be provided, and the conductive layer W1' is etched through the mask (step S1013: conductive layer etching). After the conductive layer W1' is etched by this etching, the sacrificial layer Sc is also etched. By etching the sacrificial layer Sc, the conductive layer W1' inside the cavity Cv formed in the sacrificial layer Sc is etched. With the above configuration, as shown in FIG. 17, the conductive layer W1' formed inside the cavity Cv is removed together with the sacrificial layer Sc. In other words, by etching the conductive layer W1' and the sacrificial layer Sc, the sacrificial layer Sc remains between the wiring W1 and the insulating layer IL2 in the region overlapping with the patterned conductive layer W1' (wiring W1) in a planar view. As a result, the sacrificial layer Sc is formed between the insulating layer IL2 and the wiring W1, and the sacrificial layer Sc is removed in the region not overlapping with the wiring W1 in a planar view, exposing the insulating layer IL2.

[0069] In the above example, the conductive layer etching in S1013 etches all of the sacrificial layer Sc provided in the region that does not overlap with the wiring W1 in a planar view, thereby exposing the insulating layer IL2. However, this method is not limited to this. The sacrificial layer Sc may be thinned by etching, and the thinned sacrificial layer Sc may remain on the insulating layer IL2 in the region that does not overlap with the wiring W1. In other words, at least a portion of the sacrificial layer Sc is etched by the conductive layer etching.

[0070] In the conductive layer etching of S1013, the conductive layer W1' and the sacrificial layer Sc are etched under the same etching conditions. Under these etching conditions, the etching rate of the insulating layer IL2 is slower than that of the sacrificial layer Sc. In other words, the insulating layer IL2 functions as an etching stopper during the conductive layer etching. For example, etching conditions using a chlorine-containing gas as a process gas are used for the conductive layer etching.

[0071] In order to remove the conductive layer W1' that has penetrated into the voids Cv and to suppress the generation of etching residues Rd, the thickness of the sacrificial layer Sc is preferably 50 nm or more. On the other hand, if the sacrificial layer Sc is too thick, the step between the wiring W1 and the insulating layer IL2 becomes larger, which can cause the wiring to be unable to overcome the step. Therefore, the thickness of the sacrificial layer Sc is preferably 300 nm or less.

[0072] In this embodiment, an insulating layer such as silicon nitride is formed as the sacrificial layer Sc. However, a semiconductor layer or a conductive layer may be used as the sacrificial layer Sc instead of an insulating layer. For example, ITO or an oxide semiconductor layer may be formed on the insulating layer IL2. The oxide semiconductor layer used as the sacrificial layer Sc may be the same as or different from the oxide semiconductor layer OS. In this case, when a void Cv is formed in the ITO or oxide semiconductor layer and a conductive layer W1' is formed on the void Cv, a portion of the conductive layer W1' is formed within the void Cv. However, after the conductive layer W1' is etched, the ITO or oxide semiconductor layer can be etched by wet etching, thereby removing the conductive layer W1' formed within the void Cv by lift-off. The ITO and oxide semiconductor layer function as an etching stopper during the conductive layer etching.

[0073] As shown in FIG. 17, the transistor Tr1 includes an oxide semiconductor layer OS, a gate insulating layer GI1, a gate electrode GL1, an insulating layer IL2, a wiring W1, and a sacrificial layer Sc. The gate electrode GL1 faces the oxide semiconductor layer OS and has a step portion ST1. The gate insulating layer GI1 is provided between the oxide semiconductor layer OS and the gate electrode GL1. The insulating layer IL2 is provided on the gate electrode GL1. The wiring W1 is a layer formed by patterning a conductive layer W1'. The sacrificial layer Sc is made of a different material from the insulating layer IL2. In a region where the insulating layer IL2 does not overlap with the wiring W1 in a plan view, the insulating layer IL2 is exposed from the sacrificial layer Sc and the wiring W1.

[0074] The insulating layer IL2 has a step portion ST2 that reflects the shape of the step portion ST1 of the gate electrode GL1. In the insulating layer IL2, a gap Cv is formed from the step portion ST1 to the step portion ST2.

[0075] [1-7. Materials of each component of the display device 10] The substrate SUB can be a rigid substrate that is light-transmitting and not flexible, such as a glass substrate, a quartz substrate, or a sapphire substrate. On the other hand, if the substrate SUB needs to be flexible, a flexible substrate that contains resin and has flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used as the substrate SUB. Impurities may be introduced into the resin to improve the heat resistance of the substrate SUB.

[0076] Common metal materials can be used for the gate electrodes GL1 and GL2, the wirings W1 and W2, the light-shielding layer LS, and the common auxiliary electrode CMTL. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), and silver (Ag), or alloys or compounds thereof, can be used for the electrodes. The above materials can be used as single layers or as multilayers for the electrodes.

[0077] For example, a laminated structure of Ti / Al / Ti is used as the gate electrode GL1. In this embodiment, the cross-sectional shape of the pattern end of the gate electrode GL1 having the above-mentioned laminated structure is a forward tapered shape.

[0078] The gate insulating layers GI1, GI2 and the insulating layers IL1 to IL5 can be made of a general insulating material. For example, the gate insulating layers GI1, GI2 and the insulating layers IL1 to IL3, IL5 can be made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x ) or other inorganic insulating layers can be used. As these insulating layers, insulating layers with few defects can be used. As the insulating layer IL4, organic insulating materials such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used. As the gate insulating layers GI1, GI2 and the insulating layers IL1 to IL3, IL5, the above organic insulating materials may be used. As the members of the above insulating layers, etc., the above materials may be used in a single layer or in a laminated layer.

[0079] As an example of the insulating layer, a 100 nm thick SiO x The insulating layer IL1 is made of SiO 2 having a total thickness of 300 nm to 700 nm. x / SiN x / SiO x The gate insulating layer GI2 is made of SiO 2 with a total thickness of 60 to 150 nm. x / SiN x The insulating layer IL2 is made of SiO 2 with a total thickness of 300 nm to 500 nm. xThe insulating layer IL3 is made of SiO 2 having a total thickness of 200 nm to 500 nm. x (single layer), SiN x The insulating layer IL4 is an organic layer having a thickness of 2 μm to 4 μm. The insulating layer IL5 is a SiN layer having a thickness of 50 nm to 150 nm. x (single layer) is used.

[0080] The above SiO x N y and AlO x N y is a silicon and aluminum compound containing a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).

[0081] The sacrificial layer Sc is made of a material different from that of the insulating layer IL2. For example, the materials of the sacrificial layer Sc and the insulating layer IL2 are selected so that the etching rate of the sacrificial layer Sc under certain etching conditions is faster than the etching rate of the insulating layer IL2. A general insulating material can be used for the sacrificial layer Sc. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x Alternatively, a semiconductor material or a conductive layer may be used as the sacrificial layer Sc.

[0082] The oxide semiconductor layer OS may be formed using a metal oxide having semiconductor properties. For example, the oxide semiconductor layer OS may be formed using an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). For example, the oxide semiconductor layer OS may be formed using an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and an oxide semiconductor having a different composition may be used. For example, an oxide semiconductor layer having a higher In ratio than the above may be used to improve mobility. On the other hand, an oxide semiconductor layer having a higher Ga ratio than the above may be used to increase the band gap and reduce the influence of light irradiation.

[0083] For example, an oxide semiconductor containing two or more metals including indium (In) may be used as the oxide semiconductor layer OS having a higher In ratio than the above. In this case, the ratio of indium to all metal elements in the oxide semiconductor layer OS may be 50% or more in atomic ratio. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanoid may be used as the oxide semiconductor layer OS. Elements other than those mentioned above may also be used as the oxide semiconductor layer OS.

[0084] The oxide semiconductor layer OS may be formed by adding other elements to an oxide semiconductor containing In, Ga, Zn, and O. For example, a metal element such as Al or Sn may be added to the oxide semiconductor. In addition to the above oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn, and Zn (ITZO), an oxide semiconductor containing In and W, or the like may be used as the oxide semiconductor layer OS.

[0085] When the ratio of indium element in the oxide semiconductor layer OS is high, the oxide semiconductor layer OS is likely to crystallize. As described above, by using a material in which the ratio of indium element to all metal elements is 50% or more for the oxide semiconductor layer OS, the oxide semiconductor layer OS can have a polycrystalline structure. It is preferable that the oxide semiconductor layer OS contains gallium as a metal element other than indium. Gallium belongs to the same group 13 as indium. Therefore, the crystallinity of the oxide semiconductor layer OS is not impaired by gallium, and the oxide semiconductor layer OS has a polycrystalline structure.

[0086] Although a detailed manufacturing method of the oxide semiconductor layer OS will be described later, the oxide semiconductor layer OS can be formed by a sputtering method. The composition of the oxide semiconductor layer OS formed by a sputtering method depends on the composition of the sputtering target. Even when the oxide semiconductor layer OS has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer OS are substantially the same. In this case, the composition of the metal elements in the oxide semiconductor layer OS can be determined based on the composition of the metal elements in the sputtering target.

[0087] When the oxide semiconductor layer OS has a polycrystalline structure, the composition of the oxide semiconductor layer may be determined by X-ray diffraction (XRD). Specifically, the composition of the metal elements in the oxide semiconductor layer can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by XRD. Furthermore, the composition of the metal elements in the oxide semiconductor layer OS can also be determined by X-ray fluorescence analysis or electron probe microanalyzer (EPMA) analysis. However, this is not limited to this because the oxygen element contained in the oxide semiconductor layer OS changes depending on the sputtering process conditions, etc.

[0088] As described above, the oxide semiconductor layer OS has a polycrystalline structure. An oxide semiconductor having a polycrystalline structure can be manufactured using a polycrystalline oxide semiconductor (Poly-OS) technique. Hereinafter, an oxide semiconductor having a polycrystalline structure may be referred to as a Poly-OS to distinguish it from an oxide semiconductor having an amorphous structure.

[0089] As described above, the connection electrode ZTCO, the wiring XTCO, the pixel electrode PTCO, and the common electrode CTCO are made of transparent conductive layers. The transparent conductive layers may be made of ITO and a mixture of indium oxide and zinc oxide (IZO). Materials other than those mentioned above may also be used for the transparent conductive layers.

[0090] As described above, when a metal oxide layer is provided between the oxide semiconductor layer OS and the insulating layer IL1, a metal oxide containing aluminum as a main component is used as the metal oxide layer. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x ) is used. "A metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0091] As described above, according to the configuration of the transistor Tr1 and the manufacturing method thereof of this embodiment, even if a cavity is formed in the insulating layer due to a step portion caused by a structure formed below the insulating layer, etching residues caused by the cavity can be suppressed.

[0092] Furthermore, in the transistor Tr1 according to this embodiment, electrical continuity between the oxide semiconductor layer OS including a polycrystalline structure and the connection electrode ZTCO, which is a transparent conductive layer, can be ensured by directly contacting them. Therefore, there is no need to provide a metal layer between the oxide semiconductor layer OS and the connection electrode ZTCO. Furthermore, in the transistor Tr1 according to this embodiment, the contact resistance between the oxide semiconductor layer OS and the connection electrode ZTCO can be reduced. Therefore, the process margin can be increased without degrading the electrical characteristics of the transistor Tr1.

[0093] With the above configuration, light is not blocked at the opening ZCON, thereby suppressing a decrease in aperture ratio. The oxide semiconductor layer is light-transmitting. Therefore, in this embodiment, although an oxide semiconductor layer is provided in the opening region of the pixel region, light from the backlight passes through the oxide semiconductor layer. Therefore, a decrease in transmittance of the opening region due to the oxide semiconductor layer being provided in the opening region is suppressed. Because the oxide semiconductor layer OS is light-transmitting, it is less likely to cause unevenness in transmitted light, unlike a silicon layer. By providing the oxide semiconductor layer OS in the display region, the occurrence of display unevenness can be suppressed.

[0094] [1-8. Variations] A modified example of the first embodiment will be described with reference to FIGS. 18 and 19. FIGS. 18 and 19 are cross-sectional views showing a method for manufacturing a semiconductor device according to a modified example of one embodiment of the present invention. FIGS. 18 and 19 correspond to FIGS. 16 and 17, respectively. The cross-sectional structures shown in FIGS. 18 and 19 are similar to the cross-sectional structures shown in FIGS. 16 and 17, respectively, but differ from the cross-sectional structure shown in FIG. 16 in that an insulating layer IL6 is provided between the insulating layer IL2 and the gate electrode GL1. The insulating layer IL6 is made of a different material from the insulating layer IL2. For example, silicon nitride is used as the insulating layer IL6.

[0095] The transistor Tr1 shown in Figures 18 and 19 can be fabricated by forming an insulating layer IL6 on the gate electrode GL1 before forming the insulating layer IL2, and then forming the insulating layer IL2 on the insulating layer IL6. Even in this case, similar to the above, the conductive layer W1' inside the cavity Cv formed in the sacrificial layer Sc can be etched by etching the conductive layer W1'. As a result, as shown in Figure 19, the conductive layer W1' formed inside the cavity Cv is removed together with the sacrificial layer Sc.

[0096] [2. Second Embodiment] The overall configuration of the display device described in the first embodiment will be described with reference to FIGS.

[0097] [2-1. Overview of the display device 20] FIG. 20 is a plan view showing an outline of a display device according to one embodiment of the present invention. As shown in FIG. 20, the display device 20 includes an array substrate 300, a seal portion 400, a counter substrate 500, a flexible printed circuit board 600 (FPC 600), and an IC chip 700. The array substrate 300 and the counter substrate 500 are bonded together by the seal portion 400. A plurality of pixel circuits 310 are arranged in a matrix in a liquid crystal region 22 surrounded by the seal portion 400. The liquid crystal region 22 is an area that overlaps with a liquid crystal element 410 (described later) in a planar view. The liquid crystal region 22 is an area that contributes to display. The liquid crystal region 22 may also be referred to as a "display region." The above-mentioned transistor Tr1 is provided in the liquid crystal region 22 (display region).

[0098] The sealing region 24, in which the sealing portion 400 is provided, is the region surrounding the liquid crystal region 22. The FPC 600 is provided in the terminal region 26. The terminal region 26 is the region where the array substrate 300 is exposed from the counter substrate 500, and is provided outside the sealing region 24. Note that the outside of the sealing region 24 means the outside of the region where the sealing portion 400 is provided and the region surrounded by the sealing portion 400. The IC chip 700 is provided on the FPC 600. The IC chip 700 supplies signals to drive each pixel circuit 310. The sealing region 24 or the region combining the sealing region 24 and the terminal region 26 is the region surrounding the liquid crystal region 22 (display region). These regions may be referred to as the "frame region." The above-mentioned transistor Tr2 is provided in the frame region.

[0099] [2-2. Circuit configuration of display device 20] Fig. 21 is a block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. As shown in Fig. 21, a source driver circuit 320 is provided adjacent to the liquid crystal region 22 in which the pixel circuits 310 are arranged in the direction D2 (column direction), and a gate driver circuit 330 is provided adjacent to the liquid crystal region 22 in the direction D1 (row direction). The source driver circuit 320 and the gate driver circuit 330 are provided in the sealing region 24. However, the region in which the source driver circuit 320 and the gate driver circuit 330 are provided is not limited to the sealing region 24, and may be any region outside the region in which the pixel circuits 310 are provided.

[0100] A source line 321 extends from the source driver circuit 320 in the direction D2 and is connected to a plurality of pixel circuits 310 arranged in the direction D2. A gate line 331 extends from the gate driver circuit 330 in the direction D1 and is connected to a plurality of pixel circuits 310 arranged in the direction D1. The source line 321 corresponds to the line W1 in FIG. 2. The gate line 331 corresponds to the gate electrode GL1 in FIG. 2.

[0101] A terminal portion 333 is provided in the terminal region 26. The terminal portion 333 and the source driver circuit 320 are connected by a connection wiring 341. Similarly, the terminal portion 333 and the gate driver circuit 330 are connected by a connection wiring 341. When the FPC 600 is connected to the terminal portion 333, the external device to which the FPC 600 is connected is connected to the display device 20, and each pixel circuit 310 provided in the display device 20 is driven by a signal from the external device.

[0102] The transistor Tr1 shown in the first embodiment is used in the pixel circuit 310. The transistor Tr2 shown in the first embodiment is applied to transistors included in the source driver circuit 320 and the gate driver circuit 330.

[0103] 2-3. Pixel circuit 310 of display device 20 FIG. 22 is a circuit diagram showing a pixel circuit of a display device according to one embodiment of the present invention. As shown in FIG. 22, the pixel circuit 310 includes elements such as a transistor 800, a storage capacitor 890, and a liquid crystal element 410. One electrode of the storage capacitor 890 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. Similarly, one electrode of the liquid crystal element 410 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. The transistor 800 has a first gate electrode 810, a first source electrode 830, and a first drain electrode 840. The first gate electrode 810 is connected to a gate wiring 331. The first source electrode 830 is connected to a source wiring 321. The first drain electrode 840 is connected to the storage capacitor 890 and the liquid crystal element 410. The transistor Tr1 shown in the first embodiment is applied to the transistor 800 shown in FIG. 22. In this embodiment, for convenience of explanation, 830 is referred to as a source electrode and 840 as a drain electrode, but the source and drain functions of these electrodes may be interchanged.

[0104] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies the design, or adds or omits processes or modifies conditions based on the semiconductor device of each embodiment, such combinations are included in the scope of the present invention as long as they include the gist of the present invention.

[0105] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0106] 10, 20: display device, 22: liquid crystal region, 24: sealing region, 26: terminal region, 300: array substrate, 310: pixel circuit, 320: source driver circuit, 321: source wiring, 330: gate driver circuit, 331: gate wiring, 333: terminal section, 341: connection wiring, 400: sealing section, 410: liquid crystal element, 500: opposing substrate, 600: FPC (flexible printed circuit board), 700: IC chip, 800: transistor, 810: first gate electrode, 830: first source electrode, 840: first drain electrode, 890: storage capacitor, CMTL: common auxiliary electrode, CON1, CON2: contact region, CTCO: common electrode, Cv: void, GI1, GI2: gate insulating layer, GL1, GL2: gate electrode, IL1 to IL6: insulating layer, LS: Light-shielding layer, OP: Opening, OS: Oxide semiconductor layer, PCON: Opening, PJT: Protrusion, PTCO: Pixel electrode, Rd: Etching residue, S: Semiconductor layer, Sc: Sacrificial layer, SL: Slit, SP: Spacer, ST1 to ST3: Step portion, SUB: Substrate, Tr1, Tr2: Transistor, W1, W2: Wiring, W1': Conductive layer, WCON, XCON, ZCON: Opening, XTCO: Wiring, ZTCO: Connection electrode

Claims

1. a semiconductor layer; a gate electrode facing the semiconductor layer and having a first step portion; a gate insulating layer between the semiconductor layer and the gate electrode; a first insulating layer over the gate electrode; a patterned conductive layer on the first insulating layer; a sacrificial layer between the conductive layer and the first insulating layer, the sacrificial layer being made of a material different from that of the first insulating layer; In a region of the semiconductor device where the first insulating layer does not overlap with the conductive layer in a plan view, the first insulating layer is exposed from the sacrificial layer and the conductive layer.

2. the first insulating layer includes silicon oxide; The semiconductor device of claim 1 , wherein the sacrificial layer comprises silicon nitride.

3. the first insulating layer has a second step portion that reflects the shape of the first step portion of the gate electrode; The semiconductor device according to claim 1 , wherein a cavity is formed in the second step portion of the first insulating layer.

4. The semiconductor device according to claim 1 , further comprising a second insulating layer between said gate electrode and said first insulating layer.

5. forming a semiconductor layer on a substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode having a first step portion on the gate insulating layer; forming a first insulating layer over the gate electrode; forming a sacrificial layer made of a material different from that of the first insulating layer on the first insulating layer; depositing a conductive layer on the sacrificial layer; A method for manufacturing a semiconductor device, comprising: etching at least a portion of the conductive layer and the sacrificial layer through a mask to form a pattern of the conductive layer.

6. The method for manufacturing a semiconductor device according to claim 5 , wherein the conductive layer is etched under an etching condition in which an etching rate of the first insulating layer is slower than an etching rate of the sacrificial layer.

7. the first insulating layer includes silicon oxide; The method for manufacturing a semiconductor device according to claim 5 , wherein the sacrificial layer includes silicon nitride.

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the conductive layer is etched under etching conditions in which a gas containing chlorine is used as a process gas.

9. 6. The method for manufacturing a semiconductor device according to claim 5, further comprising etching the conductive layer and the sacrificial layer so that the sacrificial layer remains between the conductive layer and the first insulating layer in a region that overlaps with the patterned conductive layer in a planar view.

10. forming the first insulating layer on the gate electrode such that a second step portion reflecting a shape of the first step portion of the gate electrode is formed in the first insulating layer, and a void is formed in the second step portion of the first insulating layer; 6. The method for manufacturing a semiconductor device according to claim 5, wherein when the sacrificial layer is deposited on the first insulating layer, the sacrificial layer is deposited so as to have a third step portion that reflects the shape of the second step portion of the first insulating layer.

11. forming the sacrificial layer on the first insulating layer so that a cavity is formed in the third step portion of the sacrificial layer; When the conductive layer is formed on the sacrificial layer, the conductive layer is formed so that a part of the conductive layer penetrates into the cavity; The method for manufacturing a semiconductor device according to claim 10 , wherein the part of the conductive layer that has entered the cavity is removed by etching the sacrificial layer.

12. forming a second insulating layer made of a material different from that of the first insulating layer on the gate electrode before forming the first insulating layer; The method for manufacturing a semiconductor device according to claim 5 , wherein the first insulating layer is formed on the second insulating layer.

13. 13. The method for manufacturing a semiconductor device according to claim 5, wherein the thickness of the sacrificial layer formed on the first insulating layer is not less than 50 nm and not more than 300 nm.

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