Device structure of semiconductor device, and method of manufacturing the same

Abstract

To reduce contact resistance in a semiconductor device by using a two-dimensional material for a contact.SOLUTION: The present invention relates to a device structure of a semiconductor device, and the device structure includes a two-dimensional material thin film, a source and a drain which are arranged at both ends of the two-dimensional material thin film and are thicker than the two-dimensional material thin film, a gate insulating film which is arranged on a principal surface of the two-dimensional material thin film between the source and the drain, and contact electrode layers which are respectively connected to the source and the drain, wherein the source and the drain are formed of a two-dimensional material.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a device structure of a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses techniques related to atomic layer deposition, particularly a method for forming a two-dimensional metal chalcogenide thin film using laser-assisted atomic layer deposition. In this patent document, a metal-containing molecular layer is adhered to the surface of a heated substrate using an atomic layer deposition (ALD) process. The metal-containing molecular layer is then reacted with a chalcogenide-containing radical precursor gas supplied using a plasma to form a two-dimensional amorphous metal chalcogenide thin film, which is then laser annealed to form a two-dimensional crystalline metal chalcogenide thin film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-61743 Summary of the Invention [Problem to be solved by the invention]

[0004] The technology according to the present disclosure reduces contact resistance by using two-dimensional materials for contacts in semiconductor devices. [Means for solving the problem]

[0005] One aspect of the present disclosure is a device structure of a semiconductor device, comprising: a two-dimensional material thin film; a source and a drain disposed at both ends of the two-dimensional material thin film and thicker than the two-dimensional material thin film; a gate insulating film disposed on a main surface of the two-dimensional material thin film between the source and the drain; and contact electrode layers connected to the source and the drain, respectively, wherein the source and the drain are made of a two-dimensional material. [Effects of the Invention]

[0006] According to the technology of the present disclosure, the contact resistance can be reduced by using a two-dimensional material for contacts in a semiconductor device. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a plan view showing an outline of the configuration of a wafer processing apparatus according to an embodiment of the present invention; [Figure 2] 1 is a schematic cross-sectional view of a device structure. [Figure 3] 1A to 1C are schematic cross-sectional views showing an example of a process for constructing a device structure. [Figure 4] FIG. 1 is a flow diagram showing an example of a process for constructing a device structure. [Figure 5] FIG. 10 is a schematic cross-sectional view of a device structure according to a first modified example. [Figure 6] FIG. 10 is a schematic cross-sectional view of a device structure according to a second modified example. [Figure 7] FIG. 11 is a schematic cross-sectional view of a device structure according to a third modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the manufacturing process of semiconductor devices, two-dimensional materials are attracting attention as semiconductor materials that can succeed silicon in breaking through the limits of miniaturization. For example, when using two-dimensional materials as the channel of a transistor, the surface of two-dimensional materials has fewer defects that adversely affect electrical conduction than silicon, and it is known that two-dimensional materials are useful in terms of electrical conduction.

[0009] Known two-dimensional materials include graphene and transition metal dichalcogenides (TMDCs) such as MoS2 (molybdenum sulfide), MoSe2 (molybdenum selenide), MoTe2 (molybdenum telluride), WSe2 (tungsten selenide), and WTe2 (tungsten telluride).When using two-dimensional materials as the channel of a transistor or the like, the two-dimensional material can be formed by transfer or CVD (chemical vapor deposition), and the conductive contact electrode layer that contacts the channel can be deposited by vacuum deposition.

[0010] However, transfer and CVD methods require a long time for film formation, and various equipment is required to build the laminated structure later, which poses challenges in terms of manufacturing cost and time. Furthermore, in semiconductor devices such as transistors, when two-dimensional materials are used as channels, the optimal combination with the contact electrode layer remains an issue, and there is a need to establish a method for building device structures using two-dimensional materials.

[0011] The technology disclosed herein has been developed in consideration of the above circumstances, and involves forming a transition metal-containing film on a substrate in advance, then annealing the transition metal-containing film to form a two-dimensional material thin film, and then manufacturing a semiconductor device using the same. In particular, in semiconductor devices such as transistors, the contact resistance between the channel and the source and / or drain can be reduced, thereby improving the performance of the device.

[0012] Hereinafter, a method for forming a two-dimensional material thin film according to this embodiment will be described with reference to the drawings. In this specification and the drawings, elements having substantially the same functional configurations are designated by the same reference numerals, and redundant explanations will be omitted.

[0013] <Wafer processing equipment> First, a wafer processing apparatus according to this embodiment will be described. Fig. 1 is a plan view showing the outline of the configuration of a wafer processing apparatus 1 according to this embodiment. In the wafer processing apparatus 1, processes such as etching, film formation, and heat treatment (annealing) are performed on a wafer W as a substrate.

[0014] 1, the wafer processing apparatus 1 has a configuration in which an atmospheric section 10 and a decompression section 11 are integrally connected via load lock modules 20 and 21. The atmospheric section 10 includes an atmospheric module that performs a desired process on a wafer W in an atmospheric pressure atmosphere. The decompression section 11 includes a decompression module that performs a desired process on a wafer W in a decompression atmosphere.

[0015] The load lock modules 20 and 21 are provided to connect a loader module 30 (described later) in the atmospheric section 10 to a transfer module 50 (described later) in the decompression section 11 via a gate valve (not shown). The load lock modules 20 and 21 are configured to temporarily hold a wafer W. The load lock modules 20 and 21 are also configured so that the interior thereof can be switched between an atmospheric pressure atmosphere and a decompression atmosphere (vacuum state).

[0016] The atmospheric section 10 has a loader module 30 equipped with a wafer transfer mechanism 40 (described later), and a load port 32 on which a FOUP 31 capable of storing a plurality of wafers W is placed. Note that an orienter module (not shown) for adjusting the horizontal orientation of the wafer W, a storage module (not shown) for storing a plurality of wafers W, and the like may be provided adjacent to the loader module 30.

[0017] The loader module 30 is made up of a rectangular housing, and the interior of the housing is maintained at atmospheric pressure. A plurality of, for example, five load ports 32 are arranged side by side on one side that constitutes the long side of the housing of the loader module 30. Load lock modules 20 and 21 are arranged side by side on the other side that constitutes the long side of the housing of the loader module 30.

[0018] A wafer transfer mechanism 40 that transfers a wafer W is provided inside the loader module 30. The wafer transfer mechanism 40 has a transfer arm 41 that holds and moves the wafer W, a rotary table 42 that rotatably supports the transfer arm 41, and a rotary table 43 on which the rotary table 42 is mounted. Also, a guide rail 44 that extends in the longitudinal direction of the loader module 30 is provided inside the loader module 30. The rotary table 43 is provided on the guide rail 44, and the wafer transfer mechanism 40 is configured to be movable along the guide rail 44.

[0019] The decompression section 11 has transfer modules 50 that simultaneously transport wafers W, and processing modules 60 that perform desired processing on the wafers W transported from the transfer modules 50. The interiors of the transfer modules 50 and the processing modules 60 are each maintained in a reduced pressure atmosphere. A plurality of processing modules 60, for example, six processing modules 60, are provided for one transfer module 50. In the following description, the six processing modules 60 may be referred to as processing modules 60a to 60f, respectively. Note that the number and arrangement of the processing modules 60 are not limited to those in this embodiment and can be set as desired.

[0020] The transfer module 50 is made up of a housing with a polygonal interior (pentagonal in the illustrated example), and is connected to the load lock modules 20 and 21 as described above. The transfer module 50 transports the wafer W loaded into the load lock module 20 to one of the processing modules 60, where the wafer W is subjected to the desired processing, and then transports the wafer W to the atmospheric section 10 via the load lock module 21.

[0021] The processing modules 60 perform processes such as etching, film formation, and heat treatment (annealing). The processing modules 60 can be arbitrarily selected to perform processes according to the purpose of wafer processing. The processing modules 60 are connected to the transfer module 50 via gate valves 61. In the following description, the six gate valves 61 may be referred to as gate valves 61a to 61f for the processing modules 60a to 60f, respectively.

[0022] A wafer transfer mechanism 70 for transferring a wafer W is provided inside the transfer module 50. The wafer transfer mechanism 70 has a transfer arm 71 that holds and moves the wafer W, a rotary table 72 that rotatably supports the transfer arm 71, and a rotary table 73 on which the rotary table 72 is mounted. Also, a guide rail 74 extending in the longitudinal direction of the transfer module 50 is provided inside the transfer module 50. The rotary table 73 is provided on the guide rail 74, and the wafer transfer mechanism 70 is configured to be movable along the guide rail 74.

[0023] In the transfer module 50, the transfer arm 71 receives the wafer W held in the load lock module 20 and transfers it to the processing module 60. The transfer arm 71 also holds the wafer W that has been subjected to the desired processing and transfers it out to the load lock module 21.

[0024] Next, a wafer processing performed using the wafer processing apparatus 1 configured as above will be described.

[0025] First, the FOUP 31 containing a plurality of wafers W is placed on the load port 32 .

[0026] Next, the wafer W is removed from the FOUP 31 by the wafer transfer mechanism 40 and loaded into the load lock module 20. Once the wafer W is loaded into the load lock module 20, the inside of the load lock module 20 is sealed and depressurized. Thereafter, the inside of the load lock module 20 and the inside of the transfer module 50 are connected to each other.

[0027] Next, the wafer W is held by the wafer transfer mechanism 70 and transferred from the load lock module 20 to the transfer module 50 .

[0028] Next, the gate valve 61 is opened, and the wafer W is loaded into the processing module 60 by the wafer transfer mechanism 70. Thereafter, the gate valve 61 is closed, and the desired processing is performed on the wafer W in the processing module 60. An example of the processing performed on the wafer W will be described later.

[0029] Next, the gate valve 61 is opened, and the wafer W is unloaded from the processing module 60 by the wafer transfer mechanism 70. Thereafter, the gate valve 61 is closed.

[0030] Next, the wafer W is loaded into the load lock module 21 by the wafer transfer mechanism 70. When the wafer W is loaded into the load lock module 21, the inside of the load lock module 21 is sealed and opened to the atmosphere. Thereafter, the inside of the load lock module 21 and the inside of the loader module 30 are connected to each other.

[0031] Next, the wafer W is held by the wafer transfer mechanism 40, and is returned from the load lock module 21 to the FOUP 31 via the loader module 30 and accommodated therein. In this way, a series of wafer processing steps in the wafer processing apparatus 1 is completed.

[0032] <Configuration of semiconductor device> 2 is a schematic cross-sectional view of a device structure 100 in which a two-dimensional material is used in a transistor as a semiconductor device. The device structure 100 has a two-dimensional material as a channel, which includes a so-called stacked nanosheet structure, and includes a source and a drain made of two-dimensional material provided on both sides.

[0033] As shown in FIG. 2, the device structure 100 includes an insulating film 102 formed on a wafer W, a two-dimensional material thin film 110 on its upper surface, and a source 120 and a drain 125 located on both sides of the insulating film 102. Between the source 120 and the drain 125, a gate insulating film 105 is formed on the upper surface of the two-dimensional material thin film 110, and a gate electrode layer 128 is formed on the upper surface of the gate insulating film 105. Contact electrode layers 130 are formed on the upper portions of the source 120 and the drain 125. While the present embodiment describes a case where the layers are stacked vertically, this is not limiting. While FIG. 2 describes a case where the gate insulating film 105 is formed on the upper surface of the two-dimensional material thin film 110, the stacking direction is arbitrary, and the surface on which other films are formed (here, the upper surface) may be referred to as the "main surface."

[0034] The gate insulating film 105 may be made of any material, and may be made of a high-dielectric-constant material such as SiZrO2 or HfO2. In a field-effect transistor with a general structure, a current flowing from the source 120 to the drain 125 is controlled by the two-dimensional material thin film 110.

[0035] The thickness T1 of the source 120 and the drain 125 is greater than the thickness T2 of the two-dimensional material thin film 110. In one embodiment, the thickness T1 of the source 120 and the drain 125 is 10 nm to 25 nm, and the thickness T2 of the two-dimensional material thin film 110 is 0.7 nm to 2.1 nm. Due to this thickness difference, the source 120 and the drain 125 have a lower resistance than the two-dimensional material thin film 110, thereby reducing the contact resistance in the device structure 100.

[0036] The two-dimensional material thin film 110 is obtained by annealing a transition metal-containing film in a chalcogen atmosphere to chalcogenize it. Similarly, the source 120 and the drain 125 are obtained by annealing a transition metal-containing film in a chalcogen atmosphere to chalcogenize it. The material of the transition metal-containing film can be any material as long as it contains a transition metal such as Mo or W. It can be an oxide containing Mo, W, Nb, or Hf, or a nitride containing Mo, W, Nb, or Hf, such as MoO3, Mo2N, W2O3, or WN.

[0037] In one embodiment, the two-dimensional material thin film 110 may be formed of MoS2, and the source 120 and drain 125 may be formed of NbS2 or HfS. The source 120 and drain 125 may be doped with a metal such as niobium to increase conductivity. The two-dimensional material thin film 110 and the source 120 and drain 125 may be formed of the same two-dimensional material or different two-dimensional materials.

[0038] The conditions for the annealing process in the chalcogen atmosphere are not particularly limited. For example, in a module among the multiple process modules 60 that performs the annealing process, the processing chamber into which the target wafer W is loaded is purged with Ar, and the chalcogen source is continuously supplied from the start of the temperature rise, and the annealing process is performed. As an example, the annealing process may be performed under the conditions of atmospheric pressure, Ar as a diluent gas, a partial pressure of the chalcogen source of about 1%, and a temperature of 800°C.

[0039] Any chalcogen raw material may be used, and may include, for example, a material containing sulfur (S), selenium (Se), or tellurium (Te) as chalcogen. Specific examples include H2S, H2Se, and H2Te.

[0040] The layers of the device structure 100 may be formed by any method, including physical vapor deposition (PVD). Vapor Deposition), ALD (Atomic Layer) The film may be formed by a method such as Chemical Vapor Deposition (CVD), vacuum deposition, or sputtering.

[0041] <Device structure construction method> The processing module 60 can perform various processes on the wafer W, such as a film formation process, an etching process, and a heat treatment (hereinafter also referred to as an annealing process). As an example, the process of constructing a device structure 100 on the wafer W will be described below with reference to the drawings. When multiple, e.g., six, processing modules 60a to 60f are provided as shown in FIG. 1 , a module for forming a stacked structure on the wafer W or a module for performing an annealing process may be arbitrarily selected from the multiple processing modules 60. For example, the stacked structure formation process may be performed in at least one of the multiple processing modules 60, and the annealing process may be performed in another processing module 60. Furthermore, each processing step may be performed in a different processing module 60, or may be performed consecutively in the same processing module 60. That is, the wafer processing apparatus 1 including the processing modules 60 may function as a forming apparatus for forming each layer, such as the two-dimensional material thin film 110, the gate insulating film 105, the source 120, the drain 125, and the gate electrode layer 128.

[0042] Fig. 3 is a schematic cross-sectional view showing an example of a process for constructing a device structure 100 using a two-dimensional material, and Fig. 4 is a flow chart showing an example of a process for constructing a device structure 100 using a two-dimensional material.

[0043] First, as shown in Fig. 3(a), a wafer W is prepared, and an insulating film 102 such as SiO2 is formed on the upper surface of the wafer W (step S1). If the surface of the wafer W is insulating, step S1 may be omitted. Then, as shown in Fig. 3(b), a transition metal-containing film (not shown) corresponding to the two-dimensional material thin film 110 is formed (step S2), and the transition metal-containing film is annealed and altered in a chalcogen atmosphere to form the two-dimensional material thin film 110 (step S3).

[0044] 3(c), a transition metal-containing film (not shown) corresponding to the source 120 and the drain 125 is formed so as to be connected to both ends of the two-dimensional material thin film 110 (step S4), and the transition metal-containing film is annealed and transformed in a chalcogen atmosphere to form the source 120 and the drain 125 (step S5). The source 120 and the drain 125 may be formed so as to overlap part or all of both ends of the two-dimensional material thin film 110 in a top view, or may be formed so as to be adjacent and electrically connected.

[0045] In one embodiment, in forming the transition metal-containing film corresponding to the source 120 and the drain 125 (step S4) and annealing the transition metal-containing film, the following method is preferably employed to obtain a desired film thickness. That is, the thickness of the two-dimensional material thin film formed after the annealing process can be varied depending on the composition ratio of the transition metal and compound element contained in the transition metal-containing film. For example, if the transition metal-containing film is made of an oxide containing Mo and the composition of the transition metal-containing film is MoO X When expressed as: by changing the value of X according to the target thickness of the two-dimensional material thin film 110, the film thickness of the two-dimensional material thin film 110 that is actually formed can be varied to some extent.

[0046] Specifically, the composition of the transition metal-containing film is MoO X When the target thickness of the two-dimensional material thin film 110 is 10 nm, setting the value of X to 1.8 or more will result in a two-dimensional material thin film 110 that is relatively thicker than the target thickness, that is, approximately 10 nm or more. When the target thickness of the two-dimensional material thin film 110 is 20 nm, setting the value of X to 2.3 or more will result in a two-dimensional material thin film 110 that is relatively thicker than the target thickness, that is, approximately 20 nm or more. When the target thickness of the two-dimensional material thin film 110 is 30 nm, setting the value of X to 2.7 or more will result in a two-dimensional material thin film 110 that is relatively thicker than the target thickness, that is, approximately 30 nm or more.

[0047] Next, as shown in Fig. 3(d), a gate insulating film 105 is formed on the upper surface of the two-dimensional material thin film 110 (step S6). Then, as shown in Fig. 3(e), a gate electrode layer 128 is formed on the upper surface of the gate insulating film 105, and contact electrode layers 130 are formed on the source 120 and the drain 125, respectively (step S7). In this manner, the device structure 100 is constructed.

[0048] 3 and 4, the two-dimensional material thin film 110 and the source 120 and drain 125 are formed by annealing at different times, but the present invention is not limited to this. For example, the transition metal-containing film corresponding to the two-dimensional material thin film 110 and the transition metal-containing films corresponding to the source 120 and drain 125 may be formed at the same time and annealed together in a chalcogen atmosphere. This method is particularly useful when the two-dimensional material thin film 110 and the source 120 and drain 125 are made of the same two-dimensional material.

[0049] <Effects of the technology of the present disclosure> As described above, according to the manufacturing method and manufacturing apparatus for a semiconductor device including the device structure 100 according to the technology of the present disclosure, in addition to forming the channel from the two-dimensional material thin film 110, the source 120 and the drain 125 are also made of two-dimensional material. This allows the use of two-dimensional materials for contacts in the semiconductor device, thereby reducing contact resistance. Contact resistance at the interface between a typical metal electrode and a two-dimensional material thin film is high, which can hinder the improvement of device performance such as a transistor. That is, for example, when the semiconductor device is a field-effect transistor, adopting the above-described configuration can improve the performance of the transistor.

[0050] In particular, in the above embodiment, the device structure 100 is configured such that the thickness T1 of the source 120 and the drain 125 is larger than the thickness T2 of the two-dimensional material thin film 110. Specifically, the thickness T1 of the source 120 and the drain 125 is 10 nm to 25 nm, while the thickness T2 of the two-dimensional material thin film 110 is 0.7 nm to 2.1 nm. With this configuration, it is possible to reduce the resistance between the source 120 and the drain 125 and the two-dimensional material thin film 110 serving as a channel, thereby reducing the contact resistance.

[0051] <Modification> Modifications of the present disclosure will be described below with reference to the drawings. In the following description, components having the same functional configuration as those described in the above embodiment will be denoted by the same reference numerals, and their description may be omitted.

[0052] (First Modification) 5 is a schematic cross-sectional view of a device structure 100a according to the first modification. In the above embodiment, the contact electrode layer 130 is formed on each of the source 120 and the drain 125 (see FIG. 2), but the configuration of the contact electrode layer 130 is not limited to this. That is, if the source 120 and the drain 125 are made of a two-dimensional material and have a certain thickness, there may be a problem in supplying current to the semiconductor device 100.

[0053] 5, holes 140 extending inward in the thickness direction may be formed in the source 120 and the drain 125, and the contact electrode layer 130a may be configured to be partially embedded in the holes 140. The depth of the holes 140 may be designed arbitrarily, and may be designed according to the state of current supply in the semiconductor device 100a, for example.

[0054] According to this modification, a sufficient current is supplied between the source and drain of the semiconductor device 100a, and when the semiconductor device is a field effect transistor, for example, the performance of the transistor is improved.

[0055] (Second Modification) 6 is a schematic cross-sectional view of a device structure 100b according to the second modification. In the above embodiment, the source 120 and the drain 125 are formed on both sides of the two-dimensional material thin film 110, but the present invention is not limited to this.

[0056] 6, in the device structure 100b, a source 120 and a drain 125 are formed on both upper surfaces of the two-dimensional material thin film 110. In the configuration according to this modification, the transition metal-containing film corresponding to the two-dimensional material thin film 110 and the transition metal-containing films corresponding to the source 120 and the drain 125 can be easily formed.

[0057] (Third Modification) 7 is a schematic cross-sectional view of a device structure 100c according to Modification 3. In the device structure 100 according to the above embodiment, the channel has a so-called single-layer channel structure, but the channel structure is not limited to this.

[0058] 7, in the device structure 100c, the channel has a so-called multi-layer channel structure. That is, as shown in the figure, the two-dimensional material thin film 110 is configured in multiple layers (three layers in the illustrated configuration). Specifically, between the source 120 and the drain 125, the two-dimensional material thin film 110 is formed on the insulating film 102, a gate insulating film 105 is formed on the upper surface thereof, a gate electrode layer 128 is formed on the upper surface thereof, and a gate insulating film 105 is formed on the upper surface thereof. Then, such a configuration in which the two-dimensional material thin film 110, the gate insulating film 105, and the gate electrode layer 128 are stacked is repeated multiple times to form a multi-layer structure.

[0059] According to this modification, a semiconductor device including a device structure 100c, which is a so-called multi-layer channel structure, is manufactured, which provides the same effects as those of the above embodiment and, further, when the semiconductor device is a field-effect transistor, improves performance and efficiency.

[0060] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims. For example, the components of the above-described embodiments may be arbitrarily combined. Such an arbitrary combination naturally provides the functions and effects of each of the components involved in the combination, and also provides other functions and effects that are apparent to those skilled in the art from the description of this specification.

[0061] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that would be apparent to a person skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0062] Note that the following configuration examples also fall within the technical scope of the present disclosure. (1) A device structure of a semiconductor device, A two-dimensional material thin film, a source and a drain disposed on both ends of the two-dimensional material thin film and having a thickness greater than that of the two-dimensional material thin film; a gate insulating film disposed on a major surface of the two-dimensional material thin film between the source and the drain; contact electrode layers connected to the source and the drain, respectively; A device structure of a semiconductor device, wherein the source and the drain are composed of a two-dimensional material. (2) the thickness of the two-dimensional material thin film is 0.7 nm to 2.1 nm; 2. The device structure of a semiconductor device according to claim 1, wherein the thickness of the source and the drain is 10 nm to 25 nm. (3) A device structure of a semiconductor device described in (1) or (2), in which contact electrode layers formed on the top of the source and the drain, respectively, are configured so that a portion of each is embedded in a hole formed in the source and the drain so as to extend to the inside in the thickness direction. (4) A device structure of a semiconductor device described in any one of (1) to (3), wherein the two-dimensional material thin film, the gate insulating film, and the contact electrode layer are formed in multiple layers between the source and the drain, forming a multi-layer channel structure. (5) A method for manufacturing a device structure included in a semiconductor device, comprising: forming a transition metal-containing film on a substrate and annealing the film in a chalcogen atmosphere to form a two-dimensional material thin film; forming a transition metal-containing film corresponding to a source and a drain on both ends of the two-dimensional material thin film, and annealing the film in a chalcogen atmosphere to form the source and the drain; forming a gate insulating film on the main surface of the two-dimensional material thin film between the source and the drain; and forming a contact electrode layer connected to the source and the drain. (6) A method for manufacturing a device structure according to (5), wherein a transition metal-containing film corresponding to the two-dimensional material thin film and a transition metal-containing film corresponding to the source and the drain are formed at the same time and annealed together in a chalcogen atmosphere. [Explanation of symbols]

[0063] 100 Device Structure 105 Gate insulating film 110 Two-dimensional thin film materials 120 sauce 125 Drain 130 Contact electrode layer

Claims

1. A device structure of a semiconductor device, comprising: a two-dimensional material thin film; a source and a drain disposed on both ends of the two-dimensional material thin film and having a thickness greater than that of the two-dimensional material thin film; a gate insulating film disposed on a major surface of the two-dimensional material thin film between the source and the drain; contact electrode layers connected to the source and the drain, respectively; A device structure of a semiconductor device, wherein the source and the drain are composed of a two-dimensional material.

2. the thickness of the two-dimensional material thin film is 0.7 nm to 2.1 nm; 2. The device structure of claim 1, wherein the thickness of the source and the drain is 10 nm to 25 nm.

3. 2. The device structure of a semiconductor device according to claim 1, wherein the contact electrode layers connected to the source and the drain, respectively, are configured so as to be partially embedded in holes extending to the inside of the source and the drain in a thickness direction.

4. The device structure of a semiconductor device according to claim 1 , wherein the two-dimensional material thin film and the gate insulating film are arranged in a plurality of layers between the source and the drain, thereby forming a multi-layer channel structure.

5. 1. A method for manufacturing a device structure included in a semiconductor device, comprising: forming a transition metal-containing film on a substrate and annealing the film in a chalcogen atmosphere to form a two-dimensional material thin film; forming a transition metal-containing film corresponding to a source and a drain on both ends of the two-dimensional material thin film, and annealing the film in a chalcogen atmosphere to form the source and the drain; forming a gate insulating film on the major surface of the two-dimensional material thin film between the source and the drain; and forming a contact electrode layer connected to the source and the drain.

6. 6. The method for manufacturing a device structure according to claim 5, wherein a transition metal-containing film corresponding to the two-dimensional material thin film and a transition metal-containing film corresponding to the source and the drain are formed at the same time and annealed together in a chalcogen atmosphere.

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