Display device

Abstract

To provide a display device capable of reducing power consumption.SOLUTION: A display device includes: a first transistor connected between an image data signal line through which a data voltage is supplied and a first node while switching is controlled by using a first control signal; a third transistor connected between the first node and a second node while switching is controlled by using the first control signal; a second transistor that has a gate electrode connected to the second node and is connected between a power line through which a constant voltage is supplied and a third node; a fourth transistor connected between a reference voltage power line through which a reference voltage is supplied and the second node while switching is controlled by using the first control signal; and a fifth transistor connected between an initialization voltage power line through which an initialization voltage is supplied and the third node while switching is controlled by using a second control signal different from the first control signal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, self-luminous display devices have become widespread and are implemented in televisions, smartphones, digital signage (electronic billboards, electronic advertising boards, etc.). A self-luminous display device includes, for example, a plurality of pixels and a control circuit for driving the plurality of pixels. Each of the plurality of pixels includes, for example, a plurality of transistors, a capacitance element, and a light-emitting element. The light-emitting element is an element that emits light in a self-luminous manner, such as a light-emitting diode (LED), a micro-light-emitting diode (micro LED), or an organic electroluminescence (EL) element. In a self-luminous display device, a control circuit supplies a voltage to each of the plurality of pixels, causing a current corresponding to the supplied voltage value to flow through the light-emitting element included in each of the plurality of pixels. Each light-emitting element emits light at a brightness corresponding to the current flowing through the light-emitting element, and the pixel including the light-emitting element can display an image with a gradation corresponding to the brightness.

[0003] For example, Patent Document 1 discloses an EL display device that addresses the issue of increasing the luminance of an EL element during the lighting period, which increases power consumption and circuit size, by focusing on the rounding of the pulse waveform and reducing the drain current of the drive transistor, thereby enabling appropriate threshold correction operation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-164133 Summary of the Invention [Problem to be solved by the invention]

[0005] As exemplified in Patent Document 1, self-luminous display devices including EL display devices have the problem of large power consumption and circuit scale. Therefore, for example, a challenge for self-luminous display devices is to reduce power consumption. Another challenge for self-luminous display devices is to reduce circuit scale.

[0006] In view of the above, an object of one embodiment of the present invention is to provide a display device that can reduce power consumption and a display device that can reduce the circuit scale. [Means for solving the problem]

[0007] a third transistor whose switching is controlled by the first control signal and electrically connected between the first node and a second node; a second transistor whose gate electrode is electrically connected to the second node and electrically connected between a power supply line to which a constant voltage is supplied and the third node; a fourth transistor whose switching is controlled by the first control signal and electrically connected between the second node and a reference voltage power supply line to which a reference voltage is supplied; a fifth transistor whose switching is controlled by a second control signal different from the first control signal and electrically connected between the third node and an initialization voltage power supply line to which an initialization voltage is supplied; a light-emitting element electrically connected to the third node; and a capacitive element electrically connected between the first node and the third node.

[0008] A display device according to one embodiment of the present invention includes a first transistor whose switching is controlled by a first control signal and electrically connected between a first node and an image data signal line to which a data voltage is supplied; a third transistor whose switching is controlled by the first control signal and electrically connected between the first node and a third node; a second transistor having a gate electrode electrically connected to the second node and electrically connected between the third node and a fourth node; a third control signal line whose switching is controlled by the first control signal and to which a first initialization voltage and a second initialization voltage different from the first initialization voltage are supplied; a fourth transistor electrically connected between a third control signal line and the fourth node, a fifth transistor whose switching is controlled by a second control signal different from the first control signal and electrically connected between a third control signal line and the fourth node, a sixth transistor whose switching is controlled by the first control signal and electrically connected between the second node and the fourth node, a seventh transistor whose switching is controlled by the first control signal and electrically connected between a power supply line to which a constant voltage is supplied and the fourth node, a light-emitting element electrically connected to the third node, and a capacitive element electrically connected between the first node and the second node. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram showing the configuration of a self-luminous display device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram showing input signals to a pixel circuit according to the first embodiment of the present invention. [Figure 3] 1 is a circuit diagram showing a configuration of a pixel circuit according to a first embodiment of the present invention. [Figure 4] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 5] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 6]3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 7] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 8] 3 is a timing chart of the self-luminous display device according to the first embodiment of the present invention. [Figure 9] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view showing a cross section taken along A1-A2 in the layout shown in FIG. [Figure 11] 3 is a sequence diagram showing a method for manufacturing the self-luminous display device according to the first embodiment of the present invention. FIG. [Figure 12] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 13] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 14] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 15] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a second embodiment of the present invention. [Figure 16] FIG. 4 is a circuit diagram showing a configuration of a pixel circuit according to a second embodiment of the present invention. [Figure 17] 10 is a timing chart of a self-luminous display device according to a second embodiment of the present invention. [Figure 18] 10 is a timing chart of a self-luminous display device according to a second embodiment of the present invention. [Figure 19] 10 is a timing chart of a self-luminous display device according to a second embodiment of the present invention. [Figure 20] 10 is a timing chart of a self-luminous display device according to a second embodiment of the present invention. [Figure 21] FIG. 10 is a diagram illustrating the setting of an input signal according to the second embodiment of the present invention. [Figure 22] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a third embodiment of the present invention. [Figure 23]FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a third embodiment of the present invention. [Figure 24] 10 is a timing chart of a self-luminous display device according to a third embodiment of the present invention. [Figure 25] 10 is a timing chart of a self-luminous display device according to a third embodiment of the present invention. [Figure 26] 10 is a timing chart of a self-luminous display device according to a third embodiment of the present invention. [Figure 27] 10 is a timing chart of a self-luminous display device according to a third embodiment of the present invention. [Figure 28] FIG. 10 is a diagram illustrating the setting of an input signal according to the third embodiment of the present invention. [Figure 29] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a fourth embodiment of the present invention. [Figure 30] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a fourth embodiment of the present invention. [Figure 31] 10 is a timing chart of a self-luminous display device according to a fourth embodiment of the present invention. [Figure 32] 32 is a schematic diagram showing the operating state of the pixel circuit shown in FIG. 30 at the timing shown in FIG. 31. [Figure 33] 32 is a schematic diagram showing the operating state of the pixel circuit shown in FIG. 30 at the timing shown in FIG. 31. [Figure 34] 10 is a timing chart of a self-luminous display device according to a fourth embodiment of the present invention. [Figure 35] 35 is a schematic diagram showing the operation state of the pixel circuit shown in FIG. 30 at the timing shown in FIG. 34. [Figure 36] 10 is a timing chart of a self-luminous display device according to a fourth embodiment of the present invention. [Figure 37] 10 is a timing chart of a self-luminous display device according to a fourth embodiment of the present invention. [Figure 38] FIG. 11 is a schematic diagram showing input signals to a pixel circuit according to a fifth embodiment of the present invention. [Figure 39]FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a fifth embodiment of the present invention. [Figure 40] 10 is a timing chart of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 41] 41 is a schematic diagram showing the operating state of the pixel circuit shown in FIG. 39 at the timing shown in FIG. 40. [Figure 42] 41 is a schematic diagram showing the operating state of the pixel circuit shown in FIG. 39 at the timing shown in FIG. 40. [Figure 43] 10 is a timing chart of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 44] 44 is a schematic diagram showing the operating state of the pixel circuit shown in FIG. 39 at the timing shown in FIG. 43. [Figure 45] 10 is a timing chart of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 46] 10 is a timing chart of a self-luminous display device according to a fifth embodiment of the present invention. [Figure 47] FIG. 13 is a schematic diagram showing input signals to a pixel circuit according to a sixth embodiment of the present invention. [Figure 48] FIG. 10 is a circuit diagram showing the configuration of a pixel circuit according to a sixth embodiment of the present invention. [Figure 49] 10 is a timing chart of a self-luminous display device according to a sixth embodiment of the present invention. [Figure 50] 10 is a timing chart of a self-luminous display device according to a sixth embodiment of the present invention. [Figure 51] 10 is a timing chart of a self-luminous display device according to a sixth embodiment of the present invention. [Figure 52] 10 is a timing chart of a self-luminous display device according to a sixth embodiment of the present invention. [Figure 53] FIG. 13 is a schematic diagram showing input signals to a pixel circuit according to a seventh embodiment of the present invention. [Figure 54] FIG. 12 is a circuit diagram showing a configuration of a pixel circuit according to a seventh embodiment of the present invention. [Figure 55]13 is a timing chart of a self-luminous display device according to a seventh embodiment of the present invention. [Figure 56] 13 is a timing chart of a self-luminous display device according to a seventh embodiment of the present invention. [Figure 57] 13 is a timing chart of a self-luminous display device according to a seventh embodiment of the present invention. [Figure 58] 13 is a timing chart of a self-luminous display device according to a seventh embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, configuration, etc. of each part schematically compared to the actual form, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element, and have no other meaning unless otherwise specified.

[0011] Furthermore, in this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0012] For example, a display device according to one embodiment of the present invention is a display device that uses EL elements as self-luminous light-emitting elements. For example, a display device that uses EL elements may be called a self-luminous display device, an EL display device, or the like. For example, in the embodiment of the present invention, a display device that uses EL elements is called a self-luminous display device.

[0013] 1. First Embodiment <1-1. Overview of the self-luminous display device 10> An overview of a self-luminous display device 10 according to the first embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing the configuration of the self-luminous display device 10. The configuration of the self-luminous display device 10 shown in Fig. 1 is an example, and the configuration of the self-luminous display device 10 is not limited to the configuration shown in Fig. 1.

[0014] The self-emissive display device 10 includes an array substrate 100, a flexible printed circuit board 160 (FPC 160), and an IC chip 110. The self-emissive display device 10 also includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0015] In the display region 22, a plurality of pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. The pixel 180 is the smallest unit that constitutes part of an image displayed in the display region 22. For example, each of the plurality of pixels 180 may correspond to a sub-pixel R, a sub-pixel G, or a sub-pixel B. One pixel may also be formed by three sub-pixels. There are no limitations on the arrangement of the pixels 180, and the arrangement of the plurality of pixels 180 may be, for example, a stripe arrangement. The arrangement of the self-luminous display device 10 may be a delta arrangement, a pentile arrangement, or the like.

[0016] The sub-pixels R, G, and B are configured to display images of different colors. For example, each of the sub-pixels R, G, and B may include a light-emitting element including a light-emitting layer that emits the three primary colors of red, green, and blue. When a desired voltage or current is supplied to each of the three sub-pixels, the self-emissive display device 10 can display an image.

[0017] The peripheral region 24 is provided with an IC chip 110, a first scan driver 120, and a second scan driver 130. The IC chip 110 is connected to the terminal section 150 using connection wiring 341. The first scan driver 120 and the second scan driver 130 are each connected to the IC chip 110 using connection wiring 342. The peripheral region 24 is sometimes referred to as a frame region. The connection wiring 341 may be referred to individually as connection wiring 341, and a bundle of multiple connection wirings 341 may be referred to as connection wiring 341. Like the connection wiring 341, the connection wiring 342 may be referred to individually as connection wiring 342, and a bundle of multiple connection wirings 342 may be referred to as connection wiring 342.

[0018] The terminal region 26 is provided with a terminal portion 150 and an FPC 160 electrically connected to the terminal portion 150. The terminal region 26 is on the opposite side of the peripheral region 24 in the first direction D1 from the region in which the display region 22 is provided.

[0019] The FPC 160 is connected to an external device (not shown) outside the self-luminous display device 10. Therefore, the self-luminous display device 10 is connected to the external device via the FPC 160 and the terminal section 150 connected to the FPC. Control signals and voltages are transmitted from the external device to the self-luminous display device 10 via the FPC 160 and the terminal section 150 connected to the FPC. The self-luminous display device 10 drives each pixel 180 provided in the self-luminous display device 10 using the control signals and voltages received from the external device. As a result, the self-luminous display device 10 can display an image in the display region 22.

[0020] The IC chip 110 supplies signals, voltages, etc. for driving each pixel 180 to the first scan driver 120, the second scan driver 130, and each pixel 180 (pixel circuit 181) via the FPC 160, the terminal section 150, and the connection wiring 341.

[0021] In this specification and drawings, each of the IC chip 110, the first scan driver 120, the second scan driver 130, and the IC chip 110 may be referred to individually as a control circuit, and a group of circuits including some or all of the IC chip 110, the first scan driver 120, the second scan driver 130, and the IC chip 110 may be referred to as a control circuit.

[0022] <1-2. Configuration of IC chip 110> 1, an overview of the IC chip 110 will be described. The IC chip 110 is provided at a position adjacent to the display area 22 in the first direction D1. Image data signal lines 321, 322, and 323 extend from the IC chip 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0023] For example, the IC chip 110 includes a plurality of selection circuits (not shown). For example, each of the plurality of selection circuits is a switch controlled based on an on signal and an off signal supplied to the selection signal. The selection circuit is selected by an on signal supplied to the selection signal, and supplies an image data signal SL(m) including a data signal VDATA to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321. The selection signal and the image data signal SL(m) are transmitted from an external device to the IC chip 110 via the FPC 160 and the terminal unit 150 connected to the FPC.

[0024] For example, an on signal is a signal including a voltage that turns on a selection circuit (switch), and an off signal is a signal including a voltage that turns off the selection circuit (switch). In the present invention, the on signal may be a high-level voltage (potential) (high, High, HI) and the off signal may be a low-level voltage (potential) (low, Low, LO), or the on signal may be a low-level voltage (potential) (low, Low, LO) and the off signal may be a high-level voltage (potential) (high, High, HI). A high-level voltage is greater (higher) than a low-level voltage. In the self-luminous display device according to the embodiments in this specification, as an example, the on signal is a high-level voltage and the off signal is a low-level voltage.

[0025] <1-3. Configuration of the first scan driver 120> 1, an overview of the first scan driver 120 will be described. The first scan driver 120 is provided at a position adjacent to the display area 22 in the second direction D2. First scan signal lines 329, 330, 331, and 332 extend from the first scan driver 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. For example, the first scan driver 120 is a so-called gate driver.

[0026] The first scan driver 120 includes multiple shift registers (e.g., shift registers 111, 112, and 113). The shift registers 111, 112, and 113 sequentially supply first scan signals (e.g., first scan signal SC1(n), first scan signal SC1(n+1), first scan signal SC1(n+2)), etc.) with different timings to the first scan signal lines 330, 331, and 332, respectively, based on control signals such as a clock signal and a start pulse supplied from the IC chip 110, thereby driving the pixels 180 (pixel circuits 181) electrically connected to each first scan signal line. The first scan signal SC1(n) may be referred to as a first control signal. For example, the first scan signal and the first scan signal line are so-called scan signals and scan signal lines.

[0027] For example, the shift register 111 is electrically connected to the shift register 112, and the shift register 112 is electrically connected to the shift register 113. The shift register 111 is electrically connected to a first scan signal line 330 and supplies, for example, a first scan signal SC1(n) to the first scan signal line 330. Like the shift register 111, the shift register 112 is electrically connected to a first scan signal line 331 and supplies, for example, a first scan signal SC1(n+1) to the first scan signal line 331, and the shift register 113 is electrically connected to a first scan signal line 332 and supplies, for example, a first scan signal SC1(n+2) to the first scan signal line 332. The first scan signal SC1(n+1) has a pulse width equivalent to that of the first scan signal SC1(n) and is a signal obtained by shifting the first scan signal SC1(n). Like the first scan signal SC1(n+1), the first scan signal SC1(n+2) has a pulse width equivalent to that of the first scan signal SC1(n+1) and is a shifted version of the first scan signal SC1(n+1).

[0028] <1-4. Configuration of the second scan driver 130> 1, an overview of the second scan driver 130 will be described. The second scan driver 130 is adjacent to the display area 22 in the second direction D2 and is provided on the opposite side of the display area 22 from the position where the first scan driver 120 is disposed. Second scan signal lines 334, 335, and 336 extend from the second scan driver 130 in the second direction D2 and are connected to a plurality of pixels 180 (pixel circuits 181) arranged in the second direction D2.

[0029] Similar to the first scan driver 120, the second scan driver 130 includes multiple shift registers (e.g., shift registers 161, 162, and 163). The shift registers 161, 162, and 163 sequentially supply second scan signals (e.g., second scan signal SC2(n), second scan signal SC2(n+1), second scan signal SC2(n+2)), etc.) with different timings to the second scan signal lines 334, 335, and 336, respectively, based on control signals such as a clock signal and a start pulse supplied from the IC chip 110, thereby driving the pixels 180 (pixel circuits 181) electrically connected to the respective second scan signal lines. The second scan signal SC2(n) may also be referred to as a second control signal.

[0030] For example, the shift register 161 is electrically connected to the shift register 162, and the shift register 162 is electrically connected to the shift register 163. The shift register 161 is electrically connected to the second scan signal line 334 and supplies, for example, a second scan signal SC2(n) to the second scan signal line 334. Like the shift register 161, the shift register 162 is electrically connected to the second scan signal line 335 and supplies, for example, a second scan signal SC2(n+1) to the second scan signal line 335, and the shift register 163 is electrically connected to the second scan signal line 336 and supplies, for example, a second scan signal SC2(n+2) to the second scan signal line 336. The pulse width of the second scan signal SC2(n+1) is the same as that of the second scan signal SC2(n), and the second scan signal SC2(n+1) is a signal obtained by shifting the second scan signal SC2(n). Similarly, the pulse width of the second scan signal SC2(n+2) is the same as that of the second scan signal SC2(n+1), and the second scan signal SC2(n+2) is a signal obtained by shifting the second scan signal SC2(n+2).

[0031] <1-5. Configuration of pixel 180> An overview of the pixel 180 and the pixel circuit 181 will be described with reference to FIGS. 1 to 3. FIG. 2 is a schematic diagram showing input signals to the pixel circuit 181 included in the pixel 180. FIG. 3 is a circuit diagram showing the configuration of the pixel circuit 181. FIGS. 2 and 3 show, as an example, the configuration of the pixel circuit 181 of the pixel 180 shown in FIG. 1. The configurations of the pixel 180 and the pixel circuit 181 are not limited to those shown in FIGS. 1 to 3. Configurations that are the same as or similar to those in FIG. 1 will be described as necessary.

[0032] The pixel circuit 181 is a circuit for driving the pixel 180. The pixel circuits of the sub-pixels R, G, and B included in the pixel 180 are similar to the pixel circuit 181, but the colors emitted by the light-emitting element OLED are different. In the following description, a light-emitting element OLED that emits red light will be described as an example.

[0033] 2, a first scan signal SC1(n), an image data signal SL(m), a second scan signal SC2(n), a reference voltage VREF, and an initialization voltage VINI are supplied to the pixel circuit 181. In addition, a drive voltage VDDEL and a reference voltage VSSEL are supplied to the pixel circuit 181 as power supplies for driving the pixel 180. For example, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL may be constant voltages or variable voltages that fluctuate according to the timing of each signal.

[0034] The reference voltage VREF is supplied to the reference voltage power line SVR, the initialization voltage VINI is supplied to the initialization voltage power line SVI, the drive voltage VDDEL is supplied to the drive power line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS. For example, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the reference voltage line PVSS are each electrically connected to a different connection wiring 342. Also, for example, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the reference voltage line PVSS may each be a different connection wiring 342.

[0035] For example, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from an external device to the IC chip 110 via the FPC 160, the terminal unit 150, and the connection wiring 341. Also, for example, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from the IC chip 110 to the plurality of pixels 180 (pixel circuits 181) via the connection wiring 342, the reference voltage power supply line SVR, the initialization voltage power supply line SVI, the drive power supply line PVDD, and the reference voltage line PVSS. Although not shown, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the standard voltage VSSEL may be connected to the reference voltage power supply line SVR, the initialization voltage power supply line SVI, the drive power supply line PVDD, and the standard voltage line PVSS from an external device via the FPC 160, the terminal unit 150, and the connection wiring 341, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to the plurality of pixels 180 (pixel circuits 181). For example, the reference voltage VREF, the initialization voltage VINI, and the standard voltage VSSEL are smaller than the drive voltage VDDEL.

[0036] 3, the pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a capacitance element CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (a source electrode and a drain electrode) consisting of a first electrode and a second electrode. Each of the capacitance element CS and the light-emitting element OLED includes a pair of electrodes consisting of a first electrode and a second electrode.

[0037] For example, the first transistor T1 is a selection transistor. The first transistor T1 has a function of supplying an image data signal SL(m) to the first node N1.

[0038] For example, the second transistor T2 is a drive transistor. The threshold voltage VTH of the second transistor T2 is corrected based on the reference voltage VREF and the initialization voltage VINI. Furthermore, the second transistor T2 controls the connection / disconnection between the drive power supply line PVDD and the light-emitting element OLED based on the corrected threshold voltage VTH and the input image data signal SL(m). That is, the second transistor T2 has the function of supplying the drive voltage VDDEL to the light-emitting element OLED and causing a current to flow therethrough, thereby causing the light-emitting element OLED to emit light.

[0039] The third transistor T3 has a function of connecting the first node N1 and the second node N2 and supplying the image data signal SL(m) to the second node N2.

[0040] The fourth transistor T4 has a function of connecting the second node N2 and the reference voltage power supply line SVR to each other, supplying the reference voltage VREF to the second node N2, and initializing the second node N2.

[0041] The fifth transistor T5 has a function of connecting the third node N3 and the initialization voltage power supply line SVI to each other, supplying the initialization voltage VINI to the third node N3, and initializing the third node N3.

[0042] For example, the capacitive element CS has a function of holding a charge (e.g., a first charge) equivalent to the initialization voltage VINI supplied to the third node N3, and a function of holding a charge (e.g., a second charge) equivalent to a data voltage (e.g., a voltage equal to or greater than the voltage VSIGL (see FIG. 6) and equal to or less than the voltage VSIGH (see FIG. 6)) included in the image data signal SL(m) supplied to the first node N1.

[0043] The light-emitting element OLED has diode characteristics and emits light based on the current flowing through the light-emitting element OLED (that is, the drain current Ion of the second transistor T2).

[0044] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the first scan signal line 330. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 634 of the third transistor T3, and the second electrode 694 of the capacitive element CS. A first scan signal SC1(n) is supplied to the first scan signal line 330. The switching of the first transistor T1 is controlled using the first scan signal SC1(n). In other words, the first transistor T1 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the first transistor T1 is in a non-conductive state. When the signal supplied to the first scan signal SC1(n+1) is HI, the first transistor T1 is in a conductive state.

[0045] The first scan signal line 330 is electrically connected to the gate electrode 612 of the first transistor T1, as well as to the gate electrode 632 of the third transistor T3 and the gate electrode 642 of the fourth transistor T4.

[0046] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to a second electrode 636 of the third transistor T3 and a second electrode 646 of the fourth transistor T4. The first electrode 624 is electrically connected to a third node N3, a second electrode 656 of the fifth transistor T5, a first electrode 692 of the capacitor CS, and a second electrode 684 of the light-emitting element OLED. The second electrode 626 is electrically connected to a driving power supply line PVDD. A driving voltage VDDEL is supplied to the driving power supply line PVDD. The threshold voltage of the second transistor T2 is a threshold voltage VTH. The second transistor T2 is controlled to be in a conductive state (ON state) or a non-conductive state (OFF state) depending on the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624, the potential difference between the second electrode 626 and the first electrode 624, and a threshold voltage VTH. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624 is smaller than the threshold voltage VTH and the potential difference between the second electrode 626 and the first electrode 624 is 0 V or less, the second transistor T2 is in a non-conductive state. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624 is equal to or greater than the threshold voltage VTH and the potential difference between the second electrode 626 and the first electrode 624 is greater than 0 V, the second transistor T2 is in a conductive state.

[0047] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The switching of the third transistor T3 is controlled using a first scan signal SC1(n). The third transistor T3 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the third transistor T3 is in a conductive state. When the signal supplied to the first scan signal SC1(n) is HI, the third transistor T3 is in a non-conductive state.

[0048] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The first electrode 644 is electrically connected to a reference voltage power supply line SVR. A reference voltage VREF is supplied to the reference voltage power supply line SVR. The switching of the fourth transistor T4 is controlled using the first scan signal line 330. In other words, the conductive state (ON state) and non-conductive state (OFF state) of the fourth transistor T4 are controlled by the first scan signal line 330. When the signal supplied to the first scan signal line 330 is LO, the fourth transistor T4 is in a non-conductive state, and when the signal supplied to the first scan signal line 330 is HI, the fourth transistor T4 is in a conductive state.

[0049] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the second scan signal line 334. The first electrode 654 is electrically connected to the initialization voltage power supply line SVI. The initialization voltage power supply line SVI is supplied with the initialization voltage VINI. The second scan signal line 334 is supplied with a second scan signal SC2(n). The switching of the fifth transistor T5 is controlled using the second scan signal SC2(n). In other words, the fifth transistor T5 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the fifth transistor T5 is in a non-conductive state, and when the signal supplied to the second scan signal SC2(n) is HI, the fifth transistor T5 is in a conductive state.

[0050] The first electrode 682 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0051] For example, the conductive state of a transistor in the self-emissive display device 10 means that the source electrode and drain electrode of the transistor are conductive and the transistor is in an ON state, and the non-conductive state of a transistor in the self-emissive display device 10 means that the source electrode and drain electrode of the transistor are non-conductive and the transistor is in an OFF state. Note that in each transistor, the source electrode and drain electrode may be interchanged depending on the voltage or potential supplied to each electrode. Furthermore, it is easily understood by those skilled in the art that even when a transistor is in an OFF state, a small amount of current, such as leakage current, still flows.

[0052] Each transistor shown in FIG. 3 may have a group 14 element such as silicon or germanium or an oxide exhibiting semiconducting properties in its channel region. For example, a metal oxide exhibiting semiconducting properties can be used as the oxide exhibiting semiconducting properties. As an example, the metal oxide exhibiting semiconducting properties is an oxide semiconductor containing two or more metals including indium (In). Furthermore, the metal oxide exhibiting semiconducting properties may be gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanide in addition to indium. Furthermore, the metal oxide exhibiting semiconducting properties may be amorphous, crystalline, or a mixed phase of amorphous and crystalline. When the self-emissive display device 10 includes both a transistor having a group 14 element in its channel region and a transistor having an oxide exhibiting semiconducting properties in its channel region, the method for manufacturing the self-emissive display device 10 includes forming a semiconductor layer containing a group 14 element and forming a semiconductor layer containing an oxide exhibiting semiconducting properties.

[0053] For example, the leakage current of a transistor having a metal oxide with semiconducting properties is extremely small. Therefore, when a transistor having a metal oxide with semiconducting properties is used, the charge corresponding to the voltage (potential) written to a capacitor element is unlikely to escape from the capacitor element. As a result, by using a transistor having a metal oxide with semiconducting properties, the charge written to the capacitor element can be retained for a long period of time. Furthermore, under the same conditions of gate-source voltage (potential difference between the gate electrode and the source electrode (Vgs)) and source-drain voltage (e.g., potential difference between the source electrode and the drain electrode (Vds)), the drain current of a transistor having a metal oxide with semiconducting properties may be larger than the drain current of a transistor having low-temperature polysilicon (LTPS). As a result, under the same conditions of drain current, the gate-source voltage and source-drain voltage of a transistor having a metal oxide with semiconducting properties can be smaller than those of a transistor having LTPS. Therefore, by using a transistor having a metal oxide with semiconducting properties, the power consumption of the self-emissive display device 10 can be reduced.

[0054] For example, the channel region of the first transistor T1 or the channel region of the fourth transistor T4 may be formed using a metal oxide having semiconducting properties. Also, the channel region of the second transistor T2 or the channel region of the fifth transistor T5 may be formed using a metal oxide having semiconducting properties. For example, when the channel region of the first transistor T1 is formed using a metal oxide, the charge (e.g., the second charge) corresponding to the voltage included in the data signal VDATA held in the first node N1 and the second electrode 694 of the capacitor CS is difficult to discharge, and the first node N1 and the second electrode 694 of the capacitor CS can hold the charge for a long time.

[0055] For example, the channel region of each transistor has crystalline silicon. For example, the crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon. For example, each transistor in the self-emissive display device 10 is formed using a thin-film transistor (TFT). The channel region of each transistor may also be formed using single-crystal silicon such as a silicon wafer or SOI substrate. Each transistor may have either an n-channel field-effect transistor or a p-channel field-effect transistor. The transistor configuration, storage capacitor connection, power supply voltage, etc. of the self-emissive display device 10 may be appropriately adapted depending on the application and specifications.

[0056] In the first embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are n-channel field effect transistors, and the third transistor T3 is a p-channel field effect transistor.

[0057] <1-6. Method for driving the self-luminous display device 10> A method for driving the self-luminous display device 10 will be described with reference to Figs. 4 to 8. Figs. 4 to 8 are schematic diagrams showing timing charts for the self-luminous display device 10. The driving methods shown in Figs. 4 to 8 are examples, and the driving methods for the self-luminous display device 10 are not limited to those shown in Figs. 4 to 8. Configurations that are the same as or similar to those in Figs. 1 to 3 will be described as necessary. The horizontal axis of the timing chart represents time.

[0058] For example, the frequency at which the self-luminous display device 10 is driven is 60 Hz, and one frame (1 FRAME) is driven at 60 Hz. For example, Fig. 4 shows the current frame (Kth FRAME), a portion of the frame immediately before the current frame (K-1st FRAME), and a portion of the frame immediately after the current frame (K+1st FRAME).

[0059] 4, the method of driving the self-emissive display device 10 includes at least an initialization and writing period PIW (period PIW) and a threshold value acquisition and holding period PVH (period PVH) in one frame. In the pixel 180 (pixel circuit 181) included in the self-emissive display device 10, the period PVH is executed after the period PIW. Furthermore, the period PIW and period PVH of the current frame are executed after the light-emitting period PEM of the frame immediately before the current frame, and the period PIW and period PVH of the frame immediately after the current frame are executed after the light-emitting period PEM of the current frame.

[0060] The period PIW is a period during which the data signal VDATA is written to the pixel 180 (pixel circuit 181) and the second node N2 and the third node N3 of the pixel 180 (pixel circuit 181) are initialized. The period PVH is a period during which the threshold voltage of the second transistor T2 is acquired by performing an operation to make the potential difference Vgs of the second transistor T2 equal to the threshold voltage, and a charge equivalent to the threshold voltage is held at the second node N2 (gate electrode 622 of the second transistor T2). The light-emission period PEM is a period during which the pixel 180 emits light based on the written (supplied) data signal VDATA and the acquired threshold voltage of the second transistor T2 (threshold voltage correction).

[0061] 5 to 8 are diagrams illustrating the periods PIW and PVH of the method for driving the pixels 180 (pixel circuits 181) of the self-luminous display device 10. Figures 5 to 8 show the light-emitting period PEM of the frame immediately preceding the current frame (K-1stFRAME), and the periods PIW and PVH of the current frame (KthFRAME). Figures 5 to 8 also show one horizontal period (horizontal period HRP) for one pixel 180 (pixel circuit 181).

[0062] In the driving method of the self-luminous display device 10, one horizontal period includes a period PIW and a period PVH. During one horizontal period, a first scan signal SC1(n), a second scan signal SC2(n), an image data signal SL(m) including a data signal VDATA, an initialization voltage VINI, and a reference voltage VREF are input to a pixel 180 (pixel circuit 181). For example, the first scan signal SC1(n) and the second scan signal SC2(n) are shifted, and a pixel 180 (pixel circuit 181) corresponding to the shifted signal is selected. The image data signal SL(m), the initialization voltage VINI, and the reference voltage VREF are input to the selected pixel 180 (pixel circuit 181). Similar operations are performed for all pixels 180 (pixel circuits 181), and an image of a frame corresponding to one frame is displayed in the display area 22 of the self-luminous display device 10 based on the image data signal SL(m) input to all pixels 180 (pixel circuits 181).

[0063] For example, Tables 1 and 2 show the voltages (potentials) supplied to the signals and nodes in each period of each frame in the timing charts shown in FIGS.

[0064] [Table 1]

[0065] [Table 2]

[0066] <1-6-1. First Example of Method for Driving Self-Emitting Display Device 10> 5, a first example of a method for driving the self-luminous display device 10 will be described. The driving method shown in the first example involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH included in the data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL included in the data signal VDATA in the KthFRAME. In other words, the driving method shown in the first example involves displaying images of different colors in successive frames.

[0067] In accordance with each horizontal period, an image data signal SL(m) including a data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data including a voltage greater than or equal to VSIGL and less than or equal to VSIGH. For example, in each horizontal period, a voltage greater than or equal to VSIGL and less than or equal to VSIGH is selected using a selection signal (not shown) and supplied to the image data signal SL(m). For example, during a period in which no data is selected using the selection signal, the data signal VDATA is maintained at a voltage greater than or equal to VSIGL and less than or equal to VSIGH. As shown in Table 2, for example, when the voltage VSIGL is −0.5 V, the pixel 180 supplied with the voltage VSIGL does not emit light and is black. For example, when the voltage VSIGH is 3.5 V, the pixel 180 supplied with the voltage VSIGH emits light and emits a color. In addition, in FIG. 5, for example, the voltage VH is 10 V, the voltage VM is 5 V, and the voltage VN is −5 V.

[0068] The light-emitting period PEM of the K-1st FRAME is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the potential difference Vgs (voltage V(N2)-voltage V(N3)=voltage Vna-voltage Vnb) of the second transistor T2. For example, the pixel 180 (pixel circuit 181) emits red light, and three pixels, a pixel 180 that emits red light, a pixel 180 that emits blue light, and a pixel 180 that emits green light, emit white light.

[0069] For example, during the light emission period PEM of the (K-1st) FRAME, no data is selected using the selection signal, the data signal VDATA is maintained at a voltage greater than or equal to the voltage VSIGL and less than or equal to the voltage VSIGH, and the first scan signal SC1(n) and the second scan signal SC2(n) are supplied with LO. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are in the OFF state. The voltage Vna supplied to the first node N1 and the second node N2 is 7 V, and the voltage Vnb supplied to the third node N3 is 2.5 V. The potential difference Vgs is 4.5 V, and the third transistor T3 is in the ON state. Therefore, the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds corresponding to the voltage VSIGH input during one horizontal period HRP of the (K-1st) FRAME. In addition, the second transistor T2 is in an on state, and the current Ion flows from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light. As shown in Table 2, for example, LO is −3.5V and HI is 10V.

[0070] During the initial period of one horizontal period HRP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, the pixel 180 (pixel circuit 181) receives the image data signal SL(m), which includes the data signal VDATA including the voltage VSIGL corresponding to the non-light-emitting black color, and the first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. The second scan signal SC2(n) is also in a state in which LO is supplied. Therefore, the first transistor T1 and the fourth transistor T4 change from an off state to an on state, the third transistor T3 changes from an on state to an off state, and the fifth transistor T5 maintains its off state. As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGL (voltage Vnd), and the voltage supplied to the second node N2 gradually drops from voltage Vna toward the reference voltage VREF. Furthermore, in response to the drop in the voltage supplied to the second node N2, the second transistor T2 changes from an on state to an off state. For example, as shown in Table 2, the reference voltage VREF is 0 V and the voltage VSIGL (voltage Vnd) is −0.5 V. At this time, the voltage supplied to the third node N3 is maintained at Vnb.

[0071] As described above, the period PIW within one horizontal period HRP of the KthFRAME is a period during which the data signal VDATA is written to the pixel 180 (pixel circuit 181), and is also a period during which the second node N2 and the third node N3 of the pixel 180 (pixel circuit 181) are initialized.

[0072] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, and the first scan signal SC1(n) maintains a state in which HI is supplied. Also, the second scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. Therefore, the fifth transistor T5 changes from an OFF state to an ON state, the first transistor T1 and the fourth transistor T4 maintain an ON state, and the third transistor T5 maintains an OFF state.

[0073] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGL (voltage Vnd, −0.5V) and becomes voltage Vnd (−0.5V). The voltage supplied to the second node N2 gradually drops from voltage Vna toward reference voltage VREF and becomes reference voltage VREF (0V). Furthermore, the voltage supplied to the third node N3 gradually drops from voltage Vnb toward initialization voltage VINI (voltage Vnc) and becomes voltage Vnc. For example, as shown in Table 2, the initialization voltage VINI (voltage Vnc) is −1.5V. That is, the voltage (0V) supplied to the second node N2 is greater than the voltage (-0.5V) supplied to the first node N1, and the voltage (-0.5V) supplied to the first node N1 is greater than the voltage (-1.5V) supplied to the third node N3, so the potential difference Vgs is 1.5V (0V-(-1.5V)) and the potential difference Vds is 9.5V (8V-(-1.5V)).

[0074] In this way, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, the second node N2 is initialized by the reference voltage VREF (0 V), and the third node N3 is initialized by the initialization voltage VINI (-1.5 V). For example, the period during which the second node N2 is initialized is the same as the period during which the data signal VDATA is supplied to the first node, and the period during which the third node N3 is initialized is different from the period during which the second node N2 is initialized and is shorter than the period during which the second node N2 is initialized.

[0075] Of one horizontal period HRP of KthFRAME, the period PVH following the period PIW is a period in which, as described above, an operation is performed to make the potential difference Vgs of the second transistor T2 equal to the threshold voltage, the threshold voltage of the second transistor T2 is obtained, and a charge equivalent to the threshold voltage is held in the second node N2 (gate electrode 622 of the second transistor T2).

[0076] During the period PVH, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, and the first scan signal SC1(n) maintains a state in which HI is supplied. Also, the second scan signal SC1(n) changes from a state in which HI is supplied to a state in which LO is supplied. Therefore, the fifth transistor T5 changes from an ON state to an OFF state, the first transistor T1 and the fourth transistor T4 maintain an ON state, and the third transistor T5 maintains an OFF state.

[0077] Immediately after the start of the period PVH, the potential difference Vgs is 1.5 V, the potential difference Vds is 9.5 V, and the potential difference Vgs and the potential difference Vds are greater than the threshold voltage VTH (1 V), so the second transistor T2 is in the on state. Therefore, the drain current Ion flows from the second electrode 626 to the first electrode 624 of the second transistor T2.

[0078] When the potential difference Vgs reaches the threshold voltage VTH, the second transistor T2 changes from the on state to the off state, and the drain current Ion stops flowing. At this time, the voltage supplied to the third node N3 rises from voltage Vnc to voltage Vne, and the potential difference Vgs becomes reference voltage VREF minus voltage Vne. That is, reference voltage VREF (0V) minus voltage Vne is threshold voltage VTH (1V), and voltage Vne is -1V.

[0079] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0080] During the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the pixel 180 emits light based on the voltage VSIGL supplied to the first node N1 and the potential difference Vsg between the voltage supplied to the second node N2 and the voltage supplied to the third node N3.

[0081] For example, during the light emission period PEM of KthFRAME, no data is selected using the selection signal, and the data signal VDATA is maintained at a voltage equal to or greater than the voltage VSIGL and equal to or less than the voltage VSIGH. Also, the first scan signal SC1(n) changes from a HI state to a LO state, and the second scan signal SC2(n) maintains the LO state.

[0082] Therefore, the first transistor T1 and the fourth transistor T4 change from an ON state to an OFF state, and the third transistor T3 changes from an OFF state to an ON state. The fifth transistor T5 maintains its OFF state. With the third transistor T3 turning ON, the first node N1 and the second node N2 become electrically connected, and the potential difference Vgs becomes voltage VSIGL (-0.5V) - (reference voltage VREF (0V) - threshold voltage VTH (1V)) = voltage Vnd (-0.5V) - voltage Vne (-1V). That is, the potential difference Vgs becomes 0.5V, which is smaller than the threshold voltage VTH. Therefore, the second transistor T2 is OFF, and no current flows from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light at all. As a result, for example, the pixel 180 (pixel circuit 181) that emits red light turns black. Furthermore, like the pixel 180 that emits red light, the pixel 180 that emits blue light and the pixel 180 that emits green light also do not emit light, so the three pixels using the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light are black.

[0083] The self-emissive display device 10 includes a first node N1 to which a data signal VDATA equal to or higher than a voltage VSIGL and equal to or lower than a voltage VSIGH is supplied (written), a second node N2 (a gate electrode 622 of the second transistor T2) to which a reference voltage VREF is supplied, and a third node N3 (a first electrode 624 of the second transistor T2) to which an initialization voltage VINI is supplied. That is, the self-emissive display device 10 can independently control the first node N1 to which data is written, and the second and third nodes N2 and N3 that contribute to the initialization of the second transistor T2 for causing a current to flow to the light-emitting element OLED. As a result, as described in the description of the method for driving the self-emissive display device 10, the method for driving the self-emissive display device 10 can include performing the process (driving) performed in the write period and the process (driving) performed in the initialization period at the same timing. In other words, the method for driving the self-emissive display device 10 does not require the process (driving) performed in the write period to be performed after the process (driving) performed in the initialization period.

[0084] For example, in a display device including a pixel circuit in which the first node N1 is the same as the second node N2 (in which the third transistor T3 is not present), the process (driving) performed in the write period and the process (driving) performed in the initialization period cannot be performed at the same timing, so the display device includes separate write and initialization periods. Therefore, in a display device including a pixel circuit in which the first node N1 is the same as the second node N2 (in which the third transistor T3 is not present), the time required for one horizontal period becomes longer.

[0085] On the other hand, as described above, the self-luminous display device 10 includes a configuration for independently controlling the first node N1, the second node N2, and the third node N3, and can execute the processing (driving) executed in the writing period and the processing (driving) executed in the initialization period at the same timing.

[0086] As a result, the self-luminous display device 10 can shorten the time required for one horizontal period. Furthermore, by shortening the time required for one horizontal period, the self-luminous display device 10 can reduce power consumption by an amount equivalent to the shortened time. Therefore, the self-luminous display device 10 is a display device that can reduce power consumption.

[0087] Furthermore, by shortening the time required for one horizontal period, the self-luminous display device 10 can increase the number of pixels that can be written in the shortened time. Therefore, the self-luminous display device 10 is a display device that can be made high-definition.

[0088] <1-6-2. Second Example of Method for Driving Self-Emitting Display Device 10> A second example of a method for driving the self-luminous display device 10 will be described with reference to FIG. 6. The driving method shown in the second example involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH included in the data signal VDATA in the frame (K-1st FRAME) immediately preceding the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH included in the data signal VDATA in the Kth FRAME as well. In other words, the driving method shown in the second example involves displaying images of the same color (white) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 5 will be described as necessary.

[0089] The configurations of the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, the image data signal SL(m), the first scan signal SC1(n), and the second scan signal SC2(n) during the light emission period PEM are the same as those in the first example. Also, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor are the same as those in the first example. Therefore, configurations similar to those in the first example will be explained as necessary.

[0090] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180 (pixel circuit 181) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH corresponding to white. The voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGH (voltage Vnf), and the voltage supplied to the second node N2 gradually drops from voltage Vna toward the reference voltage VREF. In response to the drop in the voltage supplied to the second node N2, the second transistor T2 changes from an ON state to an OFF state. For example, as shown in Table 2, the reference voltage VREF is 0 V, and the voltage VSIGH (voltage Vnf) is 3.5 V.

[0091] During the period PIW, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGH (voltage Vnf, 3.5V) and becomes voltage Vnf (3.5V). The voltage supplied to the second node N2 gradually drops from voltage Vna toward reference voltage VREF and becomes reference voltage VREF (0V). The voltage supplied to the third node N3 gradually drops from voltage Vnb toward initialization voltage VINI (voltage Vnc) and becomes voltage Vnc. For example, as shown in Table 2, the initialization voltage VINI (voltage Vnc) is −1.5V. At this time, the potential difference Vgs becomes 1.5V (0V−−1.5V), and the potential difference Vds becomes 9.5V (8V−−1.5V).

[0092] As described above, similar to the first example, during the period PIW, a data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-1.5V).

[0093] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied. Immediately after the start of the period PVH, as in the first example, the second transistor T2 is in the on state, and the drain current Ion flows from the second electrode 626 to the first electrode 624 of the second transistor T2.

[0094] During the period PVH, the first node N1 maintains a state in which the voltage Vnf is supplied, and the second node N2 maintains a state in which the reference voltage VREF (0 V) is supplied. Also, during the period PVH, as in the first example, when the potential difference Vgs becomes the threshold voltage VTH, the second transistor T2 changes from the on state to the off state, and the drain current Ion stops flowing. Also, as in the first example, the voltage supplied to the third node N3 increases from the voltage Vnc to the voltage Vne, and the reference voltage VREF minus the voltage Vne becomes the threshold voltage VTH, and the voltage Vne is -1 V.

[0095] As described above, in the same manner as in the first example, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0096] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, the third transistor T3 turns on, causing the first node N1 to become conductive with the second node N2, and the voltages of the first node N1 and the second node N2 gradually increase. As a result, the second transistor T2 turns on, and a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the voltage of the third node N3 rises in response to the rise in the voltages of the first node N1 and the second node N2.

[0097] For example, the voltages of the first node N1 and the second node N2 rise to voltage Vna, and the voltage of the third node N3 rises to voltage Vnb. As a result, the potential difference Vgs becomes voltage Vna (7 V) minus voltage Vnb (-2.5 V). That is, the potential difference Vgs becomes 4.5 V, which is greater than the threshold voltage VTH (1 V). Therefore, the second transistor T2 is in an on state, and a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. In other words, the flow of the drain current Ion causes the voltage of the third node N3 to rise to 2.5 V and exceed the threshold voltage VTHEL (0.7 V, see Table 2) of the light-emitting element OLED, causing the light-emitting element OLED to emit light. As a result, for example, the pixel 180 (pixel circuit 181) emits red, and three pixels, one using a pixel 180 that emits blue and one using a pixel 180 that emits green, emit white.

[0098] <1-6-3. Third Example of Method for Driving Self-Emitting Display Device 10> A third example of a method for driving the self-luminous display device 10 will be described with reference to FIG. 7. The driving method shown in the third example involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL included in the data signal VDATA in the frame (K-1st FRAME) immediately preceding the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGH included in the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the third example involves displaying images of the same color (black) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 6 will be described as necessary.

[0099] The configurations of the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, the image data signal SL(m), the first scan signal SC1(n), and the second scan signal SC2(n) during the light emission period PEM are the same as those in Example 1. Configurations similar to those in Example 1 and Example 2 will be explained as necessary.

[0100] The light-emitting period PEM of the K-1st FRAME is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the potential difference Vgs (voltage V(N2) - voltage V(N3) = Vnd (-0.5 V) - voltage Vne (-1 V). For example, the potential difference Vgs is 0.5 V, which is smaller than the threshold voltage VTH (1 V, see Table 2) of the second transistor T2. Therefore, the second transistor T2 is in the off state, and no current flows from the drive power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light at all. As a result, for example, the pixel 180 (pixel circuit 181) turns black.

[0101] During the initial period of one horizontal period HRP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, the pixel 180 (pixel circuit 181) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGL (-0.5V) corresponding to the non-light-emitting black color. The voltage supplied to the first node N1 remains at voltage Vnd (-0.5V), and the first node N1 maintains the state in which -0.5V is supplied. The voltage supplied to the second node N2 gradually increases from voltage Vnd (-0.5V) toward the reference voltage VREF (0V).

[0102] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied. The voltage supplied to the first node N1 remains at −0.5 V, and the first node N1 maintains a state in which −0.5 V is supplied. The voltage supplied to the second node N2 gradually increases from the voltage Vnd toward the reference voltage VREF and becomes the reference voltage VREF (0 V). In addition, the voltage supplied to the third node N3 gradually decreases from the voltage Vne (−1 V) toward the initialization voltage VINI (voltage Vnc, −1.5 V) and becomes the voltage Vnc (−1.5 V).

[0103] As described above, similarly to the first example, during the period PIW, the first node N1 is supplied (written) with a data signal VDATA including a voltage VSIGL (-0.5V), the second node N2 is initialized by a reference voltage VREF (0V), and the third node N3 is initialized by an initialization voltage VINI (-1.5V).

[0104] In the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied.

[0105] Immediately after the start of the period PVH, the potential difference Vgs is 1.5 V (reference voltage VREF (0 V) - voltage Vnc (-1.5 V)), and the potential difference Vds is 9.5 V. Since the potential differences Vgs and Vds are larger than the threshold voltage VTH (1 V), the second transistor T2 is in the on state. Therefore, the drain current Ion flows from the second electrode 626 to the first electrode 624 of the second transistor T2. Even when the drain current Ion flows through the second transistor T2, the voltage of the third node N3 is -1.5 V, which is smaller than the threshold voltage VTHEL of the light-emitting element OLED, and therefore the light-emitting element OLED does not emit light for a moment between consecutive frames in which black is displayed.

[0106] During the period PVH, when the potential difference Vgs reaches the threshold voltage VTH (1 V), the second transistor T2 changes from the on state to the off state, and the drain current Ion stops flowing. At this time, the voltage supplied to the third node N3 rises from the voltage Vnc (-1.5 V) to the voltage Vne (-1 V), and the potential difference Vgs reaches the threshold voltage VTH (1 V) (reference voltage VREF (0 V) - Vne (-1 V)).

[0107] As described above, in the same manner as in the first example, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0108] During the light-emitting period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, as in the first example, the third transistor T3 is turned on, causing the first node N1 to be electrically connected to the second node N2, and the potential difference Vgs becomes 0.5 V. As a result, as in the first example, the second transistor T2 is turned off, and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. For example, the pixel 180 (pixel circuit 181) turns black. Similarly to the pixel 180 that emits red, the pixel 180 that emits blue and the pixel 180 that emit green also do not emit light, so the three pixels that use the pixel 180 that emits red, the pixel 180 that emits blue, and the pixel 180 that emits green are black.

[0109] For example, a display device including a pixel circuit in which the first node N1 is the same as the second node N2 (i.e., the third transistor T3 is not present) has separate write and initialization periods because the process (driving) performed in the write period and the process (driving) performed in the initialization period cannot be performed at the same timing. As a result, even when displaying images of the same color (black) in consecutive frames, a display device including a pixel circuit in which the first node N1 is the same as the second node N2 executes processes in both the write and initialization periods in each consecutive frame. As a result, a display device including a pixel circuit in which the first node N1 is the same as the second node N2 may experience large fluctuations in the voltage of each node.

[0110] On the other hand, as described above, the self-luminous display device 10 includes a configuration for independently controlling the first node N1, the second node N2, and the third node N3, and can execute the processing (driving) executed in the writing period and the processing (driving) executed in the initialization period at the same timing.

[0111] As a result, the self-luminous display device 10 can suppress large fluctuations in the voltage of each node when displaying images of the same color (black) in consecutive frames. For example, as described above, the fluctuation in voltage at the first node N1 is 0, and the fluctuation in voltage at each of the second node N2 and the third node N3 is 0.5 V. Furthermore, in the self-luminous display device 10, the fluctuation in voltage at each node when displaying images of the same color (black) in consecutive frames is small, so power consumption due to fluctuations in voltage at each node can be reduced. Therefore, the self-luminous display device 10 is a display device that can achieve low power consumption.

[0112] <1-6-4. Fourth Example of the Method for Driving the Self-Emitting Display Device 10> A fourth example of a method for driving the self-luminous display device 10 will be described with reference to FIG. 8. The driving method shown in the fourth example involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL included in the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH included in the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the fourth example involves displaying images of different colors in successive frames. Configurations that are the same as or similar to those in FIGS. 1 to 5 will be described as necessary.

[0113] The configurations of the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, the image data signal SL(m), the first scan signal SC1(n), and the second scan signal SC2(n) during the light emission period PEM are the same as those in the first example. Also, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor are the same as those in the third example. Configurations similar to those in the first to third examples will be explained as necessary.

[0114] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180 (pixel circuit 181) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGH corresponding to white. The voltage supplied to the first node N1 gradually increases from the voltage Vnd (-0.5 V) toward the voltage VSIGH (voltage Vnf, 3.5 V), and the voltage supplied to the second node N2 gradually increases from the voltage Vnd toward the reference voltage VREF (0 V).

[0115] During the period PIW, the voltage supplied to the first node N1 gradually increases from voltage Vnd (-0.5V) toward voltage VSIGH (voltage Vnf, 3.5V), and the first node N1 is supplied with voltage Vnf (3.5V). The voltage supplied to the second node N2 gradually increases from voltage Vnd toward reference voltage VREF (0V), and the second node N2 is supplied with voltage VREF (0V). Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vne (-1V) toward initialization voltage VINI (voltage Vnc, -1.5V), and the third node N3 is supplied with voltage Vnc (-1.5V). At this time, the potential difference Vgs becomes 1.5V (0V - -1.5V), and the potential difference Vds becomes 9.5V (8V - -1.5V).

[0116] As described above, similar to the second example, during the period PIW, a data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-1.5V).

[0117] During the period PVH following the period PIW, as in the second example, the first node N1 maintains a state in which it is supplied with voltage Vnf, the second node N2 maintains a state in which it is supplied with reference voltage VREF (0V), the voltage supplied to the third node N3 rises from voltage Vnc to voltage Vne, and the third node N3 maintains a state in which it is supplied with voltage Vne (-1V).

[0118] As described above, in the same manner as in the second example, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0119] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, as in the second example, the voltages of the first node N1 and the second node N2 rise to voltage Vna, the voltage of the third node N3 rises to voltage Vnb, and the potential difference Vgs becomes 4.5 V (voltage Vna (7 V) - voltage Vnb (-2.5 V)). The potential difference Vgs is greater than the threshold voltage VTH (1 V), the second transistor T2 is in the on state, and a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the light emitting element OLED emits light. For example, pixel 180 emits red light, and three pixels, one for emitting blue light and one for emitting green light, emit white light.

[0120] <1-7. Cross-sectional structure of pixel 180 taken along line A1-A2> The cross-sectional structure of pixel 180 taken along line A1-A2 will be described with reference to FIGS. 3, 9, and 10. FIG. 9 is a planar layout diagram of pixel 180. FIG. 10 is a cross-sectional view showing a cross section taken along line A1-A2 in the planar layout of pixel 180 shown in FIG. 9. The planar layout of pixel 180 shown in FIG. 9 and the cross-section of pixel 180 shown in FIG. 10 are merely examples, and the planar layout and cross-section of pixel 180 are not limited to the examples shown in FIGS. 9 and 10. Configurations that are the same as or similar to those in FIGS. 1 to 8 will be described as necessary.

[0121] The cross section of pixel 180 shown in Figure 10 is an example of a cross section of pixel 180, and is a cross section along the drive power line PVDD, the contact hole opening 147 for the anode electrode, the first electrode 692 and the second electrode 694 of the capacitance element CS, the gate electrode 622 of the second transistor T2, the channel region 123 of the semiconductor layer 122, the organic insulating film opening 138A for the capacitance element CS, the second contact hole opening 138B, the first wiring 132B, the first wiring 132D, the first contact hole opening 135, the impurity region 124A, the second scan signal line 334, the reference voltage power line SVR, and the initialization voltage power line SVI.

[0122] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is provided on the first surface 101A of the substrate 101 via an underlayer 121. The semiconductor layer 122 includes a semiconductor layer 122A, which includes a channel region 123 and an impurity region 124A. For example, the impurity region is called a source region or a drain region. Also, for example, the second transistor T2 and the fifth transistor T5 include the semiconductor layer 122A, and the first electrode 624 and the second electrode 656 include the impurity region 124A. In other words, the semiconductor layer 122A includes the channel region of the second transistor T2 and the channel region of the fifth transistor T5.

[0123] A gate insulating layer 125, a conductive layer 126, an insulating layer 128, and a conductive layer 132 are provided on the semiconductor layer 122 in this order. The conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (second scan signal line 334), a gate wiring 127C (reference voltage power supply line SVR), and a gate wiring 127D (initialization voltage power supply line SVI). The conductive layer 132 includes a first wiring 132A (drive power supply line PVDD), a first wiring 132B, a first wiring 132C (second electrode 694), and a first wiring 132D. The region where the conductive layer 126 and the semiconductor layer 122 overlap is a channel region. In other words, the region where the gate electrode and the semiconductor layer of each transistor overlap is a channel region.

[0124] Each of the transistors of the pixel 180 is formed using a semiconductor layer 122 (channel region 123 and impurity region 124A), a gate insulating layer 125, and a conductive layer 126 (for example, gate wiring 127A).

[0125] A first contact hole opening 135 reaching the semiconductor layer 122 is provided in the gate insulating layer 125 and the insulating layer 128. The first contact hole opening 135 exposes the semiconductor layer 122 (e.g., impurity region 124A). The conductive layer 132 is electrically connected to the semiconductor layer 122 (e.g., impurity region 124A) through the first contact hole opening 135. An opening (not shown) reaching the conductive layer 126 (e.g., gate wiring 127A) may also be provided in the insulating layer 128.

[0126] An insulating layer 131 is provided to cover the conductive layer 132. An insulating layer 136 is provided to cover the insulating layer 131.

[0127] A second contact hole opening 138B is provided in the insulating layer 131 and the insulating layer 136. A second contact hole opening 138B is provided in the insulating layer 136. A conductive layer 139 is provided on the insulating layer 136, in the organic insulating film opening 138A for the capacitor element CS and the second contact hole opening 138B. The conductive layer 139 includes a second wiring 140A (first electrode 692), a second wiring 140B, and a third wiring 140C. The second contact hole opening 138B exposes the conductive layer 132 (e.g., the first wiring 132D). For example, the second contact hole opening 138B electrically connects the first electrode 692 and the first wiring 132D. For example, the capacitance element CS is formed using the first wiring 132C (second electrode 694) and the second wiring 140A (first electrode 692) with the insulating layer 131 as a dielectric. For example, the second wiring 140A also serves as a pixel electrode. Although not shown, the second contact hole opening 138 exposes some of the multiple terminals (not shown) included in the terminal section 150. Some of the exposed terminals are electrically connected to the FPC 160 using a conductive film such as an anisotropic conductive film (not shown).

[0128] An insulating layer 141 is provided over the conductive layer 139 .

[0129] The base layer 121 , the semiconductor layer 122 , the gate insulating layer 125 , the conductive layer 126 , the insulating layer 128 , the conductive layer 132 , the insulating layer 131 , the insulating layer 136 , the conductive layer 139 , and the insulating layer 137 are collectively called an array section 170 .

[0130] Next, a description will be given of layers above the insulating layer 141. An anode electrode contact hole opening 147 is provided in the insulating layer 141. The anode electrode contact hole opening 147 exposes the conductive layer 139 (for example, the second wiring 140A).

[0131] An anode electrode 143 is provided to cover the exposed conductive layer 139, the anode electrode contact hole opening 147, and the insulating layer 141. A functional layer 148 is provided on the anode electrode 143, and a common electrode 149 is provided on the functional layer 148 to cover the functional layer 148. The common electrode 149 is electrically connected to the cathode electrode (first electrode 682 of the light-emitting element OLED). Here, the light-emitting element OLED is composed of the anode electrode 143, the functional layer 148, and the common electrode 149 (cathode electrode).

[0132] The configuration of the functional layer 148 can be selected as appropriate. For example, the functional layer 148 can be configured by combining a carrier injection layer, a carrier transport layer, an emission layer, a carrier blocking layer, an exciton blocking layer, etc. For example, the functional layer 148 shown in Fig. 10 includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (hole) injection and transport layer, the second layer 145 is a emission layer, and the third layer 146 is a carrier (electron) injection and transport layer.

[0133] A sealing film 165 is provided on the common electrode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. The first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed so as to cover at least the display region 22. A cover film 158 is disposed on the second inorganic insulating layer 156.

[0134] For example, the first layer 144, the second layer 145 (light-emitting layer), the third layer 146, and the common electrode 149 included in the functional layer 148 are not disposed on the IC chip 110, the first scan driver 120, and the second scan driver 130. A sealing film 165 and a cover film 158 are disposed on the IC chip 110, the first scan driver 120, and the second scan driver 130. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED, each transistor, etc. from the outside of the self-luminous display device 10.

[0135] Common metal materials are used for the conductive layer 126, the conductive layer 132, the conductive layer 139, and the common electrode 149. For example, common metal materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof.

[0136] For example, the semiconductor layer 122 may include LTPS, and may include a metal oxide.

[0137] For example, general insulating materials can be used as materials for forming the base layer 121, the gate insulating layer 125, the insulating layer 131, the first inorganic insulating layer 152, and the second inorganic insulating layer 156. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiNx O y Inorganic insulating layers such as the above are used.

[0138] For example, an organic compound material with excellent surface flatness can be used as the material for forming the insulating layer 128, the insulating layer 136, the insulating layer 141, and the organic insulating layer 154. The insulating layer 128, the insulating layer 136, and the insulating layer 141 may be referred to as organic insulating layers.

[0139] <1-8. Method for manufacturing the self-luminous display device 10> A method for manufacturing the self-luminous display device 10 (pixel 180) will be described with reference to Fig. 3 and Fig. 9 to Fig. 14. Fig. 11 is a sequence diagram showing the method for manufacturing the self-luminous display device 10. Figs. 12 to 14 are layout diagrams of the pixel 180. Configurations that are the same as or similar to those in Figs. 1 to 10 will be described as necessary.

[0140] As shown in FIG. 10, when the manufacture of the self-luminous display device 10 (pixel 180) starts, the base layer 121 is formed on the first surface 101A of the substrate 101.

[0141] As shown in FIG. 10 or 12, the semiconductor layer 122 is formed on the base layer 121 (step 10 (S10) of FIG. 11). The semiconductor layer 122 includes semiconductor layers 122A, 122B, and 122C. The semiconductor layer 122A serves as both the semiconductor layer of the second transistor T2 and the semiconductor layer of the fifth transistor T5. The semiconductor layer 122B serves as both the semiconductor layer of the first transistor T1 and the semiconductor layer of the third transistor T3. The semiconductor layer 122C is the semiconductor layer of the fourth transistor T4. In other words, the semiconductor layer 122B includes the channel region of the first transistor T1 and the channel region of the third transistor T3, and the semiconductor layer 122C includes the channel region of the fourth transistor T4. That is, the pixel 180 includes semiconductor layers that serve as two transistors and a semiconductor layer of one transistor.

[0142] Impurities are implanted into the semiconductor layer 122 (step 11 (S11) of FIG. 11). S11 forms an impurity region 124A. For example, referring to FIG. 12, the first electrode 614, the second electrode 616, the first electrode 624, the second electrode 626, the first electrode 614, the second electrode 616, the first electrode 644, the second electrode 646, the first electrode 654, and the second electrode 656 include impurity regions implanted with impurities such as phosphorus (P). Also, referring to FIG. 12, for example, the first electrode 634 and the second electrode 636 include impurity regions implanted with impurities such as boron (B).

[0143] A gate insulating layer 125 (FIG. 10) is formed on the semiconductor layer 122 and on the underlying layer 121 where the semiconductor layer 122 is not formed (step 12 (S12) in FIG. 11).

[0144] A conductive layer 126 (FIG. 10) is formed on the gate insulating layer 125 (step 13 (S13) of FIG. 11). As shown in FIG. 10 or FIG. 12, the conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (second scan signal line 334), a gate wiring 127C (reference voltage power supply line SVR), a gate wiring 127D (initialization voltage power supply line SVI), a first scan signal line 330A, and a first scan signal line 330B. The gate wiring 127B (second scan signal line 334) includes a gate electrode 652. The first scan signal line 330A includes a gate electrode 612, and the first scan signal line 330B includes a gate electrode 632 and a gate electrode 642. For example, the first scan signal line 330A and the first scan signal line 330B are electrically connected to each other on the periphery of the display area 22 or in the peripheral area 24, and the same first scan signal is supplied to them.

[0145] The region where the gate electrode 622 of the second transistor T2 and the semiconductor layer 122A overlap is the channel region 123, and the channel region 123 corresponds to the channel length of the second transistor T2. Similarly, the region where the gate electrode 612 of the first transistor T1 and the semiconductor layer 122B overlap is the channel region and the channel length of the first transistor T1. As shown in FIG. 12, in a plan view, the channel region 123 of the second transistor T2 is larger (longer) than the channel regions of the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5. That is, the channel length of the second transistor T2 is longer than the channel lengths of the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5. Because the second transistor T2 operates in the saturation region, the second transistor T2 needs to have a higher hot carrier tolerance than the other transistors in the pixel 180. As a result, the channel length of the second transistor T2 is longer than the channel lengths of the other transistors in the pixel 180.

[0146] An insulating layer 128 (FIG. 10) is formed on the conductive layer 126 and on the gate insulating layer 125 where the conductive layer 126 is not formed (step 14 (S14) in FIG. 11).

[0147] As shown in FIG. 10 or 12, first contact hole openings 135, 135A, 135B, 135C, 135D, 135E, 135F, 135G, and 135H are opened (step 15 (S15)). Each opening opens the gate insulating layer 125 and the insulating layer 128, exposing the corresponding wiring, semiconductor layer, or electrode. For example, first contact hole opening 135 exposes the semiconductor layer 122A (e.g., impurity region 124A), and first contact hole opening 135A exposes the gate wiring 127D. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0148] The conductive layer 132 (FIG. 10) is formed on the insulating layer 128 (step 16 (S16)). As shown in FIG. 10 or 13, the conductive layer 132 includes a first wiring 132A (driving power supply line PVDD), a first wiring 132B, a first wiring 132C (second electrode 694), a first wiring 132D, a first wiring 132E, a first wiring 132F, a first wiring 132G, a first wiring 132H, and an image data signal line 321.

[0149] As shown in FIG. 13, in a planar view, the first wiring 132A is electrically connected to the second electrode 626 via the first contact hole opening 135D, the first wiring 132B is electrically connected to the first electrode 644 via the first contact hole opening 135J, the second electrode 694 is electrically connected to the first electrode 644 via the first contact hole opening 135J, and the first wiring 132D is electrically connected to the second electrode 656 via the first contact hole opening 135. 13, in a plan view, first wiring 132E is electrically connected to initialization voltage power supply line SVI through first contact hole opening 135A and is electrically connected to first electrode 654 through first contact hole opening 135C, first wiring 132F is electrically connected to second electrode 646 through first contact hole opening 135K, first wiring 132G is electrically connected to second electrode 636 through first contact hole opening 135F and is electrically connected to gate electrode 622 through first contact hole opening 135E, first wiring 132H is electrically connected to first contact hole opening 135B with reference voltage power supply line SVR, and image data signal line 321 is electrically connected to first contact hole opening 135B with reference voltage power supply line SVR.

[0150] 13, the second electrode 694, the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 (its channel region and gate electrode 622) overlaps with the second electrode 694 of the capacitance element CS.

[0151] An insulating layer 131 (FIG. 10) is formed on the conductive layer 132 and on the insulating layer 128 where the conductive layer 132 is not formed (step 17 (S17) in FIG. 11).

[0152] As shown in FIG. 10 or 14, second contact hole openings 138B, 138C, 138D, 138E, 138F, and 138G are opened (step 18 (S18)). Each opening opens the insulating layer 131 and exposes the corresponding wiring, semiconductor layer, or electrode. For example, second contact hole opening 138B exposes the first wiring 132D, and second contact hole opening 138G exposes the first wiring 132G. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0153] An insulating layer 136 (organic insulating layer) (FIG. 10) is formed on the insulating layer 131 (step 19 (S19) in FIG. 11).

[0154] As shown in FIG. 10 or 14, holes are opened in the insulating layer 136 (organic insulating layer) (step 20 (S20)). In the opening in S20, an organic insulating film opening 138A for the capacitor element CS is opened. In addition, in the opening in S20, second contact hole openings 138B, 138C, 138D, 138E, 138F, and 138G are opened, similar to the opening in S18. That is, the second contact hole openings 138B, 138C, 138D, 138E, 138F, and 138G are opened twice. Each opening opens the insulating layer 136 and exposes the corresponding wiring, semiconductor layer, or electrode. For example, the organic insulating film opening 138A for the capacitor element CS removes only the insulating layer 136 above the second electrode 694, exposing the insulating layer 131. On the other hand, the second contact hole opening 138G removes only the insulating layer 136 on the first wiring 132G, exposing the first wiring 132G. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0155] A conductive layer 139 (FIG. 10) is formed on the insulating layer 136 and on the insulating layer 131 exposed in the organic insulating film opening 138A for the capacitor element CS (step 21 (S21)). As shown in FIG. 9 or 10, the conductive layer 139 includes a second wiring 140A (first electrode 692), a second wiring 140B, a third wiring 140C, and a fourth wiring 140D.

[0156] 9, in a plan view, the first electrode 692 is electrically connected to the first wiring 132D and the second electrode 656 via the second contact hole opening 138B and the first contact hole opening 135. The second wiring 140B is electrically connected to the first wiring 132H and the reference voltage power supply line SVR via the second contact hole opening 138D and the first contact hole opening 135B. The third wiring 140C is electrically connected to the first wiring 132E and the initialization voltage power supply line SVI via the second contact hole opening 138C and the first contact hole opening 135A. The fourth wiring 140D is electrically connected to the first wiring 132G, the gate electrode 622, and the second electrode 636 via the second contact hole opening 138G, the first contact hole opening 135F, and the first contact hole opening 135E, and is also electrically connected to the first wiring 132F and the second electrode 646 via the second contact hole opening 138F and the first contact hole opening 135K.

[0157] The second wiring 140B overlaps with the reference voltage power line SVR and extends parallel to it along the second direction D2. Therefore, the reference voltage power line SVR is formed using two layers of metal wiring, and therefore has a lower wiring resistance than a voltage line formed using a single layer of metal wiring. As a result, the reference voltage power line SVR has a high current supply capability and can supply a stable voltage to each transistor. Similarly to the reference voltage power line SVR, the third wiring 140C overlaps with the initialization voltage power line SVI and extends parallel to it along the second direction D2. Therefore, similar to the reference voltage power line SVR, the initialization voltage power line SVI is formed using two layers of metal wiring, and therefore has a lower wiring resistance than a voltage line formed using a single layer of metal wiring. As a result, the initialization voltage power line SVI has a high current supply capability and can supply a stable voltage to each transistor.

[0158] The second wiring 140A (first electrode 692) included in the same conductive layer 139 contacts the insulating layer 131 and the conductive layer 132 (first wiring 132D), and the second wiring 140B included in the same conductive layer 139 contacts the insulating layer 136. In other words, different wirings included in the same conductive layer 139 contact different layers below the same conductive layer 139.

[0159] 9, the first electrode 692, the second electrode 694, the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 overlaps with the capacitor CS.

[0160] Furthermore, the first wiring 132C (second electrode 694) is formed on an insulating layer 128 formed on a gate wiring 127A (gate electrode 622) having an area larger than the surface area of ​​the second electrode 694. Because the insulating layer 128 reduces unevenness in the underlying layer, the second electrode 694 is formed on the large-area gate electrode 622 and on the flat insulating layer 128. Furthermore, as shown in FIG. 13, for example, in a plan view, the area of ​​the second electrode 694 is larger than the area of ​​the electrode of the same conductive layer 132. That is, the surface of the second electrode 694 is flat and the area of ​​the second electrode 694 is large. Furthermore, the film thickness of the insulating layer 131 formed on the second electrode 694 is thinner than the film thickness of the insulating layer 136. Therefore, the manufacturing method of the self-luminous display device 10 (pixel 180) includes forming the first electrode 692 on the large-area gate electrode 622 and on the second electrode 694 and thin insulating layer 131 with reduced unevenness.

[0161] An insulating layer 141 (organic insulating layer) (FIG. 10) is formed on the conductive layer 139 and on the insulating layer 136 where the conductive layer 139 is not formed (step 22 (S22) in FIG. 11).

[0162] As shown in FIG. 9 or 10, an opening is made in the insulating layer 141 (organic insulating layer) (step 23 (S23)). In the opening of S23, a contact hole opening 147 for the anode electrode is made. The contact hole opening 147 for the anode electrode removes the insulating layer 141 above the second wiring 140A, exposing the second wiring 140A. The contact hole opening 147 for the anode electrode is sometimes called an organic insulating layer opening.

[0163] An anode electrode 143 is provided on the exposed second wiring 140A, on the anode electrode contact hole opening 147, and on the insulating layer 141, and a functional layer 148 is provided thereon. A common electrode 149 is provided on the functional layer 148 (step 24 (S24)).

[0164] After S24, the sealing film 165 and the cover film 158 are provided on the common electrode 149 in this order.

[0165] As shown in FIG. 10, the manufacturing of the self-luminous display device 10 (pixel 180) is completed in this manner.

[0166] <1-9.Increasing the speed of p-channel field-effect transistors> 3, the third transistor T3 is a p-channel field effect transistor that controls the connection and disconnection between the first node N1 and the second node N2. To speed up the operation of the pixel 180, the third transistor T3 needs to quickly transfer the data signal VDATA supplied to the first node N1 to the second node N2.

[0167] On the other hand, it is known that, for example, in the conductive state of a p-channel field-effect transistor and an n-channel field-effect transistor, carriers are trapped in a trap level, which increases the threshold voltage (e.g., JP 2008-028191 A). It is also known that, due to the increase in threshold voltage, the operation of each transistor from a conductive state to a non-conductive state becomes slower than the operation of a transistor in a state in which carriers are not trapped in a trap level (e.g., JP 2008-028191 A).

[0168] For example, this phenomenon is caused by the fact that the trap level density (density of states) contributing to hole trapping is higher than the trap level density (density of states) contributing to electron trapping for two carriers, holes and electrons, and it is known that this phenomenon can occur more significantly in p-channel field effect transistors (for example, JP 2012-019146 A). For example, the density of states contributing to hole trapping is −0.4 eV to the Fermi level Ei, and the density of states contributing to electron trapping is the Fermi level Ei to 0.4 eV. Furthermore, for example, the Fermi level Ei from −0.4 eV is called a deep level.

[0169] In order to suppress such a phenomenon, the method for manufacturing the self-luminous display device 10 is to set the density of states of the deep level of the third transistor T3 to 1×10 17 eV -1 ·cm -3 The method for manufacturing the self-emissive display device 10 may include the following. For example, if the third transistor T3 includes LTPS, the method for manufacturing the self-emissive display device 10 includes forming the semiconductor layer 122 by increasing the purity of silane (SiH4) gas. Because the impurity concentration in the formed LTPS is reduced by increasing the purity of the gas, the method for manufacturing the self-emissive display device 10 can reduce the deep level density of states of the third transistor T3. Also, for example, the method for manufacturing the self-emissive display device 10 includes increasing the crystal grain size of the LTPS in accordance with the energy of the laser irradiation used to form the LTPS. Because increasing the crystal grain size of the LTPS reduces the crystal grain boundaries, the method for manufacturing the self-emissive display device 10 can reduce the deep level density of states of the third transistor T3. As a result, high-speed operation of the third transistor T3 is possible.

[0170] 2. Second Embodiment An overview of the self-luminous display device 10 according to the second embodiment will be described with reference to Figs. 1, 4, and 15 to 21. Fig. 15 is a schematic diagram showing input signals to a pixel 180A (pixel circuit 181A) according to the second embodiment of the present invention. Fig. 16 is a circuit diagram showing the configuration of the pixel circuit 181A. Figs. 17 to 20 are timing charts of the self-luminous display device 10 according to the second embodiment of the present invention. Fig. 21 is a diagram for explaining the setting of input signals according to the second embodiment of the present invention.

[0171] The self-luminous display device according to the second embodiment has a configuration and function in which the pixel 180 and pixel circuit 181 of the self-luminous display device 10 according to the first embodiment are replaced with a pixel 180A and pixel circuit 181A. Other configurations and functions are the same as those of the self-luminous display device 10 according to the first embodiment. In explaining the configuration and functions of the second embodiment, configurations and functions that are the same as those of the self-luminous display device 10 according to the first embodiment will be explained as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 14 will be explained as necessary.

[0172] <2-1. Configuration of pixel 180A> The pixel 180A and pixel circuit 181A will be outlined with reference to FIGS.

[0173] The pixel circuit 181A is connected to a scan voltage power line SVIR. The scan voltage power line SVIR is a signal line that also serves as the reference voltage power line SVR and the initialization voltage power line SVI supplied to the pixel circuit 181. In other words, it is a signal line that combines the reference voltage power line SVR and the initialization voltage power line SVI supplied to the pixel circuit 181. The scan voltage power line SVIR is a wiring that functions as a power supply, but because its potential is changed during use, it is treated as a signal line here. That is, the pixel circuit 181A has a configuration and function in which the reference voltage power line SVR and the initialization voltage power line SVI connected to the pixel circuit 181 are replaced with a scan voltage power line SVIR that combines the reference voltage power line SVR and the initialization voltage power line SVI. The pixel circuit 181A also has a configuration and function in which the reference voltage VREF and the initialization voltage VINI supplied to the pixel circuit 181 are replaced with a scan voltage power supply SIR(n). The scan voltage power supply line SVIR (a signal line that serves both as the reference voltage power supply line SVR and the initialization voltage power supply line SVI) is sometimes called a third control signal line. The scan voltage power supply SIR(n) is sometimes called a third control signal.

[0174] A scan voltage power supply SIR(n) is supplied to the scan voltage power supply line SVIR. In the pixel circuit 181A, a first electrode 644 of the fourth transistor T4 and a first electrode 654 of the fifth transistor T5 are electrically connected to the scan voltage power supply line SVIR.

[0175] For example, the scan voltage power supply line SVIR is electrically connected to a connection wiring 342 (FIGS. 1 and 15) that is different from the drive power supply line PVDD and the reference voltage line PVSS. Also, for example, the scan voltage power supply line SVIR may be one of the connection wirings 342.

[0176] For example, the scan voltage power supply SIR(n) may be supplied from an external device to the IC chip 110 (FIG. 1), similar to the initialization voltage VINI, or may be supplied from the IC chip 110 to the plurality of pixels 180A (pixel circuits 181A) via the connection wiring 342 and the scan voltage power supply line SVIR. Although not shown, the scan voltage power supply SIR(n) may be connected to the scan voltage power supply line SVIR from the external device via the FPC 160, the terminal unit 150, and the connection wiring 341, similar to the initialization voltage VINI, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to the plurality of pixels 180A (pixel circuits 181A).

[0177] The fourth transistor T4 has a function of connecting the second node N2 and the scan voltage power supply line SVIR and supplying the initialization voltage VINI1 or VINI2 to the second node N2 to initialize the second node N2. For example, the initialization voltages VINI1 and VINI2 are constant voltages.

[0178] The fifth transistor T5 has a function of connecting the third node N3 and the scan voltage power supply line SVIR to each other, supplying the initialization voltage VINI1 to the third node N3, and initializing the third node N3.

[0179] The configuration and functions of the pixel circuit 181A other than those described in "2-1. Configuration of pixel 180A" are the same as those of the pixel circuit 181. Description of the configuration and functions that are the same as those of the pixel circuit 181 will be omitted here.

[0180] <2-2. Driving Method of Pixel Circuit 181A> A method for driving the self-luminous display device 10 according to the second embodiment will be described with reference to Figures 17 to 20. Configurations that are the same as or similar to those in Figures 1 to 16 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0181] The method for driving the self-luminous display device 10 according to the second embodiment has a configuration and functions in which the operations related to the reference voltage power supply line SVR and the initialization voltage power supply line SVI (reference voltage VREF and initialization voltage VINI) in the method for driving the self-luminous display device 10 according to the first embodiment are replaced with operations related to the scan voltage power supply SIR(n). The configurations and functions other than the operations related to the scan voltage power supply SIR(n) are the same as those of the method for driving the self-luminous display device 10 according to the first embodiment. Descriptions of the configurations and functions similar to those of the method for driving the self-luminous display device 10 according to the first embodiment will be omitted here.

[0182] The method for driving the self-luminous display device 10 according to the second embodiment includes the same period as the method for driving the self-luminous display device 10 shown in FIG.

[0183] 17 to 20 are diagrams for explaining the periods PIW and PVH of the method for driving pixel 180A (pixel circuit 181A). Figures 17 to 20 show the light-emitting period PEM of the frame immediately preceding the current frame (K-1stFRAME), and the periods PIW and PVH of the current frame (KthFRAME). Figures 17 to 20 also show one horizontal period (horizontal period HRP) for one pixel 180A (pixel circuit 181A).

[0184] During one horizontal period in the driving method for the self-luminous display device 10 according to the second embodiment, the pixel 180A (pixel circuit 181A) receives a first scan signal SC1(n), a second scan signal SC2(n), an image data signal SL(m) including a data signal VDATA, and a scan voltage power supply SIR(n). For example, the first scan signal SC1(n), the second scan signal SC2(n), and the scan voltage power supply SIR(n) are shifted, and the pixel 180A (pixel circuit 181A) corresponding to the shifted signal is selected. The image data signal SL(m), an initialization voltage VINI, and a reference voltage VREF are input to the selected pixel 180A (pixel circuit 181A). Similar operations are performed for all pixels 180A (pixel circuits 181A), and an image of a frame corresponding to one frame is displayed in the display region 22 of the self-luminous display device 10 based on the image data signal SL(m) input to all pixels 180A (pixel circuits 181A).

[0185] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0186] [Table 3]

[0187] [Table 4]

[0188] <2-2-1. First Example of Method for Driving Pixel Circuit 181A> A first example of a method for driving the pixel circuit 181A will be described with reference to Fig. 17. Similar to the first example of the method for driving the self-luminous display device 10 according to the first embodiment, the first example of the method for driving the pixel circuit 181A includes displaying images of different colors in successive frames.

[0189] The configurations of the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, the image data signal SL(m), the first scan signal SC1(n), and the second scan signal SC2(n) during the light emission period PEM are the same as those of the first example of the method for driving the self-luminous display device 10 according to the first embodiment. Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor are the same as those described in "1-6-1. First Example of the Method for Driving the Self-luminous Display Device 10." Configurations similar to those described in "1-6-1. First Example of the Method for Driving the Self-luminous Display Device 10" will be explained as necessary.

[0190] In addition, the scan voltage power supply SIR(n) supplies an initialization voltage VINI2 during the light emission period PEM of the K-1st FRAME, an initialization voltage VINI1 during the first period and period PIW of one horizontal period HRP of the K FRAME, and an initialization voltage VINI2 during the period PVH and light emission period PEM of the K FRAME.

[0191] For example, as shown in Table 4, the initialization voltage VINI2 is 0 V, and the initialization voltage VINI1 is −1.5 V. The initialization voltage VINI2 is the same as the reference voltage VREF, and the initialization voltage VINI1 is the same as the initialization voltage VINI. Also, for example, similar to the first example of the method for driving the self-luminous display device 10 according to the first embodiment, the voltage VH is 10 V, the voltage VM is 5 V, and the voltage VN is −5 V.

[0192] During the initial period of one horizontal period HRP of the Kth FRAME following the light emission period PEM of the K-1st FRAME, the scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI2 is supplied to a state in which the initialization voltage VINI1 is supplied. When the scan voltage power supply SIR(n) changes to a state in which the initialization voltage VINI1 is supplied, the first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. Furthermore, the second scan signal SC2(n) remains in a state in which LO is supplied. Therefore, the first transistor T1 and the fourth transistor T4 change from an OFF state to an ON state, the third transistor T3 changes from an ON state to an OFF state, and the fifth transistor T5 remains in an OFF state. As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGL (voltage Vnd, −0.5V), and the voltage supplied to the second node N2 gradually drops from voltage Vna toward the initialization voltage VINI1 (−1.5V). Furthermore, in response to the drop in the voltage supplied to the second node N2, the second transistor T2 changes from an on state to an off state.

[0193] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, the first scan signal SC1(n) maintains a state in which HI is supplied, and the scan voltage power supply SIR(n) maintains a state in which the initialization voltage VINI1 is supplied. Furthermore, the second scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. Therefore, the fifth transistor T5 changes from an off state to an on state, the first transistor T1 and the fourth transistor T4 maintain their on states, and the third transistor T4 maintains their off state. Furthermore, during the final period of the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, the first scan signal SC1(n) maintains a state in which HI is supplied, and the scan voltage power supply SIR(n) maintains a state in which the initialization voltage VINI1 is supplied. Furthermore, the second scan signal SC1(n) changes from a state in which HI is supplied to a state in which LO is supplied. Therefore, the fifth transistor T5 changes from an on state to an off state, the first transistor T1 and the fourth transistor T4 remain on, and the third transistor T3 remains off.

[0194] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGL (voltage Vnd, −0.5V) and becomes voltage Vnd (−0.5V). The voltage supplied to the second node N2 gradually drops from voltage Vna toward initialization voltage VINI1 (−1.5V) and becomes initialization voltage VINI1 (−1.5V). In addition, the voltage supplied to the third node N3 gradually drops from voltage Vnb toward initialization voltage VINI1 (voltage Vnc, −1.5V) and becomes voltage Vnc (−1.5V). That is, the voltage (-1.5V) supplied to the second node N2 is the same as the voltage (-1.5V) supplied to the third node N3, the voltage (0V) supplied to the first node N1 is greater than the voltage (-1.5V) supplied to the second node N2 and the voltage (-1.5V) supplied to the third node N3, the potential difference Vgs is 0V (-1.5V - (-1.5V)), and the potential difference Vds is 9.5V (8V - (-1.5V)).

[0195] In this manner, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-1.5V).

[0196] During the period PVH, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, the first scan signal SC1(n) maintains a state in which HI is supplied, and the second scan signal SC1(n) maintains a state in which LO is supplied. Note that, after the second scan signal SC1(n) is supplied with LO during the period PIW, the scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2 is supplied. With the scan voltage power supply SIR(n) supplied with the initialization voltage VINI1, the first scan signal SC2(n) changes from a state in which HI is supplied to a state in which LOW is supplied. Therefore, the fifth transistor T5 changes from an ON state to an OFF state, the first transistor T1 and the fourth transistor T4 maintain their ON states, and the third transistor T5 maintains their OFF state.

[0197] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is 9.5 V, and the potential difference Vgs is smaller than the threshold voltage VTH (1 V), so the second transistor T2 is in the off state. Therefore, the drain current Ion does not flow from the second electrode 626 to the first electrode 624 of the second transistor T2.

[0198] During the period PVH, because the fourth transistor T4 remains on, when the voltage supplied to the scan voltage power supply SIR(n) changes from the initialization voltage VINI1 to the initialization voltage VINI2, the voltage supplied to the second node N2 gradually rises from voltage Vnc (-1.5 V) toward the initialization voltage VINI2 (0 V) and reaches the initialization voltage VINI2 (0 V). At this time, although the fifth transistor T5 is off, the Vgs of the second transistor T2 approaches 1.5 V, which is greater than the threshold voltage VTH (1 V) (0 V (node ​​N2) - (-1.5 V) (node ​​N3)), so the drain current Ion of the second transistor T2 begins to flow, and the voltage supplied to the third node N3 gradually rises from voltage Vnc (-1.5 V). As a result, the voltage supplied to the third node N3 becomes voltage Vne (-1 V), and the potential difference Vgs becomes 1 V (0 V - (-1 V)). Since the potential difference Vgs is equal to the threshold voltage VTH (1 V), the second transistor T2 is in the off state, and therefore the drain current Ion does not flow from the second electrode 626 to the first electrode 624 of the second transistor T2.

[0199] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0200] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, no data is selected using the selection signal, and the data signal VDATA is maintained at a voltage greater than or equal to VSIGL and less than or equal to VSIGH. Also, the first scan signal SC1(n) changes from a HI state to a LO state, the second scan signal SC2(n) maintains its LO state, and the scan voltage power supply SIR(n) maintains its initialization voltage VINI2 (0 V) state.

[0201] Therefore, the first transistor T1 and the fourth transistor T4 change from an on state to an off state, and the third transistor T3 changes from an off state to an on state. The fifth transistor T5 maintains its off state. As the third transistor T3 turns on, the first node N1 and the second node N2 become conductive, and the potential difference Vgs becomes 0.5 V. The potential difference Vgs is smaller than the threshold voltage VTH. Therefore, the second transistor T2 is off, and no current flows from the driving power supply line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light. As a result, for example, the pixel 180A (pixel circuit 181A) that emits red, the pixel 180A that emits blue, and the pixel 180A that emits green do not emit light, resulting in a black display for the three pixels using the pixel 180A that emits red, the pixel 180A that emits blue, and the pixel 180A that emits green.

[0202] As described above, the method for driving the self-luminous display device 10 according to the second embodiment (the method for driving the pixel circuit 181A) includes performing the process (driving) performed in the write period and the process (driving) performed in the initialization period at the same timing, similar to the method for driving the self-luminous display device 10 according to the first embodiment. Therefore, the method for driving the pixel circuit 181A has the same effects as the method for driving the self-luminous display device 10 according to the first embodiment.

[0203] Furthermore, the pixel circuit 181A is connected to a scan voltage power supply line SVIR, which also serves as the reference voltage power supply line SVR and the initialization voltage power supply line SVI supplied to the pixel circuit 181. Therefore, the pixel circuit 181A has a configuration that allows the number of signal lines to be reduced, and therefore a self-luminous display device including the pixel circuit 181A can reduce the pixel size. As a result, a self-luminous display device including the pixel circuit 181A can increase the number of pixels and achieve higher definition.

[0204] <2-2-2. Second Example of Method for Driving Pixel Circuit 181A> A second example of a method for driving the pixel circuit 181A will be described with reference to Fig. 18. The driving method shown in the second example of the pixel circuit 181A includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 17 will be described as necessary.

[0205] The configurations of the image data signal SL(m), scan voltage power supply SIR(n), first scan signal SC1(n), and second scan signal SC2(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "2-2-1. First Example of a Method for Driving a Pixel Circuit 181A." The voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor, are the same as those described in "2-2-1. First Example of a Method for Driving a Pixel Circuit 181A." Configurations similar to those described in "2-2-1. First Example of a Method for Driving a Pixel Circuit 181A" will be explained as necessary. Configurations similar to those described in "1-6-2. Second Example of a Method for Driving a Self-Emitting Display Device 10" will be explained as necessary.

[0206] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180A (pixel circuit 181A) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGH corresponding to white. The voltage supplied to the first node N1 gradually drops from the voltage Vna toward the voltage VSIGH (voltage Vnf, 3.5V). The voltage supplied to the second node N2 and the voltage supplied to the third node N3 are the same as those described in "2-2-1."

[0207] During the period PIW, the voltage supplied to the first node N1 gradually drops from voltage Vna to voltage Vnf, reaching voltage Vnf (3.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "2-2-1".

[0208] As described above, during the period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (−1.5 V).

[0209] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied. The first node N1 maintains a state in which the voltage Vnf is supplied. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A."

[0210] As described above, in the same manner as described in "2-2-1," during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0211] During the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, similar to the driving method of the self-luminous display device 10 of the first embodiment, the first node N1 becomes conductive with the second node N2, the voltages of the first node N1 and the second node N2 gradually rise, the second transistor T2 becomes conductive, a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, and the voltage of the third node N3 rises to follow the rise in the voltage of the first node N1 and the voltage of the second node N2.

[0212] As a result, similarly to the driving method of the self-luminous display device 10 according to the first embodiment, the potential difference Vgs becomes 4.5 V, which is greater than the threshold voltage VTH. Therefore, the second transistor T2 is in an on state, and a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180A (pixel circuit 181A) emits red light, and the three pixels, including the pixel 180A that emits blue light and the pixel 180A that emits green light, emit white light.

[0213] <2-2-3. Third Example of Method for Driving Pixel Circuit 181A> A third example of a method for driving the pixel circuit 181A will be described with reference to Fig. 19. The driving method shown in the third example of the method for driving the pixel circuit 181A includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 18 will be described as necessary.

[0214] The configurations of the image data signal SL(m), scan voltage power supply SIR(n), first scan signal SC1(n), and second scan signal SC2(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor, are the same as those described in the third example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations similar to those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A" and "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A" will be explained as necessary. Also, the same configuration as in "1-6-3. Third example of the method for driving the self-luminous display device 10" will be explained as necessary.

[0215] During the light-emitting period PEM of the (K-1st) frame, for example, the potential difference Vgs is 0.5 V, which is smaller than the threshold voltage VTH of the second transistor T2. The second transistor T2 is in an off state, and no current flows from the driving power supply line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light. As a result, for example, the pixel 180A (pixel circuit 181A) turns black.

[0216] During the initial period of one horizontal period HRP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, pixel 180A (pixel circuit 181A) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL (-0.5V) corresponding to non-light-emitting black. The voltage supplied to first node N1 remains at voltage Vnd (-0.5V), and the first node N1 maintains its state of being supplied with -0.5V. The voltage supplied to second node N2 gradually drops from voltage Vnd (-0.5V) to voltage Vnc (-1.5V).

[0217] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied. The voltage supplied to the first node N1 remains at −0.5 V, and the first node N1 maintains a state in which −0.5 V is supplied. The voltage supplied to the second node N2 gradually drops from the voltage Vnd toward the voltage Vnc and becomes the voltage Vnc (−1.5 V). In addition, the voltage supplied to the third node N3 gradually drops from the voltage Vne (−1 V) toward the initialization voltage VINI1 (voltage Vnc, −1.5 V) and becomes the voltage Vnc (−1.5 V).

[0218] As described above, during the period PIW, the data signal VDATA including the voltage VSIGL (-0.5V) is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-1.5V).

[0219] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied. The voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A."

[0220] As described above, in the same manner as described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A," during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0221] During the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those explained in "2-2-1. First example of the method of driving the pixel circuit 181A." Also, as explained in "2-2-1. First example of the method of driving the pixel circuit 181A," during the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the pixel 180A that emits red does not emit light, and the three pixels using the pixel 180A that emits red, the pixel 180A that emits blue, and the pixel 180A that emits green appear black.

[0222] As described above, in the third example of the method for driving the self-luminous display device 10 according to the second embodiment (method for driving the pixel circuit 181A), similar to the third example of the method for driving the self-luminous display device 10 according to the first embodiment, fluctuations in the voltage of each node when displaying images of the same color (black) in consecutive frames are slight, and therefore power consumption due to fluctuations in the voltage of each node can be reduced. Therefore, the self-luminous display device 10 is a display device that can reduce power consumption.

[0223] <2-2-4. Fourth Example of Method for Driving Pixel Circuit 181A> A fourth example of a method for driving the pixel circuit 181A will be described with reference to Fig. 20. The fourth example of a method for driving the pixel circuit 181A includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 19 will be described as necessary.

[0224] The configurations of the image data signal SL(m), scan voltage power supply SIR(n), first scan signal SC1(n), and second scan signal SC2(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor, are the same as those described in "2-2-3. Third Example of Method for Driving Pixel Circuit 181A." Configurations similar to those described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A" to "2-2-3. Third Example of Method for Driving Pixel Circuit 181A" will be explained as necessary. In addition, the same configuration as in "1-6-4. Fourth example of the method for driving the self-luminous display device 10" will be explained as necessary.

[0225] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180A (pixel circuit 181A) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGH corresponding to white. The voltage supplied to the first node N1 gradually increases from voltage Vnd (-0.5V) toward voltage VSIGH (voltage Vnf, 3.5V), and the voltage supplied to the second node N2 gradually decreases from voltage Vne (-1V) toward voltage Vnc (-1.5V).

[0226] During the period PIW, the voltage supplied to the first node N1 gradually increases from voltage Vnd (-0.5V) to voltage VSIGH (voltage Vnf, 3.5V), and the first node N1 is supplied with voltage Vnf (3.5V). The voltage supplied to the second node N2 gradually decreases from voltage Vne (-1V) to voltage Vnc (-1.5V), and the second node N2 is supplied with voltage Vnc (-1.5V). The voltage supplied to the third node N3 gradually decreases from voltage Vne (-1V) to initialization voltage VINI1 (voltage Vnc, -1.5V), and the third node N3 is supplied with voltage Vnc (-1.5V). At this time, the potential difference Vgs becomes 0V (-1.5V - -1.5V), and the potential difference Vds becomes 9.5V (8V - -1.5V).

[0227] As described above, during the period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (−1.5 V).

[0228] During the period PVH following the period PIW, similar to what was described in "2-2-2", the first node N1 maintains a state in which voltage Vnf is supplied, the second node N2 maintains a state in which initialization voltage VINI2 (0V) is supplied, the voltage supplied to the third node N3 rises from voltage Vnc to voltage Vne, and the third node N3 is supplied with voltage Vne (-1V).

[0229] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0230] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, the potential difference Vgs becomes 4.5 V, as explained in "2-2-2. Second Example of the Driving Method of the Pixel Circuit 181A." The potential difference Vgs is greater than the threshold voltage VTH, the second transistor T2 is in the on state, and a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the light emitting element OLED emits light. For example, the pixel 180A emits red light, and three pixels, including a pixel 180A that emits blue light and a pixel 180A that emits green light, emit white light.

[0231] <2-3. Setting values ​​of initialization voltages VINI1 and VINI2> The set values ​​of the initialization voltages VINI1 and VINI2 will be described with reference to Fig. 21. Fig. 21 is a diagram for explaining the set values ​​of the initialization voltages VINI1 and VINI2 of the scan voltage power supply line SVIR to which the scan voltage power supply SIR(n) is supplied. Configurations that are the same as or similar to those in Figs. 1 to 20 will be described as necessary.

[0232] For example, as shown in FIG. 21, between the period PIW and the period PVH, the scan voltage power supply SIR(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2 is supplied, depending on the timing of the first scan signal SC1(n) and the second scan signal SC2(n).

[0233] During the period PIW, in the pixel circuit 181A, the scan voltage power supply SIR(n) (initialization voltage VINI2) is supplied from the scan voltage power supply line SVIR to the second node N2 and the third node N3, and the second node N2 and the third node N3 are initialized. The pixel 180A including the pixel circuit 181A does not emit light during the period PIW. The condition for the light-emitting element OLED not to emit light is that the initialization voltage VINI1 supplied to the third node N3 is smaller than the threshold voltage VTHEL of the light-emitting element OLED. In other words, the initialization voltage VINI1<threshold voltage VTHEL.

[0234] Furthermore, during the period PVH, the pixel circuit 181A corrects the threshold voltage VTH and holds a charge equivalent to the threshold voltage VTH. The pixel 180A including the pixel circuit 181A does not emit light during the period PVH. The condition for the light-emitting element OLED not to emit light is that the voltage Vne supplied to the third node N3 is smaller than the threshold voltage VTHEL of the light-emitting element OLED. In other words, the voltage Vne<the threshold voltage VTHEL.

[0235] Furthermore, for example, when the pixel circuit 181A emits light based on the voltage VSIGH (initialization voltage VINI2) corresponding to white, the initialization voltage VINI2 is supplied to the second node N2, and the voltage Vne is supplied to the third node N3. At this time, the potential difference Vgs is the difference between the voltage supplied to the second node N2 and the voltage supplied to the third node N3, and the potential difference Vgs = initialization voltage VINI2 - voltage Vne. Furthermore, since a charge equivalent to the threshold voltage VTH is held in the potential difference Vgs, the initialization voltage VINI2 - voltage Vne = threshold voltage VTH.

[0236] The condition for the initialization voltage VINI2 calculated using the above formula is initialization voltage VINI2<threshold voltage VTHEL+threshold voltage VTH, as shown in Fig. 21. Also, the condition for the initialization voltage VINI1 is initialization voltage VINI1<threshold voltage VTHEL.

[0237] 3. Third Embodiment An overview of the self-luminous display device 10 according to the third embodiment will be described with reference to Figs. 1, 4, and 22 to 28. Fig. 22 is a schematic diagram showing input signals to a pixel 180B (pixel circuit 181B) according to the third embodiment of the present invention. Fig. 23 is a circuit diagram showing the configuration of the pixel circuit 181B. Figs. 24 to 27 are timing charts of the self-luminous display device 10 according to the third embodiment of the present invention. Fig. 28 is a diagram for explaining the setting of input signals according to the third embodiment of the present invention.

[0238] The self-luminous display device according to the third embodiment has a configuration and function in which the pixel 180A and pixel circuit 181A of the self-luminous display device 10 according to the second embodiment are replaced with a pixel 180B and pixel circuit 181B. Other configurations and functions are the same as those of the self-luminous display device 10 according to the second embodiment. Therefore, in describing the configuration and functions of the third embodiment, configurations and functions that are the same as those of the self-luminous display device 10 according to the second embodiment will be described as necessary.

[0239] <3-1. Configuration of pixel 180B> The pixel 180B and pixel circuit 181B will be outlined with reference to FIGS.

[0240] 22 and 23, the pixel circuit 181B has a configuration and function in which the scan voltage power supply line SVIR of the pixel circuit 181A is replaced with a scan voltage power supply line SVIRB. Also, as shown in Fig. 23, the configurations of the second transistor T2 and the light-emitting element OLED of the pixel circuit 181B are different from those of the pixel circuit 181A.

[0241] Specifically, as shown in FIG. 22, the pixel circuit 181B is connected to a scan voltage power supply line SVIRB to which a scan voltage power supply SIRB(n) is supplied. The scan voltage power supply line SVIRB, like the scan voltage power supply line SVIR, is a signal line that also serves as both a reference voltage power supply line SVR and an initialization voltage power supply line SVI. The scan voltage power supply SIRB(n) is a signal obtained by inverting the polarity of the scan voltage power supply SIR(n) supplied to the pixel circuit 181A. Like the scan voltage power supply SIRB(n), the polarity of signals other than the scan voltage power supply SIRB(n) supplied to the pixel circuit 181B is also a signal obtained by inverting the polarity of signals other than the scan voltage power supply SIR(n) supplied to the pixel circuit 181A. The scan voltage power supply line SVIRB (a signal line that also serves as both a reference voltage power supply line SVR and an initialization voltage power supply line SVI) may be referred to as a third control signal line. The scan voltage power supply SIRB(n) may be referred to as a third control signal.

[0242] 23, the pixel circuit 181B includes a second transistor T2, which is a p-channel field effect transistor. In the pixel circuit 181B, a second electrode 684 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS, and a first electrode 682 of the light-emitting element OLED is electrically connected to a first electrode 624 of the second transistor T2, a third node N3, a second electrode 656 of the fifth transistor T5, and a first electrode 692 of the capacitor CS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0243] The fourth transistor T4 has a function of connecting the second node N2 and the scan voltage power supply line SVIRB to supply the initialization voltage VINI1 or VINI2 to the second node N2, thereby initializing the second node N2.

[0244] The fifth transistor T5 has a function of connecting the third node N3 and the scan voltage power supply line SVIRB to supply the initialization voltage VINI2 to the third node N3, thereby initializing the third node N3.

[0245] The configuration and functions of the pixel circuit 181B other than those described in "3-1" are the same as those of the pixel circuit 181 or the pixel circuit 181A.

[0246] <3-2. Driving method of pixel circuit 181B> A method for driving the self-luminous display device 10 according to the third embodiment will be described with reference to Figures 24 to 27. Configurations that are the same as or similar to those in Figures 1 to 23 will be described as necessary. As in the first and second embodiments, the horizontal axis of the timing chart represents time.

[0247] For example, the method for driving the self-luminous display device 10 according to the third embodiment is a method in which the polarity of each signal in the method for driving the self-luminous display device 10 according to the second embodiment is inverted, and is a method in which the polarity of the voltage (potential) supplied to each node in the method for driving the self-luminous display device 10 according to the second embodiment is inverted. Other configurations and functions are the same as those in the method for driving the self-luminous display device 10 according to the first embodiment and the method for driving the self-luminous display device 10 according to the second embodiment. Therefore, a description here of the same configurations and functions as those in the method for driving the self-luminous display device 10 according to the second embodiment will be omitted.

[0248] The method for driving the self-luminous display device 10 according to the third embodiment includes the same period as the method for driving the self-luminous display device 10 shown in FIG.

[0249] 24 to 27 are diagrams for explaining the periods PIW and PVH of the method for driving pixel 180B (pixel circuit 181B). Figures 24 to 27 show the light-emitting period PEM of the frame immediately preceding the current frame (K-1stFRAME), and the periods PIW and PVH of the current frame (KthFRAME). Also, Figures 24 to 27 show one horizontal period (horizontal period HRP) for one pixel 180B (pixel circuit 181B).

[0250] During one horizontal period in the driving method for the self-luminous display device 10 according to the third embodiment, the pixel 180B (pixel circuit 181B) receives a first scan signal SC1(n), a second scan signal SC2(n), an image data signal SL(m) including a data signal VDATA, and a scan voltage power supply SIRB(n). For example, the first scan signal SC1(n), the second scan signal SC2(n), and the scan voltage power supply SIR(n) are shifted, and the pixel 180B (pixel circuit 181B) corresponding to the shifted signals is selected. The image data signal SL(m), an initialization voltage VINI, and a reference voltage VREF are input to the selected pixel 180B (pixel circuit 181B). Similar operations are performed for all pixels 180B (pixel circuits 181B), and an image of a frame corresponding to one frame is displayed in the display region 22 of the self-luminous display device 10 based on the image data signal SL(m) input to all pixels 180A (pixel circuits 181A).

[0251] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0252] [Table 5]

[0253] [Table 6]

[0254] As described above, the polarity of the signal supplied to pixel circuit 181B is the inverse of the polarity of the signal supplied to pixel circuit 181A. For example, as shown in Table 5, Table 6, and FIGS. 24 to 27, the voltage VSIGL included in the data signal VDATA is −3.5 V, and the pixel 180 to which the voltage VSIGL is supplied emits light. For example, one pixel emits red, one pixel emits green, one pixel emits blue, and three pixels emit white. Also, for example, the voltage VSIGH included in the data signal VDATA is 0.5 V, and the pixel 180 to which the voltage VSIGH is supplied does not emit light and is black. Also, for example, the voltage VL(LO) is −10 V, the voltage VNN is 5 V, the voltage VMN is −5 V, the initialization voltage VINI1 is 1.5 V, and the initialization voltage VINI2 is 0 V. For example, the voltage VH(HI), voltage VL(LO), voltage VNN, voltage VMN, initialization voltage VINI1, and initialization voltage VINI2 supplied to pixel circuit 181B correspond to voltages (potentials) with the polarity reversed from the voltage VL(LO), voltage VH(HI), voltage VN, voltage VM, initialization voltage VINI2, and initialization voltage VINI1 supplied to pixel circuit 181A.

[0255] <3-2-1. First Example of Method for Driving Pixel Circuit 181B> 24, a first example of a method for driving the pixel circuit 181B will be described. The first example of the method for driving the pixel circuit 181B involves the pixel 180B displaying a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then the pixel 180B displaying a black image based on the voltage VSIGH (0.5V) included in the data signal VDATA in the KthFRAME. In other words, the first example of the method for driving the self-luminous display device 10 according to the third embodiment involves displaying images of different colors in successive frames.

[0256] As described above, the configurations and functions of the image data signal SL(m), the first scan signal SC1(n), and the second scan signal SC2(n) during the light-emitting period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light-emitting period PEM are the same as those of the signals obtained by inverting the polarity of the voltage (potential) of each signal in the method for driving the self-luminous display device 10 according to the second embodiment. Furthermore, for example, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light-emitting period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light-emitting period PEM are voltages (potentials) obtained by inverting the polarity of the voltages (potentials) of each node in the method for driving the self-luminous display device 10 according to the second embodiment. The conduction and non-conduction of each transistor during the light-emitting period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light-emitting period PEM are also the same as those described in "2-2-1. First Example of the Method for Driving the Self-luminous Display Device 10."

[0257] For example, voltages Vnan, Vnbn, Vncn, Vndn, Vnen, and Vnfn are voltages (potentials) with polarities inverted from those of voltages Vna, Vnb, Vnc, Vnd, Vne, and Vnf. Referring to the voltages (potentials) in the driving method according to the second embodiment, voltage Vnan is −7V, Vnbn is −2.5V, voltage Vncn is 1.5V, voltage Vndn is 0.5V, voltage Vnen is 1V, and voltage Vnfn is −3.5V.

[0258] 24, during the light-emitting period PEM of the K-1st FRAME, pixel 180B emits light in accordance with the potential difference Vgs (voltage V(N2)-voltage V(N3)=voltage Vnan-voltage Vnbn) of the second transistor T2. The potential difference Vgs is -4.5V, and pixel 180B emits red light, and three pixels, including pixel 180 emitting red light, pixel 180 emitting blue light, and pixel 180 emitting green light, emit white light.

[0259] During the initial period of one horizontal period HRP of the Kth FRAME following the light emission period PEM of the K-1st FRAME, the scan voltage power supply SIRB(n) changes from a state in which the initialization voltage VINI2 (0 V) is supplied to a state in which the initialization voltage VINI1 (1.5 V) is supplied. When the scan voltage power supply SIRB(n) changes to a state in which the initialization voltage VINI1 is supplied, the first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. Furthermore, the second scan signal SC2(n) is a state in which LO is supplied. Referring to FIG. 24, the conductive and non-conductive states of each transistor during the initial period of one horizontal period HRP of the Kth FRAME in the first example of the driving method according to the second embodiment, the voltage supplied to the first node N1 gradually increases from voltage Vnan toward voltage VSIGH (voltage Vndn), and the voltage supplied to the second node N2 gradually increases from voltage Vnan toward the initialization voltage VINI1 (voltage Vncn). Furthermore, in response to the rise in the voltage supplied to the second node N2, the second transistor T2 changes from an on state to an off state.

[0260] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied. Also during the period PIW, the first scan signal SC1(n) maintains a state in which HI is supplied, the scan voltage power supply SIRB(n) maintains a state in which the initialization voltage VINI1 is supplied, and the second scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. Also, during the final period of the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, the first scan signal SC1(n) maintains a state in which HI is supplied, and the scan voltage power supply SIR(n) maintains a state in which the initialization voltage VINI1 is supplied. Also, the second scan signal SC1(n) changes from a state in which HI is supplied to a state in which LO is supplied.

[0261] Referring to the conductive and non-conductive states of the transistors during the period PIW of the first example in the driving method according to the second embodiment and FIG. 24, the voltage supplied to the first node N1 gradually increases from voltage Vnan toward voltage VSIGH and reaches voltage Vndn (0.5V). The voltage supplied to the second node N2 gradually increases from voltage Vnan toward the initialization voltage VINI1 (voltage Vncn) and reaches voltage Vncn (1.5V). The voltage supplied to the third node N3 gradually increases from voltage Vnbn toward the initialization voltage VINI1 (voltage Vnc) and reaches voltage Vnc (1.5V). The potential difference Vgs becomes 0V, and the potential difference Vds becomes −9.5V (−8V−(1.5V)).

[0262] As described above, during the period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (1.5 V).

[0263] During the period PVH, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied. The first scan signal SC1(n) maintains a state in which HI is supplied, and the second scan signal SC1(n) maintains a state in which LO is supplied. After the second scan signal SC1(n) is supplied with LO during the period PIW, the scan voltage power supply SIRB(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2 is supplied. When the scan voltage power supply SIR(n) changes to a state in which the initialization voltage VINI2 is supplied, the first scan signal SC1(n) changes from a state in which HI is supplied to a state in which LO is supplied.

[0264] Immediately after the start of the period PVH, the potential difference Vgs is 0 V, the potential difference Vds is −9.5 V, and the potential difference Vgs is greater than the threshold voltage VTHP (−1 V, see Table 6) of the second transistor T2, so the second transistor T2 is in the off state. Therefore, the drain current Ion does not flow from the first electrode 624 to the second electrode 626 of the second transistor T2.

[0265] 24, the fourth transistor T4 maintains its on state during the period PVH of KthFRAME in the first example of the driving method according to the second embodiment. Therefore, when the voltage supplied to the scan voltage power supply SIRB(n) changes from the initialization voltage VINI1 to the initialization voltage VINI2, the voltage supplied to the second node N2 gradually drops from voltage Vncn (1.5 V) toward the initialization voltage VINI2 (0 V). At this time, although the fifth transistor T5 is off, the Vgs of the second transistor T2 approaches −1.5 V (0 V (node ​​N2) − (1.5 V) (node ​​N3)), which is greater than the threshold voltage VTH (−1 V). Therefore, the drain current Ion of the second transistor T2 begins to flow. The voltage supplied to the third node N3 gradually drops from voltage Vncn (1.5 V) toward voltage Vne (1 V). As a result, the voltage supplied to the third node N3 becomes the voltage Vnen (1 V), and the potential difference Vgs becomes -1 V (0 V - (1 V)). Because the potential difference Vgs is equal to the threshold voltage VTHP (-1 V), the second transistor T2 is in the off state. Therefore, the drain current Ion does not flow from the second electrode 626 to the first electrode 624 of the second transistor T2.

[0266] In this way, during the period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Also, a charge equivalent to the threshold voltage VTHP is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0267] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, no data is selected using the selection signal, and the data signal VDATA is maintained at a voltage equal to or greater than the voltage VSIGL and equal to or less than the voltage VSIGH. Also, the first scan signal SC1(n) changes from a HI state to a LO state, the second scan signal SC2(n) maintains its LO state, and the scan voltage power supply SIRB(n) maintains its initialization voltage VINI2 (0 V) state.

[0268] Therefore, the first transistor T1 and the fourth transistor T4 change from an on state to an off state, and the third transistor T3 changes from an off state to an on state. The fifth transistor T5 maintains its off state. As the third transistor T3 turns on, the first node N1 and the second node N2 become conductive, and the potential difference Vgs becomes −0.5 V. The potential difference Vgs is smaller than the threshold voltage VTHP. Therefore, the second transistor T2 is off, and no current flows from the driving power supply line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light. As a result, for example, the pixel 180B (pixel circuit 181B) that emits red, the pixel 180B that emits blue, and the pixel 180B that emits green do not emit light, resulting in a black display for the three pixels using the pixel 180B that emits red, the pixel 180B that emits blue, and the pixel 180B that emits green.

[0269] As described above, the method for driving the self-luminous display device 10 according to the third embodiment (the method for driving the pixel circuit 181B), like the method for driving the self-luminous display device 10 according to the second embodiment, includes performing the process (driving) performed in the write period and the process (driving) performed in the initialization period at the same timing. Also, like the pixel circuit 181A, the pixel circuit 181B has a configuration that allows the number of signal lines to be reduced, and therefore the pixel size of a self-luminous display device including the pixel circuit 181B can be reduced. Therefore, the self-luminous display device 10 and the method for driving the self-luminous display device 10 according to the third embodiment have the same effects as the self-luminous display device 10 and the method for driving the self-luminous display device 10 according to the second embodiment.

[0270] <3-2-2. Second Example of Method for Driving Pixel Circuit 181B> A second example of a method for driving the pixel circuit 181B will be described with reference to FIG. 25. The driving method shown in the second example of the pixel circuit 181B involves the pixel 180B displaying a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then the pixel 180B displaying a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in the KthFRAME as well. In other words, the second example of the method for driving the self-luminous display device 10 according to the third embodiment involves displaying images of the same color (white) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 24 will be described as necessary.

[0271] The configurations of the image data signal SL(m), scan voltage power supply SIRB(n), first scan signal SC1(n), and second scan signal SC2(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "3-2-1." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor, are the same as those described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B." Configurations similar to those described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B" will be explained as needed. Configurations similar to those described in "2-2-2. Second Example of Method for Driving Pixel Circuit 181A" will be explained as needed.

[0272] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180B (pixel circuit 181B) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL corresponding to white. The voltage supplied to the first node N1 gradually increases from voltage Vnan toward voltage VSIGL (voltage Vnfn, −3.5V). The voltage supplied to the second node N2 and the voltage supplied to the third node N3 are the same as those described in “3-2-1. First Example of the Method for Driving the Pixel Circuit 181B.”

[0273] During the period PIW, the voltage supplied to the first node N1 gradually rises from voltage Vnan toward voltage Vnfn, and reaches voltage Vnfn (-3.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "3-2-1. First example of the method for driving the pixel circuit 181B."

[0274] As described above, during the period PIW, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (1.5 V).

[0275] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied. The first node N1 maintains a state in which the voltage Vnfn is supplied. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B."

[0276] As described above, in the same manner as described in "3-2-1", during the period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Also, a charge equivalent to the threshold voltage VTHP is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0277] During the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the conductive and non-conductive states of each transistor during the light emission period PEM of the KthFRAME in the second example of the driving method according to the second embodiment, and referring to Figure 24, the first node N1 becomes conductive with the second node N2, the voltages of the first node N1 and the second node N2 gradually drop, the second transistor T2 becomes conductive, a drain current Ion flows from the reference voltage line PVSS to the drive power supply line PVDD, and the voltage of the third node N3 drops to follow the drop in the voltage of the first node N1 and the voltage of the second node N2.

[0278] As a result, the potential difference Vgs (voltage Vnan (-7V) - voltage Vnbn (-2.5V)) becomes -4.5V, and the potential difference Vgs becomes smaller than the threshold voltage VTHP (-1V). Therefore, the second transistor T2 is in the on state, and a drain current Ion flows from the reference voltage line PVSS to the drive power supply line PVDD, causing the light-emitting element OLED to emit light. For example, pixel 180B (pixel circuit 181B) emits red, and three pixels, including pixel 180B that emits blue and pixel 180B that emits green, emit white.

[0279] <3-2-3. Third Example of Method for Driving Pixel Circuit 181B> A third example of a method for driving pixel circuit 181B will be described with reference to FIG. 26. The driving method shown in the third example of the method for driving pixel circuit 181B involves pixel 180B displaying a black image based on voltage VSIGL included in data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME) based on data signal VDATA, and then pixel 180B also displaying a black image based on voltage VSIGH included in data signal VDATA in Kth FRAME. In other words, it involves displaying images of the same color (black) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 25 will be described as necessary.

[0280] The configurations of the image data signal SL(m), scan voltage power supply SIRB(n), first scan signal SC1(n), and second scan signal SC2(n) during the light emission period PEM of the K-1stFRAME, one horizontal period HRP of the KthFRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "3-2-1. First example of driving method for pixel circuit 181B."

[0281] Referring to the conductive and non-conductive states of each transistor during the light-emitting period PEM of the K-1st FRAME in the third example of the driving method according to the second embodiment, and to FIG. 26, during the light-emitting period PEM of the K-1st FRAME, the pixel 180B emits light according to the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage Vnen - voltage Vnen) of the second transistor T2. The potential difference Vgs is 0V and is greater than the threshold voltage VTHP (-1V) of the second transistor T2. Since the second transistor T2 is in the off state and no current flows from the reference voltage line PVSS to the driving power supply line PVDD, the light-emitting element OLED does not emit light at all. As a result, for example, the pixel 180B (pixel circuit 181B) turns black.

[0282] During the initial period of one horizontal period HRP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, pixel 180B (pixel circuit 181B) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH (0.5 V) corresponding to the non-light-emitting black color. Referring to FIG. 26 , the conductive and non-conductive states of the transistors during the initial period of one horizontal period HRP of the Kth FRAME in the third example of the driving method according to the second embodiment, the voltage supplied to the first node N1 remains at voltage Vndn (0.5 V), and the first node N1 maintains the state in which 0.5 V is supplied. The voltage supplied to the second node N2 gradually rises from voltage Vndn (0.5 V) toward initialization voltage VINI1 (voltage Vncn, 1.5 V).

[0283] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied. The first node N1 maintains a state in which 0.5V is supplied. The voltage supplied to the second node N2 gradually increases from the voltage Vndn toward the voltage Vncn, and becomes the voltage Vncn (1.5V). The voltage supplied to the third node N3 gradually increases from the voltage Vnen (1V) toward the initialization voltage VINI1 (voltage Vncn, 1.5V), and becomes the voltage Vncn (1.5V).

[0284] As described above, during the period PIW, the data signal VDATA including the voltage VSIGH (0.5V) is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (1.5V).

[0285] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied. The voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "3-2-1. First example of the method for driving the pixel circuit 181B."

[0286] As described above, in the same manner as described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," during the period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Also, a charge equivalent to the threshold voltage VTHP is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0287] In the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those explained in "3-2-1. First example of the method of driving the pixel circuit 181B." As explained in "3-2-1. First example of the method of driving the pixel circuit 181B," the pixel 180B that emits red does not emit light, and the three pixels that use the pixel 180B that emits red, the pixel 180B that emits blue, and the pixel 180B that emits green appear black.

[0288] As described above, in the third example of the method for driving the self-luminous display device 10 according to the third embodiment (method for driving the pixel circuit 181B), similar to the third example of the method for driving the self-luminous display device 10 according to the second embodiment, fluctuations in the voltage of each node when displaying images of the same color (black) in consecutive frames are slight, and therefore power consumption due to fluctuations in the voltage of each node can be reduced. Therefore, the self-luminous display device 10 is a display device that can reduce power consumption.

[0289] <3-2-4. Fourth Example of Method for Driving Pixel Circuit 181B> A fourth example of a method for driving pixel circuit 181B will be described with reference to FIG. 27. The driving method shown in the fourth example of the method for driving pixel circuit 181B involves pixel 180B (pixel circuit 181B) displaying a black image based on voltage VSIGH included in data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then pixel 180 (pixel circuit 181) displaying a white image based on voltage VSIGL included in data signal VDATA in KthFRAME. In other words, it involves displaying images of different colors in successive frames. Configurations that are the same as or similar to those in FIGS. 1 to 26 will be described as necessary.

[0290] The configurations of the image data signal SL(m), scan voltage power supply SIRB(n), first scan signal SC1(n), and second scan signal SC2(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "3-2-1." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor, are the same as those described in "3-2-3. Third Example of Method for Driving Pixel Circuit 181B." Configurations similar to those described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B" to "3-2-3. Third Example of Method for Driving Pixel Circuit 181B" will be explained as necessary.

[0291] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180B (pixel circuit 181B) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGL corresponding to white. The voltage supplied to the first node N1 gradually drops from voltage Vndn (0.5 V) toward voltage VSIGL (voltage Vnfn, −3.5 V), and the voltage supplied to the second node N2 gradually rises from voltage Vnen (1 V) toward voltage Vncn (1.5 V).

[0292] During the period PIW, the voltage supplied to the first node N1 gradually drops from voltage Vndn (0.5V) toward voltage VSIGL (voltage Vnfn, −3.5V), and the first node N1 is supplied with voltage Vnfn (−3.5V). The voltage supplied to the second node N2 gradually rises from voltage Vnen (0.5V) toward voltage Vncn (1.5V), and the second node N2 is supplied with voltage Vncn (1.5V). Furthermore, the voltage supplied to the third node N3 gradually rises from voltage Vnen (1V) toward initialization voltage VINI1 (voltage Vncn, 1.5V), and the third node N3 is supplied with voltage Vncn (1.5V). At this time, the potential difference Vgs becomes 0V (1.5V-(1.5V)), and the potential difference Vds becomes -9.5V (-8V-(1.5V)).

[0293] As described above, during the period PIW, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (1.5 V).

[0294] During the period PVH following the period PIW, similar to the contents explained in "3-2-2," the first node N1 maintains a state in which the voltage Vnfn is supplied, the second node N2 maintains a state in which the initialization voltage VINI2 (0V) is supplied, the voltage supplied to the third node N3 drops from the voltage Vncn to the voltage Vnen, and the third node N3 is supplied with the voltage Vnen (1V). At this time, Vgs is -1V (0V-1V), which is the same as the threshold voltage VTHP (-1V).

[0295] In this way, during the period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Also, a charge equivalent to the threshold voltage VTHP is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0296] During the light-emitting period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, the potential difference Vgs becomes -4.5V, as described in "3-2-2." The potential difference Vgs is smaller than the threshold voltage VTHP, the second transistor T2 is in the on state, and a drain current Ion flows from the reference voltage line PVSS to the driving power supply line PVDD. As a result, the light-emitting element OLED emits light. For example, pixel 180B emits red light, and three pixels, including pixel 180B emitting blue light and pixel 180B emitting green light, emit white light.

[0297] <3-3. Setting values ​​of initialization voltages VINI1 and VINI2> The set values ​​of the initialization voltages VINI1 and VINI2 will be described with reference to Fig. 28. Fig. 28 is a diagram for explaining the set values ​​of the initialization voltages VINI1 and VINI2 of the scan voltage power supply line SVIRB to which the scan voltage power supply SIRB(n) is supplied. Configurations that are the same as or similar to those in Figs. 1 to 27 will be described as necessary.

[0298] For example, as shown in FIG. 28, between the period PIW and the period PVH, the scan voltage power supply SIRB(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2 is supplied, depending on the timing of the first scan signal SC1(n) and the second scan signal SC2(n).

[0299] During the period PIW, in the pixel circuit 181B, the scan voltage power supply SIRB(n) (initialization voltage VINI1) is supplied from the scan voltage power supply line SVIRB to the second node N2 and the third node N3, thereby initializing the second node N2 and the third node N3. The pixel 180B including the pixel circuit 181B does not emit light during the period PIW. The condition for the light-emitting element OLED not to emit light is that the initialization voltage VINI1 supplied to the third node N3 is greater than the threshold voltage VTHEL of the light-emitting element OLED. That is, the initialization voltage VINI1>threshold voltage VTHEL.

[0300] Furthermore, during the period PVH, the pixel circuit 181B corrects the threshold voltage VTHP and holds a charge equivalent to the threshold voltage VTHP. The pixel 180B including the pixel circuit 181B does not emit light during the period PVH. The condition for the light-emitting element OLED not to emit light is that the voltage Vnen supplied to the third node N3 is greater than the threshold voltage VTHEL of the light-emitting element OLED. That is, the voltage Vnen is greater than the threshold voltage VTHEL.

[0301] Furthermore, for example, when the pixel circuit 181B emits light based on the voltage VSIGL corresponding to white, the initialization voltage VINI2 is supplied to the second node N2, and the voltage Vnen is supplied to the third node N3. At this time, the potential difference Vgs is the difference between the voltage supplied to the second node N2 and the voltage supplied to the third node N3, and the potential difference Vgs = initialization voltage VINI2 - voltage Vnen. Furthermore, since a charge equivalent to the threshold voltage VTHP is held in the potential difference Vgs, the initialization voltage VINI2 - voltage Vnen = threshold voltage VTHP.

[0302] The condition for the initialization voltage VINI2 calculated using the above formula is initialization voltage VINI2>threshold voltage VTHEL+threshold voltage VTHP, as shown in Fig. 28. Also, the condition for the initialization voltage VINI1 is initialization voltage VINI1>threshold voltage VTHEL.

[0303] 4. Fourth Embodiment An overview of a self-luminous display device 10 according to a fourth embodiment will be described with reference to FIGS. 1, 4, and 29 to 37. FIG. 29 is a schematic diagram showing input signals to a pixel 180C (pixel circuit 181C) according to the fourth embodiment of the present invention. FIG. 30 is a circuit diagram showing the configuration of the pixel circuit 181C. FIGS. 31, 34, 36, and 37 are timing charts of the self-luminous display device 10 according to the fourth embodiment of the present invention. FIGS. 32 and 33 are schematic diagrams showing the operating state of the pixel circuit 181C at the timing shown in FIG. 31. FIG. 35 is a schematic diagram showing the operating state of the pixel circuit 181C at the timing shown in FIG. 34.

[0304] The self-luminous display device according to the fourth embodiment has a configuration and function in which the pixel 180A and pixel circuit 181A of the self-luminous display device 10 according to the second embodiment are replaced with a pixel 180C and pixel circuit 181C. Other configurations and functions are the same as those of the self-luminous display device 10 according to the second embodiment. Therefore, in describing the configuration and functions of the fourth embodiment, configurations and functions that are the same as those of the self-luminous display device 10 according to the second embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 28 will be described as necessary.

[0305] <4-1. Configuration of pixel 180C> The pixel 180C and pixel circuit 181C will be outlined with reference to FIGS.

[0306] The pixel circuit 181C is connected to a second scan signal line 334. The second scan signal line 334 according to the fourth embodiment is a signal line that serves both as the second scan signal line 334 supplied to the pixel circuit 181A and as the scan voltage power supply line SVIR. In other words, the second scan signal line 334 according to the fourth embodiment is a common signal line that combines the second scan signal line 334 supplied to the pixel circuit 181A and the scan voltage power supply line SVIR. The second scan signal line 334 according to the fourth embodiment is supplied with a common scan voltage power supply SIR2(n), which is a combination of the second scan signal and scan voltage power supply SIR(n) supplied to the pixel circuit 181A. The second scan signal line 334 according to the fourth embodiment (a signal line that serves both as the second scan signal line 334 and the scan voltage power supply line SVIR) may be referred to as a third control signal line. The scan voltage power supply SIR2(n) may be referred to as a third control signal.

[0307] In the pixel circuit 181C, a first electrode 644 of the fourth transistor T4 and a first electrode 654 and a gate electrode 652 of the fifth transistor T5 are electrically connected to the second scan signal line 334. The fourth transistor T4 has a function of connecting the second node N2 and the second scan signal line 334 electrically to supply an initialization voltage VINI1 or VINI2 to the second node N2, thereby initializing the second node N2.

[0308] The pixel circuit 181C also includes a fifth transistor T5, which is a p-channel field effect transistor. The fifth transistor T5 has a function of connecting the third node N3 and the second scan signal line 334 to each other, supplying an initialization voltage VINI1 to the third node N3, and initializing the third node N3.

[0309] The configuration and functions of the pixel circuit 181C other than those described in "4-1" are the same as those of the pixel circuit 181A.

[0310] <4-2. Driving method of pixel circuit 181C> A method for driving a self-luminous display device 10 according to a fourth embodiment will be described with reference to Figures 29 to 37. Configurations that are the same as or similar to those in Figures 1 to 30 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time.

[0311] The method for driving the self-luminous display device 10 according to the fourth embodiment has a configuration and functions in which the operations related to the second scan signal SC2(n) and the scan voltage power supply SIR(n) in the method for driving the self-luminous display device 10 according to the second embodiment are replaced with operations related to the scan voltage power supply SIR2(n). The configurations and functions other than the operations related to the scan voltage power supply SIR2(n) are the same as those of the method for driving the self-luminous display device 10 according to the second embodiment. Descriptions of the configurations and functions similar to those of the method for driving the self-luminous display device 10 according to the second embodiment will be omitted here.

[0312] The method for driving the self-luminous display device 10 according to the fourth embodiment includes the same period as the method for driving the self-luminous display device 10 shown in FIG.

[0313] Figures 31, 34, 36, and 37 are diagrams for explaining the periods PIW and PVH of the method for driving pixel 180C (pixel circuit 181C). Figures 31 to 34 show the light-emitting period PEM of the frame immediately before the current frame (K-1stFRAME), and the periods PIW and PVH of the current frame (KthFRAME). Figures 31, 34, 36, and 37 also show one horizontal period (horizontal period HRP) for one pixel 180C (pixel circuit 181C).

[0314] During one horizontal period in the driving method for the self-luminous display device 10 according to the fourth embodiment, the pixel 180C (pixel circuit 181C) receives an image data signal SL(m) including a scan signal SC(n), a scan voltage power supply SIR2(n), and a data signal VDATA. For example, the scan signal SC(n) and the scan voltage power supply SIR2(n) are shifted, and the pixel 180C (pixel circuit 181C) corresponding to the shifted signal is selected. The image data signal SL(m), an initialization voltage VINI, and a reference voltage VREF are input to the selected pixel 180C (pixel circuit 181C). Similar operations are performed for all pixels 180C (pixel circuits 181C), and an image of a frame corresponding to one frame is displayed in the display region 22 of the self-luminous display device 10 based on the image data signal SL(m) input to all pixels 180C (pixel circuits 181C).

[0315] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0316] [Table 7]

[0317] [Table 8]

[0318] As shown in Tables 7 and 8 and FIGS. 31 to 34, the driving method of the self-luminous display device 10 according to the fourth embodiment, the voltage VSIGL included in the data signal VDATA is −0.5 V, and the pixels 180 supplied with the voltage VSIGL do not emit light and appear black. The voltage VSIGH included in the data signal VDATA is 3.5 V, and the pixels 180 supplied with the voltage VSIGH emit light. For example, one pixel emits red, one pixel emits green, one pixel emits blue, and three pixels emit white. Also, for example, the voltage VL(LO) is −3.5V, the voltage VH(HI) is 10V, the voltage VN is −5V, the voltage VM is 5V, the initialization voltage VINI1 is −3.5V, the initialization voltage VINI2 is 0V, the threshold voltage VTH of the second transistor T2 is 1V, the threshold voltage VTHPT5 of the fifth transistor T5 is −1V, and the threshold voltage VTHEL of the light-emitting element OLED is 0.7V.

[0319] <4-2-1. First Example of Method for Driving Pixel Circuit 181C> A first example of a method for driving pixel circuit 181C will be described with reference to Figures 31 and 33. Similar to "2-2-1. First example of a method for driving pixel circuit 181A," the first example of a method for driving pixel circuit 181C includes displaying images of different colors in consecutive frames.

[0320] The configuration and function of the image data signal SL(m) during the light emission period PEM of the K-1stFRAME, one horizontal period HRP of the KthFRAME, and the light emission period PEM are the same as those in "2-2-1. First example of the driving method of the pixel circuit 181A," and the configuration and function of the scan signal SC(n) are the same as those of the first scan signal SC1(n) in the self-luminous display device 10 according to the second embodiment.

[0321] During the light emission period PEM of the K-1st FRAME, the pixel 180C emits light in accordance with the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage Vna - voltage Vnb) of the second transistor T2. For example, the scan signal SC(n) and the scan voltage power supply SIR2(n) are supplied with LO. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are in the off state, and the third transistor T3 is in the on state. Furthermore, the voltage Vna supplied to the first node N1 and the second node N2 is 7 V, and the voltage Vnb supplied to the third node N3 is 2.5 V. Therefore, the potential difference Vgs is 4.5 V, and the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds corresponding to the voltage VSIGH input during one horizontal period HRP of the K-1st FRAME. Also, the second transistor T2 is in an on state, and a current Ion flows from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180C emits red light, and the three pixels, the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180, emit white light.

[0322] For example, as shown in FIGS. 31 and 32, during the initial period of one horizontal period HRP of the Kth FRAME following the light emission period PEM of the K-1st FRAME, the scan voltage power supply SIR2(n) changes from a state in which HI is supplied to a state in which the initialization voltage VINI1 (voltage Vnh, −3.5V) is supplied. When the scan voltage power supply SIR2(n) changes to a state in which the initialization voltage VINI1 is supplied, the scan signal SC(n) changes from a state in which LO is supplied to a state in which HI is supplied. Therefore, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 change from an off state to an on state, and the third transistor T3 changes from an on state to an off state. As a result, for example, the voltage supplied to the third node N3 gradually drops from voltage Vnb. Furthermore, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGL (voltage Vnd, −0.5V), and the voltage supplied to the second node N2 gradually drops from voltage Vna toward initialization voltage VINI1 (voltage Vnh, −3.5V).

[0323] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, the scan signal SC(n) maintains a state in which HI is supplied, and the scan voltage power supply SIR2(n) maintains a state in which the initialization voltage VINI1 (voltage Vnh, −3.5 V) is supplied. Therefore, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 maintain an on state, and the third transistor T6 maintains an off state.

[0324] As a result, the voltage supplied to the third node N3 gradually drops from voltage Vnb, and when the potential difference between the initialization voltage VINI1 (-3.5 V) supplied to the gate electrode 652 and the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) becomes equal to the threshold voltage VTHPT5 (-1 V) of the fifth transistor T5, the fifth transistor T5 changes from an ON state to an OFF state. That is, when the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) becomes voltage Vng (-2.5 V), the fifth transistor T5 changes from an ON state to an OFF state. In addition, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGL (voltage Vnd, -0.5 V) and reaches voltage Vnd (-0.5 V). The voltage supplied to the second node N2 gradually drops from voltage Vna toward the initialization voltage VINI1 (voltage Vnh, −3.5V) and reaches the initialization voltage VINI1 (−3.5V). When the voltage (−3.5V) supplied to the second node N2 becomes lower than the voltage (−2.5V) of the third node N3, the second transistor T2 changes from the ON state to the OFF state. When the second transistor T2 is in the OFF state, the potential difference Vds becomes 10.5V (8V - (−2.5V)).

[0325] In this way, a data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (-3.5V), and the third node N3 is initialized to the voltage Vng (-2.5V) by the initialization voltage VINI1 (voltage Vnh, -3.5V).

[0326] 31 and 33, during the period PVH, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, and the scan signal SC(n) maintains a state in which HI is supplied. The scan voltage power supply SIR2(n) changes from a state in which the initialization voltage VINI1 (voltage Vnh, −3.5 V) is supplied to a state in which the initialization voltage VINI2 (0 V) is supplied. Therefore, the fifth transistor T5 changes from an off state to an on state, the first transistor T1 and the fourth transistor T4 maintain an on state, and the third transistor T5 maintains an off state.

[0327] Immediately after the start of the period PVH, the potential difference Vgs is −1 V, the potential difference Vds is 9.5 V, and the potential difference Vgs is smaller than the threshold voltage VTH (1 V), so the second transistor T2 is in the off state. Therefore, the drain current Ion does not flow from the second electrode 626 to the first electrode 624 of the second transistor T2.

[0328] As a result, the voltage supplied to the first node N1 remains at voltage Vnd (-0.5V), and the voltage supplied to the second node N2 gradually increases from voltage Vnh (-3.5V) toward the initialization voltage VINI2 (0V), reaching the initialization voltage VINI2 (0V). The voltage supplied to the third node N3 gradually increases from voltage Vng (-2.5V). When the potential difference between the initialization voltage VINI2 (0V) supplied to the gate electrode 652 and the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) becomes equal to the threshold voltage VTH (1V) of the second transistor T2, the second transistor T2 changes from an ON state to an OFF state. That is, the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) changes from voltage Vng (-2.5V) to voltage Vne (-1V), causing the second transistor T2 to change from an ON state to an OFF state. Therefore, the potential difference Vgs becomes 1 V (0 V - (-1 V)). Because the potential difference Vgs is the same as the threshold voltage VTH (1 V), the second transistor T2 is in the off state. Therefore, the drain current Ion does not flow from the second electrode 626 to the first electrode 624 of the second transistor T2.

[0329] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0330] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, no data is selected using the selection signal, and the data signal VDATA is maintained at a voltage greater than or equal to VSIGL and less than or equal to VSIGH. Furthermore, the scan signal SC(n) changes from a state in which HI is supplied to a state in which LO is supplied. When the scan signal SC(n) changes to a state in which LO is supplied, the scan voltage power supply SIR2(n) changes from a state in which the initialization voltage VINI2 (0 V) is supplied to a state in which HI (10 V) is supplied.

[0331] Therefore, the first transistor T1 and the fourth transistor T4 change from an on state to an off state, and the third transistor T3 changes from an off state to an on state. The fifth transistor T5 maintains its off state. When the third transistor T3 turns on, the first node N1 and the second node N2 are electrically connected, and the potential difference Vgs becomes 0.5 V (−0.5 V−(−1 V)). The potential difference Vgs is smaller than the threshold voltage VTH. Therefore, the second transistor T2 is in an off state, and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. As a result, for example, the pixel 180C emitting red, the pixel 180C emitting blue, and the pixel 180C emitting green do not emit light, and the three pixels using the pixel 180C emitting red, the pixel 180C emitting blue, and the pixel 180C emitting green are black.

[0332] As described above, the method for driving the self-luminous display device 10 according to the fourth embodiment (the method for driving the pixel circuit 181C) includes performing the process (driving) performed in the write period and the process (driving) performed in the initialization period at the same timing, similar to the method for driving the self-luminous display device 10 according to the second embodiment. Therefore, the method for driving the pixel circuit 181C has the same effects as the method for driving the self-luminous display device 10 according to the second embodiment.

[0333] Furthermore, the pixel circuit 181C is connected to a second scan signal line 334 that is a combination of the second scan signal line SC2(n) and the scan voltage power supply line SVIR that were supplied to the pixel circuit 181A. Therefore, the pixel circuit 181C has a configuration that allows the number of signal lines to be reduced, and therefore, a self-luminous display device including the pixel circuit 181C can reduce the pixel size. As a result, a self-luminous display device including the pixel circuit 181C can increase the number of pixels and achieve higher definition.

[0334] <4-2-2. Second Example of Method for Driving Pixel Circuit 181C> A second example of a method for driving pixel circuit 181C will be described with reference to Figures 34 and 35. The driving method shown in the second example of pixel circuit 181C includes displaying images of the same color (white) in consecutive frames, similar to "2-2-2. Second example of method for driving pixel circuit 181B." Configurations that are the same as or similar to those in Figures 1 to 31 will be described as necessary.

[0335] The configurations of the image data signal SL(m), scan voltage power supply SIR2(n), and scan signal SC(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "4-2-1." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor, are the same as those described in "4-2-1. First Example of Method for Driving Pixel Circuit 181C." Configurations similar to those described in "4-2-1. First Example of Method for Driving Pixel Circuit 181C" will be explained as necessary. Configurations similar to those described in "2-2-2. Second Example of Method for Driving Pixel Circuit 181A" will be explained as necessary.

[0336] During the first period of one horizontal period HRP of the KthFRAME, the pixel 180C (pixel circuit 181C) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGH corresponding to white. The voltage supplied to the first node N1 gradually drops from the voltage Vna toward the voltage VSIGH (voltage Vnf, 3.5V). The voltage supplied to the second node N2 and the voltage supplied to the third node N3 are the same as those described in "4-2-1," and therefore will not be described here.

[0337] During the period PIW, the voltage supplied to the first node N1 gradually drops from voltage Vna to voltage Vnf, reaching voltage Vnf (3.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "4-2-1," and therefore will not be described here.

[0338] In this way, during the period PIW, a data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (-3.5V), and the third node N3 is initialized by the initialization voltage VINI1 (voltage Vnh, -3.5V) and voltage Vng (-2.5V).

[0339] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied. The first node N1 maintains a state in which the voltage Vnf is supplied. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C," and therefore will not be described here.

[0340] As described above, in the same manner as described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C," during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0341] During the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, similar to the driving method of the self-luminous display device 10 of the second embodiment, for example, as shown in Figure 35, the first node N1 becomes conductive with the second node N2, the voltage of the first node N1 and the voltage of the second node N2 gradually rise, the second transistor T2 becomes conductive, a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, and the voltage of the third node N3 rises to follow the rise in the voltage of the first node N1 and the voltage of the second node N2.

[0342] As a result, similarly to the driving method of the self-luminous display device 10 according to the first embodiment, the potential difference Vgs becomes 4.5 V, which is greater than the threshold voltage VTH. Therefore, the second transistor T2 is in an on state, and a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180C (pixel circuit 181C) emits red light, and the three pixels, including the pixel 180C that emits blue light and the pixel 180C that emits green light, emit white light.

[0343] <4-2-3. Third Example of Driving Method of Pixel Circuit 181C> A third example of a method for driving the pixel circuit 181C will be described with reference to Fig. 36. The driving method shown in the third example of the method for driving the pixel circuit 181C includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the self-luminous display device 10 according to the second embodiment. Configurations that are the same as or similar to those in Figs. 1 to 35 will be described as necessary.

[0344] The light emission period PEM of the K-1st FRAME, the horizontal period HRP of the Kth FRAME, the image data signal SL(m), the scan voltage power supply SIR2(n), the scan signal SC(n), and the conductive and non-conductive states of each transistor during the light emission period PEM are the same as those described in "4-2-1." Configurations similar to those described in "4-2-1. First Example of a Method for Driving Pixel Circuit 181C" will be explained as necessary. Furthermore, configurations similar to those described in "2-2-3. Third Example of a Method for Driving Pixel Circuit 181A" will be explained as necessary.

[0345] During the light-emitting period PEM of the (K-1st) frame, for example, the potential difference Vgs is 0.5 V, which is smaller than the threshold voltage VTH (1 V, see Table 8) of the second transistor T2. Since the second transistor T2 is in the off state and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, the light-emitting element OLED does not emit light. As a result, for example, the pixel 180C (pixel circuit 181C) turns black.

[0346] During the initial period of one horizontal period HRP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, the scan voltage power supply SIR2(n) changes from a state in which HI is supplied to a state in which the initialization voltage VINI1 (voltage Vnh, −3.5V) is supplied. When the scan voltage power supply SIR2(n) changes to a state in which the initialization voltage VINI1 is supplied, the scan signal SC(n) changes from a state in which LO is supplied to a state in which HI is supplied. The pixel 180C (pixel circuit 181C) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGL (−0.5V) corresponding to the non-light-emitting black color. The voltage supplied to the first node N1 remains at voltage Vnd (−0.5V), and the first node N1 maintains the state in which −0.5V is supplied. The voltage supplied to the third node N3 gradually drops from voltage Vnd (−0.5V) to voltage Vng (−2.5V). The voltage supplied to the second node N2 gradually drops from the voltage Vnd (-0.5V) toward the voltage Vnh (-3.5V).

[0347] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied. The voltage supplied to the first node N1 remains at −0.5 V, and the first node N1 maintains a state in which −0.5 V is supplied. The voltage supplied to the second node N2 gradually drops from voltage Vnd toward voltage Vnh, becoming voltage Vnh (−3.5 V). Furthermore, the voltage supplied to the third node N3 gradually drops from voltage Vne (−1 V) toward voltage Vng (−2.5 V), becoming voltage Vng (−2.5 V).

[0348] In this way, during the period PIW, the first node N1 is supplied (written) with a data signal VDATA including a voltage VSIGL (-0.5V), the second node N2 is initialized by the initialization voltage VINI1 (-3.5V), and the third node N3 is initialized to a voltage Vng (-2.5V) by the initialization voltage VINI1 (voltage Vnh, -3.5V).

[0349] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied. The voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "4-2-1. First example of the method for driving the pixel circuit 181C."

[0350] As described above, in the same manner as described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C," during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0351] During the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those explained in "4-2-1. First example of the method of driving the pixel circuit 181C." Also, as explained in "4-2-1. First example of the method of driving the pixel circuit 181C," during the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the pixel 180C that emits red does not emit light, and the three pixels that use the pixel 180C that emits red, the pixel 180C that emits blue, and the pixel 180C that emits green appear black.

[0352] As described above, in the third example of the method for driving the self-luminous display device 10 according to the fourth embodiment (method for driving the pixel circuit 181C), similar to the third example of the method for driving the self-luminous display device 10 according to the first embodiment, fluctuations in the voltage of each node when displaying images of the same color (black) in consecutive frames are slight, and therefore power consumption due to fluctuations in the voltage of each node can be reduced. Therefore, the self-luminous display device 10 is a display device that can reduce power consumption.

[0353] <4-2-4. Fourth Example of Driving Method of Pixel Circuit 181C> A fourth example of a method for driving the pixel circuit 181C will be described with reference to Fig. 37. The fourth example of a method for driving the pixel circuit 181C includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the self-luminous display device 10 according to the second embodiment. Configurations that are the same as or similar to those in Figs. 1 to 36 will be described as necessary.

[0354] The configurations of the image data signal SL(m), scan voltage power supply SIR2(n), and scan signal SC(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "4-2-1." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor, are the same as those described in "4-2-3. Third Example of the Method for Driving the Pixel Circuit 181C." Configurations similar to those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C" to "4-2-3. Third Example of the Method for Driving the Pixel Circuit 181C" will be explained as necessary. Configurations similar to those described in "3-2-3. Fourth Example of the Method for Driving the Pixel Circuit 181C" will be explained as necessary.

[0355] During the first period of one horizontal period HRP of the KthFRAME, the pixel 180C (pixel circuit 181C) receives the image data signal SL(m), which includes the data signal VDATA, including the voltage VSIGH corresponding to white. As explained in "4-2-3," the scan voltage power supply SIR2(n) changes from a state in which HI is supplied to a state in which the initialization voltage VINI1 (voltage Vnh, -3.5V) is supplied. When the scan voltage power supply SIR2(n) receives the initialization voltage VINI1, the scan signal SC(n) changes from a state in which LO is supplied to a state in which HI is supplied. The voltage supplied to the first node N1 gradually rises from voltage Vnd (-0.5V) toward voltage VSIGH (voltage Vnf, 3.5V), the voltage supplied to the second node N2 gradually drops from voltage Vnd (-0.5V) toward voltage Vng (-3.5V), and the voltage supplied to the third node N3 gradually drops from voltage Vne (-1V) toward voltage Vnh (-2.5V).

[0356] During the period PIW, the voltage supplied to the first node N1 gradually increases from voltage Vnd (-0.5V) to voltage VSIGH (voltage Vnf, 3.5V), and the first node N1 is supplied with voltage Vnf (3.5V). The voltage supplied to the second node N2 gradually decreases from voltage Vne (-1V) to voltage Vng (-3.5V), and the second node N2 is supplied with voltage Vnd (-3.5V). The voltage supplied to the third node N3 gradually decreases from voltage Vne (-1V) to voltage Vnh (-2.5V), and the third node N3 is supplied with voltage Vnh (-2.5V). At this time, the potential difference Vgs becomes -1V (-3.5V - -3.5V), and the potential difference Vds becomes 10.5V (8V - -2.5V).

[0357] In this way, during the period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (-3.5V), and the third node N3 is initialized to the voltage Vng (-2.5V) by the initialization voltage VINI1 (voltage Vnh, -3.5V).

[0358] During the period PVH following the period PIW, similar to what was explained in "4-2-2. Second example of the driving method for pixel circuit 181C", the first node N1 remains supplied with voltage Vnf, the second node N2 rises to the initialization voltage VINI2 (0V), the voltage supplied to the third node N3 rises from voltage Vnc to voltage Vne, and the third node N3 is supplied with voltage Vne (-1V).

[0359] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0360] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, the potential difference Vgs becomes 4.5 V, as explained in "4-2-2. Second Example of the Driving Method of the Pixel Circuit 181C." The potential difference Vgs is greater than the threshold voltage VTH, the second transistor T2 is in the on state, and a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the light emitting element OLED emits light. For example, the pixel 180C emits red light, and the three pixels, including the pixel 180C that emits blue light and the pixel 180C that emits green light, emit white light.

[0361] 5. Fifth Embodiment An overview of the self-luminous display device 10 according to the fifth embodiment will be described with reference to FIGS. 1, 4, and 38 to 28. FIG. 38 is a schematic diagram showing input signals to a pixel 180D (pixel circuit 181D) according to the fifth embodiment of the present invention. FIG. 39 is a circuit diagram showing the configuration of the pixel circuit 181D. FIGS. 40, 43, 45, and 46 are timing charts of the self-luminous display device 10 according to the fifth embodiment of the present invention. FIGS. 41 and 42 are schematic diagrams showing the operating state of the pixel circuit 181D at the timing shown in FIG. 40. FIG. 44 is a schematic diagram showing the operating state of the pixel circuit 181D at the timing shown in FIG. 43.

[0362] The self-luminous display device according to the fifth embodiment has a configuration and function in which the pixel 180B and pixel circuit 181B of the self-luminous display device 10 according to the third embodiment are replaced with a pixel 180D and pixel circuit 181D. Other configurations and functions are the same as those of the self-luminous display device 10 according to the third embodiment. Therefore, in describing the configuration and functions of the fifth embodiment, configurations and functions that are the same as those of the self-luminous display device 10 according to the third embodiment will be described as necessary.

[0363] <5-1.Configuration of pixel 180D> An overview of the pixel 180D and pixel circuit 181D will be described with reference to FIGS.

[0364] 38 and 39, pixel circuit 181D includes a configuration and function in which the second scan signal SC2(n) and scan voltage power supply SIRB(n) supplied to pixel circuit 181B are replaced with a common scan voltage power supply SIR3(n) that combines the second scan signal SC2(n) and scan voltage power supply SIRB(n). Also, as shown in Fig. 39, the configurations of the second transistor T2 and light-emitting element OLED of pixel circuit 181D are different from those of pixel circuit 181B.

[0365] Specifically, as shown in FIG. 38, the pixel circuit 181D is connected to a second scan signal line 334 to which a scan voltage power supply SIR3(n) is supplied. The second scan signal line 334 according to the fifth embodiment is a signal line that serves both as the second scan signal line 334 supplied to the pixel circuit 181B and the scan voltage power supply line SVIRB. In other words, the second scan signal line 334 according to the fifth embodiment is a common signal line that combines the second scan signal line 334 supplied to the pixel circuit 181B and the scan voltage power supply line SVIRB. The scan voltage power supply SIR3(n) is a signal obtained by inverting the polarity of the scan voltage power supply SIR2(n) supplied to the pixel circuit 181C. Similar to the scan voltage power supply SIR3(n), the polarities of signals other than the scan voltage power supply SIR3(n) supplied to the pixel circuit 181D are also signals obtained by inverting the polarity of signals other than the scan voltage power supply SIR2(n) supplied to the pixel circuit 181C. The second scan signal line 334 according to the fifth embodiment (a signal line that serves both as the second scan signal line 334 and the scan voltage power supply line SVIRB) may be called a third control signal line. The scan voltage power supply SIR3(n) may be called a third control signal.

[0366] 39, the pixel circuit 181D includes a second transistor T2 that is a p-channel field effect transistor. In the pixel circuit 181D, a second electrode 684 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS, and a first electrode 682 of the light-emitting element OLED is electrically connected to a first electrode 624 of the second transistor T2, a third node N3, a second electrode 656 of the fifth transistor T5, and a first electrode 692 of the capacitor CS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0367] The fourth transistor T4 has the function of connecting the second node N2 and the second scan signal line 334 to each other, supplying the scan voltage power supply SIR3(n) (initialization voltage VINI1 or VINI2) to the second node N2, and initializing the second node N2.

[0368] The fifth transistor T5 has the function of connecting the third node N3 and the second scan signal line 334 to each other, supplying the scan voltage power supply SIR3(n) (initialization voltage VINI2) to the third node N3, and initializing the third node N3.

[0369] The configuration and functions of the pixel circuit 181D other than those described in "5-1. Configuration of the pixel 180D" are the same as those of the pixel circuit 181B.

[0370] <5-2. Driving method of pixel circuit 181D> A method for driving the self-luminous display device 10 according to the fifth embodiment will be described with reference to Figures 40 to 46. Configurations that are the same as or similar to those in Figures 1 to 39 will be described as necessary. As in the first and second embodiments, the horizontal axis of the timing chart represents time.

[0371] For example, the method for driving the self-luminous display device 10 according to the fifth embodiment has a configuration and functions in which the operations related to the second scan signal SC2(n) and the scan voltage power supply SIRB(n) in the method for driving the self-luminous display device 10 according to the third embodiment are replaced with operations related to a scan voltage power supply SIR3(n) in which the second scan signal SC2(n) and the scan voltage power supply SIRB(n) are combined into one. Descriptions of the configurations and functions similar to those of the method for driving the self-luminous display device 10 according to the third embodiment will be omitted here.

[0372] Furthermore, for example, the method for driving the self-luminous display device 10 according to the fifth embodiment is a method in which the polarity of each signal in the method for driving the self-luminous display device 10 (pixel circuit 181C) according to the fourth embodiment is inverted, and is a method in which the polarity of the voltage (potential) supplied to each node in the method for driving the self-luminous display device 10 according to the fourth embodiment is inverted. Note that the scan voltage power supply SIR3(n) is a signal in which the polarity of the scan voltage power supply SIR2(n) according to the fourth embodiment is inverted. Descriptions of configurations and functions similar to those in the method for driving the self-luminous display device 10 according to the fourth embodiment will be omitted here.

[0373] The method for driving the self-luminous display device 10 according to the fifth embodiment includes the same period as the method for driving the self-luminous display device 10 shown in FIG.

[0374] Figures 40, 43, 45, and 46 are diagrams for explaining the periods PIW and PVH of the method for driving pixel 180D (pixel circuit 181D). Figures 40, 43, 45, and 46 show the light-emitting period PEM of the frame immediately before the current frame (K-1stFRAME), and the periods PIW and PVH of the current frame (KthFRAME). Figures 40, 43, 45, and 46 also show one horizontal period (horizontal period HRP) for one pixel 180D (pixel circuit 181D).

[0375] In one horizontal period in the driving method of the self-luminous display device 10 according to the fifth embodiment, a scan signal SC(n) and a scan voltage power supply SIR3(n) are input to the pixel 180D (pixel circuit 181D). For example, the scan signal SC(n) and the scan voltage power supply SIR3(n) are shifted, and the pixel 180D (pixel circuit 181D) corresponding to the shifted signal is selected. An image data signal SL(m), an initialization voltage VINI, and a reference voltage VREF are input to the selected pixel 180D (pixel circuit 181D). Similar operations are performed for all pixels 180D (pixel circuits 181D), and an image of the current frame corresponding to one frame is displayed in the display region 22 of the self-luminous display device 10 based on the image data signal SL(m) input to all pixels 180D (pixel circuits 181D).

[0376] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS. 40, 43, 45, and 46 are shown in Tables 9 and 10.

[0377] [Table 9]

[0378] [Table 10]

[0379] As described above, the polarity of the signal supplied to pixel circuit 181D is the inverse of the polarity of the signal supplied to pixel circuit 181C. For example, as shown in Table 9, Table 10, FIGS. 40, 43, 45, and 46, the voltage VSIGL included in the data signal VDATA is −3.5 V, and the pixel 180 to which the voltage VSIGL is supplied emits light. For example, one pixel emits red, one pixel emits green, one pixel emits blue, and three pixels emit white. Also, for example, the voltage VSIGH included in the data signal VDATA is 0.5 V, and the pixel 180 to which the voltage VSIGH is supplied does not emit light and is black. Also, for example, the voltage VL(LO) is −10 V, the voltage VNN is 5 V, the voltage VMN is −5 V, the initialization voltage VINI1 is 3.5 V, and the initialization voltage VINI2 is 0 V. For example, the voltage VH(HI), voltage VL(LO), voltage VNN, voltage VMN, initialization voltage VINI1, and initialization voltage VINI2 supplied to pixel circuit 181D correspond to voltages (potentials) with the polarity reversed from the voltage VL(LO), voltage VH(HI), voltage VN, voltage VM, initialization voltage VINI2, and initialization voltage VINI1 supplied to pixel circuit 181C.

[0380] <5-2-1. First Example of Method for Driving Pixel Circuit 181D> 40 to 42, a first example of a method for driving the pixel circuit 181D will be described. The first example of the method for driving the pixel circuit 181D involves the pixel 180D displaying a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then the pixel 180D displaying a black image based on the voltage VSIGH (0.5V) included in the data signal VDATA in the KthFRAME. In other words, the first example of the method for driving the self-luminous display device 10 according to the fifth embodiment involves displaying images of different colors in successive frames.

[0381] As described above, the configurations and functions of the signals during the light-emitting period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light-emitting period PEM are the same as those of the signals with the polarity of the voltage (potential) of each signal in the method for driving the self-luminous display device 10 according to the fourth embodiment, with the polarity reversed. Also, for example, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light-emitting period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light-emitting period PEM are voltages (potentials) with the polarity reversed of the voltages (potentials) of each node in the method for driving the self-luminous display device 10 according to the fourth embodiment. The conduction and non-conduction of each transistor during the light-emitting period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light-emitting period PEM are the same as those described in "4-2-1. First Example of the Method for Driving the Pixel Circuit 181C."

[0382] For example, the voltages Vnan, Vnbn, Vncn, Vndn, Vnen, and Vnfn are voltages (potentials) with the polarity of the voltages Vna, Vnb, Vnc, Vnd, Vne, and Vnf reversed. With reference to the voltages (potentials) in the driving method according to the fourth embodiment, the voltage Vnan is −7V, Vnbn is −2.5V, the voltage Vncn is 1.5V, the voltage Vndn is 0.5V, the voltage Vnen is 1V, the voltage Vnfn is −3.5V, the voltage Vngn is 2.5V, and the voltage Vnhn is 3.5V.

[0383] 40, in the light-emitting period PEM of the K-1st FRAME, pixel 180D emits light in accordance with the potential difference Vgs (voltage V(N2)-voltage V(N3)=voltage Vnan-voltage Vnbn) of the second transistor T2. The potential difference Vgs is -4.5V, and pixel 180B emits red light, and three pixels, including pixel 180 emitting red light, pixel 180 emitting blue light, and pixel 180 emitting green light, emit white light.

[0384] For example, in the initial period of one horizontal period HRP of the Kth FRAME following the light emission period PEM of the K-1st FRAME, the scan voltage power supply SIR3(n) changes from a state in which LO is supplied to a state in which initialization voltage VINI1 (3.5 V) is supplied. When the scan voltage power supply SIR3(n) changes to a state in which initialization voltage VINI1 is supplied, the scan signal SC(n) changes from a state in which LO is supplied to a state in which HI is supplied. Referring to the conductive and non-conductive states in the initial period of one horizontal period HRP of the Kth FRAME in the first example of the driving method according to the fourth embodiment and to FIG. 40, the voltage supplied to the first node N1 gradually increases from voltage Vnan toward voltage VSIGH (voltage Vndn), and the voltage supplied to the second node N2 gradually increases from voltage Vnan toward initialization voltage VINI1 (voltage Vnhn).

[0385] 40 and 41, during the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied, the scan signal SC(n) maintains a state in which HI is supplied, and the scan voltage power supply SIR3(n) maintains a state in which the initialization voltage VINI1 is supplied. Referring to the conductive and non-conductive states of the transistors during the period PIW in the first example of the driving method according to the fourth embodiment and to FIG. 40, the voltage supplied to the third node N3 gradually increases from the voltage Vnbn, and when the potential difference between the initialization voltage VINI1 (3.5 V) supplied to the gate electrode 652 and the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) becomes equal to the threshold voltage VTHT5 (1 V) of the fifth transistor T5, the fifth transistor T5 changes from the on state to the off state. That is, when the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) becomes the voltage Vngn (2.5V), the fifth transistor T5 changes from an ON state to an OFF state. The voltage supplied to the first node N1 gradually increases from the voltage Vnan toward the voltage VSIGH (voltage Vndn, 0.5V) and becomes the voltage Vndn (0.5V). The voltage supplied to the second node N2 gradually increases from the voltage Vnan toward the initialization voltage VINI1 (voltage Vnhn, 3.5V) and becomes the initialization voltage VINI1 (3.5V). When the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 becomes equal to the threshold voltage VTHT5 (1V), the fifth transistor T5 changes from an ON state to an OFF state. When the fifth transistor T5 is in the OFF state, the potential difference Vds becomes −10.5V (−8V−(2.5V)).

[0386] In this way, during the period PIW, a data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (3.5V), and the third node N3 is initialized to the voltage Vngn (2.5V) by the initialization voltage VINI1 (voltage Vnhn, 3.5V).

[0387] During the period PVH, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied, the scan signal SC(n) maintains a state in which HI is supplied, and the scan voltage power supply SIR3(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2 is supplied.

[0388] Immediately after the start of the period PVH, the potential difference Vgs is 1 V, the potential difference Vds is −10.5 V, and the potential difference Vgs is higher than the threshold voltage VTHP (−1 V, see Table 10) of the second transistor T2, so the second transistor T2 is in the off state. Therefore, the drain current Ion does not flow from the first electrode 624 to the second electrode 626 of the second transistor T2.

[0389] During the period PVH, the conductive and non-conductive states of each transistor during the period PVH of KthFRAME in the first example of the driving method according to the fourth embodiment, and referring to Figure 40, the fourth transistor T4 maintains its on state, so when the voltage supplied to the scan voltage power supply SIR3(n) changes from the initialization voltage VINI1 to the initialization voltage VINI2, the voltage supplied to the second node N2 gradually drops from the voltage Vnhn (3.5V) toward the initialization voltage VINI2 (0V) and becomes the initialization voltage VINI2 (0V) (for example, Figures 40 and 42). At this time, for example, as shown in FIGS. 40 and 42, the fifth transistor T5 is in an off state, but the Vgs of the second transistor T2 becomes −2.5 V (0 V (node ​​N2) − (2.5 V) (node ​​N3)), which is smaller (lower) than the threshold voltage VTHP (−1 V), and the drain current Ion of the second transistor T2 begins to flow, and the voltage supplied to the third node N3 gradually drops from voltage Vngn (2.5 V) toward voltage Vnen (1 V). As a result, the voltage supplied to the third node N3 becomes voltage Vnen (1 V), and the voltage supplied to the second node N2 is the initialization voltage VINI2 (0 V), so the potential difference Vgs becomes −1 V (0 V − (1 V)). Because the potential difference Vgs is the same as the threshold voltage VTHP (−1 V), the second transistor T2 is in an off state. Therefore, the drain current Ion does not flow from the second electrode 626 to the first electrode 624 of the second transistor T2.

[0390] As described above, during the period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Also, a charge equivalent to the threshold voltage VTHP is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0391] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, no data is selected using the selection signal, and the data signal VDATA is maintained at a voltage greater than or equal to VSIGL and less than or equal to VSIGH. Furthermore, the scan signal SC(n) changes from a state in which HI is supplied to a state in which LO is supplied. When the scan signal SC(n) changes to a state in which LO is supplied, the scan voltage power supply SIR3(n) changes from a state in which the initialization voltage VINI2 (0 V) is supplied to a state in which LO (-10 V) is supplied.

[0392] Therefore, referring to the conductive and non-conductive states of the transistors in the period PVH of KthFRAME in the first example of the driving method according to the fourth embodiment and FIG. 40, the first node N1 is conductive with the second node N2, and the potential difference Vgs is −0.5V. The potential difference Vgs is greater than the threshold voltage VTHP. Therefore, the second transistor T2 is in the off state, and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. As a result, for example, the pixel 180D (pixel circuit 181D) that emits red, the pixel 180D that emits blue, and the pixel 180D that emits green do not emit light, and the three pixels using the pixel 180D that emits red, the pixel 180D that emits blue, and the pixel 180D that emits green are black.

[0393] As described above, the driving method of the self-luminous display device 10 according to the fifth embodiment (the driving method of the pixel circuit 181D) includes performing the process (driving) performed in the write period and the process (driving) performed in the initialization period at the same timing, similar to the driving method of the self-luminous display device 10 according to the fourth embodiment. Furthermore, similar to the pixel circuit 181B, the pixel circuit 181D has a configuration that allows the number of signal lines to be reduced, and therefore the pixel size of a self-luminous display device including the pixel circuit 181D can be reduced. Therefore, the self-luminous display device 10 and the driving method of the self-luminous display device 10 according to the fifth embodiment have the same effects as the self-luminous display device 10 and the driving method of the self-luminous display device 10 according to the third embodiment.

[0394] <5-2-2. Second Example of Method for Driving Pixel Circuit 181D> A second example of a method for driving the pixel circuit 181D will be described with reference to Figures 43 and 44. The driving method shown in the second example of the pixel circuit 181D involves the pixel 180D displaying a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then the pixel 180D displaying a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in the KthFRAME as well. In other words, the second example of the method for driving the self-luminous display device 10 according to the fifth embodiment involves displaying images of the same color (white) in consecutive frames. Configurations that are the same as or similar to those in Figures 1 to 40 will be described as necessary.

[0395] The configurations of the image data signal SL(m), scan voltage power supply SIR(n), and scan signal SC(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "5-2-1." Also, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, and the operation of each transistor, are the same as those described in "5-2-1." Configurations similar to those described in "5-2-1" will be explained as necessary.

[0396] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180D (pixel circuit 181D) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL corresponding to white. The voltage supplied to the first node N1 gradually increases from voltage Vnan toward voltage VSIGL (voltage Vnfn, −3.5V). The voltage supplied to the second node N2 and the voltage supplied to the third node N3 are the same as those described in “5-2-1. First Example of the Method for Driving the Pixel Circuit 181D,” and therefore will not be described here.

[0397] During the period PIW, the voltage supplied to the first node N1 gradually rises from voltage Vnan toward voltage Vnfn, and reaches voltage Vnfn (-3.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "5-2-1. First example of the method for driving the pixel circuit 181D."

[0398] In this way, during the period PIW, a data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (voltage Vnhn, -3.5V), and the third node N3 is initialized to the voltage Vngn (-2.5V) by the initialization voltage VINI1 (voltage Vnhn, -3.5V).

[0399] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied. The first node N1 maintains a state in which the voltage Vnfn is supplied. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "5-2-1. First Example of the Method for Driving the Pixel Circuit 181D."

[0400] As described above, in the same manner as described in "5-2-1. First Example of the Method for Driving the Pixel Circuit 181D," during the period PVH, the threshold voltage VTHP of the second transistor T2 is corrected so that the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTHP. Also, a charge equivalent to the threshold voltage VTHP is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0401] During the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, similar to what was explained in "4-2-1", for example, as shown in FIG. 44, the first node N1 becomes conductive with the second node N2, the voltages of the first node N1 and the second node N2 gradually drop, the second transistor T2 becomes conductive, a drain current Ion flows from the reference voltage line PVSS to the drive power supply line PVDD, and the voltage of the third node N3 drops to follow the drop in the voltage of the first node N1 and the voltage of the second node N2.

[0402] As a result, the potential difference Vgs (voltage Vnan (-7V) - voltage Vnbn (-2.5V)) becomes -4.5V, and the potential difference Vgs becomes smaller than the threshold voltage VTHP (-1V). Therefore, the second transistor T2 is in the on state, and a drain current Ion flows from the reference voltage line PVSS to the drive power supply line PVDD, causing the light-emitting element OLED to emit light. For example, pixel 180D (pixel circuit 181D) emits red, and three pixels, including pixel 180D that emits blue and pixel 180D that emits green, emit white.

[0403] <5-2-3. Third Example of Method for Driving Pixel Circuit 181D> A third example of a method for driving the pixel circuit 181D will be described with reference to FIG. 45. The driving method shown in the third example of the method for driving the pixel circuit 181D involves the pixel 180D displaying a black image based on the voltage VSIGL included in the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME) based on the voltage VSIGL, and then the pixel 180D also displaying a black image based on the voltage VSIGH included in the data signal VDATA in the Kth FRAME. In other words, it involves displaying images of the same color (black) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 44 will be described as necessary.

[0404] The configuration of the image data signal SL(m), scan voltage power supply SIR3(n), and scan signal SC(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "5-2-1. First example of the driving method for pixel circuit 181D."

[0405] Referring to the conductive and non-conductive states of each transistor during the light-emitting period PEM of the K-1st FRAME in the configuration described in "5-2-1. First Example of the Driving Method of the Pixel Circuit 181D" and to FIG. 45, during the light-emitting period PEM of the K-1st FRAME, the pixel 180D emits light according to the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage VINI2 - voltage Vnen) of the second transistor T2. The potential difference Vgs is -0.5V, which is greater than the threshold voltage VTHP (-1V) of the second transistor T2. Therefore, the second transistor T2 is in the off state, and no current flows from the reference voltage line PVSS to the driving power supply line PVDD, so the light-emitting element OLED does not emit light at all. As a result, for example, the pixel 180D (pixel circuit 181D) turns black.

[0406] During the initial period of one horizontal period HRP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, pixel 180D (pixel circuit 181D) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH (0.5 V) corresponding to the non-light-emitting black color. Referring to the conductive and non-conductive states of the transistors during the initial period of one horizontal period HRP of the Kth FRAME in the configuration described in "5-2-1. First Example of the Driving Method of the Pixel Circuit 181D" and FIG. 45, the voltage supplied to first node N1 remains at voltage Vndn (0.5 V), and the first node N1 maintains the state in which 0.5 V is supplied. The voltage supplied to second node N2 gradually rises from voltage Vndn (0.5 V) toward initialization voltage VINI1 (voltage Vnhn, 3.5 V).

[0407] During the period PIW, referring to the conductive and non-conductive states of each transistor during the initial period of one horizontal period HRP of KthFRAME in the configuration described in "5-2-1. First Example of the Method of Driving Pixel Circuit 181D," and also referring to FIG. 45, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied, the first node N1 maintains a state in which 0.5 V is supplied, and the voltage supplied to the second node N2 gradually rises to voltage Vnhn (3.5 V). Also, the voltage supplied to the third node N3 becomes voltage Vngn (2.5 V).

[0408] As described above, during the period PIW, the data signal VDATA including the voltage VSIGH (0.5V) is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (3.5V).

[0409] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied. The voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "5-2-1. First example of the method for driving the pixel circuit 181D," and therefore will not be described here.

[0410] As described above, in the same manner as described in "5-2-1. First Example of the Method for Driving the Pixel Circuit 181D," during the period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Also, a charge equivalent to the threshold voltage VTHP is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0411] During the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those explained in "3-2-3. Third Example of the Method of Driving the Pixel Circuit 181B", and therefore explanation thereof will be omitted here. As explained in "3-2-3. Third Example of the Method of Driving the Pixel Circuit 181B", during the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the pixel 180D that emits red, the pixel 180D that emits blue, and the pixel 180D that emits green do not emit light, and therefore the three pixels using the pixel 180D that emits red, the pixel 180D that emits blue, and the pixel 180D that emits green appear black.

[0412] As described above, in the third example of the method for driving the self-luminous display device 10 according to the fifth embodiment (method for driving the pixel circuit 181D), similar to the third example of the method for driving the self-luminous display device 10 according to the second embodiment, fluctuations in the voltage of each node when displaying images of the same color (black) in consecutive frames are slight, and therefore power consumption due to fluctuations in the voltage of each node can be reduced. Therefore, the self-luminous display device 10 is a display device that can reduce power consumption.

[0413] <5-2-4. Fourth Example of Method for Driving Pixel Circuit 181D> A fourth example of a method for driving pixel circuit 181D will be described with reference to FIG. 46. The driving method shown in the fourth example of the method for driving pixel circuit 181D involves pixel 180D (pixel circuit 181D) displaying a black image based on voltage VSIGH included in data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then pixel 180 (pixel circuit 181) displaying a white image based on voltage VSIGL included in data signal VDATA in KthFRAME. In other words, it involves displaying images of different colors in successive frames. Configurations that are the same as or similar to those in FIGS. 1 to 45 will be described as necessary.

[0414] The configuration of the image data signal SL(m), scan voltage power supply SIR3(n), and scan signal SC(n) during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "5-2-1. First example of the driving method for pixel circuit 181D."

[0415] The voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1st FRAME are the same as those described in "5-2-3. Third example of the method for driving the pixel circuit 181D." That is, the pixel 180D (pixel circuit 181D) does not emit light and is black.

[0416] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180D (pixel circuit 181D) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGL corresponding to white. The voltage supplied to the first node N1 gradually drops from the voltage Vndn (0.5 V) toward the voltage VSIGL (voltage Vnfn, −3.5 V), and the voltage supplied to the second node N2 gradually rises from the voltage Vnen (1 V) toward the voltage Vngn (2.5 V).

[0417] During the period PIW, the first node N1 is supplied with a voltage Vnfn (-3.5V), and the second node N2 is supplied with a voltage Vnhn (3.5V). The third node N3 is supplied with a voltage Vngn (2.5V). At this time, the potential difference Vgs becomes 1V (3.5V - 2.5V), and the potential difference Vds becomes -10.5V (-8V - 2.5V).

[0418] As described above, during the period PIW, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (3.5 V).

[0419] In the period PVH following the period PIW and the light-emitting period PEM following the period PVH, the conductive and non-conductive states of each transistor are the same as the configuration described in "5-2-2. Second example of the method for driving the pixel circuit 181D", and the voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as the states described in "5-2-2. Second example of the method for driving the pixel circuit 181D".

[0420] Similar to the state described in "5-2-2. Second Example of the Method for Driving the Pixel Circuit 181D," during the period PVH in the third example of the method for driving the pixel circuit 181D, the threshold voltage VTHP of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Also, a charge equivalent to the threshold voltage VTHP is held at the second node N2 (the gate electrode 622 of the second transistor T2).

[0421] Also, similar to the state described in "5-2-2. Second example of the method for driving pixel circuit 181D," during the light emission period PEM of KthFRAME in the third example of the method for driving pixel circuit 181D, similar to the content described in "3-3-2," pixel 180D emits red light, and three pixels, using pixel 180D that emits blue light and pixel 180D that emits green light, emit white light.

[0422] 6. Sixth Embodiment An overview of the self-luminous display device 10 according to the sixth embodiment will be described with reference to Figs. 1, 4, and 47 to 21. Fig. 47 is a schematic diagram showing input signals to a pixel 180E (pixel circuit 181E) according to the sixth embodiment of the present invention. Fig. 48 is a circuit diagram showing the configuration of the pixel circuit 181E. Figs. 49 to 52 are timing charts of the self-luminous display device 10 according to the sixth embodiment of the present invention.

[0423] The self-luminous display device according to the sixth embodiment includes a pixel 180E and a pixel circuit 181E. The configurations of the pixel 180E and the pixel circuit 181E are different from the configurations of the pixel 180 and the pixel circuit 181 of the self-luminous display device 10 according to the first embodiment. Specifically, the circuit configuration of the pixel circuit 181E is different from the circuit configuration of the pixel circuit 181. Furthermore, the pixel circuit 181E has a configuration and function in which the scan voltage power supply SIR(n) supplied to the pixel circuit 181 is replaced with a scan voltage power supply SIR4(n). Other configurations and functions are similar to those of the self-luminous display device 10 according to the first embodiment. In describing the configuration and functions of the sixth embodiment, configurations and functions similar to those of the self-luminous display device 10 according to the first embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 46 will be described as necessary.

[0424] <6-1. Configuration of pixel 180E> The pixel 180E and pixel circuit 181E will be outlined with reference to FIGS.

[0425] 47, the pixel circuit 181E is connected to a scan voltage power supply line SVIR to which a scan voltage power supply SIR4(n) is supplied. For example, the scan voltage power supply line SVIR, the drive voltage VDDEL, and the reference voltage VSSEL are each electrically connected to a different connection wiring 342. Also, for example, the scan voltage power supply line SVIR, the drive voltage VDDEL, and the reference voltage VSSEL may each be a different connection wiring 342.

[0426] 48, the pixel circuit 181E includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (a source electrode and a drain electrode) consisting of a first electrode and a second electrode. Each of the capacitor CS and the light-emitting element OLED includes a pair of electrodes consisting of a first electrode and a second electrode.

[0427] For example, the first transistor T1 is a selection transistor. The first transistor T1 has a function of supplying an image data signal SL(m) to the first node N1.

[0428] For example, the second transistor T2 is a drive transistor. The threshold voltage VTH of the second transistor T2 is corrected based on the initialization voltages VINI1 and VINI2. Furthermore, the second transistor T2 controls connection and disconnection between the third node N3 (the first electrode 724, the second electrode 736, the second electrode 746, and the second electrode 784) and the fourth node N4 (the second electrode 726, the second electrode 756, the second electrode 766, and the first electrode 774) based on the corrected threshold voltage VTH and the input image data signal SL(m).

[0429] The third transistor T3 has a function of connecting the first node N1 and the third node N3.

[0430] The fourth transistor T4 has the function of connecting the third node N3 (first electrode 724, second electrode 736, second electrode 746, second electrode 784) and the scan voltage power supply line SVIR (first electrode 744, first electrode 754) to each other, supplying the scan voltage power supply SIR4(n) to the third node N3, and initializing the third node N3.

[0431] The fifth transistor T5 has the function of connecting the fourth node N4 (the second electrode 726, the second electrode 756, the second electrode 766, and the first electrode 774) to the scan voltage power supply line SVIR, supplying the scan voltage power supply SIR4(n) to the fourth node N4 (the second electrode 726, the second electrode 756, the second electrode 766, and the first electrode 774), and initializing the fourth node N4 (the second electrode 726, the second electrode 756, the second electrode 766, and the first electrode 774).

[0432] The sixth transistor T6 has the function of connecting the second node N2 (gate electrode 722, first electrode 792, first electrode 774) and the fourth node N4 (second electrode 726, second electrode 756, second electrode 766, first electrode 774).

[0433] The seventh transistor T7 has a function of connecting the drive power supply line PVDD (second electrode 776) and the fourth node N4 (second electrode 726, second electrode 756, second electrode 766, first electrode 774).

[0434] For example, the capacitive element CS has a function of holding a charge equivalent to the voltage supplied to the second node N2, and a function of holding a charge equivalent to the data voltage contained in the image data signal SL(m) supplied to the first node N1.

[0435] The light-emitting element OLED has diode characteristics and emits light based on the current flowing through the light-emitting element OLED (that is, the drain current Ion of the second transistor T2).

[0436] The first transistor T1 includes a gate electrode 712, a first electrode 714, and a second electrode 716. The gate electrode 712 is electrically connected to the first scan signal line 330. The first electrode 714 is electrically connected to the image data signal line 321. The second electrode 716 is electrically connected to the first node N1, the first electrode 734 of the third transistor T3, and the second electrode 794 of the capacitive element CS. The switching of the first transistor T1 is controlled using a first scan signal SC1(n). In other words, the first transistor T1 is controlled between a conductive state and a non-conductive state by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the first transistor T1 is non-conductive. When the signal supplied to the first scan signal SC1(n) is HI, the first transistor T1 is conductive.

[0437] The first scan signal line 330 is electrically connected to the gate electrode 712 of the first transistor T1, as well as to the gate electrode 732 of the third transistor T3, the gate electrode 742 of the fourth transistor T4, the gate electrode 762 of the sixth transistor T6, and the gate electrode 772 of the seventh transistor T7.

[0438] The second transistor T2 includes a gate electrode 722, a first electrode 724, and a second electrode 726. The gate electrode 722 is electrically connected to the second node N2, a first electrode 764 of the sixth transistor T6, and a first electrode 792 of the capacitor CS. The first electrode 724 is electrically connected to the third node N3, a second electrode 736 of the third transistor T3, a second electrode 746 of the fourth transistor T4, and a second electrode 784 of the light-emitting element OLED. The second electrode 726 is electrically connected to a second electrode 756 of the fifth transistor T5, a second electrode 766 of the sixth transistor T6, and a first electrode 774 of the seventh transistor T7. The threshold voltage of the second transistor T2 is a threshold voltage VTH. The second transistor T2 is controlled to be conductive or non-conductive in accordance with the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3, the potential difference Vds between the second electrode 726 and the first electrode 724, and the threshold voltage VTH.

[0439] The third transistor T3 includes a gate electrode 732, a first electrode 734, and a second electrode 736. The switching of the third transistor T3 is controlled using the first scan signal SC1(n). In other words, the conductive state and non-conductive state of the third transistor T3 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the third transistor T3 is in the conductive state. When the signal supplied to the first scan signal SC1(n) is HI, the third transistor T3 is in the non-conductive state.

[0440] The fourth transistor T4 includes a gate electrode 742, a first electrode 744, and a second electrode 746. The first electrode 744 is electrically connected to the scan voltage power supply line SVIR. The switching of the fourth transistor T4 is controlled using a first scan signal SC1(n). In other words, the conductive state and non-conductive state of the fourth transistor T4 are controlled by the first scan signal SC1(n). When the first scan signal SC1(n) is LO, the fourth transistor T4 is non-conductive. When the first scan signal SC1(n) is HI, the fourth transistor T4 is conductive.

[0441] The fifth transistor T5 includes a gate electrode 752, a first electrode 754, and a second electrode 756. The gate electrode 752 is electrically connected to the second scan signal line 334. The first electrode 754 is electrically connected to the scan voltage power supply line SVIR. The switching of the fifth transistor T5 is controlled using the second scan signal SC2(n). In other words, the conductive state and non-conductive state of the fifth transistor T5 are controlled by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the fifth transistor T5 is non-conductive, and when the signal supplied to the second scan signal SC2(n) is HI, the fifth transistor T5 is conductive.

[0442] The sixth transistor T6 includes a gate electrode 762, a first electrode 764, and a second electrode 766. The gate electrode 762 is electrically connected to the first scan signal line 330. The sixth transistor T6 has its switching controlled using a first scan signal SC1(n). In other words, the sixth transistor T6 has its conductive state and non-conductive state controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the sixth transistor T6 is in a non-conductive state, and when the signal supplied to the first scan signal SC(n) is HI, the sixth transistor T6 is in a conductive state.

[0443] The seventh transistor T7 includes a gate electrode 772, a first electrode 774, and a second electrode 776. The gate electrode 772 is electrically connected to the first scan signal line 330. The second electrode 776 is electrically connected to the driving power supply line PVDD. The switching of the seventh transistor T7 is controlled using a first scan signal SC1(n). In other words, the conductive state and non-conductive state of the seventh transistor T7 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the seventh transistor T7 is in a conductive state, and when the signal supplied to the first scan signal SC(n) is HI, the seventh transistor T7 is in a non-conductive state.

[0444] The first electrode 782 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 782 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 784 of the light-emitting element OLED is, for example, an anode electrode.

[0445] Each transistor included in pixel circuit 181E may have the same configuration as each transistor included in pixel circuit 181. For example, the channel region of each transistor may have low-temperature polysilicon (LTPS), and an n-channel transistor may be formed using a metal oxide having semiconductor properties.

[0446] In the sixth embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are n-channel field effect transistors, and the third transistor T3 and the seventh transistor T7 are p-channel field effect transistors.

[0447] <6-2. Driving Method of Pixel Circuit 181E> A method for driving the self-luminous display device 10 according to the sixth embodiment will be described with reference to Figures 48 to 52. Configurations that are the same as or similar to those in Figures 1 to 48 will be described as necessary. As with the first embodiment, the horizontal axis of the timing chart represents time.

[0448] The method for driving the self-luminous display device 10 according to the sixth embodiment includes the same period as the method for driving the self-luminous display device 10 shown in FIG.

[0449] Figures 49 to 52 are diagrams for explaining the periods PIW and PVH of the method for driving the pixel 180E (pixel circuit 181E). Figures 49 to 52 show the light-emitting period PEM of the frame immediately before the current frame (K-1stFRAME), and the periods PIW and PVH of the current frame (KthFRAME). Figures 49 to 52 also show one horizontal period (horizontal period HRP) for one pixel 180E (pixel circuit 181E).

[0450] During one horizontal period in the driving method for the self-luminous display device 10 according to the sixth embodiment, the pixel 180E (pixel circuit 181E) receives a first scan signal SC1(n), a second scan signal SC2(n), an image data signal SL(m) including a data signal VDATA, and a scan voltage power supply SIR4(n). For example, the first scan signal SC1(n), the second scan signal SC2(n), and the scan voltage power supply SIR4(n) are shifted, and the pixel 180E (pixel circuit 181E) corresponding to the shifted signal is selected. The image data signal SL(m), the drive voltage VDDEL, and the reference voltage VSSEL are input to the selected pixel 180E (pixel circuit 181E). Similar operations are performed for all pixels 180E (pixel circuits 181E), and an image of a frame corresponding to one frame is displayed in the display region 22 of the self-luminous display device 10 based on the image data signal SL(m) input to all pixels 180E (pixel circuits 181E).

[0451] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0452] [Table 11]

[0453] [Table 12]

[0454] <6-2-1. First Example of Method for Driving Pixel Circuit 181E> A first example of a method for driving the pixel circuit 181E will be described with reference to Fig. 49. The first example of the method for driving the pixel circuit 181E includes displaying images of different colors in successive frames, similar to the first example of the method for driving the self-luminous display device 10 according to the first embodiment.

[0455] The timing at which the image data signal SL(m), the first scan signal SC1(n), and the second scan signal SC2(n) are supplied to the pixel circuit 181E during the light emission period PEM of the K-1stFRAME, one horizontal period HRP of the KthFRAME, and the light emission period PEM is the same as in the first example of the driving method for the self-luminous display device 10 according to the first embodiment.

[0456] As shown in Tables 11 and 12, the image data signal SL(m) including the data signal VDATA supplied to the pixel circuit 181E in accordance with each horizontal period is between −4.5V and −0.5V. For example, when the voltage VSIGL is −4.5V, the pixel 180 supplied with the voltage VSIGL emits light and produces each color. For example, when the voltage VSIGH is −0.5V, the pixel 180 supplied with the voltage VSIGH does not emit light and produces black. For example, the initialization voltage VINI2 is −1V, the initialization voltage VINI1 is 0.5V, the voltage VH is 10V, the voltage VL is −6.5V, the voltage VM is 5V, and the voltage VN is −5V.

[0457] The scan voltage power supply SIR4(n) is supplied with the initialization voltage VINI1 during the light emission period PEM of the K-1st FRAME, the initial period of one horizontal period HRP of the K FRAME, and the period PIW, and is supplied with the initialization voltage VINI2 during the period PVH of the K FRAME. The scan voltage power supply SIR4(n) is supplied with the initialization voltage VINI1 during the initial period of the light emission period PEM. When the first scan signal SC1(n) changes from a state in which HI is supplied to a state in which LO is supplied, the scan voltage power supply SIR4(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2 is supplied.

[0458] During the light emission period PEM of the K-1st FRAME, the first scan signal SC1(n) and the second scan signal SC2(n) are supplied with LO. The first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are non-conductive, while the third transistor T3 and the seventh transistor T7 are conductive. For example, the voltage Vna supplied to the second node N2 is 7 V, the voltage Vnb supplied to the first node N1 and the third node N3 is 2.5 V, the potential difference Vgs is 4.5 V, and the second transistor T2 is conductive. Therefore, the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds corresponding to the voltage VSIGH input during one horizontal period HRP of the K-1st FRAME. The seventh transistor T7 is conductive, and the current Ion flows from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, pixel 180 (pixel circuit 181) emits red light, and three pixels, one for emitting red light, one for emitting blue light, and one for emitting green light, emit white light.

[0459] During the initial period of one horizontal period HRP of the Kth FRAME following the light-emitting period PEM of the K-1st FRAME, the pixel 180E (pixel circuit 181E) receives the image data signal SL(m), which includes the data signal VDATA, including the voltage VSIGH (-0.5 V) corresponding to the non-light-emitting black color. The second scan signal SC2(n) maintains its LO state. When the first scan signal SC1(n) changes from LO to HI, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 change from a non-conductive state to a conductive state, the third transistor T3 and the seventh transistor T7 change from a conductive state to a non-conductive state, and the fifth transistor T5 maintains its non-conductive state. As a result, the voltage supplied to the first node N1 and the voltage supplied to the third node N3 drop from voltage Vnb.

[0460] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied, the first scan signal SC1(n) maintains a state in which HI is supplied, and the scan voltage power supply SIR4(n) maintains a state in which the initialization voltage VINI1 is supplied. Furthermore, the second scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. Therefore, the fifth transistor T5 changes from a non-conductive state to a conductive state, the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 maintain a conductive state, and the third transistor T3 and the seventh transistor T7 maintain a non-conductive state.

[0461] Also, during the final period of the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, the first scan signal SC1(n) maintains a state in which HI is supplied, and the scan voltage power supply SIR4(n) maintains a state in which the initialization voltage VINI1 is supplied. The second scan signal SC1(n) changes from a state in which HI is supplied to a state in which LO is supplied. Therefore, the fifth transistor T5 changes from a conductive state to a non-conductive state, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 maintain a conductive state, and the third transistor T3 and the seventh transistor T7 maintain a non-conductive state. The fifth transistor T5 changes to a non-conductive state at the final timing.

[0462] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vnb toward voltage VSIGL (voltage Vnd, −0.5V) and becomes voltage Vnd (−0.5V). The voltage supplied to the second node N2 gradually drops from voltage Vna toward the initialization voltage VINI1 (voltage Vni, 0.5V) and becomes voltage Vni (0.5V). The voltage supplied to the third node N3 gradually drops from voltage Vnb toward the initialization voltage VINI1 (voltage Vni, 0.5V) and becomes voltage Vni (0.5V). Therefore, the potential difference Vgs and the potential difference Vds become 0V (0.5−(0.5V)). As a result, because the potential difference Vgs is smaller than the threshold voltage VTH (1V), the second transistor T2 is in a non-conductive state. Therefore, the drain current Ion does not flow from the second electrode 726 to the first electrode 724 of the second transistor T2.

[0463] In this manner, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1.

[0464] During the period PVH, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, the first scan signal SC1(n) maintains a state in which HI is supplied, and the second scan signal SC1(n) changes to LO. The scan voltage power supply SIR4(n) changes from a state in which the initialization voltage VINI1 is supplied to a state in which the initialization voltage VINI2 is supplied. Therefore, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 maintain a conductive state, and the third transistor T3, the fifth transistor T5, and the seventh transistor T7 maintain a non-conductive state.

[0465] Furthermore, at the end of the period PVH, when the first scan signal SC1(n) changes from a HI state to a LO state, the scan voltage power supply SIR4(n) changes from a supply of the initialization voltage VINI2 to a supply of the initialization voltage VINI1. As a result, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 change from a conductive state to a non-conductive state, the third transistor T3 and the seventh transistor T7 change from a non-conductive state to a conductive state, and the fifth transistor T5 remains non-conductive.

[0466] Therefore, during the period PVH, the voltage supplied to the first node N1 remains at voltage Vnd (-0.5V). Because the fourth transistor T4 remains conductive, the voltage supplied to the third node N3 gradually decreases from voltage Vni (0.5V) toward the initialization voltage VINI2 (-1V), reaching the initialization voltage VINI2 (-1V). At this time, although the fifth transistor T5 is non-conductive, the Vgs of the second transistor T2 approaches 1.5V (0.5V (node ​​N2) - (-1V) (node ​​N3)), which is greater than the threshold voltage VTH (1V). As a result, the drain current Ion of the second transistor T2 begins to flow, and the voltage supplied to the second node N2 gradually decreases from voltage Vni (0.5V). Because the initialization voltage VINI2 (voltage Vne, −1 V) continues to be supplied to the third node N3, when the voltage supplied to the second node N2 becomes 0 V, the potential difference Vgs becomes the threshold voltage VTH. As a result, the second transistor T2 becomes non-conductive. Therefore, the drain current Ion does not flow from the second electrode 726 to the first electrode 724 of the second transistor T2.

[0467] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 722 of the second transistor T2).

[0468] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, no data is selected using the selection signal, and the data signal VDATA is maintained at a voltage greater than or equal to VSIGL and less than or equal to VSIGH. Also, the first scan signal SC1(n) changes from a HI state to a LO state, the second scan signal SC2(n) maintains its LO state, and the scan voltage power supply SIR4(n) maintains its initialization voltage VINI1 (0.5 V) state.

[0469] As a result, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 change from a conductive state to a non-conductive state, and the third transistor T3 and the seventh transistor T7 change from a non-conductive state to a conductive state. The fifth transistor T5 remains non-conductive. As the third transistor T3 changes to a conductive state, the first node N1 becomes conductive with the third node N3, and the voltage supplied to the first node N1 becomes voltage Vne (-1 V). Since the first node N1 becomes conductive with the third node N3, the voltage supplied to the first node N1 gradually drops toward -1 V. Therefore, due to capacitive coupling between the second node N2 (the gate electrode 722 of the second transistor T2 and the first electrode 724 of the capacitive element CS) and the third node N3, the voltage supplied to the second node N2 gradually drops from voltage Vni (0 V). For example, the voltage supplied to the second node N2 becomes voltage Vnd (-0.5 V).

[0470] Therefore, during the light-emitting period PEM of KthFRAME, the potential difference Vgs is −0.5V. The potential difference Vgs is smaller than the threshold voltage VTH. Therefore, the second transistor T2 is non-conductive, and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. As a result, for example, the pixel 180E (pixel circuit 181E) that emits red, the pixel 180E that emits blue, and the pixel 180E that emits green do not emit light, and the three pixels using the pixel 180E that emits red, the pixel 180E that emits blue, and the pixel 180E that emits green are black.

[0471] <6-2-2. Second Example of Method for Driving Pixel Circuit 181E> A second example of a method for driving the pixel circuit 181E will be described with reference to Fig. 50. The driving method shown in the second example of the pixel circuit 181E includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 49 will be described as necessary.

[0472] The timing at which the image data signal SL(m), scan voltage power supply SIR4(n), first scan signal SC1(n), and second scan signal SC2(n) are supplied to the pixel circuit 181E during the light emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the light emission period PEM is the same as the configuration described in "6-2-1. First Example of Driving Method of Pixel Circuit 181E." The voltage (potential) of the first node N1 during the light emission period PEM of the K-1st FRAME, the voltage (potential) of the second node N2 and the third node N3 during the light emission period PEM of the K-1st FRAME and one horizontal period HRP of the Kth FRAME, and the operation of each transistor are the same as the configuration described in "6-2-1. First Example of Driving Method of Pixel Circuit 181E." Configurations similar to those described in "6-2-1. First Example of Driving Method of Pixel Circuit 181E" will be explained as necessary.

[0473] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180E (pixel circuit 181E) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGL (-4.5V) corresponding to white. The voltage supplied to the first node N1 gradually drops from the voltage Vnb toward the voltage VSIGL (voltage Vnj, -4.5V).

[0474] During the period PIW, the voltage supplied to the first node N1 gradually drops from voltage Vnb to voltage Vnj, reaching voltage Vnj (-4.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "6-2-1. First example of the method for driving the pixel circuit 181E."

[0475] In this way, similar to what was explained in "6-2-1. First example of driving method for pixel circuit 181E," during the period PIW, a data signal VDATA including a voltage VSIGL is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1.

[0476] During the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied. The first node N1 maintains a state in which the voltage Vnj is supplied. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E."

[0477] As described above, in the same manner as described in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E," during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 722 of the second transistor T2).

[0478] During the light emission period PEM of the Kth FRAME following one horizontal period HRP of the Kth FRAME, the first node N1 is electrically connected to the third node N3, as described in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E." Although the fourth transistor T4 and the sixth transistor T6 are electrically non-conductive, the voltage at the third node N3 gradually increases. Due to capacitive coupling between the second node N2 (the gate electrode 722 of the second transistor T2 and the first electrode 724 of the capacitive element CS) and the third node N3, the voltage supplied to the second node N2 gradually increases from voltage Vni (0 V). When the voltage at the second node N2 gradually increases from voltage Vni (0 V) and the potential difference Vgs exceeds the threshold voltage VTH, the second transistor T2 changes from electrically non-conductive to electrically conductive. Because the seventh transistor T7 is conductive, when the second transistor T2 is conductive, a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, and the voltage supplied to the first node N1 rises to follow the rise in the voltage supplied to the first node N1 and the voltage supplied to the second node N2. Here, the potential difference between the first electrode 792 and the second electrode 794 during the period PVH is 4.5 V (the potential difference between the voltage supplied to the second node N2 and the voltage supplied to the third node N3), and the capacitive element CS holds a charge equivalent to 4.5 V. For example, since the capacitive element CS holds a charge equivalent to 4.5 V, when the voltage supplied to the first node N1 and the voltage supplied to the third node N3 rise to voltage Vnb (2.5 V), as shown in FIG. 50, the voltage supplied to the second node N2 rises to voltage Vna (7 V).

[0479] The potential difference Vgs (4.5V) is greater than the threshold voltage VTH and the threshold voltage VTHEL of the light-emitting element OLED. Therefore, the second transistor T2 is in a conductive state, and a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180E (pixel circuit 181E) emits red light, and the three pixels, including the pixel 180E that emits blue light and the pixel 180E that emits green light, emit white light.

[0480] <6-2-3. Third Example of Method for Driving Pixel Circuit 181E> A third example of a method for driving the pixel circuit 181E will be described with reference to Fig. 51. The driving method shown in the third example of the method for driving the pixel circuit 181E includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 50 will be described as necessary.

[0481] The timing at which the image data signal SL(m), scan voltage power supply SIR4(n), first scan signal SC1(n), and second scan signal SC2(n) are supplied to pixel circuit 181E during the light emission period PEM of K-1stFRAME, one horizontal period HRP of KthFRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "6-2-1. First Example of Method for Driving Pixel Circuit 181E." Configurations similar to those described in "6-2-1. First Example of Method for Driving Pixel Circuit 181E" and "6-2-2. Second Example of Method for Driving Pixel Circuit 181E" will be explained as necessary.

[0482] During the light-emitting period PEM of the K-1st FRAME, for example, the potential difference Vgs is 0.5 V, which is smaller than the threshold voltage VTH (1 V, see Table 12) of the second transistor T2. The second transistor T2 is in a non-conductive state, and no current flows from the driving power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light at all. As a result, for example, similar to the pixel 180E (pixel circuit 181E) described during the light-emitting period PEM of the Kth FRAME in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E," three pixels, each using a pixel 180E that emits red, a pixel 180E that emits blue, and a pixel 180E that emits green, are black.

[0483] During the initial period of one horizontal period HRP of the Kth FRAME following the light-emitting period PEM of the (K-1st) FRAME, the pixel 180E (pixel circuit 181E) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGLH (-0.5V) corresponding to the non-light-emitting black color. The voltage supplied to the first node N1 gradually increases from voltage Vne (-1V) to voltage Vnd (-0.5V), the voltage supplied to the second node N2 gradually increases from voltage Vnd (-0.5V) to voltage Vni (0.5V), and the voltage supplied to the third node N3 gradually increases from voltage Vne (-1V) to voltage Vni (0.5V).

[0484] During the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGH is supplied. The first node N1 is supplied with −0.5 V, and the second node N2 and the third node N3 are supplied with the voltage Vni (0.5 V).

[0485] As described above, during the period PIW, the data signal VDATA including the voltage VSIGL (-0.5V) is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1.

[0486] During the period PVH following the period PIW, as described in "6-2-1. First Example of the Method for Driving the Pixel Circuit 181E," the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Also, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 722 of the second transistor T2).

[0487] During the light emission period PEM of the KthFRAME following one horizontal period HRP of the KthFRAME, the pixel 180E that emits red light does not emit light, and the three pixels that are the pixel 180E that emits red light, the pixel 180E that emits blue light, and the pixel 180E that emits green light are black, as explained in "6-2-1. First example of the driving method of the pixel circuit 181E."

[0488] <6-2-4. Fourth Example of Method for Driving Pixel Circuit 181E> A fourth example of a method for driving the pixel circuit 181E will be described with reference to Fig. 52. The driving method shown as the fourth example of the method for driving the pixel circuit 181E includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the self-luminous display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 51 will be described as necessary.

[0489] The timing at which the image data signal SL(m), scan voltage power supply SIR4(n), first scan signal SC1(n), and second scan signal SC2(n) are supplied to pixel circuit 181E during the light emission period PEM of K-1stFRAME, one horizontal period HRP of KthFRAME, and the light emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "6-2-1. First Example of Method for Driving Pixel Circuit 181E." Configurations similar to those described in "6-2-1. First Example of Method for Driving Pixel Circuit 181E" and "6-2-2. Second Example of Method for Driving Pixel Circuit 181E" will be explained as necessary.

[0490] The voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of the K-1st FRAME, as well as the operation of each transistor, are the same as the configuration described in "6-2-3. Third example of the driving method for the pixel circuit 181E."

[0491] During the initial period of one horizontal period HRP of the KthFRAME, the pixel 180E (pixel circuit 181E) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL (-4.5V) corresponding to white. The voltage supplied to the first node N1 gradually drops from voltage Vne (-1V) toward voltage VSIGL (voltage Vnj, -4.5V). The voltage supplied to the second node N2 gradually rises from voltage Vnd (-0.5V) toward voltage Vni (0.5V). The voltage supplied to the third node N3 gradually rises from voltage Vne (-1V) toward voltage Vni (0.5V).

[0492] As a result, during the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied, the first node N1 receives the voltage Vnj (-4.5V), and the second node N2 and the third node N3 receive the voltage Vni (0.5V).

[0493] As described above, during the period PIW, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1.

[0494] The voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the KthFRAME period PVH and the light emission period PEM, as well as the operation of each transistor, are the same as the configuration described in "6-2-3. Third example of the driving method for pixel circuit 181E."

[0495] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Furthermore, a charge equivalent to the threshold voltage VTH is held at the second node N2 (the gate electrode 722 of the second transistor T2...

Claims

1. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled using the first control signal and electrically connected between the first node and a second node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between a power supply line to which a constant voltage is supplied and a third node; a fourth transistor whose switching is controlled using the first control signal and electrically connected between a reference voltage power supply line to which a reference voltage is supplied and the second node; a fifth transistor whose switching is controlled by a second control signal different from the first control signal, the fifth transistor being electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node; a light-emitting element electrically connected to the third node; a capacitance element electrically connected between the first node and the third node; Including, Display device.

2. a third control signal line; the third control signal line also serves as the reference voltage power supply line and the initialization voltage power supply line; The display device according to claim 1 .

3. a third control signal line; the third control signal line serves as a second control signal line to which the second control signal is supplied, the reference voltage power supply line, and the initialization voltage power supply line; The display device according to claim 1 .

4. a first control circuit that outputs the first control signal; a second control circuit that outputs the second control signal; The display device according to claim 1 .

5. the first control circuit supplies a high-level voltage to the first control signal to turn on the first transistor and the fourth transistor; the second control circuit supplies a high-level voltage to the second control signal to turn on the fifth transistor; The first control circuit and the second control circuit controlling a period during which the first transistor supplies the data voltage to the first node and a period during which the fourth transistor supplies the reference voltage to the second node to be equal to each other, and controlling a period during which the first transistor supplies the data voltage to the first node to be shorter than a period during which the fifth transistor supplies the initialization voltage to the third node; The display device according to claim 4 .

6. the first transistor, the second transistor, and the fourth transistor are n-channel field effect transistors, the third transistor is a p-channel field effect transistor; The display device according to claim 1 .

7. the first transistor, the fourth transistor, and the fifth transistor are n-channel field effect transistors, the second transistor and the third transistor are p-channel field effect transistors; The display device according to claim 1 .

8. The deep level of the channel region of the third transistor is 1×10 １７ eV －１ ・cm －３ has the density of states: The display device according to claim 6 or 7.

9. a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; the first semiconductor layer includes a channel region of the second transistor and a channel region of the fifth transistor; the second semiconductor layer includes a channel region of the first transistor and a channel region of the third transistor; the third semiconductor layer includes a channel region of the fourth transistor; The display device according to claim 6 or 7.

10. a channel length of the second transistor is longer than a channel length of the first transistor, a channel length of the third transistor, a channel length of the fourth transistor, and a channel length of the fifth transistor; The display device according to claim 1 .

11. a channel region of each of the second transistor, the third transistor, the fourth transistor, and the fifth transistor includes crystalline silicon; a channel region of each of the first transistor and the fourth transistor includes an oxide semiconductor; The display device according to claim 1 .

12. a first conductive layer and a second conductive layer different from the first conductive layer; the reference voltage power supply line and the initialization voltage power supply line each include the first conductive layer and the second conductive layer which are different from each other; In a plan view, the first conductive layer and the second conductive layer included in the reference voltage power supply line overlap each other, and the first conductive layer and the second conductive layer included in the initialization voltage power supply line overlap each other. The display device according to claim 1 .

13. In a plan view, the gate electrode overlaps with the capacitance element. The display device according to claim 1 .

14. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled using the first control signal and electrically connected between the first node and a third node; a second transistor having a gate electrode electrically connected to a second node and electrically connected between the third node and a fourth node; a fourth transistor whose switching is controlled by the first control signal and which is electrically connected between the third node and a third control signal line to which a first initialization voltage and a second initialization voltage different from the first initialization voltage are supplied; a fifth transistor whose switching is controlled using a second control signal different from the first control signal, the fifth transistor being electrically connected between a third control signal line and the fourth node; a sixth transistor whose switching is controlled using the first control signal and electrically connected between the second node and the fourth node; a seventh transistor whose switching is controlled using the first control signal and electrically connected between a voltage line to which a constant voltage is supplied and the fourth node; a light-emitting element electrically connected to the third node; a capacitance element electrically connected between the first node and the second node; Including, Display device.

15. a first control circuit that outputs the first control signal; a second control circuit that outputs the second control signal; The display device according to claim 14.

16. the first control circuit supplies a high-level voltage to the first control signal to turn on the first transistor, the fourth transistor, and the sixth transistor; the second control circuit supplies a high-level voltage to the second control signal to turn on the fifth transistor; the first control circuit controls so that a period during which the first transistor supplies the data voltage to the first node, a period during which the fourth transistor supplies the first initialization voltage to the third node, and a period during which the sixth transistor supplies the first and second initialization voltages to the second node are the same. The display device according to claim 15.

17. the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-channel field effect transistors, the third transistor and the seventh transistor are p-channel field effect transistors; The display device according to claim 14.

18. the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-channel field effect transistors, the second transistor, the third transistor, and the seventh transistor are p-channel field effect transistors; The display device according to claim 14.

19. The deep level of the channel region of the third transistor is 1×10 １７ eV －１ ・cm －３ has the density of states:

19. The display device according to claim 18.

20. a channel region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor includes crystalline silicon; a channel region of the sixth transistor includes an oxide semiconductor; The display device according to claim 14.

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