Display device

Abstract

To suppress generation of display defect.SOLUTION: A display device 11 comprises a display area AA, a non-display area NAA, a first pixel switching element 24α, a second pixel switching element 24β, a first pixel portion 25α, a second pixel portion 25β, first scan wiring 26α, second scan wiring 26β, first image wiring 27α, second image wiring 27β, first connection wiring 28α, second connection wiring 28β, a first signal supply part 12, a second signal supply part 13, a first non-pixel switching element 30α, a second non-pixel switching element 30β, first wiring 31, second wiring 32, and low potential wiring 33. Third potential higher than second potential is applied to the first wiring 31 and the second wiring 32 at different timings respectively. Timing for supplying the third potential to the first wiring 31 is different from timing for supplying the first potential to the first connection wiring 28α. Timing for supplying the third potential to the second wiring 32 is different from timing for supplying the first potential to the second connection wiring 28β.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a display device that suppresses the occurrence of display defects. [Background technology]

[0002] BACKGROUND ART Conventionally, one example of a display device is known, which is described in Patent Document 1 below. The display device described in Patent Document 1 includes a plurality of pixel electrodes arranged as a plurality of sub-pixels arranged two-dimensionally; a color filter having a plurality of color components, wherein one of the plurality of color components is formed corresponding to each of the plurality of pixel electrodes; switching thin film transistors, one of whose source electrode and drain electrode is connected to each of the pixel electrodes; scanning lines for supplying scanning signals to the gate electrodes of each of the switching thin film transistors; signal lines that are perpendicular to the scanning lines and connected to the source electrode or drain electrode of each of the switching thin film transistors that is not connected to the pixel electrode, for supplying data signals; and wiring lines that are connected to the scanning lines and arranged parallel to the signal lines, wherein each of the wiring lines is arranged so that the shortest distance between the wiring line and all the signal lines that transmit data signals that control the sub-pixels corresponding to colors with low luminosity is shorter than the shortest distance between the wiring line and all the signal lines that transmit data signals that control the sub-pixels corresponding to colors with higher luminosity than the colors with low luminosity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-43774 Summary of the Invention [Problem to be solved by the invention]

[0004] In the display device described in the above-mentioned Patent Document 1, the wiring lines are arranged parallel to the signal lines within the display area to achieve a narrower frame. However, the wiring lines arranged within the display area form parasitic capacitance with other wiring (e.g., signal lines or other unconnected scanning lines). Therefore, during the period when the switching thin film transistor is in the off state, there is a risk of potential fluctuations occurring in the scanning lines due to the parasitic capacitance generated in the wiring lines. This may cause charge in the pixel electrode to leak from the switching thin film transistor, resulting in a voltage drop and resulting in display defects.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to suppress the occurrence of display defects. [Means for solving the problem]

[0006] (1) A display device according to the technology described in this specification includes a display area where an image is displayed, a non-display area where the image is not displayed, a first pixel switching element arranged in the display area, a second pixel switching element arranged in the display area, a first pixel unit arranged in the display area and connected to a drain electrode of the first pixel switching element, a second pixel unit arranged in the display area and connected to a drain electrode of the second pixel switching element, a first scanning wiring arranged in the display area, extending along a first direction and connected to a gate electrode of the first pixel switching element, a second scanning wiring arranged in the display area, extending along the first direction and connected to a gate electrode of the second pixel switching element, a first image wiring arranged in the display area, extending along a second direction intersecting the first direction and connected to a source electrode of the first pixel switching element, a second image wiring arranged in the display area, extending along the second direction and connected to a source electrode of the second pixel switching element, and a first connection wiring arranged in the display area, extending along the second direction and connected to the first scanning wiring. a second connection wiring arranged in the display region, extending along the second direction and connected to the second scanning wiring; a first signal supply unit arranged in the non-display region, connected to the first connection wiring and the second connection wiring, and applying a first potential to the first connection wiring and the second connection wiring, respectively, the first potential being a potential higher than a threshold voltage of the first pixel switching element and the second pixel switching element, at different timings; a second signal supply unit arranged in the non-display region, connected to the first image wiring and the second image wiring, and supplying image signals to the first image wiring and the second image wiring, respectively; a first non-pixel switching element arranged in the non-display region, having a drain electrode connected to the first scanning wiring or the first connection wiring; a second non-pixel switching element arranged in the non-display region, having a drain electrode connected to the second scanning wiring or the second connection wiring; a first wiring arranged in the non-display region, connected to a gate electrode of the first non-pixel switching element; a second wiring arranged in the non-display region, connected to a gate electrode of the second non-pixel switching element;a low-potential wiring connected to a source electrode of the first non-pixel switching element and a source electrode of the second non-pixel switching element and maintained at a second potential lower than the threshold voltage, wherein a third potential higher than the threshold voltages of the first non-pixel switching element and the second non-pixel switching element is applied to the first wiring and the second wiring at different timings, and the timing at which the third potential is supplied to the first wiring is different from the timing at which the first potential is supplied to the first connecting wiring, and the timing at which the third potential is supplied to the second wiring is different from the timing at which the first potential is supplied to the second connecting wiring.

[0007] (2) In addition to (1), the display device may be configured such that the first non-pixel switching elements include a first switching element having a drain electrode connected to the first connection wiring and a second switching element having a drain electrode connected to the first scanning wiring, and the second non-pixel switching elements include a third switching element having a drain electrode connected to the second connection wiring and a fourth switching element having a drain electrode connected to the second scanning wiring.

[0008] (3) In addition to (1), the display device may be configured such that the first non-pixel switching elements include a second switching element having a drain electrode connected to one end of the first scanning wiring and a fifth switching element having a drain electrode connected to the other end of the first scanning wiring, and the second non-pixel switching elements include a fourth switching element having a drain electrode connected to one end of the second scanning wiring and a sixth switching element having a drain electrode connected to the other end of the second scanning wiring.

[0009] (4) In addition to (1), the display device may be configured such that the first non-pixel switching elements include a first switching element having a drain electrode connected to the first connection wiring, a second switching element having a drain electrode connected to one end of the first scanning wiring, and a fifth switching element having a drain electrode connected to the other end of the first scanning wiring, and the second non-pixel switching elements include a third switching element having a drain electrode connected to the second connection wiring, a fourth switching element having a drain electrode connected to one end of the second scanning wiring, and a sixth switching element having a drain electrode connected to the other end of the second scanning wiring.

[0010] (5) In addition to any one of (1) to (4), the display device may be configured such that the third potential and the second potential are periodically applied to the first wiring, and the third potential and the second potential are periodically applied to the second wiring.

[0011] (6) In addition to the above (5), the display device further includes a third pixel switching element disposed in the display region, a third pixel unit disposed in the display region and connected to a drain electrode of the third pixel switching element, a third scanning wiring disposed in the display region, extending along the first direction and connected to a gate electrode of the third pixel switching element, a third image wiring disposed in the display region, extending along the second direction and connected to a source electrode of the third pixel switching element, a third connection wiring disposed in the display region, extending along the second direction and connected to the third scanning wiring, a third non-pixel switching element disposed in the non-display region and having a drain electrode connected to the third scanning wiring or the third connection wiring, and a third non-pixel switching element disposed in the non-display region and having the The pixel switching element may further include a third wiring connected to a gate electrode of a third non-pixel switching element and the first signal supply unit, wherein the third potential is applied to the third wiring at a timing different from that of the first wiring and the second wiring, the timing at which the third potential is supplied to the third wiring is different from the timing at which the first potential is supplied to the third connecting wiring, the third potential is supplied to the first wiring at both timings before and after the timing at which the first potential is supplied to the first connecting wiring, the third potential is supplied to the second wiring at both timings before and after the timing at which the first potential is supplied to the second connecting wiring, and the third potential is supplied to the third wiring at both timings before and after the timing at which the first potential is supplied to the third connecting wiring.

[0012] (7) Furthermore, in addition to any one of (1) to (6), the display device may further include a third signal supply unit arranged in the non-display area, connected to the first connection wiring and the second connection wiring, and applying the first potential to the first connection wiring and the second connection wiring at different timings, the first signal supply unit being connected to one end of the first connection wiring and the second connection wiring, and the third signal supply unit being connected to the other end of the first connection wiring and the second connection wiring, wherein the timing of supplying the first potential to the first connection wiring is synchronized with the timing of supplying the first potential from the first signal supply unit to the first connection wiring, and the timing of supplying the first potential to the second connection wiring is synchronized with the timing of supplying the first potential from the first signal supply unit to the second connection wiring.

[0013] (8) Furthermore, in addition to any one of (1) to (7), the display device may further include: a fourth non-pixel switching element arranged in the non-display area, the fourth non-pixel switching element having a drain electrode connected to the first connection wiring and a gate electrode connected to the second wiring; a fifth non-pixel switching element arranged in the non-display area, the fifth non-pixel switching element having a drain electrode connected to the second connection wiring and a gate electrode connected to the first wiring; and a fourth wiring connected to the first signal supply unit, a source electrode of the fourth non-pixel switching element, and a source electrode of the fifth non-pixel switching element, wherein the timing at which the third potential is supplied to the second wiring is synchronized with the timing at which the first potential is supplied to the fourth wiring, and the timing at which the third potential is supplied to the first wiring is synchronized with the timing at which the first potential is supplied to the fourth wiring.

[0014] (9) Furthermore, in addition to any one of (1) to (8), the display device may be configured such that the first scanning wiring and the second scanning wiring are sandwiched between the first pixel unit and the second pixel unit in the second direction, the first image wiring and the first connection wiring are arranged on the opposite side of the first pixel unit from the second pixel unit in the first direction, and the second image wiring and the second connection wiring are arranged on the opposite side of the second pixel unit from the first pixel unit in the first direction.

[0015] (10) In addition to (9), the display device may further include a fifth wiring arranged in the display area, sandwiched between the first pixel unit and the second pixel unit in the first direction, and an end of the fifth wiring may be arranged in the non-display area and connected to the low-potential wiring.

[0016] (11) In addition to any one of (1) to (10), the display device may be configured such that the first wiring and the second wiring are arranged farther from the display area than the first non-pixel switching elements and the second non-pixel switching elements.

[0017] (12) In addition to any one of (1) to (11), the display device may be configured such that the first wiring and the second wiring are connected to the first signal supply unit. [Effects of the Invention]

[0018] According to the technology described in this specification, the occurrence of display defects can be suppressed. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a plan view of a liquid crystal panel, drivers, and a flexible substrate that constitute a liquid crystal display device according to a first embodiment; [Figure 2] 1 is a cross-sectional view of a liquid crystal panel, a gate driver, and a flexible substrate according to Embodiment 1. [Figure 3] 1 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a first embodiment; [Figure 4] 1 is a timing chart showing the operation of the low-potential supply circuit and the gate driver according to the first embodiment; [Figure 5] 1 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a second embodiment. [Figure 6] 10 is a timing chart showing the operation of the low-potential supply circuit and the gate driver according to the second embodiment; [Figure 7] 10 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a third embodiment. [Figure 8] 1 is a circuit diagram showing a gate drive circuit according to a third embodiment; [Figure 9] 10 is a timing chart showing the operation of the gate drive circuit and gate driver according to the third embodiment. [Figure 10] 10 is a plan view of a liquid crystal panel, each driver, and a flexible substrate according to a fourth embodiment. [Figure 11] 10 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a fourth embodiment. [Figure 12] 10 is a timing chart showing the operation of the switch circuit and the gate driver according to the fourth embodiment. [Figure 13] 10 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] <Embodiment 1> Embodiment 1 will be described with reference to Figs. 1 to 4. In this embodiment, a liquid crystal display device 10 will be illustrated. Note that X-axis, Y-axis, and Z-axis are shown in parts of each drawing, and each axis direction is depicted as being in the direction shown in each drawing. Also, the upper side of Fig. 2 is the front side, and the lower side of the drawing is the back side.

[0021] As shown in Fig. 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display device) 11 capable of displaying images, and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light to be used for display. The backlight device is disposed on the rear side (back surface) of the liquid crystal panel 11 and includes a light source (e.g., an LED) that emits white light and optical components that convert the light from the light source into planar light by applying an optical effect. The central portion of the main surface of the liquid crystal panel 11 is a display area AA where an image is displayed. In contrast, a frame-shaped outer peripheral portion of the main surface of the liquid crystal panel 11 that surrounds the display area AA is a non-display area NAA where no image is displayed.

[0022] The liquid crystal panel 11 will be described with reference to FIG. 1 and FIG. 2. As shown in FIGS. 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. The front side of the pair of substrates 20 and 21 is the counter substrate 20, and the back side is the array substrate 21. The counter substrate 20 and the array substrate 21 are both formed by laminating various films on the inner surface of a glass substrate. A liquid crystal layer 22 containing liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied, is disposed between the pair of substrates 20 and 21. A seal portion 23 that seals the liquid crystal layer 22 is disposed between the outer peripheral edges of the pair of substrates 20 and 21. The seal portion 23 is formed in a rectangular frame shape so as to surround the liquid crystal layer 22. A polarizing plate 15 is attached to the outer surface of each of the substrates 20 and 21.

[0023] 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 so that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally from the counter substrate 20 and is exposed. The entire exposed portion 21A is a non-display area NAA, and drivers 12 and 13 and a flexible substrate 14 for supplying various signals are mounted on the exposed portion 21A.

[0024] The drivers 12 and 13 are each composed of an LSI chip having an internal drive circuit. The drivers 12 and 13 are both mounted on the exposed portion 21A of the array substrate 21 by COG (Chip On Glass). The drivers 12 and 13 process various signals transmitted by the flexible substrate 14. As shown in FIGS. 1 and 2, the drivers 12 and 13 are both arranged adjacent to one side of the display area AA in the Y-axis direction, and are sandwiched between the flexible substrate 14 (described later) and the display area AA. The drivers 12 and 13 each have a horizontally elongated rectangular shape in plan view. The long side of each driver 12 and 13 is smaller than the long side of the display area AA.

[0025] As shown in FIG. 1 , the drivers 12 and 13 include a gate driver (first signal supply unit) 12 and a source driver (second signal supply unit) 13. The gate driver 12 processes various signals transmitted by the flexible substrate 14 and supplies scanning signals to gate wiring 26 (described later). The gate driver 12 includes a shift register circuit that outputs scanning signals at predetermined timing and a buffer circuit for amplifying the scanning signals. The source driver 13 processes various signals transmitted by the flexible substrate 14 and supplies image signals to source wiring 27 (described later). Three source drivers 13 are arranged at intervals in the X-axis direction in the exposed portion 21A of the array substrate 21, near both ends and near the center in the X-axis direction. Two gate drivers 12 are arranged at intervals in the X-axis direction in the exposed portion 21A of the array substrate 21, sandwiched between the source drivers 13 arranged at both ends in the X-axis direction and the source driver 13 arranged near the center. A predetermined distance is provided between the gate driver 12 and the source driver 13 that are adjacent to each other in the X-axis direction.

[0026] The flexible substrate 14 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). As shown in FIGS. 1 and 2, one end of the flexible substrate 14 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (e.g., a control board). The flexible substrate 14 is connected to an end of the exposed portion 21A on the opposite side of the display area AA in the Y-axis direction from the drivers 12 and 13. In other words, the flexible substrate 14 is attached to the exposed portion 21A of the array substrate 21 at a position where the drivers 12 and 13 are sandwiched between the exposed portion 21A and the display area AA. Two flexible substrates 14 are arranged at positions spaced apart in the X-axis direction in the exposed portion 21A of the array substrate 21.

[0027] Next, the configuration of the display area AA of the array substrate 21 will be described with reference to FIG. 3. As shown in FIG. 3, at least pixel TFTs (pixel switching elements) 24 and pixel electrodes (pixel portions) 25 are provided on the inner surface of the display area AA of the array substrate 21. Multiple pixel TFTs 24 and multiple pixel electrodes 25 are arranged in a matrix (row and column) with spaces between them along the X-axis direction and the Y-axis direction. Gate wiring (scanning wiring) 26 and source wiring (image wiring, signal wiring) 27, which intersect with each other at right angles, are disposed around the pixel TFTs 24 and pixel electrodes 25. The gate wiring 26 extends along the X-axis direction (first direction), with multiple wirings spaced apart along the Y-axis direction. The source wiring 27 extends along the Y-axis direction (second direction intersecting the first direction), with multiple wirings spaced apart along the X-axis direction. The gate wiring 26 is made of a part of a first metal film among the films formed on the array substrate 21. The source wiring 27 is made of a part of a second metal film disposed above the first metal film with a gate insulating film interposed therebetween. The gate wiring 26 and source wiring 27, which intersect with each other, are kept in an insulated state by the gate insulating film interposed therebetween. The first metal film and the second metal film are both made of a single layer film made of one type of metal material or a laminated film or alloy made of different types of metal materials, and are therefore conductive. Examples of materials that can be used for the first metal film and the second metal film include copper, tantalum, molybdenum, titanium, and aluminum. The gate insulating film is made of silicon nitride (SiN x ), and silicon dioxide (SiO2), among other inorganic materials.

[0028] As shown in FIG. 3, the pixel TFT 24 includes a pixel gate electrode (gate electrode) 24A connected to the gate line 26, a pixel source electrode (source electrode) 24B connected to the source line 27, a pixel drain electrode (drain electrode) 24C connected to the pixel electrode 25, and a pixel semiconductor portion (semiconductor portion) 24D connected to the pixel source electrode 24B and the pixel drain electrode 24C and made of a semiconductor material. The pixel gate electrode 24A is made of a part of a first metal film. The pixel source electrode 24B and the pixel drain electrode 24C are each made of a part of a second metal film. The pixel semiconductor portion 24D is made of, for example, a part of a semiconductor film located above the gate insulating film and below the second metal film. When the pixel gate electrode 24A becomes equal to or higher than a threshold voltage, a current flows between the pixel source electrode 24B and the pixel drain electrode 24C. A potential higher than this threshold voltage is set to a first potential (high potential Vgh) (see FIG. 4). The gate line 26 transmits a first potential as a scanning signal to the pixel gate electrode 24A of the pixel TFT 24 at a predetermined timing. The gate line 26 is maintained at a second potential (low potential Vgl) lower than the first potential and the threshold voltage during all periods except for the timing at which the scanning signal is transmitted (see FIG. 4). When the scanning signal (first potential) is supplied to the pixel gate electrode 24A by the gate line 26, the pixel TFT 24 is driven. Then, a potential related to an image signal (data signal) supplied to the pixel source electrode 24B by the source line 27 is supplied to the pixel drain electrode 24C via the pixel semiconductor portion 24D. As a result, the pixel electrode 25 is charged to the potential related to the image signal.

[0029] As shown in FIG. 3, the pixel electrode 25 is disposed in a region surrounded by the gate wiring 26 and the source wiring 27, and has a planar shape of, for example, a substantially rectangular shape. The pixel electrode 25 is made of a part of a transparent electrode film disposed above the second metal film constituting the pixel drain electrode 24C, with one or more insulating films interposed therebetween. The transparent electrode film is made of a transparent electrode material (e.g., ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)). The pixel electrode 25 overlaps with a color filter disposed in the display area AA of the counter substrate 20, and together with the color filter, constitutes a pixel, which is a display unit. The color filter may be of three colors, for example, blue (B), green (G), and red (R). In addition, a common electrode made of the same transparent electrode material as the pixel electrode 25 and disposed to overlap the pixel electrode 25 with a gap therebetween is provided on either the counter substrate 20 or the array substrate 21. A common potential (reference potential) is supplied to the common electrode. In the liquid crystal panel 11, a predetermined electric field is applied to the liquid crystal layer 22 based on the potential difference between the common electrode and each pixel electrode 25, thereby enabling each pixel to display a predetermined gray scale. When the common electrode is provided on the array substrate 21, an insulating film is interposed between the common electrode and each pixel electrode 25, and a slit is provided in the upper electrode (closer to the liquid crystal layer 22) between the common electrode and each pixel electrode 25. With this configuration, the electric field generated based on the potential difference between the common electrode and the pixel electrode 25 includes a fringe field including a component normal to the main surface of the array substrate 21 in addition to a component along the main surface of the array substrate 21. Therefore, the display mode of the liquid crystal panel 11 configured as such is a so-called FFS (Fringe Field Switching) mode, in which the fringe field is used to control the alignment state of the liquid crystal contained in the liquid crystal layer 22. Note that alignment films for aligning the liquid crystal molecules contained in the liquid crystal layer 22 are provided on the innermost surfaces of both substrates 20 and 21.

[0030] As shown in FIG. 3, connection wiring 28 connected to the gate wiring 26 is provided on the inner surface of the display region AA of the array substrate 21. The connection wiring 28 extends along the Y-axis direction parallel to the source wiring 27, and multiple connection wirings 28 are arranged at intervals in the X-axis direction. Like the source wiring 27, the connection wiring 28 is made of part of the second metal film. The connection wiring 28 is arranged at a position spaced apart from the source wiring 27 in the X-axis direction to prevent short-circuiting with the source wiring 27. More specifically, the connection wiring 28 is arranged at an interval on the side (left side of FIG. 3) opposite to the pixel TFT 24 to which the source wiring 27 is connected in the X-axis direction (right side of FIG. 3). The connection wiring 28 is arranged between the source wiring 27 and the pixel electrode 25 that is not connected to the source wiring 27 in the X-axis direction. The connection wiring 28 is arranged across the entire length of the display region AA in the Y-axis direction. Therefore, although the connection wiring 28 intersects with all the gate wirings 26 arranged in the display area AA, it is kept insulated from the gate wirings 26 that are not to be connected by the intervening gate insulating film. The connection wiring 28 is connected to the gate wirings 26 that are to be connected through contact holes CH formed in the intervening gate insulating film. The number of connection wirings 28 is, for example, the same as the number of gate wirings 26. In this case, the multiple connection wirings 28 are individually connected to the multiple gate wirings 26. One end of each connection wiring 28 (the lower end in FIG. 3 ) is drawn out to the outside of the display area AA (the non-display area NAA) and connected to the gate driver 12. A scanning signal (first potential) is input to the connection wiring 28 from the gate driver 12. The scanning signal input to the connection wiring 28 is transmitted to the gate wirings 26 connected in the display area AA. The gate driver 12 inputs scanning signals to the plurality of connection wirings 28 in a predetermined order. For example, the scanning signals are input in the order of the connection wiring 28 connected to the gate wiring 26 located in the top row, the connection wiring 28 connected to the gate wiring 26 located in the second row, the connection wiring 28 connected to the gate wiring 26 located in the third row, and finally the scanning signal is input to the connection wiring 28 connected to the gate wiring 26 located in the bottom row.Furthermore, the connection wirings 28 have different lengths from the gate driver 12 to the gate wirings 26 to be connected.

[0031] As described above, according to the present embodiment, the gate wiring 26 is connected to the gate driver 12 via the connection wiring 28, and therefore, compared to the case where the gate wiring 26 is directly connected to the gate driver 12, it is not necessary to secure installation space for the gate driver 12 near the end of the non-display area NAA in the X-axis direction. This makes it possible to narrow the end of the non-display area NAA in the X-axis direction, thereby enabling the liquid crystal panel 11 to have a narrower frame.

[0032] Here, of the multiple gate wirings 26, the gate wiring 26 that is odd-numbered counting from the top and is located in the top row in Fig. 3 will be referred to as the "first gate wiring (first scanning wiring) 26α," and the gate wiring 26 that is even-numbered counting from the top and is located in the row next to the first gate wiring 26α will be referred to as the "second gate wiring (second scanning wiring) 26β." Of the multiple connection wirings 28, the connection wiring 28 connected to the first gate wiring 26α will be referred to as the "first connection wiring 28α," and the connection wiring 28 connected to the second gate wiring 26β will be referred to as the "second connection wiring 28β." Of the multiple source wirings 27, the source wiring 27 adjacent to the first connection wiring 28α (the source wiring 27 located second from the left end of FIG. 3) is referred to as the “first source wiring (first image wiring) 27α,” and the source wiring 27 adjacent to the second connection wiring 28β (the source wiring 27 located third from the left end of FIG. 3) is referred to as the “second source wiring (second image wiring) 27β.” Of the multiple pixel TFTs 24, the pixel TFT 24 having a pixel gate electrode 24A connected to the first gate wiring 26α and a source electrode 27B connected to the first source wiring 27α is referred to as the “first pixel TFT (first pixel switching element) 24α,” and the pixel TFT 24 having a pixel gate electrode 24A connected to the second gate wiring 26β and a source electrode 27B connected to the second source wiring 27β is referred to as the “second pixel TFT (second pixel switching element) 24β.” Of the multiple pixel electrodes 25, the pixel electrode 25 connected to the pixel drain electrode 24C of the first pixel TFT 24α is referred to as the "first pixel electrode (first pixel portion) 25α," and the pixel electrode 25 connected to the pixel drain electrode 24C of the second pixel TFT 24β is referred to as the "second pixel electrode (second pixel portion) 25β."

[0033] Next, the configuration of the non-display area NAA of the array substrate 21 will be described with reference to Fig. 3. As shown in Fig. 3, the non-display area NAA of the array substrate 21 is provided with a low-potential supply circuit (second-potential supply circuit) 29 that can supply a second potential to at least one of the gate lines 26 and the connection lines 28 at a predetermined timing. The low-potential supply circuit 29 is arranged over three sides of the non-display area NAA, which has a frame shape surrounding the display area AA, excluding the sides on the drivers 12 and 13 sides. The low-potential supply circuit 29 has a plurality of non-pixel TFTs (non-pixel switching elements) 30, a first clock line (first line) 31, a second clock line (second line) 32, and a low-potential line (second-potential line) 33.

[0034] In Figure 3, the scanning signal input to the second gate wiring 26β and the second connection wiring 28β is designated by the symbol "G(i)" (hereinafter, i is an integer greater than or equal to 1), the scanning signal input to the first gate wiring 26α and the first connection wiring 28α located above the second gate wiring 26β and the second connection wiring 28β is designated by the symbol "G(i-1)", and the scanning signal input to the gate wiring 26 and the connection wiring 28 located above that is designated by the symbol "G(i-2)". Furthermore, the symbol "G(i+1)" is assigned to the scanning signal input to the gate wiring 26 and connection wiring 28 located below the second gate wiring 26β and second connection wiring 28β, the symbol "G(i+2)" is assigned to the scanning signal input to the gate wiring 26 and connection wiring 28 located below that, the symbol "G(i+3)" is assigned to the scanning signal input to the gate wiring 26 and connection wiring 28 located below that, and the symbol "G(i+4)" is assigned to the scanning signal input to the gate wiring 26 and connection wiring 28 located below that. Similarly, the symbol "S(j)" is assigned to the image signal input to the second source wiring 27β, and the symbol "S(j-1)" is assigned to the image signal input to the first source wiring 27α located before (to the left of) the second source wiring 27β. Furthermore, the symbol "S(j+1)" (hereinafter, j is an integer greater than or equal to 1) is assigned to the image signal input to the source wiring 27 located in the next stage (the next to the right in Figure 3) of the second source wiring 27β, the symbol "S(j+2)" is assigned to the image signal input to the source wiring 27 located in the next stage after that, the symbol "S(j+3)" is assigned to the image signal input to the source wiring 27 located in the next stage after that, and the symbol "S(j+4)" is assigned to the image signal input to the source wiring 27 located in the next stage after that.

[0035] As shown in FIG. 3 , the non-pixel TFT 30 includes a non-pixel gate electrode (gate electrode) 30A connected to the first clock line 31 or the second clock line 32, a non-pixel source electrode (source electrode) 30B connected to the low-potential line 33, a non-pixel drain electrode (drain electrode) 30C connected to the gate line 26 or the connecting line 28, and a non-pixel semiconductor portion (semiconductor portion) 30D connected to the non-pixel source electrode 30B and the non-pixel drain electrode 30C and made of a semiconductor material. Like the pixel gate electrode 24A, the non-pixel gate electrode 30A is made of a part of a first metal film. Like the pixel source electrode 24B and the pixel drain electrode 24C, the non-pixel source electrode 30B and the non-pixel drain electrode 30C are made of a part of a second metal film. Like the pixel semiconductor portion 24D, the non-pixel semiconductor portion 30D is made of a part of a semiconductor film. The threshold voltage of the non-pixel TFT 30 is set to be the same as that of the pixel TFT 24. When the non-pixel gate electrode 30A becomes equal to or higher than the threshold voltage, a current flows between the non-pixel source electrode 30B and the non-pixel drain electrode 30C. A potential higher than this threshold voltage is set as a third potential (high potential Vgh), which is set to be the same as the first potential (high potential Vgh) (see FIG. 4). The threshold voltage of the non-pixel TFT 30 is higher than the second potential (low potential Vgl).

[0036] 3, the plurality of non-pixel TFTs 30 include at least a first non-pixel TFT (first non-pixel switching element) 30α and a second non-pixel TFT (second non-pixel switching element) 30β. The first non-pixel TFT 30α has a non-pixel gate electrode 30A connected to the first clock line 31 and a non-pixel drain electrode 30C connected to the first gate line 26α or the first connection line 28α. The second non-pixel TFT 30β has a non-pixel gate electrode 30A connected to the second clock line 32 and a non-pixel drain electrode 30C connected to the second gate line 26β or the second connection line 28β. A plurality of first non-pixel TFTs 30α and a plurality of second non-pixel TFTs 30β are provided, and are distributed along three sides of the non-display area NAA, excluding the sides on the drivers 12 and 13 sides.

[0037] As shown in FIG. 3, the plurality of first non-pixel TFTs 30α include at least a first TFT (first switching element) 30α1, a second TFT (second switching element) 30α2, and a fifth TFT (fifth switching element) 30α3. The first TFT 30α1 is disposed on a side of the non-display area NAA opposite to the side of the drivers 12 and 13 (the upper side of FIG. 3). The first TFT 30α1 has a non-pixel drain electrode 30C connected to the first connection wiring 28α. The non-pixel drain electrode 30C of the first TFT 30α1 is connected to an end of the first connection wiring 28α opposite to the gate driver 12 side. The second TFT 30α2 is disposed on one of two sides of the non-display area NAA sandwiching the display area AA in the X-axis direction (the left side of FIG. 3). The second TFT 30α2 has a non-pixel drain electrode 30C connected to one end (left side in FIG. 3) of the first gate line 26α. The fifth TFT 30α3 is arranged on the other side (right side in FIG. 3) of the two sides of the non-display area NAA that sandwich the display area AA in the X-axis direction. The fifth TFT 30α3 has a non-pixel drain electrode 30C connected to the other end (right side in FIG. 3) of the first gate line 26α.

[0038] As shown in FIG. 3, the plurality of second non-pixel TFTs 30β include at least a third TFT (third switching element) 30β1, a fourth TFT (fourth switching element) 30β2, and a sixth TFT (sixth switching element) 30β3. The third TFT 30β1 is disposed on a side of the non-display area NAA opposite to the side of the drivers 12 and 13 (the upper side of FIG. 3). The third TFT 30β1 has a non-pixel drain electrode 30C connected to the second connection wiring 28β. The non-pixel drain electrode 30C of the third TFT 30β1 is connected to an end of the second connection wiring 28β opposite to the gate driver 12 side. The fourth TFT 30β2 is disposed on one of two sides (the left side of FIG. 3) sandwiching the display area AA in the X-axis direction. The fourth TFT 30β2 has a non-pixel drain electrode 30C connected to one end (left side in FIG. 3) of the second gate line 26β. The sixth TFT 30β3 is arranged on the other side (right side in FIG. 3) of the two sides of the non-display area NAA that sandwich the display area AA in the X-axis direction. The sixth TFT 30β3 has a non-pixel drain electrode 30C connected to the other end (right side in FIG. 3) of the second gate line 26β.

[0039] As shown in FIG. 3 , the first clock wiring 31 is connected to the gate driver 12 and to the non-pixel gate electrodes 30A of the non-pixel TFTs 30 (including the first non-pixel TFTs 30α) connected to the odd-numbered gate wiring 26 (including the first gate wiring 26α) among the multiple non-pixel TFTs 30 or the connection wiring 28 (including the first connection wiring 28α) connected to that gate wiring 26. The first clock wiring 31 is arranged across the four sides of the non-display area NAA. Specifically, the first clock wiring 31 has a portion extending along the X-axis direction on a side of the non-display area NAA opposite the side on the drivers 12 and 13 side in the Y-axis direction, two portions extending along the Y-axis direction on two sides sandwiching the display area AA from both sides in the X-axis direction, and a portion routed toward the gate driver 12 on the side on the drivers 12 and 13 side. The first clock wiring 31 is configured from a part of the first metal film or a part of the second metal film.

[0040] As shown in FIG. 3 , the second clock wiring 32 is connected to the gate driver 12 and to the non-pixel gate electrodes 30A of the non-pixel TFTs 30 (including the second non-pixel TFTs 30β) connected to the even-numbered gate wiring 26 (including the second gate wiring 26β) or the connection wiring 28 (including the second connection wiring 28β) connected to that gate wiring 26 among the multiple non-pixel TFTs 30. The second clock wiring 32 is arranged across the four sides of the non-display area NAA. Specifically, the second clock wiring 32 has a portion extending along the X-axis direction on a side of the non-display area NAA opposite the side on the drivers 12 and 13 side in the Y-axis direction, two portions extending along the Y-axis direction on two sides sandwiching the display area AA from both sides in the X-axis direction, and a portion routed toward the gate driver 12 on the side on the drivers 12 and 13 side. The second clock wiring 32 is configured from a part of the first metal film or a part of the second metal film. The second clock wiring 32 is arranged closer to the display area AA than the first clock wiring 31 on three sides of the non-display area NAA excluding the sides on the drivers 12 and 13 sides. The first clock wiring 31 and the second clock wiring 32 may be connected to the flexible substrate 14 without being connected to the gate driver 12. When the first clock wiring 31 and the second clock wiring 32 are connected to the flexible substrate 14, signals (clock signals GCK1 and GCK2, described later) are supplied to the first clock wiring 31 and the second clock wiring 32 from a circuit board (such as a control board) connected to the flexible substrate 14.

[0041] As shown in Fig. 3, the low-potential wiring 33 is connected to the non-pixel source electrodes 30B of all non-pixel TFTs 30 (including the first non-pixel TFT 30α and the second non-pixel TFT 30β). The low-potential wiring 33 is connected to the gate driver 12 or the flexible substrate 14, and is always maintained at a second potential (low potential Vgl) lower than the first potential by the gate driver 12 or the flexible substrate 14 (see Fig. 4). When the non-pixel TFT 30 is driven, the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B is supplied to the gate wiring 26 or the connection wiring 28 via the non-pixel drain electrode 30C and the non-pixel semiconductor portion 30D. The low-potential wiring 33 is arranged over the four sides of the non-display area NAA. Specifically, the low-potential wiring 33 has a portion extending along the X-axis direction on a side of the non-display area NAA opposite to the side on the side of each driver 12, 13 in the Y-axis direction, two portions extending along the Y-axis direction on two sides sandwiching the display area AA from both sides in the X-axis direction, and a portion routed toward the gate driver 12 or the flexible substrate 14 on the side on the side of each driver 12, 13. The low-potential wiring 33 is configured from a part of the first metal film or the second metal film.

[0042] 3, the first clock wiring 31 and the second clock wiring 32 are arranged at positions farther from the display area AA than any of the non-pixel TFTs 30 on three sides of the non-display area NAA excluding the sides on the drivers 12 and 13 sides. This makes it less likely that the electric field generated by the first clock wiring 31 and the second clock wiring 32 will adversely affect the signals transmitted by the source wirings 27 and the gate wirings 26 arranged in the display area AA or the potential of the pixel electrodes 24.

[0043] Next, the operation of the low-potential supply circuit 29 and the gate driver 12 will be described with reference to the timing chart shown in FIG. 4. FIG. 4 shows signal waveforms on the first clock line 31, the second clock line 32, the first gate line 26α, and the second gate line 26β. FIG. 4 also includes a scale for each unit period (one horizontal period) H. Specifically, FIG. 4 shows, from top to bottom, a first clock signal GCK1 transmitted by the first clock line 31, a second clock signal GCK2 transmitted by the second clock line 32, a first scanning signal G(i-1) transmitted by the first gate line 26α, and a second scanning signal G(i) transmitted by the second gate line 26β. The first clock signal GCK1, the second clock signal GCK2, the first scanning signal G(i-1), and the second scanning signal G(i) are all output from the gate driver 12. In other words, it can be said that the operation of the low-potential supply circuit 29 is controlled by the gate driver 12.

[0044] As shown in FIG. 4 , the high-level potential (hereinafter referred to as the high potential) of the first clock signal GCK1, the second clock signal GCK2, the first scanning signal G(i-1), and the second scanning signal G(i) is “Vgh,” which corresponds to the first and third potentials described above, and the low-level potential (hereinafter referred to as the low potential) is “Vgl,” which corresponds to the second potential described above. The first clock signal GCK1 and the second clock signal GCK2 are both roughly rectangular waves, and have signal waveforms that periodically repeat a high potential Vgh and a low potential Vgl for each unit period H. The first clock signal GCK1 and the second clock signal GCK2 have signal waveforms that are out of phase with each other by 180 degrees. Therefore, during the unit period H in which the first clock signal GCK1 is at the high potential Vgh, the second clock signal GCK2 is at the low potential Vgl, and during the unit period H in which the first clock signal GCK1 is at the low potential Vgl, the second clock signal GCK2 is at the high potential Vgh. That is, the gate driver 12 applies the high potential Vgh to the first clock wire 31 and the second clock wire 32 at different timings.

[0045] As shown in Fig. 4, the first scanning signal G(i-1) and the second scanning signal G(i) have signal waveforms that are at a high potential Vgh only in one predetermined unit period H of one frame display period and at a low potential Vgl in the other unit periods H. The first scanning signal G(i-1) is synchronized so that the unit period H during which it is at a high potential Vgh coincides with the unit period H during which it is at a high potential Vgh in the second clock signal GCK2 (the unit period H during which it is at a low potential Vgl in the first clock signal GCK1). The second scanning signal G(i) is synchronized so that the unit period H during which it is at a high potential Vgh coincides with the unit period H during which it is at a high potential Vgh in the first clock signal GCK1 (the unit period H during which it is at a low potential Vgl in the second clock signal GCK2).

[0046] The specific operations of the low-potential supply circuit 29 and the gate driver 12 will be described. As shown in FIG. 4, the gate driver 12 outputs the high potential Vgh of the first scanning signal G(i-1) to the first connection wiring 28α in synchronization with a predetermined unit period H during which the second clock signal GCK2 is at the high potential Vgh. The high potential Vgh of the first scanning signal G(i-1) is then transmitted to the first gate wiring 26α via the first connection wiring 28α and supplied to the pixel gate electrode 24A of the first pixel TFT 24α. When the first pixel TFT 24α is driven in response to this, the image signal supplied from the source driver 13 to the first source wiring 27α is supplied from the pixel source electrode 24B to the pixel drain electrode 24C via the pixel semiconductor portion 24D, and as a result, the first pixel electrode 25α is charged to a potential based on the image signal.

[0047] As shown in FIG. 4, the gate driver 12 outputs the high potential Vgh of the second scanning signal G(i) to the second connection wiring 28β at the timing when the first scanning signal G(i-1) switches from the high potential Vgh to the low potential Vgl. That is, the gate driver 12 applies the high potential Vgh to the first connection wiring 28α and the second connection wiring 28β at different times. Then, the high potential Vgh of the second scanning signal G(i) is transmitted to the second gate wiring 26β via the second connection wiring 28β and supplied to the pixel gate electrode 24A of the second pixel TFT 24β. When the second pixel TFT 24β is driven in response to this, the image signal supplied from the source driver 13 to the second source wiring 27β is supplied from the pixel source electrode 24B to the pixel drain electrode 24C via the pixel semiconductor portion 24D, and as a result, the second pixel electrode 25β is charged to a potential based on the image signal.

[0048] 4, during a unit period H in which the first scanning signal G(i-1) is at a high potential Vgh, the gate driver 12 sets the first clock signal GCK1 to a low potential Vgl and the second clock signal GCK2 to a high potential Vgh. On the other hand, during a unit period H in which the second scanning signal G(i) is at a high potential Vgh, the gate driver 12 sets the first clock signal GCK1 to a high potential Vgh and the second clock signal GCK2 to a low potential Vgl. In this way, the gate driver 12 according to this embodiment supplies the high potential Vgh to the first clock wiring 31 at a timing different from that of supplying the high potential Vgh to the first connection wiring 28α, and supplies the high potential Vgh to the second clock wiring 32 at a timing different from that of supplying the high potential Vgh to the second connection wiring 28β.

[0049] 4, the timing at which the high potential Vgh is supplied to the first clock line 31 is different from the timing at which the high potential Vgh is supplied to the first connection line 28α. Therefore, during the unit period H in which the first non-pixel TFT 30α is driven, the first gate line 26α is deselected and the first pixel TFT 24α is in the OFF state. Thus, during the unit period H in which the first pixel TFT 24α is in the OFF state, the first non-pixel TFT 30α supplies the low potential Vgl to the first gate line 26α and the first connection line 28α. This reduces the likelihood of potential fluctuations in the first gate line 26α and the first connection line 28α due to parasitic capacitance that may occur between the first connection line 28α and other lines (such as the first source line 27α and the gate lines 26 other than the first gate line 26α). This reduces the likelihood of charge leakage from the first pixel electrode 25α from the first pixel TFT 24α, reducing the likelihood of display defects.

[0050] 4, the timing at which the high potential Vgh is supplied to the second clock line 32 is different from the timing at which the high potential Vgh is supplied to the second connection line 28β. Therefore, during the unit period H in which the second non-pixel TFT 30β is driven, the second gate line 26β is deselected and the second pixel TFT 24β is in the OFF state. Thus, during the unit period H in which the second pixel TFT 24β is in the OFF state, the second non-pixel TFT 30β supplies the low potential Vgl to the second gate line 26β and the second connection line 28β. This reduces the likelihood of potential fluctuations in the second gate line 26β and the second connection line 28β due to parasitic capacitance that may occur between the second connection line 28β and other lines (such as the second source line 27β and the gate lines 26 other than the second gate line 26β). This reduces the likelihood of charge leakage from the second pixel electrode 25β from the second pixel TFT 24β, reducing the likelihood of display defects.

[0051] 3, the first non-pixel TFT 30α includes a first TFT 30α1 having a non-pixel drain electrode 30C connected to the first connection wiring 28α, a second TFT 30α2 having a non-pixel drain electrode 30C connected to one end of the first gate wiring 26α, and a fifth TFT 30α3 having a non-pixel drain electrode 30C connected to the other end of the first gate wiring 26α. Therefore, when the high potential Vgh is supplied from the gate driver 12 to the first clock wiring 31, the first non-pixel TFTs 30α, that is, the first TFT 30α1, the second TFT 30α2, and the fifth TFT 30α3, are driven. Then, the low potential Vgl supplied from the low potential wiring 33 to the non-pixel source electrode 30B of the first TFT 30α1 is supplied to the end of the first connection wiring 28α opposite the gate driver 12 side via the non-pixel drain electrode 30C and non-pixel semiconductor portion 30D of the first TFT 30α1. Also, the low potential Vgl supplied from the low potential wiring 33 to the non-pixel source electrode 30B of the second TFT 30α2 is supplied to one end of the first gate wiring 26α via the non-pixel drain electrode 30C and non-pixel semiconductor portion 30D of the second TFT 30α2. Furthermore, the low potential Vgl supplied from the low potential wiring 33 to the non-pixel source electrode 30B of the fifth TFT 30α3 is supplied to the other end of the first gate wiring 26α via the non-pixel drain electrode 30C and non-pixel semiconductor portion 30D of the fifth TFT 30α3. In this way, the low potential Vgl is supplied to the end of the first connection wiring 28α opposite the gate driver 12 side and to both ends of the first gate wiring 26α, which is advantageous in maintaining a stable potential (low potential Vgl) of the first connection wiring 28α and the first gate wiring 26α. Furthermore, compared to a case where only one of the first TFT 30α1, the second TFT 30α2, and the fifth TFT 30α3 is provided, the first TFT 30α1, the second TFT 30α2, and the fifth TFT 30α3 can each be made smaller. This is advantageous in achieving a narrower frame.

[0052] 3, the second non-pixel TFT 30β includes a third TFT 30β1 having a non-pixel drain electrode 30C connected to the second connection wiring 28β, a fourth TFT 30β2 having a non-pixel drain electrode 30C connected to one end of the second gate wiring 26β, and a sixth TFT 30β3 having a non-pixel drain electrode 30C connected to the other end of the second gate wiring 26β. Therefore, when the high potential Vgh is supplied from the gate driver 12 to the second clock wiring 32, the third TFT 30β1, the fourth TFT 30β2, and the sixth TFT 30β3, which constitute the second non-pixel TFT 30β, are driven. Then, the low potential Vgl supplied from the low potential wiring 33 to the non-pixel source electrode 30B of the third TFT 30β1 is supplied to the end of the second connection wiring 28β opposite the gate driver 12 side via the non-pixel drain electrode 30C and non-pixel semiconductor portion 30D of the third TFT 30β1. The low potential Vgl supplied from the low potential wiring 33 to the non-pixel source electrode 30B of the fourth TFT 30β2 is supplied to one end of the second gate wiring 26β via the non-pixel drain electrode 30C and non-pixel semiconductor portion 30D of the fourth TFT 30β2. The low potential Vgl supplied from the low potential wiring 33 to the non-pixel source electrode 30B of the sixth TFT 30β3 is supplied to the other end of the second gate wiring 26β via the non-pixel drain electrode 30C and non-pixel semiconductor portion 30D of the sixth TFT 30β3. In this way, the second potential is supplied to the end of the second connection wiring 28β opposite the gate driver 12 side and to both ends of the second gate wiring 26β, which is advantageous in maintaining a stable potential (low potential Vgl) of the second connection wiring 28β and the second gate wiring 26β. Furthermore, compared to the case where only one of the third TFT 30β1, the fourth TFT 30β2, and the sixth TFT 30β3 is provided, the third TFT 30β1, the fourth TFT 30β2, and the sixth TFT 30β3 can each be made smaller. This is advantageous in achieving a narrower frame.

[0053] The gate driver 12 also periodically applies a low potential Vgl and a high potential Vgh to the first clock line 31 and the second clock line 32, respectively, and inverts the voltages so that their phases are shifted by 180 degrees. Therefore, during a period in which the first gate line 26α is deselected and the first pixel TFT 24α is off, the first non-pixel TFT 30α is repeatedly driven and the low potential Vgl is repeatedly supplied to the first gate line 26α and the first connection line 28α. Specifically, the low potential Vgl is supplied to the first gate line 26α and the first connection line 28α during approximately half of the unit period H included in one frame display period. Similarly, during a period in which the second gate line 26β is deselected and the second pixel TFT 24β is off, the second non-pixel TFT 30β is repeatedly driven and the low potential Vgl is repeatedly supplied to the second gate line 26β and the second connection line 28β. Specifically, a low potential Vgl is supplied to the second gate wiring 26β and the second connection wiring 28β during approximately half of the unit periods H included in one frame display period. This makes it more difficult for potential fluctuations to occur in the first gate wiring 26α, the first connection wiring 28α, the second gate wiring 26β, and the second connection wiring 28β, and therefore more difficult for display defects to occur.

[0054] As described above, the liquid crystal panel (display device) 11 of this embodiment includes a display area AA where an image is displayed, a non-display area NAA where an image is not displayed, a first pixel TFT (first pixel switching element) 24α arranged in the display area AA, a second pixel TFT (second pixel switching element) 24β arranged in the display area AA, a first pixel electrode (first pixel portion) 25α arranged in the display area AA and connected to a pixel drain electrode (drain electrode) 24C of the first pixel TFT 24α, and a second pixel electrode (first pixel portion) 25α arranged in the display area AA and connected to a pixel drain electrode 24C of the second pixel TFT 24β. a first gate wiring (first scanning wiring) 26α disposed in the display region AA, extending along the first direction, and connected to a pixel gate electrode (gate electrode) 24A of the first pixel TFT 24α; a second gate wiring (second scanning wiring) 26β disposed in the display region AA, extending along the first direction, and connected to a pixel gate electrode 24A of the second pixel TFT 24β; a first source wiring (first image wiring) 27α disposed in the display region AA, extending along a second direction intersecting the first direction, and connected to a pixel source electrode (source electrode) 24B of the first pixel TFT 24α; a second source wiring (second image wiring) 27β disposed in the display area AA, extending along the second direction, and connected to the pixel source electrode 24B of the second pixel TFT 24β; a first connection wiring 28α disposed in the display area AA, extending along the second direction, and connected to the first gate wiring 26α; a second connection wiring 28β disposed in the display area AA, extending along the second direction, and connected to the second gate wiring 26β; and a second connection wiring 28β disposed in the non-display area NAA, connected to the first connection wiring 28α and the second connection wiring 28β, and connected to the first pixel TFT 24α and the second pixel TFT 24β, respectively. a gate driver (first signal supply unit) 12 that applies a first potential, which is a potential higher than the threshold voltage of the pixel TFT 24β, at different timings; a source driver (second signal supply unit) 13 that is arranged in the non-display area NAA and connected to the first source wiring 27α and the second source wiring 27β and that supplies image signals to the first source wiring 27α and the second source wiring 27β, respectively; a first non-pixel TFT (first non-pixel switching element) 30α that is arranged in the non-display area NAA and has a non-pixel drain electrode (drain electrode) 30C that is connected to the first gate wiring 26α or the first connection wiring 28α;a second non-pixel TFT (second non-pixel switching element) 30β arranged in the non-display area NAA and having a non-pixel drain electrode 30C connected to the second gate line 26β or the second connection line 28β; a first clock line (first line) 31 arranged in the non-display area NAA and connected to the non-pixel gate electrode (gate electrode) 30A of the first non-pixel TFT 30α; a second clock line (second line) 32 arranged in the non-display area NAA and connected to the non-pixel gate electrode 30A of the second non-pixel TFT 30β; and a low-potential wiring 33 connected to the non-pixel source electrode 30B of the first non-pixel TFT 30α and the second non-pixel TFT 30β and maintained at a second potential lower than the first potential, and a third potential higher than the threshold voltages of the first non-pixel TFT 30α and the second non-pixel TFT 30β is applied to the first clock wiring 31 and the second clock wiring 32 at different timings, the timing at which the third potential is supplied to the first clock wiring 31 being different from the timing at which the first potential is supplied to the first connection wiring 28α, and the timing at which the third potential is supplied to the second clock wiring 32 being different from the timing at which the first potential is supplied to the second connection wiring 28β.

[0055] When the gate driver 12 supplies a first potential to the first connection wiring 28α, the first potential is supplied to the pixel gate electrode 24A of the first pixel TFT 24α via the first gate wiring 26α connected to the first connection wiring 28α, thereby driving the first pixel TFT 24α. At this time, when an image signal supplied to the first source wiring 27α by the source driver 13 is supplied to the pixel source electrode 24B of the first pixel TFT 24α, the first pixel electrode 25α connected to the pixel drain electrode 24C of the first pixel TFT 24α is charged to a potential based on the image signal. When the gate driver 12 supplies the first potential to the second connection wiring 28β at a timing different from that of the first connection wiring 28α, the first potential is supplied to the pixel gate electrode 24A of the second pixel TFT 24β via the second gate wiring 26β connected to the second connection wiring 28β, thereby driving the second pixel TFT 24β. At this time, when the image signal supplied from the source driver 13 to the second source line 27β is supplied to the pixel source electrode 24B of the second pixel TFT 24β, the second pixel electrode 25β connected to the pixel drain electrode 24C of the second pixel TFT 24β is charged to a potential based on the image signal.

[0056] In this way, the first gate wiring 26α and the second gate wiring 26β are connected to the gate driver 12 via the first connection wiring 28α and the second connection wiring 28β, and therefore, compared to the case where the first gate wiring 26α and the second gate wiring 26β are directly connected to the gate driver 12, there is no need to ensure installation space for the gate driver 12 near the end of the non-display area NAA in the first direction. This makes it possible to narrow the end of the non-display area NAA in the first direction, thereby enabling the liquid crystal panel 11 to have a narrower frame.

[0057] The third potential is supplied to the first clock line 31 at a timing different from the timing at which the gate driver 12 supplies the first potential to the first connection line 28α. This drives the first non-pixel TFT 30α, and the second potential supplied from the low-potential line 33 to the non-pixel source electrode 30B is supplied to the first gate line 26α or the first connection line 28α via the non-pixel drain electrode 30C. Thus, at a predetermined timing when the first gate line 26α is deselected and the first pixel TFT 24α is turned off, the first non-pixel TFT 30α supplies the second potential to the first gate line 26α and the first connection line 28α. This reduces the likelihood of potential fluctuations in the first gate line 26α and the first connection line 28α due to parasitic capacitance that may occur between the first connection line 28α and other lines. This reduces the likelihood of charge leakage from the first pixel electrode 25α to the first pixel TFT 24α, reducing the likelihood of display defects.

[0058] The third potential is supplied to the second clock line 32 at a timing different from the timing at which the gate driver 12 supplies the first potential to the second connection line 28β. This drives the second non-pixel TFT 30β, and the second potential supplied from the low-potential line 33 to the non-pixel source electrode 30B is supplied to the second gate line 26β or the second connection line 28β via the non-pixel drain electrode 30C. Thus, at a predetermined timing when the second gate line 26β is deselected and the second pixel TFT 24β is turned off, the second potential is supplied to the second gate line 26β and the second connection line 28β by the second non-pixel TFT 30β. This reduces the likelihood of potential fluctuations in the second gate line 26β and the second connection line 28β due to parasitic capacitance that may occur between the second connection line 28β and other lines. This reduces the likelihood of charge leakage from the second pixel TFT 24β, reducing the likelihood of display defects.

[0059] The first non-pixel TFT 30α includes a first TFT (first switching element) 30α1 having a non-pixel drain electrode 30C connected to the first connection wiring 28α, and a second TFT (second switching element) 30α2 having a non-pixel drain electrode 30C connected to the first gate wiring 26α, and the second non-pixel TFT 30β includes a third TFT (third switching element) 30β1 having a non-pixel drain electrode 30C connected to the second connection wiring 28β, and a fourth TFT (fourth switching element) 30β2 having a non-pixel drain electrode 30C connected to the second gate wiring 26β. When a third potential is supplied to the first clock wiring 31, the first TFT 30α1 and second TFT 30α2, which are the first non-pixel TFT 30α, are driven. As a result, the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the first TFT 30α1 is supplied to the first connection wiring 28α via the non-pixel drain electrode 30C of the first TFT 30α1, and the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the second TFT 30α2 is supplied to the first gate wiring 26α via the non-pixel drain electrode 30C of the second TFT 30α2. In this manner, the second potential is supplied to both the first connection wiring 28α and the first gate wiring 26α, which is advantageous for maintaining stable potentials (second potentials) of the first connection wiring 28α and the first gate wiring 26α. Furthermore, compared to the case where only one of the first TFT 30α1 and the second TFT 30α2 is provided, the first TFT 30α1 and the second TFT 30α2 can each be made smaller. This is advantageous for achieving a narrower frame. On the other hand, when the third potential is supplied to the second clock wiring 32, the third TFT 30β1 and the fourth TFT 30β2, which are the second non-pixel TFT 30β, are driven. Then, the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the third TFT 30β1 is supplied to the second connection wiring 28β via the non-pixel drain electrode 30C of the third TFT 30β1, and the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the fourth TFT 30β2 is supplied to the second gate wiring 26β via the non-pixel drain electrode 30C of the fourth TFT 30β2.In this way, the second potential is supplied to both the second connection wiring 28β and the second gate wiring 26β, which is advantageous in maintaining the potentials (second potentials) of the second connection wiring 28β and the second gate wiring 26β stably. Furthermore, compared to the case where only one of the third TFT 30β1 and the fourth TFT 30β2 is provided, the third TFT 30β1 and the fourth TFT 30β2 can each be made smaller. This is advantageous in achieving a narrower frame.

[0060] The first non-pixel TFT 30α includes a second TFT 30α2 having a non-pixel drain electrode 30C connected to one end of the first gate line 26α, and a fifth TFT (fifth switching element) 30α3 having a non-pixel drain electrode 30C connected to the other end of the first gate line 26α, and the second non-pixel TFT 30β includes a fourth TFT 30β2 having a non-pixel drain electrode 30C connected to one end of the second gate line 26β, and a sixth TFT (sixth switching element) 30β3 having a non-pixel drain electrode 30C connected to the other end of the second gate line 26β. When a third potential is supplied to the first clock line 31, the second TFT 30α2 and fifth TFT 30α3, which are the first non-pixel TFTs 30α, are driven. As a result, the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the second TFT 30α2 is supplied to one end of the first gate wiring 26α via the non-pixel drain electrode 30C of the second TFT 30α2, and the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the fifth TFT 30α3 is supplied to the other end of the first gate wiring 26α via the non-pixel drain electrode 30C of the fifth TFT 30α3. In this manner, the second potential is supplied to both ends of the first gate wiring 26α, which is advantageous for maintaining a stable potential (second potential) of the first gate wiring 26α. Furthermore, compared to the case where only one of the second TFT 30α2 and the fifth TFT 30α3 is provided, the second TFT 30α2 and the fifth TFT 30α3 can each be made smaller. This is advantageous for achieving a narrower frame. On the other hand, when the third potential is supplied to the second clock line 32, the fourth TFT 30β2 and the sixth TFT 30β3, which are the second non-pixel TFT 30β, are driven. Then, the second potential supplied from the low-potential line 33 to the non-pixel source electrode 30B of the fourth TFT 30β2 is supplied to one end of the second gate line 26β via the non-pixel drain electrode 30C of the fourth TFT 30β2, and the second potential supplied from the low-potential line 33 to the non-pixel source electrode 30B of the sixth TFT 30β3 is supplied to the other end of the second gate line 26β via the non-pixel drain electrode 30C of the sixth TFT 30β3.In this way, the second potential is supplied to both ends of the second gate wiring 26β, which is advantageous in maintaining a stable potential (second potential) of the second gate wiring 26β. Furthermore, compared to the case where only one of the fourth TFT 30β2 and the sixth TFT 30β3 is provided, the fourth TFT 30β2 and the sixth TFT 30β3 can each be made smaller. This is advantageous in achieving a narrower frame.

[0061] The first non-pixel TFT 30α includes a first TFT 30α1 having a non-pixel drain electrode 30C connected to the first connection wiring 28α, a second TFT 30α2 having a non-pixel drain electrode 30C connected to one end of the first gate wiring 26α, and a fifth TFT 30α3 having a non-pixel drain electrode 30C connected to the other end of the first gate wiring 26α, and the second non-pixel TFT 30β includes a third TFT 30β1 having a non-pixel drain electrode 30C connected to the second connection wiring 28β, a fourth TFT 30β2 having a non-pixel drain electrode 30C connected to one end of the second gate wiring 26β, and a sixth TFT 30β3 having a non-pixel drain electrode 30C connected to the other end of the second gate wiring 26β. When the third potential is supplied to the first clock wiring 31, the first non-pixel TFT 30α, that is, the first TFT 30α1, the second TFT 30α2, and the fifth TFT 30α3, are driven. Then, the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the first TFT 30α1 is supplied to the first connection wiring 28α via the non-pixel drain electrode 30C of the first TFT 30α1, the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the second TFT 30α2 is supplied to one end of the first gate wiring 26α via the non-pixel drain electrode 30C of the second TFT 30α2, and further the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the fifth TFT 30α3 is supplied to the other end of the first gate wiring 26α via the non-pixel drain electrode 30C of the fifth TFT 30α3. In this way, the second potential is supplied to the first connection wiring 28α and both ends of the first gate wiring 26α, respectively, which is advantageous for maintaining stable potentials (second potentials) of the first connection wiring 28α and the first gate wiring 26α. Furthermore, compared to a case where only the first TFT 30α1, the second TFT 30α2, and the fifth TFT 30α3 are provided, the first TFT 30α1, the second TFT 30α2, and the fifth TFT 30α3 can be made smaller. This is advantageous for achieving a narrower frame. Meanwhile, when the third potential is supplied to the second clock wiring 32, the third TFT 30β1, the fourth TFT 30β2, and the sixth TFT 30β3, which are the second non-pixel TFTs 30β, are driven.As a result, the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the third TFT 30β1 is supplied to the second connection wiring 28β via the non-pixel drain electrode 30C of the third TFT 30β1, the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the fourth TFT 30β2 is supplied to one end of the second gate wiring 26β via the non-pixel drain electrode 30C of the fourth TFT 30β2, and the second potential supplied from the low-potential wiring 33 to the non-pixel source electrode 30B of the sixth TFT 30β3 is supplied to the other end of the second gate wiring 26β via the non-pixel drain electrode 30C of the sixth TFT 30β3. In this way, the second potential is supplied to the second connection wiring 28β and both ends of the second gate wiring 26β, which is advantageous in maintaining the potentials (second potentials) of the second connection wiring 28β and the second gate wiring 26β stable. Furthermore, compared to the case where only one of the third TFT 30β1, the fourth TFT 30β2, and the sixth TFT 30β3 is provided, the third TFT 30β1, the fourth TFT 30β2, and the sixth TFT 30β3 can be made smaller, which is preferable for achieving a narrower frame.

[0062] Furthermore, the third potential and the second potential are periodically applied to the first clock wiring 31, and the third potential and the second potential are periodically applied to the second clock wiring 32. Because the third potential and the second potential are periodically applied to the first clock wiring 31, during a period in which the first gate wiring 26α is not selected and the first pixel TFT 24α is in an off state, the first non-pixel TFT 30α is repeatedly driven and the second potential is repeatedly supplied to the first gate wiring 26α and the first connection wiring 28α. This makes it more difficult for potential fluctuations to occur in the first gate wiring 26α and the first connection wiring 28α, and therefore more difficult for display defects to occur. On the other hand, since the third potential and the second potential are periodically applied to the second clock line 32, during a period in which the second gate line 26β is not selected and the second pixel TFT 24β is in an off state, the second non-pixel TFT 30β is repeatedly driven and the second potential is repeatedly supplied to the second gate line 26β and the second connection line 28β. This makes it more difficult for potential fluctuations to occur in the second gate line 26β and the second connection line 28β, making display defects less likely to occur.

[0063] Furthermore, the first clock wiring 31 and the second clock wiring 32 are arranged at positions farther from the display area AA than the first non-pixel TFT 30α and the second non-pixel TFT 30β. This makes it less likely that the electric field generated by the first clock wiring 31 and the second clock wiring 32 will adversely affect the signals transmitted by the source wirings 27 and the gate wirings 26 arranged in the display area AA or the potential of the pixel electrodes 25.

[0064] Furthermore, the first clock wiring 31 and the second clock wiring 32 are connected to the gate driver 12. In this way, the third potential and the second potential are applied from the gate driver 12 to the first clock wiring 31 and the second clock wiring 32. This eliminates the need to apply the second potential and the third potential from a circuit board or the like via the flexible substrate 14, and also eliminates the need for terminals for connecting the first clock wiring 31 and the second clock wiring 32 to the flexible substrate 14, so there is no need to reduce the width of the terminals for various signals transmitted from the flexible substrate 14.

[0065] <Embodiment 2> A second embodiment will be described with reference to Fig. 5 or 6. In this second embodiment, a case where the configuration of the low potential supply circuit 129 is changed is shown. Note that a duplicated description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0066] 5, the low potential supply circuit 129 according to this embodiment includes a third clock wiring (third wiring) 34 and a third non-pixel TFT (third non-pixel switching element) 130γ connected to the third clock wiring 34. That is, in this embodiment, the non-pixel gate electrode 130A of the non-pixel TFT 130 is connected to any one of the first clock wiring 131, the second clock wiring 132, and the third clock wiring 34. The third non-pixel TFT 130γ is one of the multiple non-pixel TFTs 130 that is not connected to the first clock wiring 131 or the second clock wiring 132, but is connected to the third clock wiring 34.

[0067] Hereinafter, of the multiple gate lines 126, the gate line 126 located next to the second gate line 126β will be referred to as the "third gate line (third scanning line) 126γ." Of the multiple connection lines 128, the connection line 128 connected to the third gate line 126γ will be referred to as the "third connection line 128γ." Of the multiple source lines 127, the source line 127 adjacent to the third connection line 128γ (the source line 127 located fourth from the left end in FIG. 5) will be referred to as the "third source line (third image line) 127γ." Of the multiple pixel TFTs 124, the pixel TFT 124 having a pixel gate electrode 124A connected to the third gate line 126γ and a source electrode 124B connected to the third source line 127γ will be referred to as the "third pixel TFT (third pixel switching element) 124γ." Of the plurality of pixel electrodes 125, the pixel electrode 125 connected to the pixel drain electrode 124C of the third pixel TFT 124γ is referred to as a "third pixel electrode (third pixel portion) 125γ."

[0068] In Figure 5, the scanning signal input to the second gate wiring 126β and the second connection wiring 128β is designated by the symbol "G(i)", the scanning signal input to the first gate wiring 126α and the first connection wiring 128α located above the second gate wiring 126β and the second connection wiring 128β is designated by the symbol "G(i-1)", and the scanning signal input to the gate wiring 126 and the connection wiring 128 located above that is designated by the symbol "G(i-2)". Furthermore, the symbol "G(i+1)" is assigned to the scanning signal input to the gate wiring 126 and connection wiring 128 located below the second gate wiring 126β and the first connection wiring 128α, the symbol "G(i+2)" is assigned to the scanning signal input to the gate wiring 126 and connection wiring 128 located below that, the symbol "G(i+3)" is assigned to the scanning signal input to the gate wiring 126 and connection wiring 128 located below that, and the symbol "G(i+4)" is assigned to the scanning signal input to the gate wiring 126 and connection wiring 128 located below that. Similarly, the symbol "S(j)" is assigned to the image signal input to the second source wiring 127β, and the symbol "S(j-1)" is assigned to the image signal input to the first source wiring 127α located before (to the left of) the second source wiring 127β. Furthermore, the symbol "S(j+1)" is assigned to the image signal input to the source wiring 127 located in the next stage (the next to the right in Figure 5) of the second source wiring 127β, the symbol "S(j+2)" is assigned to the image signal input to the source wiring 127 located in the next stage after that, the symbol "S(j+3)" is assigned to the image signal input to the source wiring 127 located in the next stage after that, and the symbol "S(j+4)" is assigned to the image signal input to the source wiring 127 located in the next stage after that.

[0069] 5, the third non-pixel TFT 130γ has a non-pixel gate electrode 130A connected to the third clock line 34, and a non-pixel drain electrode 130C connected to the third gate line 126γ or the third connection line 128γ. A plurality of third non-pixel TFTs 130γ are provided, and are distributed and arranged along three sides of the non-display area NAA excluding the sides on the drivers 12 and 13 (see FIG. 1).

[0070] As shown in FIG. 5, the plurality of third non-pixel TFTs 130γ include at least a seventh TFT (seventh switching element) 130γ1, an eighth TFT (eighth switching element) 130γ2, and a ninth TFT (ninth switching element) 130γ3. The seventh TFT 130γ1 is disposed on a side of the non-display area NAA opposite to the side of the drivers 12 and 13 (the upper side of FIG. 5). The seventh TFT 130γ1 has a non-pixel drain electrode 130C connected to the third connection wiring 128γ. The non-pixel drain electrode 130C of the seventh TFT 130γ1 is connected to an end of the third connection wiring 128γ opposite to the gate driver 12 side. The eighth TFT 130γ2 is disposed on one of two sides of the non-display area NAA sandwiching the display area AA in the X-axis direction (the left side of FIG. 5). The eighth TFT 130γ2 has a non-pixel drain electrode 130C connected to one end (left side in FIG. 5) of the third gate line 126γ. The ninth TFT 130γ3 is arranged on the other side (right side in FIG. 5) of the two sides of the non-display area NAA that sandwich the display area AA in the X-axis direction. The ninth TFT 130γ3 has a non-pixel drain electrode 130C connected to the other end (right side in FIG. 5) of the third gate line 126γ.

[0071] 5 , the third clock wiring 34 is connected to the gate driver 12 and to the non-pixel gate electrode 130A of the non-pixel TFT 130 (including the third non-pixel TFT 130γ) connected to the gate wiring 126 (including the third gate wiring 126γ) located 3nth (hereinafter, n is an integer equal to or greater than 1) from the top of the plurality of non-pixel TFTs 130 or the connection wiring 128 (including the third connection wiring 128γ) connected to that gate wiring 126. The third clock wiring 34 is arranged across the four sides of the non-display area NAA. Specifically, the third clock wiring 34 has a portion extending along the X-axis direction on a side of the non-display area NAA opposite the side on the drivers 12 and 13 side in the Y-axis direction, two portions extending along the Y-axis direction on two sides sandwiching the display area AA from both sides in the X-axis direction, and a portion routed toward the gate driver 12 on the side on the drivers 12 and 13 side. The third clock wiring 34 is made up of a part of the first metal film or the second metal film.

[0072] In this embodiment, the first clock wiring 131 is connected to the non-pixel gate electrode 130A of the non-pixel TFT 130 (including the first non-pixel TFT 130α) connected to the gate wiring 126 (including the first gate wiring 126α) located at the (3n−2)th position counting from the top among the plurality of non-pixel TFTs 130 or the connection wiring 128 (including the first connection wiring 128α) connected to that gate wiring 126. The second clock wiring 132 is connected to the non-pixel gate electrode 130A of the non-pixel TFT 130 (including the second non-pixel TFT 130β) connected to the gate wiring 126 (including the second gate wiring 126β) located at the (3n−1)th position counting from the top among the plurality of non-pixel TFTs 130 or the connection wiring 128 (including the second connection wiring 128β) connected to that gate wiring 126.

[0073] Next, the operation of the low-potential supply circuit 129 and the gate driver 12 will be described with reference to the timing chart shown in Fig. 6. Fig. 6 shows signal waveforms on the first clock wiring 131, the second clock wiring 132, the third clock wiring 34, the first gate wiring 126α, the second gate wiring 126β, and the third gate wiring 126γ. Specifically, Fig. 6 shows, from top to bottom, a first clock signal GCK1 transmitted by the first clock wiring 131, a second clock signal GCK2 transmitted by the second clock wiring 132, a second clock signal GCK3 transmitted by the third clock wiring 34, a first scanning signal G(i-1) transmitted by the first gate wiring 126α, a second scanning signal G(i) transmitted by the second gate wiring 126β, and a third scanning signal G(i+1) transmitted by the third gate wiring 126γ. The first clock signal GCK1, the second clock signal GCK2, the third clock signal GCK3, the first scanning signal G(i-1), the second scanning signal G(i), and the third scanning signal G(i+1) are all output from the gate driver 12. In other words, it can be said that the operation of the low potential supply circuit 129 is controlled by the gate driver 12.

[0074] As shown in FIG. 6 , the third clock signal GCK3, like the first clock signal GCK1 and the second clock signal GCK2, is a generally rectangular wave, and has a signal waveform that periodically repeats a high potential Vgh and a low potential Vgl as follows: In this embodiment, the first clock signal GCK1, the second clock signal GCK2, and the third clock signal GCK3 each have a cycle in which they are continuously at a high potential Vgh for two unit periods H, and then at a low potential Vgl for one unit period H. The first clock signal GCK1, the second clock signal GCK2, and the third clock signal GCK3 have signal waveforms that are shifted in phase by one unit period H. Specifically, the latter unit period H of the two unit periods H in which the first clock signal GCK1 is at a high potential Vgh is synchronized with the former unit period H of the two unit periods H in which the second clock signal GCK2 is at a high potential Vgh, so that they overlap. The second clock signal GCK2 is synchronized so that the latter unit period H of two unit periods H in which the second clock signal GCK2 is set to the high potential Vgh overlaps with the former unit period H of two unit periods H in which the third clock signal GCK3 is set to the high potential Vgh. The third clock signal GCK3 is synchronized so that the latter unit period H of two unit periods H in which the third clock signal GCK3 is set to the high potential Vgh overlaps with the former unit period H of two unit periods H in which the first clock signal GCK1 of the next cycle is set to the high potential Vgh. As described above, during the unit period H in which the first clock signal GCK1 is set to the low potential Vgl, the second clock signal GCK2 and the third clock signal GCK3 are both at the high potential Vgh. During the unit period H in which the second clock signal GCK2 is set to the low potential Vgl, the first clock signal GCK1 and the third clock signal GCK3 are both at the high potential Vgh. During the unit period H in which the third clock signal GCK3 is at the low potential Vgl, the first clock signal GCK1 and the second clock signal GCK2 are both at the high potential Vgh. In this way, the gate driver 12 applies the high potential Vgh to the first clock wire 131, the second clock wire 132, and the third clock wire 34 at different timings.

[0075] As shown in FIG. 6, the third scanning signal G(i+1), like the first scanning signal G(i-1) and the second scanning signal G(i), has a signal waveform that is at a high potential Vgh only during a predetermined unit period H of one frame display period and at a low potential Vgl during the other unit periods H. In this embodiment, the first scanning signal G(i-1) is synchronized so that the unit period H during which the first scanning signal G(i-1) is at a high potential Vgh coincides with the unit period H during which the second clock signal GCK2 and the third clock signal GCK3 are at a high potential Vgh (the unit period H during which the first clock signal GCK1 is at a low potential Vgl). The second scanning signal G(i) is synchronized so that the unit period H during which the second scanning signal G(i) is at a high potential Vgh coincides with the unit period H during which the first clock signal GCK1 and the third clock signal GCK3 are at a high potential Vgh (the unit period H during which the second clock signal GCK2 is at a low potential Vgl). The third scanning signal G(i+1) is synchronized so that the unit period H during which it is at high potential Vgh coincides with the unit period H during which it is at high potential Vgh in the first clock signal GCK1 and the second clock signal GCK2 (the unit period H during which it is at low potential Vgl in the third clock signal GCK3).

[0076] The specific operations of the low-potential supply circuit 129 and the gate driver 12 will be described. As shown in FIG. 6, the gate driver 12 outputs the high potential Vgh of the first scanning signal G(i-1) to the first connection wiring 128α in synchronization with a predetermined unit period H in which both the second clock signal GCK2 and the third clock signal GCK3 are at the high potential Vgh. This drives the first pixel TFT 124α. The gate driver 12 outputs the high potential Vgh of the second scanning signal G(i) to the second connection wiring 128β at the timing when the first scanning signal G(i-1) switches from the high potential Vgh to the low potential Vgl (the timing when both the first clock signal GCK1 and the third clock signal GCK3 are at the high potential Vgh). This drives the second pixel TFT 124β. The gate driver 12 outputs the high potential Vgh of the third scanning signal G(i+1) to the third connection wiring 128γ at the timing when the second scanning signal G(i) switches from the high potential Vgh to the low potential Vgl (the timing when both the first clock signal GCK1 and the second clock signal GCK2 become the high potential Vgh). This drives the third pixel TFT 124γ. In this way, the gate driver 12 applies the high potential Vgh to the first connection wiring 128α, the second connection wiring 128β, and the third connection wiring 128γ at different timings. When the third pixel TFT 124γ is driven, the image signal supplied from the source driver 13 to the third source wiring 127γ is supplied from the pixel source electrode 124B to the pixel drain electrode 124C via the pixel semiconductor portion 124D. As a result, the third pixel electrode 125γ is charged to a potential based on the image signal.

[0077] 6, during a unit period H in which the first scanning signal G(i-1) is set to a high potential Vgh, the gate driver 12 sets the first clock signal GCK1 to a low potential Vgl and sets the second clock signal GCK2 and the third clock signal GCK3 to a high potential Vgh. During a unit period H in which the second scanning signal G(i) is set to a high potential Vgh, the gate driver 12 sets the first clock signal GCK1 and the third clock signal GCK3 to a high potential Vgh and sets the second clock signal GCK2 to a low potential Vgl. During a unit period H in which the third scanning signal G(i+1) is set to a high potential Vgh, the gate driver 12 sets the third clock signal GCK3 to a low potential Vgl and sets the first clock signal GCK1 and the second clock signal GCK2 to a high potential Vgh. In this way, the gate driver 12 of this embodiment differentiates the timing at which the high potential Vgh is supplied to the first clock wiring 131 (the timing at which the first clock signal GCK1 rises to the high potential Vgh) from the timing at which the high potential Vgh is supplied to the first connection wiring 128α, differentiates the timing at which the high potential Vgh is supplied to the second clock wiring 132 (the timing at which the second clock signal GCK2 rises to the high potential Vgh) from the timing at which the high potential Vgh is supplied to the second connection wiring 128β, and differentiates the timing at which the high potential Vgh is supplied to the third clock wiring 34 (the timing at which the third clock signal GCK3 rises to the high potential Vgh) from the timing at which the high potential Vgh is supplied to the third connection wiring 128γ.

[0078] 6, the timing at which the high potential Vgh is supplied to the first clock line 131 is different from the timing at which the high potential Vgh is supplied to the first connection line 128α, so that the first gate line 126α is not selected and the first pixel TFT 124α is in the off state during the unit period H in which the first non-pixel TFT 130α is driven. In this way, during the unit period H in which the first pixel TFT 124α is in the off state, the low potential Vgl is supplied to the first gate line 126α and the first connection line 128α by the first non-pixel TFT 130α, so that potential fluctuations are less likely to occur in the first gate line 126α and the first connection line 128α due to parasitic capacitance that may occur between the first connection line 128α and other lines (such as the first source line 127α and each gate line 126 other than the first gate line 126α). This makes it difficult for the charge of the first pixel electrode 125α to leak from the first pixel TFT 124α, making it difficult for display defects to occur.

[0079] 6, the timing at which the high potential Vgh is supplied to the second clock line 132 is different from the timing at which the high potential Vgh is supplied to the second connection line 128β, so that the second gate line 126β is not selected and the second pixel TFT 124β is in the off state during the unit period H in which the second non-pixel TFT 130β is driven. In this way, during the unit period H in which the second pixel TFT 124β is in the off state, the low potential Vgl is supplied to the second gate line 126β and the second connection line 128β by the second non-pixel TFT 130β, so that potential fluctuations are less likely to occur in the second gate line 126β and the second connection line 128β due to parasitic capacitance that may occur between the second connection line 128β and other lines (such as the second source line 127β and each gate line 126 other than the second gate line 126β). This makes it difficult for the charge of the second pixel electrode 125β to leak from the second pixel TFT 124β, making it difficult for display defects to occur.

[0080] 6 , the timing at which the high potential Vgh is supplied to the third clock line 34 is different from the timing at which the high potential Vgh is supplied to the third connection line 128γ, so that the third gate line 126γ is deselected and the third pixel TFT 124γ is turned off during the unit period H in which the third non-pixel TFT 130γ is driven. In this way, during the unit period H in which the third pixel TFT 124γ is turned off, the low potential Vgl is supplied to the third gate line 126γ and the second connection line 128γ by the third non-pixel TFT 130γ, so that potential fluctuations are less likely to occur in the third gate line 126γ and the third connection line 128γ due to parasitic capacitance that may occur between the third connection line 128γ and other lines (such as the third source line 127γ and each gate line 126 other than the third gate line 126γ). This makes it difficult for the charge of the third pixel electrode 125γ to leak from the third pixel TFT 124γ, making it difficult for display defects to occur.

[0081] In this embodiment, as shown in FIG. 6 , the gate driver 12 supplies the high potential Vgh to the first clock line 131 both before and after the timing at which the high potential Vgh is supplied to the first connection line 128α. Therefore, during a period in which the first gate line 126α is deselected and the first pixel TFT 124α is in the off state, the first non-pixel TFT 130α is driven and the low potential Vgl is supplied to the first gate line 126α and the first connection line 128α both before and after the timing at which the first pixel TFT 124α is turned on. This makes it more difficult for potential fluctuations to occur in the first gate line 126α and the first connection line 128α, thereby making it more difficult for display defects to occur. The gate driver 12 supplies the high potential Vgh to the second clock line 132 both before and after the timing at which the high potential Vgh is supplied to the second connection line 128β. Therefore, during the period when the second gate line 126β is deselected and the second pixel TFT 124β is in the off state, the second non-pixel TFT 130β is driven and a low potential Vgl is supplied to the second gate line 126β and the second connection line 128β both before and after the timing when the second pixel TFT 124β is turned on. This makes it more difficult for potential fluctuations to occur in the second gate line 126β and the second connection line 128β, making it more difficult for display defects to occur. The gate driver 12 supplies a high potential Vgh to the third clock line 34 both before and after the timing when the high potential Vgh is supplied to the third connection line 128γ. Therefore, during the period when the third gate line 126γ is deselected and the third pixel TFT 124γ is in the off state, the third non-pixel TFT 130γ is driven and the low potential Vgl is supplied to the third gate line 126γ and the third connecting line 128γ both before and after the timing when the third pixel TFT 124γ is turned on. This makes it more difficult for potential fluctuations to occur in the third gate line 126γ and the third connecting line 128γ, making it more difficult for display defects to occur.

[0082] 5, the third non-pixel TFT 130γ includes a seventh TFT 130γ1 having a non-pixel drain electrode 130C connected to the third connecting line 128γ, an eighth TFT 130γ2 having a non-pixel drain electrode 130C connected to one end of the third gate line 126γ, and a ninth TFT 130γ3 having a non-pixel drain electrode 130C connected to the other end of the third gate line 126γ. Therefore, when the gate driver 12 supplies a high potential Vgh to the third clock line 34, the seventh TFT 130γ1, the eighth TFT 130γ2, and the ninth TFT 130γ3, which constitute the third non-pixel TFT 130γ, are driven. Then, the low potential Vgl supplied from the low potential wiring 133 to the non-pixel source electrode 130B of the seventh TFT 130γ1 is supplied to the end of the third connection wiring 128γ opposite the gate driver 12 side via the non-pixel drain electrode 130C and non-pixel semiconductor portion 130D of the seventh TFT 130γ1. The low potential Vgl supplied from the low potential wiring 133 to the non-pixel source electrode 130B of the eighth TFT 130γ2 is supplied to one end of the third gate wiring 126γ via the non-pixel drain electrode 130C and non-pixel semiconductor portion 130D of the eighth TFT 130γ2. The low potential Vgl supplied from the low potential wiring 133 to the non-pixel source electrode 130B of the ninth TFT 130γ3 is supplied to the other end of the third gate wiring 126γ via the non-pixel drain electrode 130C and non-pixel semiconductor portion 130D of the ninth TFT 130γ3. In this way, the low potential Vgl is supplied to the end of the third connection wiring 128γ opposite the gate driver 12 side and to both ends of the third gate wiring 126γ, which is advantageous in maintaining a stable potential (low potential Vgl) of the third connection wiring 128γ and the third gate wiring 126γ. Furthermore, compared to the case where only one of the seventh TFT 130γ1, the eighth TFT 130γ2, and the ninth TFT 130γ3 is provided, the seventh TFT 130γ1, the eighth TFT 130γ2, and the ninth TFT 130γ3 can each be made smaller. This is advantageous in achieving a narrower frame.

[0083] Furthermore, the gate driver 12 outputs the first clock signal GCK1, the second clock signal GCK2, and the third clock signal GCK3 in a cycle in which the gate driver 12 continuously applies a high potential Vgh to the first clock wiring 131, the second clock wiring 132, and the third clock wiring 34 for two unit periods H, and then applies a low potential Vgl for one unit period H. Therefore, during a period in which the first gate wiring 126α is not selected and the first pixel TFT 124α is in an off state, the first non-pixel TFT 130α is repeatedly driven for two unit periods H, and the low potential Vgl is repeatedly supplied to the first gate wiring 126α and the first connection wiring 128α for two unit periods H. Specifically, the low potential Vgl is supplied to the first gate wiring 126α and the first connection wiring 128α for approximately two-thirds of the unit periods H included in one frame display period. Similarly, during a period in which the second gate line 126β is deselected and the second pixel TFT 124β is in an off state, the second non-pixel TFT 130β is repeatedly driven for two unit periods H, and a low potential Vgl is repeatedly supplied to the second gate line 126β and the second connection line 128β for two unit periods H. Specifically, the low potential Vgl is supplied to the second gate line 126β and the second connection line 128β for approximately two-thirds of the unit periods H included in one frame display period. Furthermore, during a period in which the third gate line 126γ is deselected and the third pixel TFT 124γ is in an off state, the third non-pixel TFT 130γ is repeatedly driven for two unit periods H, and a low potential Vgl is repeatedly supplied to the third gate line 126γ and the third connection line 128γ for two unit periods H. Specifically, a low potential Vgl is supplied to the third gate wiring 126γ and the third connection wiring 128γ during approximately two-thirds of the unit period H included in one frame display period. This makes it more difficult for potential fluctuations to occur in each of the first gate wiring 126α, the first connection wiring 128α, the second gate wiring 126β, the second connection wiring 128β, the third gate wiring 126γ, and the third connection wiring 128γ, making it more difficult for display defects to occur.

[0084] As described above, according to this embodiment, there are provided a third pixel TFT (third pixel switching element) 124γ arranged in the display region AA, a third pixel electrode (third pixel portion) 125γ arranged in the display region AA and connected to the pixel drain electrode 124C of the third pixel TFT 124γ, a third gate wiring (third scanning wiring) 126γ arranged in the display region AA, extending along the first direction, and connected to the pixel gate electrode 124A of the third pixel TFT 124γ, and a third gate wiring (third scanning wiring) 126γ arranged in the display region AA, extending along the first direction, and connected to the pixel gate electrode 124A of the third pixel TFT 124γ. a third source wiring (third image wiring) 127γ arranged in the display area AA, extending along the second direction, and connected to the pixel source electrode 124B of the third pixel TFT 124γ; a third connection wiring 128γ arranged in the display area AA, extending along the second direction, and connected to the third gate wiring 126γ; and a third non-pixel TFT (third non-pixel TFT) arranged in the non-display area NAA, having a non-pixel drain electrode 130C connected to the third gate wiring 126γ or the third connection wiring 128γ. and a third clock wiring (third wiring) 34 arranged in the non-display area NAA and connected to the non-pixel gate electrode 130A of the third non-pixel TFT 130γ, wherein a third potential is applied to the third clock wiring 34 at a timing different from that of the first clock wiring 131 and the second clock wiring 132, the timing at which the third potential is supplied to the third clock wiring 34 is different from the timing at which the first potential is supplied to the third connecting wiring 128γ, the third potential is supplied to the first clock wiring 131 both before and after the timing at which the first potential is supplied to the first connecting wiring 128α, the third potential is supplied to the second clock wiring 132 both before and after the timing at which the first potential is supplied to the second connecting wiring 128β, and the third potential is supplied to the third clock wiring 34 both before and after the timing at which the first potential is supplied to the third connecting wiring 128γ. When the gate driver 12 supplies a first potential to the third connection wiring 128γ, the first potential is supplied to the pixel gate electrode 124A of the third pixel TFT 124γ via the third gate wiring 126γ connected to the third connection wiring 128γ, thereby driving the third pixel TFT 124γ.At this time, when an image signal supplied from the source driver 13 to the third source line 127γ is supplied to the non-pixel source electrode 130B of the third pixel TFT 124γ, the third pixel electrode 125γ connected to the non-pixel drain electrode 130C of the third pixel TFT 124γ is charged to a potential based on the image signal. A third potential is supplied to the third clock line 34 at a timing different from the timing at which the gate driver 12 supplies the first potential to the third connecting line 128γ. Then, the third non-pixel TFT 130γ is driven, and the second potential supplied from the low-potential line 133 to the non-pixel source electrode 130B is supplied to the third gate line 126γ or the third connecting line 128γ via the non-pixel drain electrode 130C. In this way, at a predetermined timing when the third gate line 126γ is deselected and the third pixel TFT 124γ is turned off, the third non-pixel TFT 130γ supplies the third gate line 126γ and the third connecting line 128γ with the second potential, which makes it difficult for potential fluctuations to occur in the third gate line 126γ and the third connecting line 128γ due to parasitic capacitance that may occur between the third connecting line 128γ and other lines. This makes it difficult for the charge of the third pixel electrode 125γ to leak from the third pixel TFT 124γ, making it less likely for display defects to occur. Moreover, since the third potential is supplied to the first clock line 131 both before and after the timing when the gate driver 12 supplies the first potential to the first connection line 128α, the first non-pixel TFT 130α is driven and the second potential is supplied to the first gate line 126α and the first connection line 128α both before and after the timing when the first pixel TFT 124α is turned on during the period when the first gate line 126α is deselected and the first pixel TFT 124α is turned off. This makes it more unlikely that potential fluctuations will occur on the first gate line 126α and the first connection line 128α, and therefore makes it more unlikely that display defects will occur.Because the third potential is supplied to the second clock line 132 both before and after the timing at which the gate driver 12 supplies the first potential to the second connection line 128β, the second non-pixel TFT 130β is driven and the second potential is supplied to the second gate line 126β and the second connection line 128β both before and after the timing at which the second pixel TFT 124β is turned on during the period in which the second gate line 126β is deselected and the second pixel TFT 124β is turned off. This makes it more unlikely that potential fluctuations will occur on the second gate line 126β and the second connection line 128β, making display defects less likely to occur. Because the third potential is supplied to the third clock line 34 both before and after the timing at which the gate driver 12 supplies the third connecting line 128γ with the first potential, the third non-pixel TFT 130γ is driven and the second potential is supplied to the third gate line 126γ and the third connecting line 128γ both before and after the timing at which the third pixel TFT 124γ is turned on during the period in which the third gate line 126γ is deselected and the third pixel TFT 124γ is turned off. This makes it more difficult for potential fluctuations to occur on the third gate line 126γ and the third connecting line 128γ, and therefore makes it more difficult for display defects to occur.

[0085] <Embodiment 3> Embodiment 3 will be described with reference to Figures 7 to 9. In this embodiment 3, a gate drive circuit (third signal supply unit) 35 is added to the above-mentioned embodiment 1. Note that redundant explanations of the structure, action, and effects similar to those of the above-mentioned embodiment 1 will be omitted.

[0086] As shown in FIG. 7, a gate drive circuit 35 is monolithically provided in the non-display area NAA of the array substrate 221 according to this embodiment. The gate drive circuit 35 is arranged on a side of the non-display area NAA opposite (upper side in FIG. 7) from the side on which the drivers 12 and 13 (see FIG. 1) are located in the Y-axis direction. The gate drive circuit 35 is arranged in a strip-shaped area extending along the X-axis direction. Each circuit element T1 to T3, C, net (see FIG. 8) constituting the gate drive circuit 35 is formed using each metal film, semiconductor film, and transparent electrode film formed on the array substrate 221. The gate drive circuit 35 is connected to the ends of the multiple connection wirings 228 opposite (the other side) from the gate driver 12 side, and can apply scanning signals to each connection wiring 228 at different timings. The gate drive circuit 35 is connected to the first clock wiring 231, the second clock wiring 232, the low-potential wiring 233, etc., and operates based on the clock signals GCK1, GCK2, etc. supplied from the gate driver 12 to the first clock wiring 231, the second clock wiring 232, etc. As a result, the operation of the gate drive circuit 35 (such as the timing of outputting the scanning signal) is synchronized with the operation of the gate driver 12. In this way, the gate drive circuit 35 can be said to be an auxiliary circuit whose driving is controlled by the gate driver 12.

[0087] In Figure 7, the scanning signal input to the second gate wiring 226β and the second connection wiring 228β is designated by the symbol "G(i)", the scanning signal input to the first gate wiring 226α and the first connection wiring 228α located above the second gate wiring 226β and the second connection wiring 228β is designated by the symbol "G(i-1)", and the scanning signal input to the gate wiring 226 and the connection wiring 228 located above that is designated by the symbol "G(i-2)". Furthermore, the symbol "G(i+1)" is assigned to the scanning signal input to the gate wiring 226 and connection wiring 228 located below the second gate wiring 226β and second connection wiring 228β, the symbol "G(i+2)" is assigned to the scanning signal input to the gate wiring 226 and connection wiring 228 located below that, the symbol "G(i+3)" is assigned to the scanning signal input to the gate wiring 226 and connection wiring 228 located below that, and the symbol "G(i+4)" is assigned to the scanning signal input to the gate wiring 226 and connection wiring 228 located below that. Similarly, the symbol "S(j)" is assigned to the image signal input to the second source wiring 227β, and the symbol "S(j-1)" is assigned to the image signal input to the first source wiring 227α located before (to the left of) the second source wiring 227β. Furthermore, the symbol "S(j+1)" is assigned to the image signal input to the source wiring 227 located in the next stage (the next to the right in Figure 7) of the second source wiring 227β, the symbol "S(j+2)" is assigned to the image signal input to the source wiring 227 located in the next stage after that, the symbol "S(j+3)" is assigned to the image signal input to the source wiring 227 located in the next stage after that, and the symbol "S(j+4)" is assigned to the image signal input to the source wiring 227 located in the next stage after that.

[0088] The gate drive circuit 35 is a so-called shift register circuit. More specifically, as shown in FIG. 7, the gate drive circuit 35 has a plurality of unit gate circuits 35U arranged along its length (the X-axis direction). The unit gate circuits 35U are individually connected to a plurality of connection wirings 228 arranged at intervals in the X-axis direction in the display area AA, and output scanning signals sequentially from the connection wiring 228 located at the left end of FIG. 7 to the connection wiring 228 located at the right end of FIG. 7. Of the plurality of unit gate circuits 35U, one end of a start wiring 36 is connected to the first-stage unit gate circuit 35U that outputs a scanning signal first during one frame display period. The other end of the start wiring 36 is connected to the gate driver 12, and a start signal G(SP) is input from the gate driver 12 at a predetermined timing. Of the plurality of unit gate circuits 35U, one end of an end wiring 37 is connected to the last-stage unit gate circuit 35U that outputs a scanning signal last during one frame display period. The other end of the end wiring 37 is connected to the gate driver 12, and receives a termination signal G(LT) at a predetermined timing from the gate driver 12. The plurality of unit gate circuits 35U include a first unit gate circuit 35Uα connected to the first connection wiring 228α and outputting a scanning signal to the first connection wiring 228α, and a second unit gate circuit 35Uβ connected to the second connection wiring 228β and outputting a scanning signal to the second connection wiring 228β.

[0089] As shown in FIG. 8, the unit gate circuit section 35U includes three transistors (switching elements) T1 to T3 and one capacitor C. In the following, the wiring connecting the transistors T1 to T3 and the capacitor C is referred to as the internal node net. The first transistor T1 has a gate electrode connected to the connection wiring 228 of the previous stage, a source electrode connected to the first clock wiring 231 or the second clock wiring 232, and a drain electrode connected to the internal node net. This "connection wiring 228 of the previous stage" refers to the connection wiring 228 to which the unit gate circuit section 35U located in the previous stage (the adjacent left side in FIG. 8) of the unit gate circuit section 35U to which the first transistor T1 belongs outputs a scan signal. The second transistor T2 has a gate electrode connected to the internal node net, a source electrode connected to the first clock wiring 231 or the second clock wiring 232, and a drain electrode connected to the connection wiring 228 to which the scan signal is output. The "connection wiring 228 of the output target" refers to the connection wiring 228 of the target to which the unit gate circuit 35U to which the first transistor T1 belongs outputs a scanning signal. The source electrode of the second transistor T2 is connected to clock wirings 231 and 232 that are separate from the source electrode of the first transistor T1. The third transistor T3 has a gate electrode connected to the connection wiring 228 of the next stage, a source electrode connected to a low-potential wiring 233, and a drain electrode connected to the internal node net. The capacitor C has one electrode connected to the internal node net, and the other electrode connected to the drain electrode of the second transistor T2 and the connection wiring 228 of the output target.

[0090] In FIG. 8, in order to distinguish between the circuit elements T1 to T3,C,net that make up each unit gate circuit section 35U, the symbol "(i)" is added to each of the circuit elements T1 to T3,C,net that make up the second unit gate circuit section 35Uβ, and the symbol "(i-1)" is added to each of the circuit elements T1 to T3,C,net that make up the first unit gate circuit section 35Uα that is located in the preceding stage of the second unit gate circuit section 35Uβ. Furthermore, the symbol "(i+1)" is added to each of the circuit elements T1 to T3,C,net constituting the unit gate circuit section 35U located in the next stage after the second unit gate circuit section 35Uβ, the symbol "(i+2)" is added to each of the circuit elements T1 to T3,C,net constituting the unit gate circuit section 35U located in the next stage after that, the symbol "(i+3)" is added to each of the circuit elements T1 to T3,C,net constituting the unit gate circuit section 35U located in the next stage after that, and the symbol "(i+4)" is added to each of the circuit elements T1 to T3,C,net constituting the unit gate circuit section 35U located in the next stage after that.

[0091] The first transistor T1(i-1) included in the first unit gate circuit section 35Uα has a gate electrode connected to the preceding connection wiring 228 and a source electrode connected to the first clock wiring 231. The second transistor T2(i-1) included in the first unit gate circuit section 35Uα has a gate electrode connected to the internal node net(i-1), a source electrode connected to the second clock wiring 232, and a drain electrode connected to the first connection wiring 228α to be output. The third transistor T3(i-1) included in the first unit gate circuit section 35Uα has a gate electrode connected to the next-stage second connection wiring 228β. One electrode of the capacitor C(i-1) included in the first unit gate circuit section 35Uα is connected to the drain electrode of the first transistor T1(i-1), and the other electrode is connected to the first connection wiring 228α to be output. The first transistor T1(i) included in the second unit gate circuit section 35Uβ has a gate electrode connected to the first connection wiring 228α of the previous stage and a source electrode connected to the second clock wiring 232. The second transistor T2(i) included in the second unit gate circuit section 35Uβ has a gate electrode connected to the internal node net(i), a source electrode connected to the first clock wiring 231, and a drain electrode connected to the second connection wiring 228β of the output target. The third transistor T3(i) included in the second unit gate circuit section 35Uβ has a gate electrode connected to the connection wiring 228 of the next stage. The other electrode of the capacitor C(i) included in the second unit gate circuit section 35Uβ is connected to the drain electrode of the second transistor T2(i) and the second connection wiring 228β of the output target.

[0092] The first transistor T1 provided in the first-stage unit gate circuit section 35U has a gate electrode connected to the start wiring 36. The third transistor T3 provided in the final-stage unit gate circuit section 35U has a gate electrode connected to the end wiring 37.

[0093] Next, the operation of the gate drive circuit 35 will be described with reference to the timing chart shown in Fig. 9. Fig. 9 shows signal waveforms on the first clock wiring 231, the second clock wiring 232, the internal node net(i-1), the first gate wiring 226α, the internal node net(i), and the second gate wiring 226β. Fig. 9 also shows a scale for each unit period (one horizontal period) H. 9 shows, from top to bottom, a first clock signal GCK1 transmitted by the first clock wiring 231, a second clock signal GCK2 transmitted by the second clock wiring 232, the potential of an internal node net(i-1) in the first unit gate circuit unit 35Uα, a first scanning signal G(i-1) transmitted by the first gate wiring 226α, the potential of an internal node net(i) in the second unit gate circuit unit 35Uβ, and a second scanning signal G(i) transmitted by the second gate wiring 226β. The first clock signal GCK1, the second clock signal GCK2, the first scanning signal G(i-1), and the second scanning signal G(i) are all output from the gate driver 12. In other words, it can be said that the operation of the gate drive circuit 35 is controlled by the gate driver 12. The signal waveforms of the first clock signal GCK1, the second clock signal GCK2, the first scanning signal G(i-1), and the second scanning signal G(i) are the same as those in the first embodiment described above.

[0094] Specific operations of the gate drive circuit 35 will be described, particularly focusing on the first unit gate circuit section 35Uα and the second unit gate circuit section 35Uβ. As shown in FIG. 9, at time t1, when a scanning signal G(i-2) is input to the preceding connection wiring 228, the first transistor T1(i-1) provided in the first unit gate circuit section 35Uα is driven by applying a high potential Vgh to its gate electrode. At this timing, the first clock signal GCK1 is at a high potential Vgh, so that a high potential Vgh is applied from the source electrode to the drain electrode of the first transistor T1(i-1). This causes the potential of the internal node net(i-1) to become a high potential Vgh, charging the capacitor C(i-1) and driving the second transistor T2(i-1).

[0095] Next, at time t2, the first clock signal GCK1 goes to the low potential Vgl. However, in the first unit gate circuit section 35Uα, the high potential Vgh of the internal node net(i-1) is maintained by the capacitor C(i-1), and the second clock signal GCK2 goes to the high potential Vgh, so that the high potential Vgh is applied from the source electrode of the second transistor T2(i-1) to the other electrode of the capacitor C(i-1). This further charges the capacitor C(i-1), causing the potential of the internal node net(i-1) to rise above the high potential Vgh. In other words, the potential of the internal node net(i-1) is pushed up (bootstrapped). As a result, the gate electrode of the second transistor T2(i-1) goes to a higher potential, so that the high potential Vgh supplied to the source electrode from the second clock signal GCK2 can be supplied as the scanning signal G(i-1) to the first connection wiring 228α via the drain electrode without delay. Furthermore, at time t2, the first transistor(i) included in the second unit gate circuit section 35Uβ is driven in response to input of the scanning signal G(i-1) to the first connection wiring 228α of the preceding stage. At this timing, the second clock signal GCK2 is at the high potential Vgh, so the high potential Vgh is applied from the source electrode to the drain electrode of the first transistor(i). As a result, the potential of the internal node net(i) becomes the high potential Vgh, the capacitor C(i) is charged, and the second transistor T2(i) is driven.

[0096] At time t3, the second clock signal GCK2 goes to the low potential Vgl. However, in the second unit gate circuit section 35Uβ, the high potential Vgh of the internal node net(i) is maintained by the capacitor C(i). Furthermore, the first clock signal GCK1 goes to the high potential Vgh, so that the high potential Vgh is applied from the source electrode of the second transistor T2(i) to the other electrode of the capacitor C(i). This further charges the capacitor C(i), causing the potential of the internal node net(i) to rise above the high potential Vgh. In other words, the potential of the internal node net(i) is pushed up (bootstrapped). This causes the gate electrode of the second transistor T2(i) to go to a higher potential, so that the high potential Vgh supplied to the source electrode from the second clock signal GCK2 can be supplied as the scanning signal G(i) to the second connection wiring 228β via the drain electrode without delay.

[0097] At time t3, when the second clock signal GCK2 becomes low potential Vgl, the low potential Vgl is supplied to the first connection wiring 228α via the source electrode and drain electrode of the second transistor T2(i-1) provided in the first unit gate circuit section 35Uα. Then, at time t3, when the scanning signal G(i) is supplied to the second connection wiring 228β, the high potential Vgh is applied to the gate electrode of the third transistor T3(i-1) provided in the first unit gate circuit section 35Uα, driving the third transistor T3(i-1). Then, the low potential Vgl supplied to the source electrode of the third transistor T3(i-1) from the low potential wiring 233 is supplied to the internal node net(i-1) via the drain electrode. As the internal node net(i-1) becomes the low potential Vgl, the capacitor C(i-1) in the first unit gate circuit section 35Uα is discharged and the second transistor T2(i-1) is turned off.

[0098] At time t4, the unit gate circuit 35U in the next stage of the second unit gate circuit unit 35Uβ supplies a scanning signal G(i+1) to the connection wiring 228 in the next stage of the second connection wiring 228β. At this time, the first clock signal GCK1 becomes low potential Vgl, so that the low potential Vgl is supplied to the second connection wiring 228β via the source and drain electrodes of the second transistor T2(i) in the second unit gate circuit unit 35Uβ. Then, at time t4, when the scanning signal G(i+1) is supplied to the connection wiring 228 in the next stage of the second connection wiring 228β, a high potential Vgh is applied to the gate electrode of the third transistor T3(i) in the second unit gate circuit unit 35Uβ, driving the third transistor T3(i). Then, the low potential Vgl supplied to the source electrode of the third transistor T3(i) from the low potential wiring 233 is supplied to the internal node net(i) via the drain electrode. As the internal node net(i) becomes the low potential Vgl, the capacitor C(i) provided in the first unit gate circuit section 35Uα is discharged and the second transistor T2(i) is turned off. In this way, scanning signals are output from the multiple unit gate circuit sections 35U in sequence from the upper stage.

[0099] As described above, according to this embodiment, a scanning signal is supplied from the gate driver 12 to one end of the connection wiring 228 in synchronization with the timing at which the gate driver 12 supplies the scanning signal to the other end of the connection wiring 228. Among the multiple gate wirings 226, the gate wirings 226 located on the upper side of the display area AA are farther from the gate driver 12 than the gate wirings 226 located on the lower side of the display area AA. Meanwhile, the gate wirings 226 located on the upper side of the display area AA are closer to the gate driver 12 than the gate wirings 226 located on the lower side of the display area AA. The connection wirings 228 connected to the gate wirings 226 located farther from the gate driver 12 are supplied with scanning signals from the gate driver circuit 35 located on the opposite side of the gate driver 12 in the Y-axis direction. This reduces the likelihood of dullness in the scanning signals supplied to the gate wirings 226. This increases the reliability of driving the pixel TFTs 224, reducing the likelihood of display defects.

[0100] As described above, according to this embodiment, the device includes a gate drive circuit (third signal supply unit) 35 that is arranged in the non-display area NAA, is connected to the first connection wiring 228α and the second connection wiring 228β, and applies a first potential to the first connection wiring 228α and the second connection wiring 228β at different timings, the gate driver 12 is connected to one end of the first connection wiring 228α and the second connection wiring 228β, and the gate drive circuit 35 is connected to the other end of the first connection wiring 228α and the second connection wiring 228β, and the timing of supplying the first potential to the first connection wiring 228α is synchronized with the timing of supplying the first potential from the gate driver 12 to the first connection wiring 228α, and the timing of supplying the first potential to the second connection wiring 228β is synchronized with the timing of supplying the first potential from the gate driver 12 to the second connection wiring 228β. The gate drive circuit 35 supplies the first potential to the other end of the first connection wiring 228α in synchronization with the timing at which the gate driver 12 supplies the first potential to one end of the first connection wiring 228α. Therefore, even if the connection point between the first gate wiring 226α and the first connection wiring 228α is located far from the gate driver 12, for example, the first potential is supplied to the first connection wiring 228α from the gate drive circuit 35, which is located on the opposite side of the gate driver 12 in the second direction, so that the first potential supplied to the first gate wiring 226α is less likely to become dull. This increases the reliability with which the first pixel TFT 224α is driven, making display defects less likely to occur. The gate drive circuit 35 supplies the first potential to the other end of the second connection wiring 228β in synchronization with the timing at which the gate driver 12 supplies the first potential to one end of the second connection wiring 228β. Therefore, for example, even if the connection point between the second gate wiring 226β and the second connection wiring 228β is located far from the gate driver 12, the first potential supplied to the second gate wiring 226β is less likely to become dull by supplying the first potential to the second connection wiring 228β from the gate drive circuit 35 located on the opposite side of the gate driver 12 in the second direction. This increases the reliability with which the second pixel TFT 224β is driven, making display defects less likely to occur.

[0101] <Embodiment 4> A fourth embodiment will be described with reference to Figs. 10 to 12. In this fourth embodiment, the number of gate drivers 312 installed is reduced from that of the first embodiment, and a switch circuit 38 is added. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0102] As shown in FIG. 10, one gate driver 312 is mounted in the non-display area NAA of the array substrate 321 according to this embodiment. That is, in this embodiment, the number of gate drivers 312 is reduced by one from that of the first embodiment. To reduce the number of gate drivers 312, a switch circuit 38 is monolithically provided in the non-display area NAA of the array substrate 321 according to this embodiment, as shown in FIG. 11. The switch circuit 38 is arranged on a side of the non-display area NAA on the side of the drivers 312 and 313 in the Y-axis direction (the lower side in FIG. 11) (see FIG. 1). The switch circuit 38 is disposed between the display area AA and the drivers 312 and 313 in the Y-axis direction. The switch circuit 38 is arranged in a strip-shaped range extending along the X-axis direction. The circuit elements 39 to 41 constituting the switch circuit 38 are configured using metal films, semiconductor films, and transparent electrode films formed on the array substrate 321. The switch circuit 38 is connected to one end of the plurality of connection wirings 328 on the gate driver 312 side, and is also connected to the gate driver 312. The switch circuit 38 has a function of distributing and supplying scan signals output from the gate driver 312 to the plurality of connection wirings 328. The switch circuit 38 is connected to a first clock wiring 331 and a second clock wiring 332, and operates based on clock signals GCK1 and GCK2 supplied from the gate driver 312 to the first clock wiring 331 and the second clock wiring 332. As a result, the operation of the switch circuit 38 (such as the timing at which the scan signals are distributed to the plurality of connection wirings 328) is synchronized with the operation of the gate driver 312. In other words, the drive of the switch circuit 38 is controlled by the gate driver 312.

[0103] In this embodiment, of the multiple gate wirings 326, the third gate wiring 326 counting from the top is referred to as the "first gate wiring 326α." Furthermore, of the multiple gate wirings 326, the second gate wiring 326 counting from the top is referred to as the "second gate wiring 326β." That is, in this embodiment, the second gate wiring 326β is located on the upper side relative to the first gate wiring 326α. Accordingly, the second connection wiring 328β is disposed adjacent to the first connection wiring 328α on the left side (previous side) in FIG. 11. Similarly, the second source wiring 327β is disposed adjacent to the first source wiring 327α on the left side (previous side) in FIG. 11.

[0104] 11, the scanning signal input to the second gate wiring 326β and the second connection wiring 328β is designated by the symbol "G(i)", the scanning signal input to the first gate wiring 326α and the first connection wiring 328α located below the second gate wiring 326β and the second connection wiring 328β is designated by the symbol "G(i+1)", and the scanning signal input to the gate wiring 326 and the connection wiring 328 located below that is designated by the symbol "G(i+2)". Furthermore, the scanning signal input to the gate wiring 326 and the connection wiring 328 located above the second gate wiring 326β and the second connection wiring 328β is designated by the symbol "G(i-1)". Similarly, the symbol "S(j)" is assigned to the image signal input to the second source wiring 327β, the symbol "S(j+1)" is assigned to the image signal input to the first source wiring 327α located in the next stage (adjacent to the right in FIG. 11) of the second source wiring 327β, the symbol "S(j+2)" is assigned to the image signal input to the source wiring 327 located in the next stage after that, the symbol "S(j+3)" is assigned to the image signal input to the source wiring 327 located in the next stage after that, and the symbol "S(j+4)" is assigned to the image signal input to the source wiring 327 located in the next stage after that. Furthermore, the symbol "S(j-1)" is assigned to the image signal input to the source wiring 327 located in the previous stage (adjacent to the left in FIG. 11) of the second source wiring 327β, and the symbol "S(j-2)" is assigned to the image signal input to the source wiring 327 located in the previous stage.

[0105] As shown in FIG. 11 , the switch circuit 38 has a plurality of unit switch circuits 38U arranged along its length (X-axis direction), two clock connection wires 39 and 40, and a plurality of connection trunk wires (fourth wires) 41. The unit switch circuit 38U is connected to two adjacent connection wires 328 spaced apart in the X-axis direction in the display area AA. The number of unit switch circuits 38U is half the number of connection wires 328. The first clock connection wire 39 extends along the X-axis direction, crosses the switch circuit 38 along its length, and both ends are connected to the first clock wire 331. The first clock connection wire 39 is connected to all of the unit switch circuits 38U. The second clock connection wire 40 extends along the X-axis direction, crosses the switch circuit 38 along its length, and both ends are connected to the second clock wire 332. The second clock connection wire 40 is connected to all of the unit switch circuits 38U. The connection trunk wiring 41 extends along the Y-axis direction, with one end connected to the gate driver 312 and the other end connected to the unit switch circuit 38U. The multiple connection trunk wirings 41 are arranged side by side at intervals in the X-axis direction. The number of connection trunk wirings 41 installed matches the number of unit switch circuits 38U installed, and is half the number of connection wirings 328 installed.

[0106] As shown in FIG. 11 , the unit switch circuit 38U has two switch TFTs 42. The switch TFT 42 has a switch gate electrode (gate electrode) 42A connected to the first clock connection wiring 39 or the second clock connection wiring 40, a switch source electrode (source electrode) 42B connected to the connection trunk wiring 41, a switch drain electrode (drain electrode) 42C connected to the connection wiring 328, and a switch semiconductor portion (semiconductor portion) 42D made of a semiconductor material and connected to the switch source electrode 42B and the switch drain electrode 42C. The switch gate electrode 42A, like the non-pixel gate electrode 330A, is made of a part of a first metal film. The switch source electrode 42B and the switch drain electrode 42C, like the non-pixel source electrode 330B and the non-pixel drain electrode 330C, are each made of a part of a second metal film. The switch semiconductor portion 42D, like the non-pixel semiconductor portion 330D, is made of a part of a semiconductor film. The threshold voltage of the switch TFT 42 is set to be the same as that of the non-pixel TFT 330, and a potential higher than this threshold voltage is set to a third potential (high potential Vgh). Note that, since a voltage drop equivalent to the threshold voltage of the switch TFT 42 may occur in the potential supplied to the connection wiring 328, the third potential is preferably set to be at least higher than the first potential, and more preferably the third potential is higher than a potential obtained by adding the threshold voltage of the switch TFT 42 to the first potential.

[0107] 11, the plurality of unit switch circuits 38U include a first unit switch circuit 38Uα connected to a first connection wiring 328α and a second connection wiring 328β. Specifically, the first unit switch circuit 38Uα includes two switch TFTs 42: a first switch TFT (fourth non-pixel switching element) 42α and a second switch TFT (fifth non-pixel switching element) 42β. The first switch TFT 42α has a switch gate electrode 42A connected to the second clock connection wiring 40, and a switch drain electrode 42C connected to the first connection wiring 328α. The second switch TFT 42β has a switch gate electrode 42A connected to the first clock connection wiring 39, and a switch drain electrode 42C connected to the second connection wiring 328β. The plurality of connection trunk lines 41 also include a first connection trunk line 41α connected to each switch source electrode 42B of the first switch TFT 42α and the second switch TFT 42β that constitute the first unit switch circuit section 38Uα.

[0108] Next, the operation of the switch circuit 38 and the gate driver 312 will be described with reference to the timing chart shown in Fig. 12. Fig. 12 shows signal waveforms on the first clock wiring 331 (first clock connection wiring 39), the second clock wiring 332 (second clock connection wiring 40), and the gate wiring 326 (including the first gate wiring 326α and the second gate wiring 326β). Specifically, FIG. 12 shows, from top to bottom, a first clock signal GCK1 transmitted by the first clock wiring 331 (first clock connection wiring 39), a second clock signal GCK2 transmitted by the second clock wiring 332 (second clock connection wiring 40), a scanning signal G(i-2, i-1) transmitted by the connection trunk wiring 41 located above the first connection trunk wiring 41α, a scanning signal G(i-2) transmitted by the gate wiring 326 located two levels above the second gate wiring 326β, a scanning signal G(i-1) transmitted to the gate wiring 326 located above the second gate wiring 326β, a scanning signal G(i, i+1) transmitted by the first connection trunk wiring 41α, a second scanning signal G(i) transmitted by the second gate wiring 326β, and a first scanning signal G(i+1) transmitted by the first gate wiring 326α. The scanning signals G(i-2, i-1) and G(i, i+1) transmitted by the respective connection trunk lines 41 are output from the gate driver 312, similar to the first clock signal GCK1 and the second clock signal GCK2. The switch circuit 38 operates based on the first clock signal GCK1 and the second clock signal GCK2. In other words, it can be said that the operation of the switch circuit 38 is controlled by the gate driver 312.

[0109] In this embodiment, as shown in FIG. 12 , each of the scanning signals G(i-2, i-1) and G(i, i+1) transmitted by each connection trunk line 41 is continuously set to the first potential (high potential Vgh) over two unit periods H. The scanning signals G(i-2, i-1) in the preceding stage are synchronized so that the timing at which the scanning signal G(i-2, i-1) falls and the timing at which the scanning signal G(i, i+1) in the succeeding stage rises coincide with each other. The unit period H in which the first clock signal GCK1 is set to the high potential Vgh is synchronized with the first half of the two unit periods H in which the scanning signals G(i-2, i-1) and G(i, i+1) transmitted by each connection trunk line 41 are set to the high potential Vgh. The second clock signal GCK2 is synchronized so as to overlap with the latter of two unit periods H during which the second clock signal GCK2 is at a high potential Vgh, during which the scanning signals G(i-2, i-1) and G(i, i+1) transmitted by each connection main wiring 41 are at a high potential Vgh. The signal waveforms of the first clock signal GCK1 and the second clock signal GCK2 and the signal waveforms of the scanning signals G(i-2), G(i-1), G(i), and G(i+1) transmitted by each gate wiring 326 are all as described in the first embodiment above.

[0110] A description will now be given of specific operations of the switch circuit 38 and the gate driver 312. The gate driver 312 outputs scanning signals G(i-2, i-1) and G(i, i+1) to the connection main wiring 41 in synchronization with a unit period H during which the first clock signal GCK1 is at a high potential Vgh and a subsequent unit period H during which the second clock signal GCK2 is at a high potential Vgh, as shown in Fig. 12 .

[0111] Here, a specific description will be given of the scanning signal G(i,i+1) output from the gate driver 312 to the first connection trunk line 41α. As shown in Fig. 12, the scanning signal G(i,i+1) is output from the gate driver 312 to the first connection trunk line 41α over two unit periods H, during which the first clock signal GCK1 is at high potential Vgh in the first half unit period H (between time t1 and time t2), and the second clock signal GCK2 is at high potential Vgh in the second half unit period H (between time t2 and time t3). When the first clock signal GCK1 is at high potential Vgh at time t1, in the switch circuit 38, the high potential Vgh is supplied from the first clock connection line 39 to the switch gate electrode 42A of the second switch TFT 42β included in the first unit switch circuit section 38Uα. Then, the second switch TFT 42β is driven, and the high potential Vgh of the scanning signal G(i, i+1) is supplied from its switch source electrode 42B to its switch drain electrode 42C. As a result, the high potential Vgh is supplied to the second connection wiring 328β connected to the switch drain electrode 42C of the second switch TFT 42β, and the high potential Vgh is supplied to the second gate wiring 326β.

[0112] At time t2, when the second clock signal GCK2 becomes high potential Vgh, in the switch circuit 38, the high potential Vgh is supplied from the second clock connection wiring 40 to the switch gate electrode 42A of the first switch TFT 42α included in the first unit switch circuit section 38Uα. This drives the first switch TFT 42α, and the high potential Vgh of the scanning signal G(i, i+1) is supplied from its switch source electrode 42B to its switch drain electrode 42C. As a result, the high potential Vgh is supplied to the first connection wiring 328α connected to the switch drain electrode 42C of the first switch TFT 42α, and the high potential Vgh is supplied to the first gate wiring 326α.

[0113] As described above, according to this embodiment, the number of wirings (connection trunk wirings 41) existing between the gate driver 12 and the switch circuit 38 can be reduced to half compared to the case where each connection wiring 28 is directly connected to the gate driver 12 as in the above-described first embodiment (see FIG. 4). As a result, even if the frame of the liquid crystal panel 11 continues to become narrower, the routing of the connection trunk wirings 41 can be facilitated and the number of gate drivers 312 installed can be reduced.

[0114] As described above, according to this embodiment, the first switch TFT (fourth non-pixel switching element) 42α is arranged in the non-display area NAA, and has a switch drain electrode (drain electrode) 42C connected to the first connection wiring 328α and a switch gate electrode (gate electrode) 42A connected to the second clock wiring 332; and the second switch TFT (fifth non-pixel switching element) 42α is arranged in the non-display area NAA, and has a switch drain electrode 42C connected to the second connection wiring 328β and a switch gate electrode 42A connected to the first clock wiring 331. The first switch TFT 42α includes a first switch TFT (element) 42β, a gate driver 312, a switch source electrode (source electrode) 42B of the first switch TFT 42α, and a connection trunk line (fourth line) 41 connected to the switch source electrode 42B of the second switch TFT 42β. The timing at which the third potential is supplied to the second clock line 332 is synchronized with the timing at which the first potential is supplied to the connection trunk line 41, and the timing at which the third potential is supplied to the first clock line 331 is synchronized with the timing at which the first potential is supplied to the connection trunk line 41. When the gate driver 312 supplies the second clock line 332 with the third potential, the first switch TFT 42α is driven. When the gate driver 312 supplies the first potential to the connection trunk line 41 in synchronization with this timing, the first potential is supplied to the first connection line 328α connected to the switch drain electrode 42C of the first switch TFT 42α. When the gate driver 312 supplies a third potential to the first clock line 331, the second switch TFT 42β is driven. When the gate driver 312 supplies a first potential to the connection trunk line 41 in synchronization with this timing, the first potential is supplied to the second connection line 328β connected to the switch drain electrode 42C of the second switch TFT 42β. In this way, the first potential is supplied from the gate driver 312 to the first connection line 328α and the second connection line 328β via the first switch TFT 42α, the second switch TFT 42β, and the connection trunk line 41, so that the number of lines directly connected to the gate driver 312 can be reduced.

[0115] <Embodiment 5> Embodiment 5 will be described with reference to Fig. 13. In this embodiment 5, the arrangement of the gate wiring 426 and the source wiring 427 is changed from that of the above-mentioned embodiment 1. Note that redundant explanations of the structure, action, and effect similar to those of the above-mentioned embodiment 1 will be omitted.

[0116] In the array substrate 421 according to this embodiment, as shown in FIG. 13 , two gate lines 426 are arranged between adjacent pixel electrodes 425 in the Y-axis direction. Therefore, the number of gate lines 426 is approximately twice the number of pixel electrodes 425 arranged in the Y-axis direction. On the other hand, the source lines 427 are arranged side by side in the X-axis direction, spaced apart so as to sandwich two pixel electrodes 425 therebetween. In other words, a source line 427 is arranged every other space between adjacent pixel electrodes 425 in the X-axis direction. Therefore, the number of source lines 427 is approximately half the number of pixel electrodes 425 arranged in the X-axis direction. The connection lines 428 are arranged at intervals in the X-axis direction relative to the source lines 427. Furthermore, one connection line 428 is arranged on each side of the source line 427. Therefore, like the source lines 427, the connection lines 428 are arranged side by side at intervals in the X-axis direction, sandwiching two pixel electrodes 425 between them. In other words, a connection line 428 is arranged every other space between adjacent pixel electrodes 425 in the X-axis direction. The number of connection lines 428 installed is approximately twice the number of source lines 427 installed, and roughly matches the number of pixel electrodes 425 arranged in the X-axis direction.

[0117] 13, the pixel TFTs 424 include those (including the first pixel TFT 424α) that are connected to one of two gate wirings 426 (e.g., the lower side shown in FIG. 13) that are aligned consecutively between adjacent pixel electrodes 425 in the Y-axis direction and the adjacent pixel electrode 425, and those (including the second pixel TFT 424β) that are connected to the other of the two gate wirings 426 (e.g., the upper side shown in FIG. 13) and the adjacent pixel electrode 425. The former of the two types of pixel TFTs 424 is connected to the even-numbered pixel electrode 425 counting from the end (e.g., the left end shown in FIG. 13) in the X-axis direction. The latter of the two types of pixel TFTs 424 is connected to the odd-numbered pixel electrode 425 counting from the end in the X-axis direction.

[0118] As shown in FIG. 13 , each pixel TFT 424 connected to each pixel electrode 425 forming two columns sandwiching a source wiring 427 (connection wiring 428) in the X-axis direction is connected to a source wiring 427 sandwiched between the pixel electrodes 425 forming two columns. That is, an image signal transmitted by a common source wiring 427 is supplied to each pixel electrode 425 forming two columns adjacent to each other with the source wiring 427 in the X-axis direction sandwiched between the two source wirings 427 via each pixel TFT 424. Furthermore, each pixel TFT 424 connected to each pixel electrode 425 forming two columns sandwiched between the two source wirings 427 in the X-axis direction is connected to a different source wiring 427. That is, an image signal transmitted by a different source wiring 427 is supplied to each pixel electrode 425 forming two columns sandwiched between the source wirings 427 in the X-axis direction via each pixel TFT 424.

[0119] 13, the pixel TFTs 424 connected to a common source wiring 427 are each connected to one of two gate wirings 426 that sandwich a pixel electrode 425 in the Y-axis direction, and are repeatedly arranged in a zigzag (staggered) pattern so as to be diagonally opposite each other with the source wiring 427 in between. Therefore, an image signal supplied to the common source wiring 427 is supplied to each of the pixel electrodes 425 that form two columns and sandwich the source wiring 427 in the X-axis direction via each pixel TFT 424 connected to a different gate wiring 426. Then, scanning signals are supplied at different times to the two gate wirings 426 that sandwich, in the Y-axis direction, the pixel electrodes 425 that form a row aligned along the X-axis direction, so that the pixel electrodes 425 in a row can be charged to different potentials. Specifically, of the multiple pixel electrodes 425 arranged along the X-axis direction to form one row, the even-numbered and odd-numbered electrodes counting from the end in the X-axis direction are charged at different timings. The gate driver 12 (see FIG. 1) supplies scanning signals to each gate line 426 sequentially from the top row via each connection line 428, and each scanning period (period during which the first potential is supplied) is approximately half that of the first embodiment. The source driver 13 (see FIG. 1) alternately supplies, to each source line 427, an image signal to be supplied to the pixel TFT 424 located on one side (the left side in FIG. 13) of the source line 427, and an image signal to be supplied to the pixel TFT 424 located on the other side (the right side in FIG. 13) of the source line 427. According to this configuration, the number of source wirings 427 installed is reduced compared to the above-mentioned embodiment 1, making it easier to route the source wirings 427 in the non-display area NAA all the way to the source driver 13, and as a result, the frame of the liquid crystal panel 11 can be made narrower.

[0120] 13, the non-pixel TFTs 430 constituting the low potential supply circuit 429 are arranged in accordance with the number of gate wirings 426 and connection wirings 428. More specifically, the non-pixel TFTs 430 arranged on both sides of the non-display area NAA sandwiching the display area AA in the X-axis direction have non-pixel drain electrodes 430C connected to ends of the gate wirings 426, and the number of non-pixel TFTs 430 arranged thereon is twice that of the first embodiment. On the other hand, the non-pixel TFTs 430 arranged on the sides of the non-display area NAA on the opposite side (upper side in FIG. 13) from the drivers 12 and 13 side (see FIG. 1) with respect to the display area AA in the Y-axis direction also have non-pixel drain electrodes 430C connected to ends of the connection wirings 428, and the number of non-pixel TFTs arranged thereon is approximately twice that of the first embodiment.

[0121] In this embodiment, of the multiple gate wirings 426, the third gate wiring 426 counting from the top is referred to as the "first gate wiring 426α." Furthermore, of the multiple gate wirings 426, the second gate wiring 426 counting from the top is referred to as the "second gate wiring 426β." That is, in this embodiment, the second gate wiring 426β is located on the upper side relative to the first gate wiring 426α. Accordingly, the second connection wiring 428β is arranged adjacent to the first connection wiring 428α on the left side (previous side) in FIG. 13. Similarly, the second source wiring 427β is arranged adjacent to the first source wiring 427α on the left side (previous side) in FIG. 13. The second pixel TFT 424β connected to the second gate wiring 426β and the second source wiring 427β and the first pixel TFT 424α connected to the first gate wiring 426α and the first source wiring 427α are disposed diagonally opposite each other in a plan view. Similarly, the second pixel electrode 425β connected to the second pixel TFT 424β and the first pixel electrode 425α connected to the first pixel TFT 424α are disposed diagonally opposite each other in a plan view. The first gate wiring 426α and the second gate wiring 426β are disposed between the first pixel electrode 425α and the second pixel electrode 425β in the Y-axis direction. The first source wiring 427α and the first connection wiring 428α are disposed on the opposite side of the first pixel electrode 425α from the second pixel electrode 425β in the X-axis direction. The second source wiring 427β and the second connection wiring 428β are arranged on the opposite side of the second pixel electrode 425β from the first pixel electrode 425α in the X-axis direction.

[0122] In FIG. 13, the scanning signal input to the second gate wiring 426β and the second connection wiring 428β is designated by the symbol "G(i-2)", the scanning signal input to the first gate wiring 426α and the first connection wiring 428α located below the second gate wiring 426β and the second connection wiring 428β is designated by the symbol "G(i-1)", the scanning signal input to the gate wiring 426 and the connection wiring 428 located below that is designated by the symbol "G(i)", and the scanning signal input to the gate wiring 426 and the connection wiring 428 located below that is designated by the symbol "G(i)". The scanning signal input to the gate wiring 426 and connection wiring 428 located below that is designated by the symbol "G(i+1)", the scanning signal input to the gate wiring 426 and connection wiring 428 located below that is designated by the symbol "G(i+2)", the scanning signal input to the gate wiring 426 and connection wiring 428 located below that is designated by the symbol "G(i+3)", and the scanning signal input to the gate wiring 426 and connection wiring 428 located below that is designated by the symbol "G(i+4)". Furthermore, the scanning signal input to the gate wiring 426 and connection wiring 428 located above the second gate wiring 426β and second connection wiring 428β is designated by the symbol "G(i-3)". Similarly, the symbol "S(j)" is assigned to the image signal input to the first source wiring 427α, and the symbol "S(j-1)" is assigned to the image signal input to the second source wiring 427β located in the previous stage (adjacent to the left in FIG. 13) of the first source wiring 427α. The symbol "S(j+1)" is assigned to the image signal input to the source wiring 427 located in the next stage (adjacent to the right in FIG. 13) of the first source wiring 427α, and the symbol "S(j+2)" is assigned to the image signal input to the source wiring 427 located in the next stage after that.

[0123] 13, a low potential branch wiring (fifth wiring) 43 connected to a low potential wiring 433 is provided in the display area AA of the array substrate 421 according to this embodiment. Specifically, the low potential branch wiring 43 extends along the Y-axis direction in the display area AA, crossing the entire length of the display area AA, and an end portion on the opposite side to the drivers 12 and 13 (the upper side in FIG. 13) is drawn out to the non-display area NAA and connected to a portion of the low potential wiring 433 extending along the X-axis direction. Note that an end portion of the low potential branch wiring 43 on the driver 12 and 13 side may be connected to the gate driver 12. The low potential branch wiring 43 has the same potential as the low potential wiring 433 to which it is connected, and is maintained at a low potential Vgl.

[0124] 13 , in the display area AA, a plurality of low-potential branch wirings 43 are arranged at positions sandwiching pixel electrodes 425 between the source wirings 427 (connection wirings 428) in the X-axis direction. More specifically, two columns of pixel electrodes 425 are arranged between two source wirings 427 spaced apart in the X-axis direction, and each low-potential branch wiring 43 is arranged between one of the two columns of pixel electrodes 425 and the other column of pixel electrodes 425 in the X-axis direction. Therefore, the plurality of low-potential branch wirings 43 includes a low-potential branch wiring 43 sandwiched between a first pixel electrode 425α and a second pixel electrode 425β in the X-axis direction. In this way, the low-potential branch wiring 43 sandwiches the pixel electrode 425 between itself and the source wirings 427 in the X-axis direction, and is arranged to be sandwiched between the two pixel electrodes 425 sandwiched between the two source wirings 427. That is, the low potential branch wirings 43 are arranged by utilizing the space between the two pixel electrodes 425 sandwiched between the two source wirings 427. The number of low potential branch wirings 43 installed is approximately the same as the number of source wirings 427 (connection wirings 428) installed.

[0125] In this embodiment, a "double gate structure" is adopted in which the number of gate lines 426 is doubled compared to the first embodiment, and the number of source lines 427 is reduced to half that of the first embodiment. By reducing the number of source lines 427, space is secured for arranging the low-potential branch lines 43 between pixel electrodes 425 adjacent to each other in the X-axis direction. By connecting the ends of the low-potential branch lines 43 to the low-potential lines 433 in the non-display area NAA, the low potential Vgl in the low-potential lines 433 can be stabilized. This allows the low-potential lines 433 to be made thinner, thereby enabling the frame of the liquid crystal panel 11 to be made narrower.

[0126] As described above, according to this embodiment, the first gate wiring 426α and the second gate wiring 426β are arranged sandwiched between the first pixel electrode 425α and the second pixel electrode 425β in the second direction, the first source wiring 427α and the first connection wiring 428α are arranged on the opposite side of the first pixel electrode 425α from the second pixel electrode 425β in the first direction, and the second source wiring 427β and the second connection wiring 428β are arranged on the opposite side of the second pixel electrode 425β from the first pixel electrode 425α in the first direction. By arranging the first gate wiring 426α and the second gate wiring 426β so as to be sandwiched between the first pixel electrode 425α and the second pixel electrode 425β in the second direction, and by arranging the first pixel electrode 425α and the second pixel electrode 425β so as to be sandwiched between the first source wiring 427α and the first connection wiring 428α and the second source wiring 427β and the second connection wiring 428β in the first direction, it is possible to ensure space for arranging the low potential branch wiring 43 between the first pixel electrode 425α and the second pixel electrode 425β in the first direction. Furthermore, since the number of source wirings 427 to be installed is reduced, it becomes easier to route the source wirings 427 up to the source driver 13 in the non-display area NAA, and as a result, it is possible to narrow the frame of the liquid crystal panel 11.

[0127] Furthermore, in the display area AA, a low-potential branch wiring (fifth wiring) 43 is provided, which is sandwiched between the first pixel electrode 425α and the second pixel electrode 425β in the first direction, and an end of the low-potential branch wiring 43 is arranged in the non-display area NAA and connected to the low-potential wiring 433. By connecting the end of the low-potential branch wiring 43 to the low-potential wiring 433 in the non-display area NAA, it is possible to stabilize the second potential in the low-potential wiring 433. This allows the low-potential wiring 433 to be made thinner, thereby enabling the frame of the liquid crystal panel 11 to be narrower.

[0128] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0129] (1) The non-pixel TFTs 30, 130, 330, and 430 may have their non-pixel drain electrodes 30C, 130C, 330C, and 430C connected only to the connecting wiring 28, 128, 228, 328, and 428. That is, the first non-pixel TFTs 30α and 130α may include only the first TFT 30α1 and not the second TFT 30α2 and the fifth TFT 30α3. Similarly, the second non-pixel TFTs 30β and 130β may include only the third TFT 30β1 and not the fourth TFT 30β2 and the sixth TFT 30β3. With this configuration, the non-pixel TFTs 30, 130, 330, and 430 are not disposed on both sides of the non-display area NAA that sandwich the display area AA in the X-axis direction. This allows the widths of these sides to be narrowed, which is advantageous for achieving a narrower frame.

[0130] (2) The non-pixel TFTs 30, 130, 330, and 430 may have their non-pixel drain electrodes 30C, 130C, 330C, and 430C connected only to the gate lines 26, 126, 226, 326, and 426. That is, the first non-pixel TFTs 30α and 130α may include the second TFT 30α2 and the fifth TFT 30α3, but may not include the first TFT 30α1. Similarly, the second non-pixel TFTs 30β and 130β may include the fourth TFT 30β2 and the sixth TFT 30β3, but may not include the third TFT 30β1.

[0131] (3) In the above (2), the non-pixel TFTs 30, 130, 330, and 430 may have the non-pixel drain electrodes 30C, 130C, 330C, and 430C connected to only one end of the gate wiring 26, 126, 226, 326, and 426. That is, the first non-pixel TFTs 30α and 130α may include either the second TFT 30α2 or the fifth TFT 30α3. Similarly, the second non-pixel TFTs 30β and 130β may include either the fourth TFT 30β2 or the sixth TFT 30β3.

[0132] (4) The non-pixel TFTs 30, 130, 330, 430 may include a non-pixel drain electrode 30C, 130C, 330C, 430C connected to the connecting wiring 28, 128, 228, 328, 428, and a non-pixel drain electrode 30C, 130C, 330C, 430C connected to one end of the gate wiring 26, 126, 226, 326, 426. That is, the first non-pixel TFT 30α, 130α may include a first TFT 30α1 and either a second TFT 30α2 or a fifth TFT 30α3. Similarly, the second non-pixel TFT 30β, 130β may include a third TFT 30β1 and either a fourth TFT 30β2 or a sixth TFT 30β3.

[0133] (5) In addition to the configuration described in the second embodiment, the number of clock wirings 31, 131, 231, 331, 32, 132, 232, 332 may be four or more. In this way, the period during which the low potential Vgl is supplied to each of the gate wirings 26, 126, 226, 326, 426 and each of the connection wirings 28, 128, 228, 328, 428 becomes longer. Specifically, when the number of clock wirings 31, 131, 231, 331, 32, 132, 232, 332 installed is "m (m is an integer greater than or equal to 2)", "(m-1) / m" of the unit periods H included in one frame display period is the period during which a low potential Vgl is supplied to each gate wiring 26, 126, 226, 326, 426 and each connection wiring 28, 128, 228, 328, 428. Therefore, the more clock wirings 31, 131, 231, 331, 32, 132, 232, 332 installed, the longer the period during which a low potential Vgl is supplied to each gate wiring 26, 126, 226, 326, 426 and each connection wiring 28, 128, 228, 328, 428 tends to be. If the period during which the low potential Vgl is supplied to each of the gate wirings 26, 126, 226, 326, 426 and each of the connection wirings 28, 128, 228, 328, 428 is longer, potential fluctuations in each of the gate wirings 26, 126, 226, 326, 426 and each of the connection wirings 28, 128, 228, 328, 428 are less likely to occur, making display defects less likely to occur.

[0134] (6) It is also possible to combine the configuration described in the second embodiment with the configurations described in the third to fifth embodiments.

[0135] (7) The specific circuit configuration of the gate drive circuit 35 described in the third embodiment can be modified as appropriate in addition to the above.

[0136] (8) It is also possible to combine the configuration described in the third embodiment with the configuration described in the fourth or fifth embodiment.

[0137] (9) It is also possible to combine the configuration described in the fifth embodiment with the configuration described in the fourth embodiment.

[0138] (10) The number of connection wirings 28, 128, 228, 328, 428 may be greater than the number of gate wirings 26, 126, 226, 326, 426. For example, the number of connection wirings 28, 128, 228, 328, 428 may be multiple times the number of gate wirings 26, 126, 226, 326, 426, and multiple connection wirings 28, 128, 228, 328, 428 may be connected to one gate wiring 26, 126, 226, 326, 426. Furthermore, the number of connection wirings 28, 128, 228, 328, 428 connected to one gate wiring 26, 126, 226, 326, 426 may differ for each gate wiring 26, 126, 226, 326, 426.

[0139] (11) The number of connecting wires 28, 128, 228, 328, and 428 may be less than the number of source wires 27, 127, 227, 327, and 427. In this case, instead of the connecting wires 28, 128, 228, 328, and 428, dummy wires may be arranged at intervals from the source wires 27, 127, 227, 327, and 427.

[0140] (12) The second clock wirings 32, 132, 232, and 332 may be arranged farther from the display area AA than the first clock wirings 31, 131, 231, and 331.

[0141] (13) In the configuration described in the second embodiment, the third clock wiring 34 may be arranged farther from the display area AA than the second clock wiring 132. Also, the third clock wiring 34 may be arranged farther from the display area AA than the first clock wiring 131.

[0142] (14) Each of the clock wirings 31, 131, 231, 331, 32, 132, 232, 332 and the low-potential wirings 33, 133, 233, 333, 433 may be made of different metal films depending on the portion arranged in the non-display area NAA. For example, when a portion of the low-potential wirings 33, 133, 233, 333, 433 extending along the X-axis direction intersects with the connection wirings 28, 128, 228, 328, 428, the portion may be made of a first metal film, and the portion that does not intersect with the connection wirings 28, 128, 228, 328, 428 (the portion extending along the Y-axis direction) may be made of a second metal film.

[0143] (15) A third metal film may be provided above the second metal film via an insulating film on the array substrate 21, 221, 321, 421. In this case, the connection wiring 28, 128, 228, 328, 428 may be made of the third metal film and may be arranged to overlap the source wiring 27, 127, 227, 327, 427.

[0144] (16) The number and arrangement of the gate drivers 12, 312 and source drivers 13, 313 can be changed as appropriate to other than those shown in the drawings.

[0145] (17) The material of the semiconductor film provided on the array substrate 21, 221, 321, 421 may be any of amorphous silicon material, oxide semiconductor material, polycrystalline polysilicon material, etc. When polycrystalline polysilicon material is used as the material of the semiconductor film, the semiconductor film may be provided below the first metal film.

[0146] (18) Each of the TFTs 24, 124, 224, 424, 30, 130, 330, 430, 42, and T1 to T3 may be a bottom gate type, a top gate type, or a double gate type.

[0147] (19) The gate drivers 12 and 312 may be provided monolithically on the array substrate 21, 221, 321, and 421.

[0148] (20) The drivers 12, 312, 13, and 313 may be mounted on the flexible substrate 14 by COF (Chip On Film), which is mounted on the array substrates 21, 221, 321, and 421 by FOG (Film On Glass).

[0149] (21) The planar shape of the liquid crystal panel 11 may be a vertically long rectangle, a square, a circle, a semicircle, an oval, an ellipse, a trapezoid, or the like.

[0150] (22) The liquid crystal panel 11 may be a reflective or semi-transmissive type in addition to a transmissive type.

[0151] (23) The display mode of the liquid crystal panel 11 may be MVA (Multi-domain Vertical Alignment) mode, IPS (In-Plane Switching) mode, TN (Twisted Nematic) mode, or the like.

[0152] (24) The display device may be other than the liquid crystal panel 11 (such as an organic EL (Electro Luminescence) display panel) or an EPD (microcapsule electrophoretic display panel). [Explanation of symbols]

[0153] 11... liquid crystal panel (display device), 12, 312... gate driver (first signal supply unit), 13, 313... source driver (second signal supply unit), 24A, 124A... pixel gate electrode (gate electrode), 24B, 124B... pixel source electrode (source electrode), 24C, 124C... pixel drain electrode (drain electrode), 24α, 124α, 224α, 424α... first pixel TFT (first pixel switching element), 24β, 124β, 224β, 424β... second pixel TFT (second pixel switching element) , 25α, 125α, 425α... first pixel electrode (first pixel section), 25β, 125β, 425β... second pixel electrode (second pixel section), 26α, 126α, 226α, 326α, 426α... first gate wiring (first scanning wiring), 26β, 126β, 226β, 326β, 426β... second gate wiring (second scanning wiring), 27α, 127α, 227α, 327α, 427α... first source wiring (first image wiring), 27β, 127β, 227β, 327β, 427β... second source wiring (second image wiring), 2 8α, 128α, 228α, 328α, 428α...first connecting wiring, 28β, 128β, 228β, 328β, 428β...second connecting wiring, 30A, 130A, 330A...non-pixel gate electrode (gate electrode), 30B, 130B, 330B...non-pixel source electrode (source electrode), 30C, 130C, 330C, 430C...non-pixel drain electrode (drain electrode), 30α, 130α...first non-pixel TFT (first non-pixel switching element), 30α1...first TFT (first switching element), 30α2 ...second TFT (second switching element), 30α3...fifth TFT (fifth switching element), 30β, 130β...second non-pixel TFT (second non-pixel switching element), 30β1...third TFT (third switching element), 30β2...fourth TFT (fourth switching element), 30β3...sixth TFT (sixth switching element), 31, 131, 231, 331...first clock wiring (first wiring), 32, 132, 232, 332...second clock wiring (second wiring), 33, 133, 233, 333,433...low potential wiring, 34...third clock wiring (third wiring), 35...gate drive circuit (third signal supply unit), 41...connection trunk wiring (fourth wiring), 42α...first switch TFT (fourth non-pixel switching element), 42β...second switch TFT (fifth non-pixel switching element), 42A...switch gate electrode (gate electrode), 42B...switch source electrode (source electrode), 42C...switch drain electrode (drain electrode), 43...low potential branch wiring (fifth wiring), 124γ...third pixel TFT (third pixel switching element), 125γ...third pixel electrode (third pixel unit), 126γ...third gate wiring (third scanning wiring), 127γ...third source wiring (third image wiring), 128γ...third connection wiring, 130γ...third non-pixel TFT (third non-pixel switching element), AA...display area, NAA...non-display area

Claims

1. a display area in which an image is displayed; a non-display area in which the image is not displayed; a first pixel switching element disposed in the display area; a second pixel switching element disposed in the display area; a first pixel unit arranged in the display region and connected to a drain electrode of the first pixel switching element; a second pixel unit arranged in the display region and connected to a drain electrode of the second pixel switching element; a first scanning line disposed in the display region, extending along a first direction, and connected to a gate electrode of the first pixel switching element; a second scanning line disposed in the display region, extending along the first direction, and connected to a gate electrode of the second pixel switching element; a first image wiring arranged in the display region, extending along a second direction intersecting the first direction, and connected to a source electrode of the first pixel switching element; a second image wiring that is arranged in the display region, extends along the second direction, and is connected to a source electrode of the second pixel switching element; a first connection wiring that is arranged in the display region, extends along the second direction, and is connected to the first scanning wiring; second connection wiring arranged in the display region, extending along the second direction, and connected to the second scanning wiring; a first signal supply unit that is arranged in the non-display area, is connected to the first connection wiring and the second connection wiring, and applies a first potential, which is a potential higher than a threshold voltage of the first pixel switching element and the second pixel switching element, to the first connection wiring and the second connection wiring at different timings; a second signal supply unit disposed in the non-display area, connected to the first image wiring and the second image wiring, and supplying image signals to the first image wiring and the second image wiring, respectively; a first non-pixel switching element disposed in the non-display area and having a drain electrode connected to the first scanning line or the first connecting line; a second non-pixel switching element disposed in the non-display area and having a drain electrode connected to the second scanning line or the second connecting line; a first wiring arranged in the non-display area and connected to a gate electrode of the first non-pixel switching element; a second wiring arranged in the non-display area and connected to a gate electrode of the second non-pixel switching element; a low-potential wiring that is arranged in the non-display area, connected to a source electrode of the first non-pixel switching element and a source electrode of the second non-pixel switching element, and maintained at a second potential that is lower than the threshold voltage; a third potential higher than threshold voltages of the first non-pixel switching element and the second non-pixel switching element is applied to the first wiring and the second wiring at different timings, A display device in which the timing at which the third potential is supplied to the first wiring is different from the timing at which the first potential is supplied to the first connection wiring, and the timing at which the third potential is supplied to the second wiring is different from the timing at which the first potential is supplied to the second connection wiring.

2. the first non-pixel switching elements include a first switching element having a drain electrode connected to the first connection line and a second switching element having a drain electrode connected to the first scanning line; 2. The display device according to claim 1, wherein the second non-pixel switching elements include a third switching element having a drain electrode connected to the second connection wiring, and a fourth switching element having a drain electrode connected to the second scanning wiring.

3. the first non-pixel switching elements include a second switching element having a drain electrode connected to one end of the first scanning line, and a fifth switching element having a drain electrode connected to the other end of the first scanning line; 2. The display device according to claim 1, wherein the second non-pixel switching elements include a fourth switching element having a drain electrode connected to one end of the second scanning line, and a sixth switching element having a drain electrode connected to the other end of the second scanning line.

4. the first non-pixel switching elements include a first switching element having a drain electrode connected to the first connection wiring, a second switching element having a drain electrode connected to one end of the first scanning wiring, and a fifth switching element having a drain electrode connected to the other end of the first scanning wiring; 2. The display device according to claim 1, wherein the second non-pixel switching elements include a third switching element having a drain electrode connected to the second connection wiring, a fourth switching element having a drain electrode connected to one end of the second scanning wiring, and a sixth switching element having a drain electrode connected to the other end of the second scanning wiring.

5. 5. The display device according to claim 1, wherein the third potential and the second potential are periodically applied to the first wiring, and the third potential and the second potential are periodically applied to the second wiring.

6. a third pixel switching element disposed in the display area; a third pixel unit arranged in the display region and connected to a drain electrode of the third pixel switching element; a third scanning line disposed in the display region, extending along the first direction, and connected to a gate electrode of the third pixel switching element; a third image wiring that is arranged in the display region, extends along the second direction, and is connected to a source electrode of the third pixel switching element; a third connection wiring that is arranged in the display region, extends along the second direction, and is connected to the third scanning wiring; a third non-pixel switching element disposed in the non-display area and having a drain electrode connected to the third scanning line or the third connecting line; a third wiring that is arranged in the non-display area and connected to a gate electrode of the third non-pixel switching element; the third potential is applied to the third wiring at a timing different from that of the first wiring and the second wiring; a timing at which the third potential is supplied to the third wiring is different from a timing at which the first potential is supplied to the third connection wiring; 6. A display device as described in claim 5, wherein the third potential is supplied to the first wiring at both timings before and after the timing when the first potential is supplied to the first connection wiring, the third potential is supplied to the second wiring at both timings before and after the timing when the first potential is supplied to the second connection wiring, and the third potential is supplied to the third wiring at both timings before and after the timing when the first potential is supplied to the third connection wiring.

7. a third signal supply unit that is arranged in the non-display area, is connected to the first connection wiring and the second connection wiring, and applies the first potential to the first connection wiring and the second connection wiring at different timings; the first signal supply unit is connected to one end of the first connection wiring and one end of the second connection wiring; 5. A display device according to claim 1, wherein the third signal supply unit is connected to the other end of the first connection wiring and the second connection wiring, and the timing of supplying the first potential to the first connection wiring is synchronized with the timing of supplying the first potential from the first signal supply unit to the first connection wiring, and the timing of supplying the first potential to the second connection wiring is synchronized with the timing of supplying the first potential from the first signal supply unit to the second connection wiring.

8. a fourth non-pixel switching element disposed in the non-display area, the fourth non-pixel switching element having a drain electrode connected to the first connection wiring and a gate electrode connected to the second wiring; a fifth non-pixel switching element disposed in the non-display area, the fifth non-pixel switching element having a drain electrode connected to the second connection wiring and a gate electrode connected to the first wiring; a fourth wiring connected to the first signal supply unit, the source electrode of the fourth non-pixel switching element, and the source electrode of the fifth non-pixel switching element; 5. The display device according to claim 1, wherein the timing at which the third potential is supplied to the second wiring is synchronized with the timing at which the first potential is supplied to the fourth wiring, and the timing at which the third potential is supplied to the first wiring is synchronized with the timing at which the first potential is supplied to the fourth wiring.

9. the first scanning wiring and the second scanning wiring are disposed between the first pixel unit and the second pixel unit in the second direction, the first image wiring and the first connection wiring are arranged on the opposite side of the first pixel unit to the second pixel unit in the first direction; 5 . The display device according to claim 1 , wherein the second image wiring and the second connection wiring are arranged on a side of the second pixel unit opposite to the first pixel unit side in the first direction.

10. a fifth wiring disposed in the display region and sandwiched between the first pixel unit and the second pixel unit in the first direction; The display device according to claim 9 , wherein the fifth wiring has an end disposed in the non-display area and connected to the low-potential wiring.

11. 5. The display device according to claim 1, wherein the first wiring and the second wiring are arranged at positions farther from the display region than the first non-pixel switching elements and the second non-pixel switching elements.

12. The display device according to claim 1 , wherein the first wiring and the second wiring are connected to the first signal supply unit.

Images