Integrated circuit package

Abstract

To provide an integrated circuit package that improves a margin of a data-effective window for a data signal transmitted or received between chips.SOLUTION: An integrated circuit package according to the present invention includes: a first semiconductor chip that outputs a first clock signal and a first data signal on a board; a delay circuit that delays at least one of the first clock signal and the first data signal to output a second clock signal and a second data signal based on the first clock signal and the first data signal; and a second semiconductor chip that receives the second clock signal and the second data signal horizontally away from the first semiconductor chip on the board.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to integrated circuit packages. [Background technology]

[0002] As electronic products are required to be smaller, more multifunctional, and more powerful, there is also a demand for lighter, thinner, more integrated, more powerful, and faster packages, which increases the demand for integrated circuit packages that can realize systems with high data bandwidth, and thus increases the data input / output speed within the package.

[0003] As data input / output speeds increase, the data valid window margin decreases, and coupling noise increases due to increased data pattern density, resulting in a decrease in signal integrity of data signals, which must be improved. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned conventional problems, and an object of the present invention is to provide an integrated circuit package that improves the margin of the data valid window for data signals transmitted and received between chips. [Means for solving the problem]

[0005] In order to achieve the above object, an integrated circuit package according to one aspect of the present invention includes a substrate, a first semiconductor chip on the substrate that outputs a first clock signal and a first data signal, a delay circuit that delays at least one of the first clock signal and the first data signal and outputs a second clock signal and a second data signal based on the first clock signal and the first data signal, and a second semiconductor chip that is horizontally spaced from the first semiconductor chip on the substrate and receives the second clock signal and the second data signal.

[0006] According to one embodiment, an integrated circuit package includes a first semiconductor chip that outputs a first clock signal and a first data signal; an active interposer connected to the first semiconductor chip and including a delay circuit that delays at least one of the first clock signal and the first data signal to output a second clock signal and a second data signal; and a second semiconductor chip that is horizontally spaced apart from the first semiconductor chip on the active interposer and receives the second clock signal and the second data signal.

[0007] According to one embodiment, a method for operating an integrated circuit package includes the steps of: receiving an input / output tuning command from a first semiconductor chip mounted on a substrate; receiving a first clock signal and a first data signal from the first semiconductor chip in response to receiving the input / output tuning command; performing an input / output tuning operation to delay at least one of the first clock signal and the first data signal and outputting a second clock signal and a second data signal; checking a data valid interval for the second data signal based on the second clock signal and the second data signal; setting a delay setting value for the input / output tuning operation in response to a result of the checking step; and outputting the second clock signal and the second data signal based on the delay setting value. [Effects of the Invention]

[0008] The integrated circuit package of the present invention can improve the data valid window margin for data signals transmitted and received between chips, and can also improve the skew between clock signals and data signals transmitted and received synchronously between chips, thereby reducing data errors that occur during data transmission. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram illustrating an integrated circuit package according to one embodiment. [Figure 2] FIG. 1 is a block diagram illustrating an example of an integrated circuit package according to one embodiment. [Figure 3] FIG. 1 is a circuit diagram illustrating a delay circuit according to an embodiment. [Figure 4] 1 is a diagram illustrating an example of an integrated circuit package according to an embodiment. [Figure 5] 1 is a flowchart illustrating an example method of operating an integrated circuit package according to one embodiment. [Figure 6] 1 is a timing diagram illustrating an input / output tuning operation of an integrated circuit package according to an embodiment. [Figure 7] 1 is a timing diagram illustrating an input / output tuning operation of an integrated circuit package according to an embodiment. [Figure 8] FIG. 1 is a block diagram illustrating another example of an integrated circuit package according to one embodiment. [Figure 9] 10 is a flowchart illustrating another example of a method of operating an integrated circuit package according to one embodiment. [Figure 10] 10A and 10B are diagrams illustrating another example of an integrated circuit package according to an embodiment. [Figure 11] 10A and 10B are diagrams illustrating yet another example of an integrated circuit package according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0011] The present invention can be embodied in various different forms and is not limited to the embodiments described herein. In order to clearly describe the present invention, parts that are not relevant to the description will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0012] Also, throughout the specification, when a part is said to "comprise" a certain element, this means that it can further include other elements, rather than excluding other elements, unless otherwise specified.

[0013] Furthermore, even if a specific numerical value recited in a claim is expressly recited within the claim, it should not be understood that the specific numerical limitation does not exist in the claim where such recitation is absent. For example, for ease of understanding, the phrases "at least one" and "one or more" may be included in subsequent dependent claims. However, the use of such syntax should not be understood as a limitation described, for example, by the indefinite article "one."

[0014] Furthermore, when a convention such as "at least one of A, B, or C" is used, such syntax will be well understood by those skilled in the art. (i.e., "a system including at least one of A, B, or C" includes, but is not limited to, A alone, B alone, C alone, A and B, A and C, B and C, and / or combinations of A, B, and C.) Alternatively, in the detailed description, claims, or drawings, text and / or syntax having two or more separate alternative terms should be considered to potentially include either one or both terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A," or "B," or "A and B."

[0015] As used herein, terms such as "module," "unit," and "section" are used to refer to components that perform at least one function or operation, and these components may be implemented in hardware or software, or a combination of hardware and software.

[0016] FIG. 1 is a block diagram illustrating an integrated circuit package according to one embodiment.

[0017] 1, an integrated circuit package 1a includes a host device 10, a memory device 20, and an input / output tuning circuit 30c. In this embodiment, the integrated circuit package 1a is a memory system. The host device 10 and the memory device 20 are connected via physical layers (PHY1, PHY2) and the input / output tuning circuit 30c, and data signals (DQ1, DQ2) are transmitted synchronously with clock signals (CLK1, CLK2).

[0018] The host device 10 provides a command (CMD), an address (ADDR), and a power signal (PWR) to the memory device 20 via the physical layers (PHY1, PHY2). In this embodiment, the host device 10 receives a response signal (Rsp) to the command (CMD) from the memory device 20 via the data line (DL) through which data signals (DQ1, DQ2) are transmitted and received. In this embodiment, the host device 10 provides an input / output tuning command (IT_CMD) to the memory device 20 and the input / output tuning circuit 30c.

[0019] According to this embodiment, the host device 10 outputs an I / O tuning command (IT_CMD) at the time of boot-on of the integrated circuit package 1a or in accordance with a predetermined tuning update period. After transmitting the I / O tuning command (IT_CMD), the host device 10 provides tuning block signals for an I / O tuning operation to the I / O tuning circuit 30c. The tuning block signals include a first clock signal (CLK1) and a first data signal (DQ1). According to this embodiment, the host device 10 provides a response signal (Rsp) and data strobe signals (DQS1, DQS2) in response to the I / O tuning command (IT_CMD) via the data line (DL).

[0020] According to this embodiment, the host device 10 provides a first clock signal (CLK1) and a first data signal (DQ1) to the input / output tuning circuit 30c via the first physical layer (PHY1). According to this embodiment, the input / output tuning circuit 30c performs an input / output tuning operation in response to receiving an input / output tuning command (IT_CMD) and outputs a second clock signal (CLK2) and a second data signal (DQ2) based on the first clock signal (CLK1) and the first data signal (DQ1). According to this embodiment, the output second clock signal (CLK2) and second data signal (DQ2) are provided to the memory device 20 via the second physical layer (PHY2).

[0021] The host device 10 includes a first physical layer (PHY1) and a memory controller (10MC). The host device 10 may be a separate logic semiconductor chip (first semiconductor chip) or a plurality of semiconductor chiplets. According to this embodiment, the host device 10 is a system on chip (SoC), a graphics processing unit (GPU) die, a central processing unit (CPU) die, or the like, and according to this embodiment, the host device 10 has a built-in memory controller (10MC).

[0022] The memory controller 10MC provides various signals to the memory device 20 via the first physical layer PHY1 and controls memory operations such as write and read operations.

[0023] The memory controller (10MC) outputs a first clock signal (CLK1), a command (CMD), an address (ADDR), and a power signal (PWR) to the memory device 20 via the first physical layer (PHY1), and transmits and receives data signals (DQ1, DQ2) and data strub signals (DQS1, DQS2) to and from the memory device 20 via the first physical layer (PHY1).

[0024] The first physical layer (PHY1) is an interface configuration for die-to-die communication and is the lowest physical layer (Physical Layer, hereinafter referred to as PHY). In this embodiment, the first physical layer (PHY1) is a physical layer of a serial high-speed interface. In this embodiment, the first physical layer (PHY1) is any of, but not limited to, HBM2E / 2 PHY, HBM3 PHY, HBI PHY, DDR5 / 4 PHY, USR / XSR PHY, and MIPI I3C PHY that comply with JEDEC HBM.

[0025] In this embodiment, the first physical layer (PHY1) physically connects systems to transmit data, converts and controls electrical signals, synchronizes clock signals, performs link training, etc., and controls configurations related to the sideband that transmits clock signals.

[0026] In this embodiment, the memory device 20 is a High Bandwidth Memory (HBM) device including multiple memory channels, but is not limited to this and may be a Dynamic Random Access Memory (DRAM) such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate (LPDDR) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, or Rambus Dynamic Random Access Memory (RDRAM).

[0027] The memory device 20 receives a command (CMD), an address (ADDR), a power signal (PWR), and a second clock signal (CLK2) output from the input / output tuning circuit 30c via the second physical layer (PHY2), and transmits and receives a second data signal (DQ2) and a second data strobe signal (DQS2) via the second physical layer (PHY2) and the input / output tuning circuit 30c. In this embodiment, the second physical layer (PHY2) corresponds to the first physical layer (PHY1) and is one of a JEDEC HBM-compliant HBM2E / 2 PHY, an HBM3 PHY, an HBI PHY, a DDR5 / 4 PHY, a USR / XSR PHY, and an I3C PHY of MIPI, but is not limited to these.

[0028] Although not shown, the second physical layer (PHY2) includes a serial-to-parallelizer. The second physical layer (PHY2) performs read and write operations based on the number of data pads arranged in the second physical layer (PHY2) through the serial-to-parallelizer. The memory device 20 performs parallelization and serialization of data signals according to write and read operations through the serial-to-parallelizer.

[0029] The input / output tuning circuit 30c includes a delay controller 31 and a delay circuit 32. According to this embodiment, the input / output tuning circuit 30c performs an input / output tuning operation to delay at least one of a first clock signal CLK1 and a first data signal DQ1 received from the host device 10, and outputs a second clock signal CLK2 and a second data signal DQ2.

[0030] According to this embodiment, the delay controller 31 receives an input / output tuning command (IT_CMD) output from the host device 10, and outputs a selection signal (SS) in response to the reception of the input / output tuning command (IT_CMD) to control the delay circuit 32.

[0031] According to this embodiment, the delay controller 31 receives the second clock signal CLK2 and the second data signal DQ2 output by the input / output tuning operation of the delay circuit 32, and checks the data valid section for the second data signal DQ2.

[0032] According to this embodiment, the delay controller 31 determines the completion of the input / output tuning operation according to the result of the check operation on the data valid section. According to this embodiment, the delay controller 31 provides the result of the determination to the host device 10 as a response signal (Rsp). According to this embodiment, the delay controller 31 sets a delay set value (DSV) in response to the completion of the input / output tuning operation, and outputs a selection signal (SS) to the delay circuit 32 based on the set delay set value (DSV). The specific configuration and operation of the delay controller 31 will be described later with reference to FIGS. 2 to 7.

[0033] In this embodiment, the delay circuit 32 receives a selection signal (SS) from the delay controller 31 and performs an input / output tuning operation to delay at least one of a first clock signal (CLK1) and a first data signal (DQ1) based on the selection signal (SS). Based on the input / output tuning operation, the delay circuit 32 outputs a second clock signal (CLK2) and a second data signal (DQ2).

[0034] Thereafter, the delay circuit 32 provides a selection signal (SS) based on the set delay set value (DSV). According to this embodiment, when the delay circuit 32 receives a first clock signal (CLK1) and a first data signal (DQ1) together with a write command from the host device 10, it performs an input / output tuning operation in accordance with the selection signal (SS) based on the set delay set value (DSV) and outputs a second clock signal (CLK2) and a second data signal (DQ2). The specific configuration and operation of the delay circuit 32 will be described later with reference to FIGS. 2 to 7.

[0035] FIG. 2 is a block diagram illustrating an example of an integrated circuit package according to one embodiment.

[0036] Specifically, FIG. 2 illustrates the connection relationship between the host device 10, the memory device 20, and the input / output tuning circuit 30c, focusing on clock signals CLK1 and CLK2 and data signals DQ1 and DQ2.

[0037] 1 and 2, the delay controller 31 includes a delay selector (31S) and a data checker (31C). The delay circuit 32 includes a clock delay circuit (32_c) and 0th to nth delay circuits (32_0 to 32_n).

[0038] The delay circuit 32 receives a first clock signal (CLK1) and a first data signal (DQ1) output from the host device 10 as a delayed clock signal and a delayed data signal. According to this embodiment, the first data signal (DQ1) includes 1_0th to 1_nth data signals (DQ1[n:0], where n is an integer equal to or greater than 3), and each of the 1_0th to 1_nth data signals (DQ1[n:0]) includes 1-bit data. According to this embodiment, the first clock signal (CLK1) and the 1_0th to 1_nth data signals (DQ1[n:0]) are output from a first clock pad (cp1) and 1_0th to 1_nth data pads (dp1_0 to dp1_n) of the first physical layer (PHY1), respectively, and are provided to the clock delay circuit (32_c) and the 0th to nth delay circuits (32_0 to 32_n), respectively. n is any of 15, 31, and 63, but is not limited to these.

[0039] In this embodiment, the first clock signal (CLK1) and the 1_0th to 1_nth data signals (DQ1[n:0]) are delayed by the wiring between each of the first clock pads (cp1) and the 1_0th to 1_nth data pads (dp1_0 to dp1_n) and each of the clock delay circuits (32_c) and the 0th to nth delay circuits (32_0 to 32_n), and are input to the clock delay circuit (32_c) and the 0th to nth delay circuits (32_0 to 32_n) as the first delayed clock signal (CLK1') and the 1_0th to 1_nth delayed data signals (DQ1[n:0]'), respectively.

[0040] 2, the first clock signal (CLK1) and the 1_0th to 1_n-1th data signals (DQ1[n-1:0]) are delayed by the first wiring capacitor (Cl1) and are provided to the clock delay circuit (32_c) and the 0th to n-1th delay circuits (32_0 to 32_n-1) as the first delayed clock signal (CLK1') and the 1_0th to 1_n-1th delayed data signals (DQ1[n-1:0]'). The 1_nth data signal (DQ1[n]) is delayed by the second wiring capacitor (Cl2) and is provided to the nth delay circuit (32_n) as the 1_nth delayed data signal (DQ1[n]').

[0041] The clock delay circuit (32_c) and the 0th to nth delay circuits (32_0 to 32_n) are respectively provided with a clock selection signal (SS_c) and 0th to nth selection signals (SS_0 to SS_n) from the delay selector (31S). According to this embodiment, the clock delay circuit (32_c) and the 0th to nth delay circuits (32_0 to 32_n) perform delay operations on the first delayed clock signal (CLK1') and the 1_0th to 1_nth delayed data signals (DQ1[n:0]') based on the clock selection signal (SS_c) and the 0th to nth selection signals (SS_0 to SS_n). By the delay operation, the clock delay circuit (32_c) and the 0th to nth delay circuits (32_0 to 32_n) output the second clock signal (CLK2) and the 2_0th to 2_nth data signals (DQ2[n:0]), respectively.

[0042] According to this embodiment, the clock delay circuit (32_c) and the 0th to nth delay circuits (32_0 to 32_n) individually perform delay operations based on the clock selection signal (SS_c) and the 0th to nth selection signals (SS_0 to SS_n). As described above, the delay circuit 32 performs input / output tuning operations due to the individual operations of the clock delay circuit (32_c) and the 0th to nth delay circuits (32_0 to 32_n).

[0043] According to this embodiment, the second clock signal (CLK2) and the 2_0th to 2_nth data signals (DQ2[n:0]) generated by the input / output tuning operation are input to the second clock pad (cp2) and the 2_0th to 2_nth data pads (dp2_0 to dp2_n) of the second physical layer (PHY2), respectively. According to this embodiment, the second clock signal (CLK2) and the 2_0th to 2_nth data signals (DQ2[n:0]) are provided to the data checker (31C). According to this embodiment, the data checker (31C) receives the second clock signal (CLK2) and the 2_0th to 2_nth data signals (DQ2[n:0]) and checks the data valid section for the second data signal (DQ2) based on the received signals.

[0044] According to this embodiment, the data checker (31C) determines the completion of the input / output tuning operation according to the result of the check operation for the data valid section. According to this embodiment, the data checker (31C) provides the determination result to the host device 10 as a response signal (Rsp). According to this embodiment, the data checker (31C) sets a delay set value (DSV) in response to the completion of the input / output tuning operation and provides the delay set value (DSV) to the delay selector (31S).

[0045] According to this embodiment, the delay selector (31S) provides a clock selection signal (SS_c) and 0th to nth selection signals (SS_0 to SS_n) to the clock delay circuit (32_c) and 0th to nth delay circuits (32_0 to 32_n), respectively, based on the delay set value (DSV).

[0046] FIG. 3 is a circuit diagram showing a delay circuit according to an embodiment.

[0047] The xth delay circuit (32_x) in Fig. 3 is either the clock delay circuit (32_c) or the 0th to nth delay circuits (32_0 to 32_n) in Fig. 2. For ease of explanation, the explanation of the xth delay circuit (32_x) will replace the explanation of the clock delay circuit (32_c) and the 0th to nth delay circuits (32_0 to 32_n).

[0048] 2 and 3, the xth delay circuit (32_x) includes first to fifth delay buffers (DBF1 to DBF5) and a multiplexer (MUX).

[0049] According to this embodiment, the first to fifth delay buffers (DBF1 to DBF5) are serially connected in the form of a chain between the input terminal of the xth delay circuit (32_x) and one input terminal of the multiplexer (MUX). According to this embodiment, each of the first to fifth delay buffers (DBF1 to DBF5) delays an input signal by a predetermined delay time and outputs the delayed signal. The predetermined delay time may be, but is not limited to, 1 ns to 10 ns. According to this embodiment, the first to fifth delay buffers (DBF1 to DBF5) include, but are not limited to, an inverter chain. Although FIG. 3 shows five delay buffers, this is for illustrative purposes only, and the technical concept of the present invention is not limited to the number of delay buffers.

[0050] The first delay buffer (DBF1) delays the first_x delay data signal (DQ1[x]') by a predetermined delay time and outputs a first delay buffer signal (DQ1[x]_d1). The second delay buffer (DBF2) delays the first delay buffer signal (DQ1[x]_d1) by a predetermined delay time and outputs a second delay buffer signal (DQ1[x]_d2). The third delay buffer (DBF3) delays the second delay buffer signal (DQ1[x]_d2) by a predetermined delay time and outputs a third delay buffer signal (DQ1[x]_d3). The fourth delay buffer (DBF4) delays the third delay buffer signal (DQ1[x]_d3) by a predetermined delay time and outputs a fourth delay buffer signal (DQ1[x]_d4). The fifth delay buffer (DBF5) delays the fourth delay buffer signal (DQ1[x]_d4) by a predetermined delay time and outputs a fifth delay buffer signal (DQ1[x]_d5).

[0051] The multiplexer (MUX) receives the first_xth delayed data signal (DQ1[x]') and the first through fifth delay buffer signals (DQ1[x]_d1 through DQ1[x]_d5) and receives an xth selection signal (SS_x) from the delay selector (31S). According to this embodiment, the multiplexer (MUX) selects one of the first_xth delayed data signal (DQ1[x]') and the first through fifth delay buffer signals (DQ1[x]_d1 through DQ1[x]_d5) based on the xth selection signal (SS_x), and outputs the selected signal as the second_xth data signal (DQ2[x]). The output second_xth data signal (DQ2[x]) is provided to the second_xth data pad (dp2_x) of the second physical layer (PHY2).

[0052] In this embodiment, when the xth delay circuit (32_x) is a clock delay circuit (32_c), the first_xth delayed data signal (DQ1[x]') in FIG. 3 corresponds to the first delayed clock signal (CLK1') in FIG. 2, the first to fifth delay buffer signals (DQ1[x]_d1 to DQ1[x]_d5) in FIG. 3 correspond to the first to fifth clock delay buffer signals (not shown), the second_xth data signal (DQ2[x]) in FIG. 3 corresponds to the second clock signal (CLK2) in FIG. 2, and the second_xth data pad (dp2_x) in FIG. 3 corresponds to the second clock pad (cp2) in FIG. 2.

[0053] FIG. 4 is a diagram illustrating an example of an integrated circuit package according to an embodiment.

[0054] 1 to 4, an integrated circuit package 1a includes a host device 10, a memory device 20, an interposer 30, and a printed circuit board (hereinafter, referred to as PCB) 40.

[0055] The host device 10 and the memory device 20 are arranged and mounted on an interposer 30. The host device 10 and the memory device 20 are spaced apart from each other in the first direction (X) and are arranged so as not to overlap each other in a plane based on the third direction (Z).

[0056] A plurality of first command and address bumps (cab1), a plurality of first data bumps (db1), a plurality of first power bumps (pb1), and a plurality of first control signal bumps (cdb) are arranged on the bottom surface of the host device 10. The host device 10 includes a first physical layer (PHY1) connected to the plurality of first command and address bumps (cab1), the plurality of first power bumps (pb1), and the first data bump (db1). In this embodiment, the first data bump (db1) is connected to the data line (DL) in FIGS. 1 and 2 and is in contact with and connected to data pads 1_0 to 1_n that transmit and receive a first data signal (DQ1).

[0057] The memory device 20 includes a memory die 100 including four core dies stacked in a third direction (Z) and a buffer die 200. In this embodiment, each of the memory die 100 and the buffer die 200 is implemented in the form of a semiconductor chip (second semiconductor chip). A plurality of first bumps (MB) are formed between the stacked core dies and the buffer die 200, and first through silicon vias (TSV1) are formed between the stacked first bumps (MB) that penetrate the core dies.

[0058] In other embodiments, unlike those shown, memory device 20 may include five or more stacked core dies, and in other embodiments, buffer die 200 may be stacked on top of, rather than underneath, the stacked core dies.

[0059] Although not shown, each of the stacked core dies includes a memory channel (not shown), and each of the multiple memory channels (not shown) includes a predetermined number of memory banks (not shown). Data terminals, command and address terminals, and power terminals are arranged between the multiple memory channels, and second data signals (DQ2), commands (CMD), addresses (ADDR), and power signals (PWR) are input / output to / from the multiple memory channels via the data terminals, command and address terminals, and power terminals. According to this embodiment, the data terminals, command and address terminals, and power terminals are connected to a second physical layer (PHY2).

[0060] Each of the data terminals, the command and address terminals, and the power terminals is a plurality of first bumps (MB) shown in Fig. 4. According to this embodiment, the conductors that vertically pass through the data terminals, the command and address terminals, and the power terminals are first through-silicon vias (TSV1).

[0061] Based on the third direction (Z), a plurality of first direct access bumps (dab), a plurality of second power bumps (pb2), a plurality of second command and address bumps (cab2), and a plurality of second data bumps (db2) are arranged on the bottom surface of the buffer die 200.

[0062] The buffer die 200 also includes a second physical layer (PHY2) connected to a plurality of second command and address bumps (cab2), a plurality of second power bumps (pb2), and a second data bump (db2). The second data bump (db2) according to the present embodiment is connected to and in contact with data pads 2_0 to 2_n (dp2_0 to dp2_n) connected to the data line (DL) in FIGS. 1 and 2 to transmit and receive a second data signal (DQ2).

[0063] According to this embodiment, the second physical layer (PHY2) is connected to some of the first through silicon vias (TSV1) arranged on the top surface of the buffer die 200 to transmit and receive data to and from the memory die 100. According to this embodiment, the second physical layer (PHY2) includes a serial / deserializer (SER / DES), which inputs and outputs data to and from the memory die 100 via a second data signal (DQ2). According to this embodiment, the second physical layer (PHY2) is connected to some of the first through silicon vias (TSV1) to provide a power signal (PWR) to the memory die 100.

[0064] The second physical layer (PHY2) is arranged so as to overlap in a planar manner with at least a portion of the plurality of second data bumps (db2), the plurality of second command and address bumps (cab2), and the second power bump (pb2) based on the third direction (Z).

[0065] The plurality of first bumps (MB), the plurality of first direct access bumps (dab), the plurality of first and second power bumps (pb1, pb2), the plurality of first and second command and address bumps (cab1, cab2), and the plurality of first and second data bumps (db1, db2) and the plurality of first control signal bumps (cdb) are microbumps.

[0066] According to this embodiment, the interposer 30 is disposed between the host device 10 and the PCB 40 and between the memory device 20 and the PCB 40. According to this embodiment, a plurality of second direct access bumps (DAFBs), a plurality of third power bumps (PBFBs), and a plurality of second control signal bumps (CDFBs) are disposed on the bottom surface of the interposer 30. The plurality of second direct access bumps (DAFBs), the plurality of third power bumps (PBFBs), and the plurality of second control signal bumps (CDFBs) are connected to the PCB 40.

[0067] The interposer 30 includes, but is not limited to, a silicon interposer, an organic interposer, etc. In another embodiment, the interposer 30 may be an active interposer including a logic circuit.

[0068] According to this embodiment, the interposer 30 includes a redistribution layer 310 and a substrate 320. According to this embodiment, the redistribution layer 310 is disposed on the substrate 320 in the third direction (Z).

[0069] According to this embodiment, the substrate 320 is a semiconductor wafer having opposing upper and lower surfaces and including a semiconductor element such as silicon or germanium, or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). According to this embodiment, the substrate 320 includes an active surface (e.g., upper surface) having an active region doped with impurities, and an opposite inactive surface (e.g., lower surface).

[0070] According to this embodiment, an input / output tuning circuit 30c is disposed on at least a portion of the upper surface of the substrate 320. The input / output tuning circuit 30c includes discrete elements constituting an integrated circuit disposed on the upper surface of the substrate 320. In this case, the discrete elements are electrically connected to the redistribution structures 312 of the redistribution layer 310. According to this embodiment, the input / output tuning circuit 30c is connected to a plurality of first data bumps db1 and a plurality of second data bumps db2 via data lines DL. Although not shown, the input / output tuning circuit 30c is also connected to a plurality of first command and address bumps cab1.

[0071] The discrete elements include various active and / or passive elements such as FETs such as planar FETs and FinFETs, memory elements such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, and RRAM, logic elements such as AND, OR, and NOT, system LSIs, CIS, and MEMS.

[0072] The redistribution layer 310 includes a redistribution structure 312 and an insulating layer 314 surrounding the redistribution structure 312. The redistribution structure 312 is formed as a multilayer structure including a conductive pattern and vias made of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film (not shown) including titanium (Ti), titanium nitrate (TiN), tantalum (Ta), or tantalum nitrate (TaN) is disposed between the conductive pattern and / or vias and the insulating layer 314.

[0073] The insulating layer 314 may include flowable oxide (FOX), TonenSilaZen (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphorus silica glass (PSG), borophosphosilica glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), high-density plasma oxide (HDP), plasma-enhanced oxide (PEOX), flowable CVD (FCVD) oxide, or a combination thereof. At least a portion of the insulating layer 314 surrounding the redistribution structure 312 is composed of a low-k dielectric layer. The insulating layer 314 may be formed using a chemical vapor deposition (CVD), flowable CVD, or spin-coating process.

[0074] According to this embodiment, the rewiring structure 312 includes data lines DL connecting the plurality of first data bumps db1 to the input / output tuning circuit 30c and the plurality of second data bumps db2 to the input / output tuning circuit 30c. According to this embodiment, the rewiring structure 312 connects the plurality of first command and address bumps cab1 to the plurality of second command and address bumps cab2, and connects the plurality of first power bumps pb1 to the plurality of second power bumps pb2.

[0075] According to this embodiment, the redistribution structure 312 includes a plurality of direct lines connected to some of the second through silicon vias (TSV2) that penetrate at least a portion of the substrate 320 and the insulating layer 314 in the third direction (Z) and electrically connect the plurality of first direct access bumps (dab) and the plurality of second direct access bumps (DAFB), and a plurality of control signal lines connected to some of the second through silicon vias (TSV2) and electrically connect the plurality of first control signal bumps (cdb) and the plurality of second control signal bumps (CDFB). According to this embodiment, the redistribution structure 312 includes a power line connected to some of the second through silicon vias (TSV2) and connecting the plurality of third power bumps (PBFB) and the plurality of first power bumps (pb1) of the host device 10.

[0076] A plurality of direct access balls (DAB), a plurality of power balls (PB), and a plurality of control signal balls (CDB) are arranged on the bottom surface of the PCB 40.

[0077] In this embodiment, on PCB 40, a plurality of second direct access bumps (DAFB) are connected to a plurality of direct access balls (DAB), a plurality of third power bumps (PBFB) are connected to a plurality of power balls (PB), and a plurality of second control signal bumps (CDFB) are connected to a plurality of control signal balls (CDB).

[0078] Figure 5 is a flowchart illustrating an example of a method for operating an integrated circuit package according to an embodiment. Figure 6 is a timing diagram illustrating an input / output tuning operation of an integrated circuit package according to an embodiment. Figure 7 is a timing diagram illustrating an input / output tuning operation of an integrated circuit package according to an embodiment.

[0079] 1 to 5, the host device 10 provides an input / output tuning command (IT_CMD) to the memory device 20 (step S110). According to this embodiment, the host device 10 provides the input / output tuning command (IT_CMD) to the memory device 20 and the input / output tuning circuit (30c).

[0080] According to this embodiment, the host device 10 outputs an input / output tuning command (IT_CMD) at boot-on or according to a predetermined tuning update period, and provides it to the memory device 20 and the input / output tuning circuit 30c.

[0081] In response to receiving the input / output tuning command (IT_CMD), the memory device 20 controls a part of the second physical layer (PHY2) to a high impedance state (step S120). According to this embodiment, the memory device 20 controls the second clock pad (cp2) and the 2_0th to 2_nth data pads (dp2_0 to dp2_n) of the second physical layer (PHY2) so that they appear to be in a high impedance state from the outside. Through this control operation, in response to receiving the input / output tuning command (IT_CMD), the memory device 20 blocks signals input from the second clock pad (cp2) and the 2_0th to 2_nth data pads (dp2_0 to dp2_n). The operation of step S120 efficiently performs the operation of the input / output tuning circuit (30c) in steps S130 to S190, which will be described later.

[0082] After outputting the input / output tuning command (IT_CMD), the host device 10 provides the first clock signal (CLK1) and the first data signal (DQ1) to the input / output tuning circuit (30c) (step S130).

[0083] According to this embodiment, the host device 10 provides a tuning block signal for an input / output tuning operation together with a first clock signal (CLK1), and the data signal included in the tuning block signal includes a predetermined data pattern.

[0084] The delay circuit 32 delays at least one of the first clock signal (CLK1) and the first data signal (DQ1) to perform an input / output tuning operation (step S140).

[0085] 6 is a timing diagram illustrating an example of the input / output tuning operation of the delay circuit 32. Referring to FIG. 6 as an example, at time t1, the host device 10 outputs a first data signal (DQ1). According to this embodiment, the host device 10 outputs a first clock signal (CLK1) synchronously with the first data signal (DQ1), and the first clock signal (CLK1) is output while toggling with a clock period (T).

[0086] After time t1, the host device 10 sequentially outputs first to fourth valid data (DV1 to DV4) as the first data signal (DQ1) in a data period (TD) that is half the clock period (T). In this embodiment, the first to fourth valid data (DV1 to DV4) are tuning blocks of a predetermined data pattern.

[0087] At time t2, the first clock signal (CLK1) rises from logic low to logic high, and the remaining data period (TD) after time t2 is the hold period (tH). Time t2 is the time after the setup period (tSU) has elapsed from time t1.

[0088] After time t3, in response to the output of the first to fourth valid data (DV1 to DV4), the delay circuit 32 sequentially receives the first invalid data (DIv1), the first valid data (DV1), the second invalid data (DIv2), the second valid data (DV2), the third invalid data (DIv3), the third valid data (DV3), the fourth invalid data (DIv4), and the fourth valid data (DV4) as the first delayed data signal (DQ1').

[0089] 2, the first clock signal (CLK1) and the 1_0th to 1_n-1th data signals (DQ1[n-1:0]) are delayed by a first wiring capacitor (Cl1) by a first wiring delay time (tdl1) and provided to the clock delay circuit 32_c and the 0th to n-1th delay circuits 32_0 to 32_n-1 as the first delayed clock signal (CLK1') and the 1_0th to 1_n-1th delayed data signals (DQ1[n-1:0]'). In addition, the 1_nth data signal (DQ1[n]) is delayed by a second wiring capacitor (Cl2) by a second wiring delay time (tdl2) and provided to the nth delay circuit 32_n as the 1_nth delayed data signal (DQ1[n]').

[0090] At time t3, the 1_n delayed data signal (DQ1[n]') of the first valid data (DV1) has not yet reached the n-th delay circuit (32_n), and the delay circuit 32 receives the first invalid data (DIv1) as the first delayed data signal (DQ1'). Time t3 is the time when the first wiring delay time (tdl1) has elapsed since time t1.

[0091] At time t4, the delay circuit 32 receives the first valid data (DV1) as the first delayed data signal (DQ1'). Time t4 is the time when the second wiring delay time (tdl2) has elapsed since time t1.

[0092] Similarly, at time t5, the first delay clock signal (CLK1') rises from logic low to logic high, which is the time when the first wiring delay time (tdl1) has elapsed since time t2.

[0093] The delay circuit 32 delays the first delayed clock signal (CLK1') by the clock delay time (tdc) and outputs a second clock signal (CLK2) and a second data signal (DQ2) based on the first delayed clock signal (CLK1') and the first delayed data signal (DQ1').

[0094] Due to the delay operation of the delay circuit 32 on the first delayed clock signal (CLK1'), a phase difference corresponding to the clock delay time (tdc) occurs between the first delayed clock signal (CLK1') and the second clock signal (CLK2). No phase difference occurs between the 1_0th to 1_nth delayed data signals (DQ1[n:0]') and the 2_0th to 2_nth data signals (DQ2[n:0]). According to this embodiment, the phase difference between each of the 1_0th to 1_nth delayed data signals (DQ1[n:0]') and each of the 2_0th to 2_nth data signals (DQ2[n:0]) is the same.

[0095] At time t6, the second clock signal CLK2 rises from logic low to logic high, which is the time when the valid setup period tSU' has elapsed since time t4.

[0096] The delay circuit 32 outputs the first valid data (DV1) as the second data signal (DQ2) during a data valid section (TD') from time t4 to time t7 when the delay circuit 32 outputs the second invalid data (DIv2). The remaining data valid section (TD') after time t6, from time t6 to time t7, is a valid hold section (tH').

[0097] 5, the delay circuit 32 performs an input / output tuning operation to delay the first delayed clock signal (CLK1') corresponding to the first clock signal (CLK1) in step S140. Through the input / output tuning operation, the delay circuit 32 adjusts the time interval between the setup period and the hold period between the data valid periods to improve the skew between the clock signal and the data signal, thereby reducing errors that occur during data transmission between the host device 10 and the memory device 20.

[0098] 7 is a timing diagram for explaining an example of the input / output tuning operation of the delay circuit 32. The output operation of the first clock signal (CLK1) and the first data signal (DQ1) from time t1' to time t5' in FIG. 7 and the reception operation of the first delayed clock signal (CLK1') and the first delayed data signal (DQ1') correspond to the output operation of the first clock signal (CLK1) and the first data signal (DQ1) from time t1 to time t5 in FIG. 6 and the reception operation of the first delayed clock signal (CLK1') and the first delayed data signal (DQ1'). For ease of explanation, FIG. 7 will be explained mainly with reference to the output operation of the second clock signal (CLK2) and the second data signal (DQ2).

[0099] Referring to FIG. 7 as an example, the delay circuit 32 delays the 1_0th to 1_n-1th delayed data signals (DQ1[n-1:0]') by the data delay time (tdd), and outputs a second clock signal (CLK2) and a second data signal (DQ2) based on the first delayed clock signal (CLK1') and the first delayed data signal (DQ1').

[0100] Due to the delay operation of the delay circuit 32 on the 1_0th to 1_n-1th delayed data signals (DQ1[n-1:0]'), a phase difference corresponding to the data delay time (tdd) occurs between each of the 1_0th to 1_n-1th delayed data signals (DQ1[n-1:0]') and each of the 2_0th to 2_n-1th data signals (DQ2[n-1:0]). No phase difference occurs between the first delayed clock signal (CLK1') and the second clock signal (CLK2) and between the 1_nth delayed data signal (DQ1[n]') and the 2_nth delayed data signal (DQ2[n]). In another embodiment, the phase difference between the first delayed clock signal (CLK1') and the second clock signal (CLK2) may be the same as the phase difference between the 1_nth delayed data signal (DQ1[n]') and the 2_nth delayed data signal (DQ2[n]).

[0101] After time t4', the delay circuit 32 sequentially outputs the first to fourth valid data (DV1 to DV4) as the second data signal (DQ2) in a period of the data valid section (TD'). The delay circuit 32 and the first and second wiring capacitors (Cl1, Cl2) delay the first data signal (DQ1) as a whole by the second wiring delay time (tdl2), and output it as the second data signal (DQ2). According to this embodiment, the delay circuit 32 sequentially outputs multiple valid data as the second data signal (DQ2) without any inactive data.

[0102] At time t5', the second clock signal CLK2 rises from logic low to logic high, which is the point in time when the valid setup period tSU' has elapsed since time t4'.

[0103] The delay circuit 32 outputs the first valid data (DV1) as the second data signal (DQ2) during a data valid period (TD') from time t4' to time t6' when the delay circuit 32 outputs the second valid data (DV2). The remaining data valid period (TD') after time t5', from time t5' to time t6', is a valid hold period (tH').

[0104] 5, the delay circuit 32 performs an input / output tuning operation to delay a portion of the first delayed data signal (DQ1') corresponding to the first data signal (DQ1) in step S140. Through the input / output tuning operation, the delay circuit 32 secures the time interval of the data valid period, thereby improving the margin of the data valid window for the data signal and reducing errors that occur during data transmission between the host device 10 and the memory device 20.

[0105] The data checker 31C checks the data valid section for the second clock signal CLK2 and the second data signal DQ2 for which the input / output tuning operation has been performed (step S150).

[0106] The data checker (31C) receives the second clock signal (CLK2) and the second data signal (DQ2) and performs a check operation to measure the time interval between the data valid section (TD') and the valid setup section (tSU') for the second data signal (DQ2) of Figures 6 and 7.

[0107] The data checker (31C) determines whether the input / output tuning operation has been completed based on the result of the check operation (step S160).

[0108] In this embodiment, the data checker (31C) compares the time interval of the measured data valid interval (TD') with a predetermined first time interval, and if the time interval of the data valid interval (TD') is longer than the predetermined first time interval, the data checker (31C) determines that the input / output tuning operation is completed.

[0109] In this embodiment, the data checker (31C) compares the time interval of the measured valid setup interval (tSU') with a predetermined second time interval, and if the time interval of the valid setup interval (tSU') is longer than the predetermined second time interval, the data checker (31C) determines that the input / output tuning operation is completed.

[0110] In one embodiment, the data checker (31C) determines that the I / O tuning operation is complete when both the conditions for the data valid interval (TD') and the conditions for the valid setup interval (tSU') are met, but in other embodiments, it can determine that the I / O tuning operation is complete when one of the above conditions is met.

[0111] The data checker (31C) checks the data validity interval for the second data signal (DQ2), and if it determines based on the result of the check operation that the input / output tuning operation has not been completed, it provides a failure response signal (Rsp) to the host device 10 (step S170).

[0112] Upon receiving the failure response signal (Rsp), the integrated circuit package 1a repeatedly performs steps S130 to S160 while changing the selection signal (SS) of the delay selector (31S).

[0113] The data checker (31C) checks the data validity interval for the second data signal (DQ2), and if it determines that the input / output tuning operation is completed based on the result of the check operation, it provides a success response signal (Rsp) to the host device 10 and sets the delay setting value (DSV) (step S180).

[0114] The data checker 31C sets the delay set value (DSV) based on the selection signal (SS) corresponding to the completion determination of the input / output tuning operation. According to this embodiment, when the data checker 31C provides a success response signal (Rsp) to the host device 10, the data checker 31C sets the delay set value (DSV) based on the clock selection signal (SS_c) and the 0th to nth selection signals (SS_0 to SS_n), and provides the set delay set value (DSV) to the delay selector 31S.

[0115] Thereafter, the second physical layer (PHY2), at least a portion of which has been controlled to a high impedance state in step S120, is controlled to a data input / output state for write and read operations.

[0116] The delay circuit 32 outputs the second clock signal (CLK2) and the second data signal (DQ2) based on the set delay set value (DSV) (step S190).

[0117] The delay selector 31S outputs a selection signal SS based on the set delay setting value DSV and provides it to the delay circuit 32. According to this embodiment, the delay circuit 32 performs an input / output tuning operation based on the received selection signal SS, and outputs a second clock signal CLK2 and a second data signal DQ2 to provide them to the memory device 20.

[0118] Through steps S110 to S190, the integrated circuit package 1a according to this embodiment can improve the data valid window margin of the data signals (DQ1, DQ2) transmitted and received between the host device 10 and the memory device 20, and can improve the skew between the clock signals (CLK1, CLK2) and the data signals (DQ1, DQ2), thereby reducing data errors that occur during data transmission.

[0119] In step S140, the input / output tuning operation of FIG. 6 and the input / output tuning operation of FIG. 7 are described as being performed in different embodiments, but in other embodiments, the integrated circuit package 1a can perform a combination of the input / output tuning operation of FIG. 6 and the input / output tuning operation of FIG. 7.

[0120] According to this embodiment, the first data signal (DQ1) and the first clock signal (CLK1) are delayed by the second interconnect delay time (tdl2) by the delay circuit 32 and the first and second interconnect capacitors (Cl1, Cl2), and the second clock signal (CLK2) and the second data signal (DQ2) are output based on the first delayed clock signal (CLK1') and the first delayed data signal (DQ1'). Therefore, the delay circuit 32 secures the time interval of the data valid period through the input / output tuning operation, thereby improving the margin of the data valid period for the data signal and reducing errors that occur during data transmission between the host device 10 and the memory device 20.

[0121] FIG. 8 is a block diagram illustrating another example of an integrated circuit package according to one embodiment.

[0122] The host device 10, memory device 20', and input / output tuning circuit 30c' in the integrated circuit package 1b in Figure 8 correspond to the host device 10, memory device 20, and input / output tuning circuit 30c in the integrated circuit package 1a in Figure 2. For ease of explanation, the integrated circuit package 1b in Figure 8 will be described focusing on the differences from the integrated circuit package 1a in Figure 2, and the commonalities with the integrated circuit package 1a in Figure 2 will be explained in conjunction with Figure 2.

[0123] Referring to Figures 1, 3, 4 and 8, an integrated circuit package 1b includes a host device 10, a memory device 20' and an input / output tuning circuit 30c'.

[0124] The memory device 20' further includes a data checker 21 compared to the memory device 20 of Figure 2. The data checker 21 corresponds to the data checker 31C of Figure 2. According to this embodiment, the input / output tuning circuit 30c' does not include a separate data checker, but includes a delay selector 31S and a delay circuit 32.

[0125] According to this embodiment, the data checker 21 checks the data valid section of the second data signal (DQ2) based on the second clock signal (CLK2) input via the second clock pad (cp2) and the 2_0 to 2_n data pads (dp2_0 to dp2_n) in the second physical layer (PHY2) and the 2_0 to 2_n data signals (DQ2[n:0]).

[0126] According to this embodiment, the data checker 21 determines whether the input / output tuning operation is complete based on the result of the check operation for the data valid section. According to this embodiment, the data checker 21 provides the result of the determination to the host device 10 as a response signal (Rsp) via the data line (DL).

[0127] According to this embodiment, the data checker 21 in the memory device 20 provides the set delay set value (DSV) to the delay selector 31S via the data line (DL).

[0128] The memory device 20' of the integrated circuit package 1b according to this embodiment includes a data checker 21, which checks the data validity interval based on the second clock signal CLK2 and the second data signal DQ2 input to the memory device 20', thereby improving the reliability of the input / output tuning operation.

[0129] According to this embodiment, the data checker 21 is arranged separately from the delay circuit 32 and the delay selector (31S).

[0130] FIG. 9 is a flowchart illustrating another example method of operating an integrated circuit package according to one embodiment.

[0131] Steps S210 to S280 in Fig. 9 correspond to step S110 and steps S130 to S190 in Fig. 5, respectively. For ease of explanation, the steps of the operation method in Fig. 9 will be explained focusing on the differences from the operation method in Fig. 5, and the commonalities with the operation method in Fig. 5 will be substituted with the explanation in Fig. 5.

[0132] 1, 3, 4, 8, and 9, the host device 10 provides an input / output tuning command (IT_CMD) to the memory device 20′ (step S210). Step S210 corresponds to step S110 in FIG.

[0133] After outputting the input / output tuning command (IT_CMD), the host device 10 provides the first clock signal (CLK1) and the first data signal (DQ1) to the input / output tuning circuit 30c' (step S220). Step S220 corresponds to step S130 in FIG.

[0134] Before step S220, the memory device 20' does not control a part of the second physical layer PHY2 to a high impedance state in response to receiving the input / output tuning command IT_CMD.

[0135] The delay circuit 32 delays at least one of the first clock signal (CLK1) and the first data signal (DQ1) to perform an input / output tuning operation (step S230). Step S230 corresponds to step S140 in FIG.

[0136] The data checker 21 checks the data valid section for the second clock signal (CLK2) and the second data signal (DQ2) for which the input / output tuning operation has been performed (step S240). Step S240 corresponds to step S150 in FIG.

[0137] The data checker 21 receives a second clock signal (CLK2) and a second data signal (DQ2) input via a second physical layer (PHY2) and checks the data valid intervals for the second clock signal (CLK2) and the second data signal (DQ2).

[0138] The data checker 21 determines whether the input / output tuning operation is complete or not based on the result of the check operation (step S250). Step S250 corresponds to step S160 in FIG.

[0139] The data checker 21 checks the data valid section for the second data signal (DQ2), and if it determines based on the result of the check operation that the input / output tuning operation has not been completed, it provides a failure response signal (Rsp) to the host device 10 (step S260). Step S260 corresponds to step S170 in FIG. 5.

[0140] The data checker 21 checks the data valid section of the second data signal (DQ2), and if it determines based on the result of the check operation that the input / output tuning operation is completed, it provides a success response signal (Rsp) to the host device 10 and sets the delay set value (DSV) (step S270). Step S270 corresponds to step S180 in FIG. 5.

[0141] According to this embodiment, when the data checker 21 provides a successful response signal (Rsp) to the host device 10, the data checker 21 sets a delay setting value (DSV) based on the clock selection signal (SS_c) and the 0th to nth selection signals (SS_0 to SS_n), and provides the set delay setting value (DSV) to the delay selector (31S) via the data line (DL).

[0142] In step S270, the second physical layer (PHY2) controls the data input / output state for the write operation and the read operation without changing the impedance state.

[0143] The delay circuit 32 outputs the second clock signal (CLK2) and the second data signal (DQ2) based on the set delay set value (DSV) (step S280). Step S280 corresponds to step S190 in FIG.

[0144] FIG. 10 is a diagram illustrating another example of an integrated circuit package according to an embodiment.

[0145] The a-th chiplet 10a, the b-th chiplet 10b, the interposer 30, and the PCB 40 in the integrated circuit package 1c in Figure 10 correspond to the host device 10, the memory device 20, the interposer 30, and the PCB 40 in the integrated circuit package 1a in Figure 4, respectively. For ease of explanation, the integrated circuit package 1c in Figure 10 will be described focusing on the differences from the integrated circuit package 1a in Figure 4, and the commonalities with the integrated circuit package 1a in Figure 4 will be substituted for the explanation of Figure 4.

[0146] Referring to FIGS. 1 to 3 and 10, an integrated circuit package 1c includes an a-th chiplet 10a, a b-th chiplet 10b, an interposer 30, and a PCB 40.

[0147] Each of the a-th chiplet 10a and the b-th chiplet 10b includes at least one functional block. A functional block, also called intellectual property (IP), refers to a unit block divided into functional units to be actually developed. According to this embodiment, each of the a-th chiplet 10a and the b-th chiplet 10b is a chiplet in which each functional block is formed on a separate semiconductor chip. According to this embodiment, the a-th chiplet 10a and the b-th chiplet 10b have different functional blocks, are spaced apart from each other in the first direction (X) on the interposer 30, and are mounted on the interposer 30. According to this embodiment, the a-th chiplet 10a and the b-th chiplet 10b operate as a single logic semiconductor chip and transmit and receive clock signals and data signals to and from each other.

[0148] A plurality of first_a command and address bumps (cab1a), a plurality of first_a data bumps (db1a), a plurality of first_a power bumps (pb1a), and a plurality of first_a control signal bumps (cdba) are arranged on a bottom surface of the a-th chiplet 10a. According to this embodiment, the a-th chiplet 10a includes a first_a physical layer (PHY1a) connected to the plurality of first_a command and address bumps (cab1a), the plurality of first_a data bumps (db1a), and the plurality of first_a power bumps (pb1a). The plurality of first_a command and address bumps (cab1a), the plurality of first_a data bumps (db1a), and the plurality of first_a power bumps (pb1a), respectively, correspond to the plurality of first command and address bumps (cab1), the first data bumps (db1), and the plurality of first power bumps (pb1) in FIG.

[0149] A plurality of first_b command and address bumps (cab1b), a plurality of first_b data bumps (db1b), a plurality of first_b power bumps (pb1b), and a plurality of first_b control signal bumps (cdbb) are arranged on a bottom surface of the b-th chiplet 10b. According to this embodiment, the b-th chiplet 10b includes a first_b physical layer (PHY1b) connected to the plurality of first_b command and address bumps (cab1b), the plurality of first_b data bumps (db1b), and the plurality of first_b power bumps (pb1b). The plurality of first_b command and address bumps (cab1b), the plurality of first_b data bumps (db1b), and the plurality of first_b power bumps (pb1b), respectively, correspond to the plurality of second command and address bumps (cab2), the second data bumps (db2), and the plurality of second power bumps (pb2) in FIG. 4.

[0150] The first_a physical layer (PHY1a) and the first_b physical layer (PHY1b) are UCIe PHYs based on the Universal Chiplet Interconnect Express (UCIe) open standard, but are not limited to this. According to this embodiment, the first_a physical layer (PHY1a) and the first_b physical layer (PHY1b) transmit and receive clock signals (CLK1, CLK2) and data signals (DQ1, DQ2) via the interposer 30.

[0151] The plurality of first_a data bumps (db1a) and the plurality of first_b data bumps (db1b) are electrically connected to the input / output tuning circuit 30c via data lines (DL) included in the rewiring structure 312. The a-th chiplet 10a and the b-th chiplet 10b transmit and receive clock signals and data signals via the input / output tuning circuit 30c.

[0152] In this embodiment, the a-th chiplet 10a outputs a first clock signal CLK1 and a first data signal DQ1. The input / output tuning circuit 30c performs an input / output tuning operation to delay at least a portion of the first clock signal CLK1 and the first data signal DQ1, as shown in Figures 5 to 7, and outputs a second clock signal CLK2 and a second data signal DQ2 to the b-th chiplet 10b.

[0153] The integrated circuit package (1c) according to this embodiment can improve the data valid window margin for the data signals (DQ1, DQ2) transmitted and received between the a-th chiplet (10a) and the b-th chiplet (10b) through the input / output tuning operation of the input / output tuning circuit (30c), and can improve the skew between the clock signals (CLK1, CLK2) and the data signals (DQ1, DQ2), thereby reducing data errors that occur during data transmission.

[0154] FIG. 11 is a diagram illustrating yet another example of an integrated circuit package according to an embodiment.

[0155] The host device 10, memory device 20, bridge chip 50, and PCB 40' in the integrated circuit package 1d in Figure 11 correspond to the host device 10, memory device 20, interposer 30, and PCB 40 in the integrated circuit package 1a in Figure 4, respectively. For ease of explanation, the integrated circuit package 1d in Figure 11 will be described focusing on the differences from the integrated circuit package 1a in Figure 4, and the commonalities with the integrated circuit package 1a in Figure 4 will be substituted for the explanation of Figure 4.

[0156] 1 to 3 and 11, an integrated circuit package 1d includes a host device 10, a memory device 20, a bridge chip 50, and a PCB 40'. The host device 10 and the memory device 20 are arranged and mounted on the PCB 40'. The host device 10 and the memory device 20 are spaced apart from each other in a first direction (X) and are arranged so as not to overlap each other in a plane based on a third direction (Z).

[0157] The bridge chip 50 is accommodated and disposed in a cavity (CAV) formed on the top surface of the PCB 40'. According to this embodiment, the bridge chip 50 includes an input / output tuning circuit 30c.

[0158] The bridge chip 50 is disposed to overlap at least a portion of the host device 10 and at least a portion of the memory device 20 in the third direction (Z). The bridge chip 50 is connected to a plurality of first data bumps (db1) disposed on the bottom surface of the host device 10 and a plurality of second data bumps (db2) disposed on the bottom surface of the buffer die 200. According to this embodiment, the bridge chip 50 includes data lines (DL) connecting the plurality of first data bumps (db1) to the input / output tuning circuit 30c and connecting the plurality of second data bumps (db2) to the input / output tuning circuit 30c.

[0159] According to this embodiment, the PCB 40' connects a plurality of first command and address bumps (cab1) to a plurality of second command and address bumps (cab2), and connects a plurality of first power bumps (pb1) to a plurality of second power bumps (pb2). According to this embodiment, the PCB 40' includes direct lines electrically connecting a plurality of direct access balls (DAB) to a plurality of second direct access bumps (DAFB), and a plurality of control signal lines electrically connecting a plurality of control signal balls (CDB) to a plurality of second control signal bumps (CDFB). According to this embodiment, the PCB 40' includes power lines connecting a plurality of power balls (PB) to a plurality of first power bumps (pb1) of the host device 10.

[0160] The integrated circuit package (1d) according to this embodiment can improve the data valid window margin for the data signals (DQ1, DQ2) transmitted and received between the host device 10 and the memory device 20 through the input / output tuning operation of the input / output tuning circuit (30c), and can improve the skew between the clock signals (CLK1, CLK2) and the data signals (DQ1, DQ2), thereby reducing data errors that occur during data transmission.

[0161] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0162] 1a, 1b, 1c, 1d Integrated Circuit Packages 10 Host device (first semiconductor chip) 10a, 10b a-th and b-th chiplets 10MC Memory Controller 20, 20' Memory device (second semiconductor chip) 21, 31C Data Checker 30 Interposer 30c, 30c' Input / Output Tuning Circuit 31 Delay Controller 31S Delay Selector 32 Delay circuit 32_0~32_n 0th to nth delay circuits 32_c Clock delay circuit 32_x xth delay circuit 40, 40' Printed Circuit Board (PCB) 50 Bridge Chip 100 memory dies 200 Buffer Dies 310 Redistribution layer 312 Rewiring Structure 314 Insulating Layer 320 board ADDR Address Cl1, Cl2 First and second wiring capacitors cab1, cab2 1st, 2nd command and address bump cab1a, cab1b 1st_a, 1st_b command and address bump CAV cavity CDB control signal ball cdb 1st control signal bump cdba, cdbb 1st_a, 1st_b control signal bump CDFB Second control signal bump CLK1, CLK2 First and second clock signals CLK1' 1st delay clock signal CMD command cp1, cp2 1st and 2nd clock pads dab 1st direct access bump DAB Direct Access Ball DAFB No. 2 Direct Access Bump db1, db2 1st and 2nd data bumps db1a, db1b 1st_a, 1st_b data bump dp1_0~dp1_n Data Pad 1_0~1_n dp2_0~dp2_n Data Pad 2_0~2_n DBF1~DBF5 1st to 5th delay buffers DIv1~DIv4 1st~4th invalid data DL data line dp2_x Datapad 2 DQ1, DQ2 First and second data signals DQ1[n:0] 1_0th to 1_nth data signals DQ1[x]_d1~DQ1[x]_d5 1st to 5th delay buffer signals DQ1' 1st delay data signal DQ1[n:0]' 1_0th to 1_nth delay data signals DQ1[x]' 1st_x delayed data signal DQ1 / Rsp, DQ2 / Rsp DQ2[n:0] 2_0th to 2_nth data signals DQ2[x] 2nd_x data signal DQS1, DQS2 First and second data strobe signals DSV delay setting value DV1~DV4 1st to 4th valid data IT_CMD I / O tuning command MB 1st Bump MUX Multiplexer PB Powerball pb1, pb2 1st and 2nd power bumps pb1a, pb1b 1st_a, 1st_b power bump PBFB 3rd Power Bump PHY1, PHY2 1st, 2nd physical layer PHY1a, PHY1b 1st_a, 1_b physical layer PWR power signal Rsp response signal SS selection signal SS_0~SS_n 0th to nth selection signals SS_c Clock selection signal SS_x xth selection signal TSV1, TSV2 First and second through silicon vias

Claims

1. A substrate; a first semiconductor chip on the substrate that outputs a first clock signal and a first data signal; a delay circuit that delays at least one of the first clock signal and the first data signal and outputs a second clock signal and a second data signal based on the first clock signal and the first data signal; a second semiconductor chip horizontally spaced apart from the first semiconductor chip on the substrate for receiving the second clock signal and the second data signal.

2. 2. The integrated circuit package of claim 1, further comprising a data checker that receives the second clock signal and the second data signal and checks a data valid section of the second data signal.

3. further including an active interposer disposed between the substrate and the first semiconductor chip, on which the first semiconductor chip and the second semiconductor chip are mounted; The integrated circuit package according to claim 1 , wherein the active interposer includes the delay circuit.

4. a bridge chip connected to the first semiconductor chip and the second semiconductor chip and including the delay circuit; 2. The integrated circuit package according to claim 1, wherein the bridge chip is disposed in a cavity formed on one side of the substrate.

5. 5. The integrated circuit package according to claim 4, wherein the first semiconductor chip and the second semiconductor chip are mounted on the substrate.

6. the first data signal includes a third data signal and a fourth data signal each including 1-bit data; the second data signal includes a fifth data signal and a sixth data signal output by the delay circuit based on the third and fourth data signals; 2. The integrated circuit package of claim 1, wherein the delay circuit includes a first delay circuit that outputs the fifth data signal based on the third data signal, a second delay circuit that outputs the sixth data signal based on the fourth data signal, and a clock delay circuit that outputs the second clock signal based on the first clock signal.

7. 7. The integrated circuit package of claim 6, wherein the first delay circuit includes: a first delay buffer that delays the third data signal by a predetermined delay time and outputs a first delay buffer signal; a second delay buffer that delays the first delay buffer signal by the delay time and outputs a second delay buffer signal; and a multiplexer that outputs the fifth data signal based on the third data signal, the first delay buffer signal, and the second delay buffer signal.

8. 8. The integrated circuit package of claim 7, further comprising a delay selector that provides a selection signal to said multiplexer.

9. the fifth data signal is generated by performing a delay operation on the third data signal; 7. The integrated circuit package of claim 6, wherein a phase difference between the sixth data signal and the fourth data signal is the same as a phase difference between the second clock signal and the first clock signal.

10. the second clock signal is generated by performing a delay operation on the first clock signal; 7. The integrated circuit package of claim 6, wherein a phase difference between the fifth data signal and the third data signal is the same as a phase difference between the sixth data signal and the fourth data signal.

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