Small-sized light-emitting diodes fabricated via regrowth

Abstract

To provide a small-sized light-emitting diode fabricated via comfortable regrowth.SOLUTION: A method for fabricating and transferring high quality and manufacturable light-emitting devices, such as small-sized light-emitting diodes (μLEDs), using epitaxial lateral overgrowth (ELO) and isolation methods. III-nitride ELO layers are grown on a host substrate using a growth restrict mask, and III-nitride device layers are grown on wings of the III-nitride ELO layers. The resulting devices are isolated from the host substrate while attached by a connecting link comprising an epitaxial or non-epitaxial bridge. A regrowth is performed on selected mesas of the device layers to realize improved devices with help of the bridge. The bridge is broken, and the devices are then plucked from the host substrate and placed on a display panel.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit under 35 USC Section 119(e) of the following co-pending and commonly assigned applications:

[0002] U.S. Provisional Application No. 63 / 104,580 (Attorney Docket No. G&C30794.0784USP1 (UC 2020-561-1)), entitled "SMALL SIZE LIGHT EMITING DIODES FABRICATED VIA REGROWTH," filed October 23, 2020, by Srinivas Gandrothula and Takeshi Kamikawa, which application is incorporated herein by reference.

[0003] This application is related to the following co-pending and commonly assigned applications:

[0004] U.S. Utility Patent Application No. 16 / 608,071 (Attorney Docket No. 30794.0653USWO(UC2017-621-2)), filed October 24, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled "METHOD OF REMOVING A SUBSTRATE," which application was filed May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled "METHOD OF REMOVING A SUBSTRATE," under 35 U.S.C. Section 365(c). This application claims the benefit of commonly assigned, copending PCT International Patent Application No. PCT / US18 / 31393 (Attorney Docket No. 30794.0653WOU1 (UC2017-621-2)), entitled "METHOD OF REMOVING A SUBSTRATE," which in turn claims the benefit of commonly assigned, copending U.S. Provisional Patent Application No. 62 / 502,205 (Attorney Docket No. 30794.0653USP1 (UC2017-621-1)), filed May 5, 2017, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, entitled "METHOD OF REMOVING A SUBSTRATE," under 35 U.S.C. § 119(e).

[0005] U.S. Utility Patent Application No. 16 / 642,298 (Attorney Docket No. 30794.0659USWO(UC2018-086-2)) filed on February 26, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE," which was filed on September 17, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE" under 35 U.S.C. Section 365(c) (U.S.C. 365(c)). This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US18 / 51375 (Attorney Docket No. 30794.0659WOU1 (UC2018-086-2)), entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE," filed September 15, 2017, under 35 U.S.C. Section 119(e) by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE." This application claims the benefit of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 559,378 (Attorney Docket No. 30794.0659USP1 (UC2018-086-1)), entitled "METHOD OF USE IN A HIGH-FREQUENCY PHOTOMETRY TECHNIQUE."

[0006] U.S. Utility Patent Application No. 16 / 978,493 (Attorney Docket No. 30794.0680USWO(UC2018-427-2)) filed September 4, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH," which application was filed April 1, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH" under 35 U.S.C. Section 365(c) (35 U.S.C. § 365(c)). This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US19 / 25187 (Attorney Docket No. 30794.0680WOU1 (UC2018-427-2)), entitled "METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL MICROFIBER OVERGROWTH," filed March 30, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li under 35 U.S.C. Section 119(e) and entitled "METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL MICROFIBER OVERGROWTH." This application claims the benefit of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 650,487 (Attorney Docket No. G&C30794.0680USP1 (UC2018-427-1)), entitled "METHOD OF USE IN A HIGH-FREQUENCY PHASE OVERGROWTH."

[0007] U.S. Utility Patent Application No. 17 / 048,383 (Attorney Docket No. 30794.0681USWO(UC2018-605-2)), filed on October 16, 2020, by Takeshi Kamikawa and Srinivas Gandrothula, entitled "METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES," which application was filed on May 17, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, under 35 U.S.C. Section 365(c) (U.S.C. 365(c)). This application claims the benefit of commonly assigned, copending PCT International Patent Application No. PCT / US19 / 32936 (Attorney Docket No. 30794.0681WOU1 (UC2018-605-2)), entitled "METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES," which in turn claims the benefit under 35 U.S.C. § 119(e) of commonly assigned, copending U.S. Provisional Application No. 62 / 672,913 (Attorney Docket No. G&C30794.0681USP1 (UC2018-605-1)), filed May 17, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled "METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES."

[0008] U.S. Utility Patent Application No. 17 / 049,156 (Attorney Docket No. 30794.0682USWO(UC 2018-614-2)), filed October 20, 2020, by Srinivas Gandrothula and Takeshi Kamikawa, entitled "METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE," which application is hereby incorporated by reference in its entirety under 35 U.S.C. § 365(c) by Srinivas Gandrothula and Takeshi Kamikawa, filed May 30, 2019 ... This application claims the benefit of co-pending and commonly assigned PCT International Patent Application No. PCT / US19 / 34868 (Attorney Docket No. G&C30794.0682WOU1 (UC 2018-614-2)) entitled "METHOD OF REMOVING SEMICONDUCTION LAYERS FROM A SEMICONDUCTION SUBSTRATE," filed May 30, 2018, by Srinivas Gandrothula and Takeshi Kamikawa under 35 U.S.C. Section 119(e) and entitled "METHOD OF REMOVING SEMICONDUCTION LAYERS FROM A SEMICONDUCTION SUBSTRATE." This application claims the benefit of co-pending and commonly assigned U.S. Provisional Application No. 62 / 677,833 (Attorney Docket No. G&C30794.0682USP1 (UC2018-614-1)), entitled "A Method and Apparatus for Producing a Novel Substrate."

[0009] All of those applications are incorporated herein by reference.

[0010] FIELD OF THE INVENTION The present invention is directed to small size light emitting diodes (LEDs) fabricated by regrowth. [Background technology]

[0011] Microdisplays based on arrays of micro-sized light-emitting diodes (μLEDs) are a promising technology for a wide range of applications. μLEDs are inorganic LEDs at micron dimensions and are self-emissive, which means they can achieve the highest contrast ratios and simplify display panel design.

[0012] Recently, several studies have shown interest in employing μLEDs in the 100-200 μm size range as backlight sources in liquid crystal displays (LCDs) to increase the contrast ratio, reduce the complexity of the LCD architecture, and improve other display parameters such as the viewing angle and aperture ratio.

[0013] Because μLEDs are dimensioned on a microscopic scale, each μLED represents a pixel in a monochrome display, or three red, green, and blue μLEDs form a pixel in a full-color display. In addition, μLEDs are made from mature inorganic semiconductor materials such as InGaN or AlGaInP, which offer advantages over existing display technologies such as LCDs and organic LEDs, including high peak brightness, significant energy efficiency, chemical robustness, and long operating lifetimes.

[0014] In a two-dimensional array, each μLED acts as a single pixel of the overall image. These microdisplays can be used in applications ranging from TVs, laptops, smartphones, heads-up displays (HUDs), and augmented reality, virtual reality, and mixed reality (AR / VR / MR) applications.

[0015] One current focus is μLEDs based on group III nitride materials, which have the chemical formula Ga x Al y In zN, where 0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z=1. While most of the research attention has been focused on InGaN-based μLEDs, there has also been some work on UV-A AlGaN μLEDs for display applications.

[0016] One of the most essential advantages of III-nitride material systems is the emission wavelength tunability by varying the composition percentage of indium and gallium in the active region, also known as quantum well (QW), because the bandgaps of GaN and InN are 3.4 eV and 0.7 eV, respectively, and InGaN-based alloys can theoretically span the entire visible spectrum.

[0017] Unfortunately, III-nitride-based LEDs become inefficient as device dimensions decrease due to nonradiative recombination losses at exposed surfaces. These losses arise from nonradiative surface states, such as point defects and dangling bonds on gallium (Ga) atoms, which are primarily introduced during plasma-based device patterning. Due to the high surface area / volume ratio, these effects become more important than ever for microLEDs. Analysis of external quantum efficiency (EQE) curves suggests that the Shockley-Read-Hall (SRH) recombination rate increases by more than an order of magnitude as device dimensions decrease.

[0018] III-nitride μLEDs have great potential in displays and other emerging applications, but several challenges remain that must be addressed before commercial products can be realized for mass production. Three essential issues for III-nitride μLEDs are size-dependent efficiency, color gamut (long wavelength emission), and mass transfer techniques. The present invention addresses these issues. Summary of the Invention [Means for solving the problem]

[0019] To overcome the limitations in the prior art described above, as well as other limitations that will become apparent upon perusal and understanding of this specification, the present invention discloses a method for fabricating a semiconductor layer on a host substrate, which can be a homogeneous or heterogeneous substrate, or a template comprising the material of the separated semiconductor layer, and then separating the semiconductor layer from the host substrate. The separation is performed on wings of III-nitride layers grown by epitaxial lateral overgrowth (ELO), thereby resulting in devices on these layers having good crystalline quality in terms of reduced dislocation density and stacking faults.

[0020] Specifically, the present invention implements the following steps: an island-shaped III-nitride semiconductor layer is grown on a substrate using a growth-limiting mask and an ELO method; the ELO region is a region with a reduced dislocation density compared to a non-ELO region; and the light-emitting aperture of the light-emitting region of the micro LED is at least partially limited to the wings of the ELO region, where a good crystal quality layer can be guaranteed.

[0021] The following device realization can be implemented in two ways. In one method, an epitaxial bridge is constructed when the ELO layer includes a p-type layer. In such a scenario, some care must be taken in the re-introduced crystal growth chamber temperature, as higher temperatures may damage or degrade the previously grown quantum well layer of the active region. Pulsed laser deposition techniques can be used to deposit the p-type layer, or alternatively, molecular beam epitaxy (MBE) equipment can be used as the re-grown crystal layer chamber, in which case the growth temperature is less aggressive than metalorganic chemical vapor phase epitaxy (MOVPE) or metalorganic chemical vapor deposition (MOCVD), etc.

[0022] Alternatively, the epitaxial bridge is formed after completion of the n-type ELO layer. Because the carrier activation energy in the n-type layer is smaller than that of carriers from the p-type layer, damage to the n-type layer when exposed to plasma etching may be less severe than that to the p-type layer. In this case, a mesa for the regrowth layer is opened across the ELO wings in addition to forming the epitaxial bridge. In this scenario, much more accelerated parameters can be used to grow the complete light-emitting device layer, since regrowth is performed to fully grow the device layer in addition to the regrowth chamber described above.

[0023] In both of the above scenarios, instead of an epitaxial bridge, a non-epitaxial bridge, i.e., a layer that may or may not be different from the growth-limiting mask material, can be used to push the optical aperture onto the ELO wings while holding the device layer when reintroduced into the crystalline layer regrowth chamber.

[0024] After that, front-end processing is performed until the p-pad and n-pad can be finished on the ELO wings, and then the device unit is extracted from the host substrate. Note that the isolated device unit remains on the host substrate with very minimal connections using epitaxial or non-epitaxial bridges until the device process is finished. The device can then be removed from the substrate by an elastomer stamp, or a vacuum chuck, or adhesive tape, or simply by bonding or attaching the device to a separate carrier substrate.

[0025] In particular, the interface between the growth-limiting mask surface and the ELO region is sufficiently smooth. The measured roughness was approximately <2 nm, since the surfaces of these layers are simply replicas of the surface of the growth-limiting mask for the ELO process. This smoothness can help keep the element units on the display panel for further processing, such as electrical connection pads.

[0026] The as-fabricated μLEDs on the ELO wings can be transferred onto a different carrier for further processing using a simple stamp, a vacuum chuck, or a carrier plate attached with glue. The III-nitride semiconductor layers are dimensioned so that one or more of the III-nitride semiconductor island layers form one or more device rods. This allows nearly identical devices to be fabricated adjacent to each other in a self-assembled array, and therefore scale-up through integration can be more easily achieved. Alternatively, the ELO III-nitride layers can be first fabricated to coalesce so that they can later be separated into device rods or individual chips.

[0027] All elements of such a rod can be addressed separately or together with other elements by designing an appropriate fabrication process. For example, a common cathode or anode for such element rods can be fabricated for monolithic integration, or individual elements can be addressed for full-color display applications. As a result, high yields can be obtained.

[0028] A significant advantage of the present invention includes connecting layers above the element unit and open areas using epitaxial and non-epitaxial bridges that allow layers damaged by dry etching to harden the surface defects by regrowth of the epitaxial layer.

[0029] The epitaxial or non-epitaxial bridge can avoid contamination and distortion of the bridge even when the bridge is exposed to high regrowth temperature conditions. The key point is to implement regrowth to repair damage to the layer before removing the growth limiting mask. The growth limiting mask can support the epitaxial bridge, which can avoid deformation of the epitaxial bridge.

[0030] Furthermore, the epitaxial or non-epitaxial bridge can position the light-emitting aperture away from the surface of the substrate, away from open areas with many defects. This can reduce the number of defects in the light-emitting aperture. The use of low-defect areas on the growth-limiting mask can effectively improve the reliability of long-wavelength elements, such as green or red light-emitting elements, by fabricating them.

[0031] Important aspects of the present invention include the following: The present invention can utilize homogeneous and heterogeneous substrates, including III-nitride substrates, III-nitride templates on substrates, and foreign substrates such as Si, SiC, sapphire, etc., to expand manufacturability for industrial needs. Furthermore, the present invention is independent of the crystal orientation of the original substrate. The present invention fabricates the light emitting area of ​​the device on the wings of III-nitride ELO layers, thereby providing better crystal quality in the light emitting area, which improves performance. The present invention can be utilized to increase yield by fabricating smaller footprint devices confined to the wings of III-nitride ELO layers. The light emitting aperture of the device is fabricated on the wings of the III-nitride ELO layer, which provides better crystal quality than an aperture fabricated directly on the original substrate in terms of reduced defects and stacking faults. Epitaxial or non-epitaxial bridges may assist in reintroducing isolated device units and layers into the crystalline layer growth environment. The regrown crystalline layer repairs the damage associated with the plasma-based etching experienced in creating the mesa. A very thin highly carrier doped layer (p-type) is regrown on the reintroduced completed device layers, which can avoid damage by reducing the exposure time of the active area in the regrowth chamber. Alternatively, the n-type ELO layer with epitaxial or non-epitaxial bridges can be reintroduced into the regrowth chamber for complete device crystal layer growth. No damage is caused because laser lift-off is not used to separate the device layer from the substrate. The damage-free separation process can be applied to any type of substrate, including homogeneous and heterogeneous substrates. The process for transferring devices is improved because selected devices can be extracted from the host substrate. · Vacuum or stamping processes allow for device selectivity. Inter-wafer bonding problems such as warping can be avoided because the present invention bonds separate or isolated devices from the host substrate to an external carrier (which is typically a better thermally conductive carrier). Instead of attaching the separate devices together to the external carrier (which limits the available heat spreading on the carrier), more thermal space can be allocated to each device on the carrier by selective transfer. The substrate can be recycled for the next batch of devices.

[0032] Some possible designs using the method are illustrated in the detailed description of the invention below. The present invention, when combined with the cross-referenced inventions relating to removing semiconductor devices from semiconductor substrates described above, has many advantages over conventional manufacturable device elements. The present invention provides, for example, the following items. (Item 1) 1. A method, comprising: growing one or more epitaxial lateral overgrowth (ELO) layers and device layers on the substrate using a growth-limiting mask; isolating the ELO layer and device layer on the growth limiting mask while forming connecting joints between the substrate and the isolated ELO layer and device layer; fabricating a light emitting aperture over the wing region of the ELO layer and device layer; transferring the ELO layer and device layer to a display panel by cutting the connecting joints; A method comprising: (Item 2) Item 14. The method of item 1, wherein device fabrication is performed before severing the connecting link. (Item 3) Item 10. The method of item 1, wherein the connecting link is an epitaxial bridge. (Item 4) Item 10. The method of item 1, wherein the connecting link is a non-epitaxial bridge. (Item 5) Item 10. The method of item 1, wherein the connecting link comprises a separation length between the light-emitting aperture on the wing region of the ELO layer and the open area of ​​the ELO layer. (Item 6) Item 6. The method of item 5, wherein the separation length is at least partially on the wing region of the ELO layer. (Item 7) Item 10. The method of claim 1, wherein the cutting comprises breaking and / or cleaving the connecting link. (Item 8) Item 10. The method of item 1, wherein the isolating comprises separating the ELO layer and device layer into devices. (Item 9) Item 10. The method of item 1, wherein the connecting joints hold the ELO layer and device layer on the substrate. (Item 10) Item 10. The method of item 1, wherein the transferring integrates the ELO layer and device layer onto a larger wafer. (Item 11) Item 10. The method of claim 1, wherein the fabricating is performed after the transferring. (Item 12) 2. The method of claim 1, wherein the transferring is performed using a pick-and-place method. (Item 13) 2. The method of claim 1, wherein the transferring is performed selectively. (Item 14) Item 2. The method according to item 1, wherein the substrate is a semiconductor substrate. (Item 15) Item 12. The method of item 11, wherein the semiconductor substrate is independent of crystal orientation. (Item 16) A device fabricated by the method described in item 1. (Item 17) 1. A method, comprising: growing one or more epitaxial lateral overgrowth (ELO) layers on the substrate using a growth limiting mask; isolating the ELO layer on the growth limiting mask while forming a contact joint between the substrate and the isolated ELO layer; regrowing one or more device layers on the isolated ELO layer; fabricating a light emitting aperture over the ELO layer and a wing region of the device layer; transferring the device layer to a display panel by cutting the connecting joints; A method comprising: [Brief explanation of the drawings]

[0033] Reference is now made to the drawings in which like reference numbers represent corresponding parts throughout.

[0034] [Figure 1] FIG. 1 is a schematic diagram of a substrate, a growth-limiting mask, a non-coalesced III-nitride epitaxial lateral overgrowth (ELO) layer, and a coalesced III-nitride ELO layer according to one embodiment of the present invention.

[0035] [Figure 2A] 2A, 2B, and 2C illustrate that a III-nitride ELO layer and a III-nitride device layer together form an island-shaped III-nitride semiconductor layer according to one embodiment of the present invention. [Figure 2B] 2A, 2B, and 2C illustrate that a III-nitride ELO layer and a III-nitride device layer together form an island-shaped III-nitride semiconductor layer according to one embodiment of the present invention. [Figure 2C] 2A, 2B, and 2C illustrate that a III-nitride ELO layer and a III-nitride device layer together form an island-shaped III-nitride semiconductor layer according to one embodiment of the present invention.

[0036] [Figure 3A] 3A and 3B illustrate III-nitride ELO device layers isolated from the host substrate in the desired shape with epitaxial bridges designated, regardless of the ELO layer pattern in FIGS. 2A and 2B. [Figure 3B] 3A and 3B illustrate III-nitride ELO device layers isolated from the host substrate in the desired shape with epitaxial bridges designated, regardless of the ELO layer pattern in FIGS. 2A and 2B.

[0037] [Figure 3C] 3C and 3D illustrate III-nitride ELO device layers isolated from the host substrate in the desired shape with designated non-epitaxial interconnects, regardless of the ELO layer pattern in FIGS. 2A and 2B. [Figure 3D] 3C and 3D illustrate III-nitride ELO device layers isolated from the host substrate in the desired shape with designated non-epitaxial interconnects, regardless of the ELO layer pattern in FIGS. 2A and 2B.

[0038] [Figure 4A]FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4B] FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4C]FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4D] FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4E]FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4F] FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4G]FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4H] FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4I]FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4J] FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4K]FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4L] FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4M]FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel. [Figure 4N] FIG. 4A illustrates an ELO wing with merged regions including an open region; FIG. 4B illustrates a mesa structure formed on the device layer of the ELO wing; FIG. 4C illustrates a blanket deposited passivation layer; FIG. 4D illustrates a light emitting region opening on the p-type layer; FIG. 4E illustrates the device mesa with epitaxial bridge structure formation; FIG. 4F illustrates a deep etch to expose a growth limiting mask; and FIG. 4G illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa during the deep etch. FIG. 4H illustrates the regrowth mesa opening on the p-layer, FIG. 4I illustrates the thin p-layer regrowth, FIG. 4J illustrates the hanging epitaxial bridge device structure, FIG. 4K illustrates the TCO layer window formation, FIG. 4L illustrates the p-pad and n-pad deposition, FIG. 4M illustrates the use of a stamp to extract the hanging epitaxial bridge device structures and then placing them on a display panel, and FIG. 4N is a flowchart of a process for realizing a micro LED display panel.

[0039] [Figure 5A] FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5B]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5C]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5D]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5E]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5F]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5G]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5H]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5I]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5J]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5K]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5L]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel. [Figure 5M]FIG. 5A illustrates an ELO wing with merged regions including an open region; FIG. 5B illustrates a device mesa structure formed on the device n-type layer of the ELO wing; FIG. 5C illustrates a deep etch to isolate device units along with the formation of an epitaxial bridge; FIG. 5D illustrates a growth limiting layer to protect the exposed epitaxial layer of the device mesa in the deep etch; FIG. 5E illustrates an opening in a regrowth patch on the n-type ELO layer wing; and FIG. 5F illustrates a regrown device including an n-type active region, an electron blocking layer, and a p-type layer. FIG. 5G illustrates TCO blanket deposition; FIG. 5H illustrates anchoring the light-emitting portion onto the device mesa; FIG. 5I illustrates etching away the short circuit path; FIG. 5J illustrates a lift-off anchoring mask layer; FIG. 5K illustrates p-pad and n-pad formation; FIG. 5L illustrates using a stamp to extract hanging epitaxial bridge device structures and then placing them on a display panel; and FIG. 5M is a flowchart of a process for realizing a microLED display panel.

[0040] [Figure 6A] 6A, 6B, and 6C illustrate a vertical pad configuration, where the interface between the base ELO layer and the growth limiting mask will be used as an n-type current injector. [Figure 6B] 6A, 6B, and 6C illustrate a vertical pad configuration, where the interface between the base ELO layer and the growth limiting mask will be used as an n-type current injector. [Figure 6C] 6A, 6B, and 6C illustrate a vertical pad configuration, where the interface between the base ELO layer and the growth limiting mask will be used as an n-type current injector.

[0041] [Figure 7] FIG. 7 is a vacuum chuck design for removing the isolated III-nitride ELO device layers from the host substrate.

[0042] [Figure 8]FIG. 8 is a flow chart illustrating a method for fabricating a semiconductor device in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0043] In the following description of the preferred embodiment, reference is made to specific embodiments in which the present invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0044] (overview) The present invention describes a method for fabricating semiconductor devices, such as light-emitting devices, including LEDs, in which the semiconductor layers remain on a host substrate with highly fragile contacts known as epitaxial bridges. Because ELO is relied upon, the present invention is easily applicable to foreign substrates, such as Si, SiC, sapphire, host substrates containing semiconductor layer templates, or ELO-engineered layer templates. The present invention addresses LEDs, allowing microcavity LEDs to be fabricated on ELO wings with good crystal quality, which can be isolated from the host substrate and then selectively removed or transferred onto a display back panel.

[0045] 1 illustrates the method using schematic diagrams 100A and 100B. The method begins by providing a III-nitride based substrate 101, such as a bulk GaN substrate 101.

[0046] In schematic diagram 100A, a growth-limiting mask 102 is formed on or above a III-nitride based substrate 101. Specifically, the growth-limiting mask 102 is placed in direct contact with the substrate 101, or indirectly through an intermediate layer grown, such as by MOCVD, from a III-nitride based semiconductor layer or template deposited on the substrate 101.

[0047] The growth limiting mask 102 can be formed from an insulator film, for example, a SiO2 film, deposited on the base substrate 101 by, for example, plasma-enhanced chemical vapor deposition (CVD), sputtering, ion beam deposition (IBD), etc., and the SiO2 film is photolithographically patterned using a predetermined optical mask to include open areas 103 and no-growth regions 104 (which may or may not be patterned), and then etched. The present invention can use SiO2, SiN, SiON, TiN, etc. as the growth limiting mask 102. A multi-layer growth limiting mask 102 made of the above materials is preferred.

[0048] An epitaxial III-nitride layer 105, such as a GaN-based layer 105, is grown on the GaN substrate 101 and the growth-limiting mask 102 using the ELO method. Growth of the III-nitride ELO layer 105 occurs first in the open areas 103 on the III-nitride-based substrate 101 and then laterally from the open areas 103 over the growth-limiting mask 102. The growth of the III-nitride ELO layer 105 can be stopped (or interrupted) before the III-nitride ELO layer 105 in adjacent open areas 103 can coalesce on top of the growth-limiting mask 102, and this interrupted growth results in no-growth regions 104 between adjacent III-nitride ELO layers 105. Alternatively, the growth of III-nitride ELO layer 105 may continue and coalesce with neighboring III-nitride ELO layers 105, thereby forming coalesced regions 106 of increased defects in the encountered areas, as shown in schematic diagram 100B.

[0049] 2A, 2B, and 2C, schematic diagrams 200a, 200b, 200c, 200d, and 200e illustrate how additional III-nitride device layers 107 may be deposited on or above III-nitride ELO layer 105, including active region 107a, p-type layer 107b, electron blocking layer (EBL) 107c, and cladding layer 107d, as well as other layers. Open regions of the III-nitride ELO layer are labeled as regions 201, and regions where neighboring III-nitride ELO layer wings may or may not meet are labeled as regions 202.

[0050] III-nitride ELO layer 105 and III-nitride device layer 107 include one or more flat surface regions 108 and layer bending regions 109 at the edges of flat surface regions 108 adjacent no-growth regions 104 when III-nitride ELO layer 105 is stopped before coalescence, as shown at 100a, or when III-nitride ELO layer 105 is continued to coalesce within coalesced regions 106, as shown at 100b. The width of flat surface region 108 is at least 3 μm, and most preferably 10 μm or greater.

[0051] The light-emitting active region 107a of the element 110 is treated with flat surface regions 108 on either side of region 201, preferably between the open area 103 and the edge portion 109 or merged region 106. By doing so, the rod of the element 110 will possess an array of pairs or nearly identical light-emitting apertures 111 along the length of the rod, on either side of the open area 103, as shown in schematic diagrams 200d and 200e.

[0052] There are many methods for removing the light emitting region from the substrate 101. For example, the present invention can utilize an ELO method to remove the light emitting device 110. In the present invention, the bond strength between the substrate 101 and the III-nitride ELO layer 105 is weakened by a growth-limiting mask 102. In this case, the bond area between the substrate 101 and the III-nitride ELO layer 105 is an open area 103, and the width of the open area 103 is narrower than that of the III-nitride ELO layer 105. As a result, the bond area is reduced by the growth-limiting mask 102 so that the method is favorable for removing the epitaxial layers 105, 107.

[0053] The present invention proposes two approaches for realizing micro LED devices. In one approach, a connecting link comprising an epitaxial bridge 301 is formed, as shown in schematic diagrams 300a and 300b in FIGS. 3A and 3B. The epitaxial bridge 301 connects the region 202 and the element unit pattern 302. As shown in FIG. 3B, the epitaxial bridge 301 has a length L and a width W1, and has a narrow taper with a width W2 smaller than the width W1. The epitaxial bridge 301 can be formed while implementing the desired element unit pattern 302, or alternatively, a separate etching step can be performed dedicated to realizing the non-epitaxial bridge 303. The element unit pattern 302 can be square, rectangular, circular, or any arbitrary shape. To form the pattern 302 shown in FIG. 3A, the region 201 and the region 202 are etched in a plasma-based environment as described in FIG. 2. This step isolates the element unit pattern 302 from the host substrate 101 while keeping the epitaxial bridge 301 together with the host substrate 101 .

[0054] 3C and 3D, connecting ties comprising non-epitaxial bridges 303 instead of epitaxial bridges 301 can be produced using a material other than or the same as growth-limiting mask 102. Separation length 304 remains at least partially on the wing regions of ELO layer 105 to ensure good crystal quality for light-emitting aperture 111 and fragile flanks when removing device 110 using methods described later herein.

[0055] There are many methods for removing the light emitting region from the substrate 101. For example, the present invention can utilize the ELO method to remove the light emitting device 110. In the present invention, the bond strength between the substrate 101 and the III-nitride ELO layer 105 is weakened by the narrower design of W2 in the epitaxial bridge 301. As a result, the bond area is reduced, and therefore the method is preferred for removing the epitaxial layers 105, 107.

[0056] In one embodiment, III-nitride ELO layers 105 are allowed to coalesce with one another in regions 106, as shown by schematic diagram 100b in Figure 1. After III-nitride ELO layers 105 coalesce in regions 106, subsequent III-nitride semiconductor device layers 107 are deposited. Light emitting element openings 111 will be fabricated on wings of III-nitride ELO layers 105 away from the coalesced regions 106 and 201 later in the fabrication process.

[0057] 3A and 3C , the III-nitride semiconductor layer 107 can be divided into element unit patterns 302 using, for example, dry etching or laser scribing. A separation distance 304 is the distance between the III-nitride ELO layer 105 after etching a portion of the region 202. Furthermore, the length L of the epitaxial bridge 301 or the non-epitaxial bridge 303 is defined as the separation distance 304, which ensures good crystal quality for the light-emitting aperture 111 on the wing of the III-nitride ELO layer 105 by positioning the element unit patterns 302 away from the non-growth region 104. In particular, a distance of at least 1 μm from the non-growth region 104 will ensure good crystal quality for the light-emitting aperture 111.

[0058] The element unit pattern 302 may include light-emitting apertures 111, as described above, located at separation distances 304 in isolation regions 202 located directly above or above the growth-limiting mask 102 for the purpose of facilitating removal of the elements 110. The separation distances 304 are preferably 1 μm or greater, which facilitates cutting of the epitaxial bridges 301 or non-epitaxial bridges 303 by breaking and / or cleaving the connecting ligatures.

[0059] Preferably, the edge of the light-emitting aperture 111, which emits light of a predetermined wavelength upon application of a current, is more than 1 μm away from the edge of the region 202. If the isolation region 202 is destroyed to remove the element 110, it may damage the light-emitting aperture 111. More preferably, the light-emitting aperture 111 is 2 μm or more away from the edge of the region 202, which reduces the number of defects in the aperture 111 area.

[0060] By doing so, there will be a larger process tolerance for yield. As can be seen from Figures 3A and 3C, the element unit pattern 302 is shown with the host substrate 101, with either epitaxial bridges 301 or non-epitaxial bridges 303.

[0061] Two approaches for epitaxial bridge 301 or non-epitaxial bridge 303 are as follows. (i) Epitaxial bridge to hold the p-type regrowth layer

[0062] For clarity, this description is limited to one device 110, as illustrated in Figures 4A-4N. In one approach, the epitaxial device layer 107 consists of the complete device structure, i.e., at least an n-type region, an active region, and a p-type region.

[0063] Exemplary fabrication steps for the present invention are described in further detail below.

[0064] Step 1: A growth-limiting mask 102 is formed directly or indirectly on a substrate 101 together with a plurality of striped open areas 103, the substrate 101 being a group III nitride-based semiconductor, or the substrate being a hetero-substrate (such as Si, SiN, sapphire, etc.), or a template prepared to include the growth-limiting mask 102.

[0065] Step 2: As shown in schematic diagram 400a in FIG. 4A , III-nitride ELO layer 105 is grown on or above substrate 101 using growth-limiting mask 102 such that the growth extends in a direction parallel to striped open areas 103 of growth-limiting mask 102, and wings of III-nitride ELO layer 105 on either side of open areas 103 merge into regions 106. Then, multiple epitaxial device layers 107 are grown on III-nitride ELO layer 105. This step isolates III-nitride ELO layer 105 and device layer 107 on growth-limiting mask 102, while forming connecting joints comprising bridges 301, 303 between substrate 101 and the isolated III-nitride ELO layer 105 and device layer 107.

[0066] Step 3: As shown in schematic diagrams 400b1 (top view), 400b2 (side view), and 400b3 (side view) in FIG. 4B , a light emitting mesa 401 with area a1×b1 is fabricated on the wings of the III-nitride ELO layer 105 away from the merged region 106 and on the flat surface region 108 using an optical mask and conventional methods to expose the underlying layers by plasma-based ambient etching.

[0067] Step 4: As shown in schematic diagrams 400c1 (top view), 400c2 (side view), and 400c3 (side view) in FIG. 4C, a second growth-limiting mask 402 is blanket deposited. This second growth-limiting mask 402 can be a similar or different material to that previously used for ELO patterning. This second growth mask 402 can also function as a passivation mask to repair or ameliorate damage associated with plasma-based etching. Lift-off of the selectively masked regions 403 can be performed while protecting the surrounding etched portions, as shown in schematic diagrams 400d1 (top view), 400d2 (side view), and 400d3 (side view) in FIG. 4D.

[0068] Step 5: As shown in schematic diagrams 400e1 (top view), 400e2 (side view), and 400e3 (side view) in FIG. 4E, a structure 404 having an area (a2 × b2) larger than the previous light-emitting mesa 401 having an area (a1 × b1) is formed to separate the devices 110, isolating them from each other while maintaining their connection to the host substrate 101 via the previously mentioned bridges 301 and 303. As shown in schematic diagrams 400f1 (top view), 400f2 (side view), and 400f3 (side view) in FIG. 4F, a long etch is performed to expose at least the underlying growth limiting mask 102. In this step, during the long etch, the epitaxial bridge 301 design was such that the n-type layer connection portion 405 remained along with the open area 103. The mesa etch layer 406 used to form the mesa (a2 x b2) can be a hard mask such as SiO2, SiN, etc. Alternatively, a photoresist (PR) mask can also be used.

[0069] Step 6: As shown in schematic diagrams 400g1 (top view), 400g2 (side view), and 400g3 (side view) in FIG. 4G, a protective layer 407 is blanket deposited. Layers 406 and 407 can be the same or different materials. Layer 407 protects the exposed mesa 401 during the formation of structure 404. As shown in schematic diagrams 400h1 (top view), 400h2 (side view), and 400h3 (side view) in FIG. 4H, a regrowth area 408 having an area (a3 × b3) is defined. When a photoresist mask is used to define structure 404 with an area (a2 × b2), lift-off is performed to realize structure 404 after blanket depositing protective layer 407. Otherwise, protective layer 407 and mesa etch layer 406 are selectively exposed on the p-layer for regrowth.

[0070] Step 7: As shown in schematic diagrams 400i1 (top view), 400i2 (side view), and 400i3 (side view) in Figure 4I, the structure 404 is returned to a crystalline layer growth environment. Because the exposed regrown area 408 consists of a p-type region, an active region, and an n-type region, care must be taken to re-grow the layer. MBE or a reduced temperature environment must be used to regrow a thin, more highly doped p-type layer over the exposed regrown area 408. Alternatively, pulsed laser deposition (PLD) or pulsed sputtering deposition (PSD) techniques can be used to avoid damage to the previously grown active region. The epitaxial bridge 301 (not shown) and epitaxial layer ties 405 may be strong enough to hold the isolated structure 404 together, even at slightly elevated parameters. However, in this scenario, to avoid degradation of the active region, one may choose any of the deposition methods mentioned above to regrow a thin, highly doped p-type layer 409. Regrowing a high carrier density p-type layer 409 over the etched mesa 401 will repair the damage caused by the plasma-based etching environment.

[0071] Step 8: As shown in schematic diagrams 400j1 (top view), 400j2 (side view), and 400j3 (side view) in Figure 4J, the second growth limiting mask 402 and the protective layer 407 are dissolved using a chemical etchant, such as buffered hydrofluoric acid (BHF) or hydrofluoric acid (HF), resulting in epitaxial bridges 301 or non-epitaxial bridges 303 as hanging bridges.

[0072] Step 9: As shown in schematic diagrams 400k1 (top view), 400k2 (side view), and 400k3 (side view) in Figure 4K, a transparent conductive oxide (TCO) layer 410, such as ITO (indium tin oxide), is deposited over the hanging bridge element 110. The mesa structure patterning of the TCO layer 410 with an area (a4 x b4) is selected to be smaller than the regrown area 408 with an area (a3 x b3), so that the difference can be used to deposit a p-type conductive layer.

[0073] Step 10: As shown in schematic diagrams 400l1 (top view), 400l2 (side view), and 400l3 (side view) in Figure 4L, electrical contact pads 411 are placed over the p-type layer 412 and the n-type layer 413 for electrical injection.

[0074] Step 11: The completed micro LED device 110 has highly frangible hanging bridges 301, 303 to the host substrate 101. The strength of the bridges 301, 303 can be designed to be frangible by controlling the parameters of the bridges 301, 303. As shown in the schematic diagram of FIG. 4M, the hanging bridge micro LED 110 achieved in step 10 is extracted from the host substrate 101 by a stamp 414, a vacuum chuck, or the like. For example, when a c-plane substrate is used, the epitaxial bridge 301 can be cut using the m-plane cleavage property for the purpose of removing the micro LED device 110. When using an epitaxial bridge 301, the mechanical force of the stamp 414 or vacuum chuck can easily cut the connection 301 and separate the device 110 from the host substrate 101.

[0075] Step 12: The extracted LED elements are placed on an intermediate imposer 415, and then the LED elements are dispersed from the imposer onto a display panel 416. The display panel 416 has an embedded electrode track pad for n-type electrical connection 417, and p-pad electrical track 418 is placed on an insulator or separator 419. The micro LED display 416 can be used in several applications such as TVs, laptops, phones, AR / VR / MR, HUD, retina display applications, etc.

[0076] FIG. 4N is a flow chart further illustrating steps 1-12 described above. (ii) an epitaxial bridge to hold the n-type, active region, and p-type regrowth layer;

[0077] For clarity, this description is limited to one device unit, as illustrated in Figures 5A-5N. In this approach, the epitaxial layer consists of only n-type layers before regrowth is performed.

[0078] Exemplary fabrication steps for the present invention are described in further detail below.

[0079] Step 1: A growth-limiting mask 102 is formed directly or indirectly on a substrate 101 together with a plurality of striped open areas 103, the substrate 101 being a group III nitride-based semiconductor, or the substrate being a heterosubstrate, or a template prepared to include the growth-limiting mask.

[0080] Step 2: As shown in schematic diagram 500a in Figure 5A, a plurality of III-nitride ELO layers 105 are grown on substrate 101 using growth-limiting mask 102 such that the growth extends in a direction parallel to striped open areas 103 of growth-limiting mask 102 and wings of III-nitride ELO layers 105 on either side of open areas 103 merge into regions 106. Then, a plurality of epitaxial device layers 107 are grown on III-nitride ELO layers 105.

[0081] Step 3: As shown in schematic diagrams 500b1 (top view) and 500b2 (side view) in FIG. 5B, a structure 400 having an area (a2 × b2) is formed to separate the n-type layer into isolated elements 110. The isolation separates each element 110 from its neighbors and maintains the connection of the bridges 301, 303 with the host substrate 101. As shown in schematic diagrams 500c1 (top view) and 500c2 (side view) in FIG. 5C, a deeper etch is performed to expose at least the underlying ELO growth limiting mask 102. In this step, during the long etch of the epitaxial bridge 301, the design is such that the n-type layer connection 405 remains together with the open area 103. The layer 406 used to form the mesa (a2 × b2) can be a hard mask such as SiO2, SiN, etc., or photoresist (PR) can also be used.

[0082] Step 4: As shown in schematic diagrams 500d1 (top view) and 500d2 (side view) in FIG. 5D, protective layer 407 is blanket deposited. Layers 407 and 406 can be made of the same or different materials. Layer 407 protects exposed mesa 401 during the formation of structure 404 (a2 × b2). As shown in schematic diagrams 500e1 (top view) and 500e2 (side view) in FIG. 5E, regrowth area 408 having area (a3 × b3) is defined. When a photoresist mask is used to define structure 404 with area a2 × b2, lift-off is performed to realize structure 404 after blanket deposition of protective layer 407. Otherwise, protective layer 407 and mesa etch layer 406 are selectively exposed on the n-type layer for regrowth.

[0083] Step 5: As shown in schematic diagrams 500f1 (top view) and 500f2 (side view) in Figure 5F, the structure 404 is returned to a crystalline layer growth environment. Because the exposed regrowth area 408 includes an n-type layer, an n-layer, and an active region, a p-type is grown in the regrowth step. Because no active region was previously included, a conventional MOCVD chamber can be used to regrow the complete device 100 structure. Alternatively, MBE or reduced temperature environments, pulsed laser deposition (PLD), or pulsed sputtering deposition (PSD) techniques can also be used. The epitaxial bridge 301 and epitaxial layer connections 405 can be sufficiently robust to hold the isolated structure 404 together, even at elevated parameters.

[0084] Step 6: As shown in schematic diagrams 500g1 (top view) and 500g2 (side view) in Figure 5G, a TCO layer 410 is deposited over the regrown layer of the isolated structure 404, the protective layer 407, and the mesa etch layer 406.

[0085] Step 7: As shown in schematic diagrams 500h1 (top view) and 500h2 (side view) in Figure 5H, a protective mesa 501 with area a4 x b4 is placed over the re-grown area 408 (now the light-emitting region) to protect the TCO layer 410. As shown in schematic diagrams 500i1 (top view) and 500i2 (side view) in Figure 5I, the remaining TCO layer 410 and protective layer 407 are removed, resulting in the epitaxial bridge 301 maintaining only a connection to the host substrate 101. As shown in schematic diagrams 500j1 (top view) and 500j2 (side view) in Figure 5J, the protective mesa 501 is removed from the re-grown area 408.

[0086] Step 8: As shown in schematic diagrams 500k1 (top view), 500k2 (side view), and 500k3 (side view) in Figure 5K, electrical contact pads 411 are placed over the p-type layer 412 and the n-type layer 413 for electrical injection.

[0087] Step 9: The completed micro LED device 110 has highly frangible hanging bridges 301, 303 to the host substrate 101. The strength of the bridges 301, 303 can be designed to be frangible by controlling the parameters of the bridges 301, 303. As shown in the schematic diagram of FIG. 5L, the hanging bridge micro LED 110 achieved in step 8 is extracted from the host substrate 101 by a stamp 414, a vacuum chuck, or the like. When using an epitaxial bridge 301, the mechanical force of the stamp 414 or vacuum chuck can easily sever the connection 301 and separate the device 110 from the host substrate 101.

[0088] Step 10: The extracted LED elements are placed on an intermediate imposer 415, and then the LED elements are dispersed from the imposer onto a display panel 416. The display panel 416 has an embedded electrode track pad for n-type electrical connection 417, and p-pad electrical track 418 is placed on an insulator or separator 419. The micro LED display 416 can be used in several applications such as TVs, laptops, phones, AR / VR / MR, HUD, retina display applications, etc.

[0089] FIG. 5M is a flow chart further illustrating steps 1-10 described above.

[0090] (vertical pad configuration) The epitaxial bridge 301 can also be applied to extract vertical pad-configured chips, as shown in Figures 6A, 6B, and 6C. This is independent of the approach to extracting the device 110, i.e., whether regrowth is performed for only the p-type layers or whether the complete LED structure is grown. The back interface 601, i.e., the interface between the growth-limiting mask 102 and the ELO layer 105, can be used as an n-type current injection layer, as shown in schematic diagrams 600a1 (top view), 600a2 (side view), 600a3 (side view), 600a3 (top view), and 600a5 (side view) in Figure 6A. As shown in the schematic diagram of Figure 6B, the LED 110 is extracted from the host substrate 101 by stamp 414, vacuum chuck, or the like. The extracted LED elements 110 are placed on an intermediate imposer 415, and then the LED elements are dispersed from the imposer 415 to a display panel 416. As shown in the schematic diagram of Figure 6C, the display panel 416 has a buried electrode track pad for n-type electrical connection 417, and p-pad electrical track 418 is placed on an insulator or separator 419. The micro LED display 416 can be used in several applications such as TVs, laptops, phones, AR / VR / MR, HUD, retina display applications, etc.

[0091] In the separation process, regions 201, 202 are etched to expose at least the growth-limiting mask 102, as needed, and the III-nitride ELO layer 105 is either separated into individual elements 110 or kept together as a group of elements 110. The separated III-nitride ELO layer 105 still remains on the growth-limiting mask 102 of the host substrate 101 for processes such as solvent cleaning, UV-ozone exposure, etc. Therefore, cleaning the III-nitride ELO layer 105 after separation using RIE or some other technique helps to remove residues, and cleaning can also help prepare the surface for a bonding process or chemical treatment to repair etching damage. This is a significant advantage for reducing process time and cost. Alternatively, as shown above, the protective layer 407 still serves as an auxiliary layer to secure the III-nitride device layer to the host substrate.

[0092] Many types of materials can be used as the protective layer 407, such as SiOx, SiNx, AlOx, SiONx, AlONx, TaOx, ZrOx, AlNx, TiOx, NbOx (x>0), etc. The protective layer 407 is preferably transparent to light from the active region 107a of the device 110 because there is no need to remove the protective layer 407 after removing the III-nitride ELO layer 105 from the substrate 101. Alternatively, the protective layer 407 can be an insulating layer. If the protective layer 407 is not an insulating layer, it will connect the p-type layer 107b and the n-type layer 405 of the device 110, which will eventually result in a short-circuit current. In this case, the protective layer 407 must be removed. Therefore, the protective layer 407 should be both transparent and insulating.

[0093] Furthermore, AlONx, AlNx, AlOx, SiOx, SiN, and SiON can passivate the surface of the device 110, especially the etched GaN crystal. Because the protective layer 407 covers the sidewalls of the device 110, selecting these materials is preferable to reduce current leakage from the sidewalls of the device 110. Furthermore, the smaller the size of the device 110, the greater the current leakage. Passivating the sidewalls of the device 110 is very important, especially in the isolation region.

[0094] (Forming a growth restriction mask) In one embodiment, a III-nitride based layer 105 is grown by ELO on a III-nitride substrate 101, such as an m-plane GaN substrate 101, patterned with a growth-limiting mask 102 made of SiO, where the III-nitride ELO layer 105 may or may not coalesce at 106 on top of the growth-limiting mask 102.

[0095] The growth-limiting mask 102 consists of striped open areas 103, and the SiO2 stripes of the growth-limiting mask 102 between the open areas 103 have a width of 1 μm to 20 μm and a spacing of 10 μm to 100 μm. If a non-polar substrate is used, the open areas 103 may be <0001> The open areas 103 are oriented along the [-1014] or

[1014] axis. If a semipolar (20-21) or (20-2-1) substrate is used, the open areas 103 are oriented parallel to the [-1014] or

[1014] axis, respectively. Other planes of the substrate may be used as well, with the open areas 103 oriented in other directions.

[0096] When using the III-nitride substrate 101, the present invention can obtain high-quality III-nitride semiconductor layers 105, 107. As a result, the present invention can also easily obtain a device 110 with a reduced defect density, such as a reduced dislocation and stacking fault.

[0097] Furthermore, these techniques can be used with heterosubstrates such as sapphire, SiC, LiAlO 2 , Si, Ga 2 O 3 , etc., as long as they allow growth of the ELO GaN-based layer 105 through the growth-limiting mask 102.

[0098] (Multiple epitaxial layers are grown on a substrate using growth-limiting masks) III-nitride semiconductor device layer 107 is grown by conventional methods on III-nitride ELO layer 105 in planar region 108. In one embodiment, MOCVD is used for epitaxial growth of III-nitride semiconductor layers, including III-nitride ELO layer 105 and III-nitride semiconductor device layer 107. The resulting III-nitride semiconductor layers 105, 107 are separated from each other because the MOCVD growth is stopped before III-nitride ELO layer 105 coalesces at 106. In one embodiment, III-nitride ELO layer 105 is made to coalesce, after which etching is performed to remove unwanted regions.

[0099] Trimethylgallium (TMGa), trimethylindium (TMIn), and triethylaluminum (TMAl) are used as III-element sources. Ammonia (NH3) is used as the source gas and supplies nitrogen. Hydrogen (H2) and nitrogen (N2) are used as carrier gases for the III-element sources. It is important to include hydrogen in the carrier gas to obtain a smooth surface epilayer.

[0100] Salt and bis(cyclopentadienyl)magnesium (CpMg) are used as n-type and p-type dopants. Pressure settings are typically 50-760 Torr. III-nitride semiconductor layers are generally grown at temperatures ranging from 700-1,250°C.

[0101] For example, the growth parameters include: TMG is 12 sccm, NH3 is 8 slm, carrier gas is 3 slm, SiH4 is 1.0 sccm, and the V / III ratio is about 7,700.

[0102] (ELO of Limited Area Epitaxy (LAE) Group III Nitride Layers) In the prior art, several pyramidal hillocks have been observed on the surface of m-plane III-nitride films following growth. See, for example, U.S. Patent Application Publication No. 2017 / 0092810. Furthermore, wavy surfaces and depressions appear on the growth surface, which worsen the surface roughness. This is a very serious problem. For example, according to some papers, a smooth surface can be obtained by controlling the deviation angle (>1 degree) of the substrate's growth surface and by using N carrier gas conditions. However, these conditions are very limited for mass production due to high production costs. Furthermore, GaN substrates have large deviation angle variations relative to their origin due to their fabrication method. For example, if a substrate has a large deviation angle distribution, it will have different surface morphologies at these points within the wafer. In this case, the yield is reduced due to the large deviation angle distribution. Therefore, it is necessary for the technique to be independent of the deviation angle distribution.

[0103] The present invention, as described below, solves these problems. 1. The growth area is limited by the area of ​​the growth limiting mask 102 from the edge of the substrate 101. 2. The substrate 101 is a non-polar or semi-polar III-nitride substrate 101 with a tilt angle ranging from -16 degrees to +30 degrees from the m-plane towards the c-plane. Alternatively, a heterosubstrate on which III-nitride based semiconductor layers are deposited can be used, with the layers having a tilt angle ranging from +16 degrees to -30 degrees from the m-plane towards the c-plane. 3. The island-shaped III-nitride semiconductor layers 105 and 107 have long sides that are perpendicular to the a-axis of the III-nitride semiconductor crystal. 4. During MOCVD growth, a hydrogen atmosphere can be used.

[0104] In the present invention, a hydrogen atmosphere can be used during non-polar and semi-polar growth. This condition is preferred because hydrogen can prevent excessive growth at the edges of the open area 103 from occurring in the initial growth stage.

[0105] These results were obtained under the following growth conditions:

[0106] In one embodiment, the growth pressure ranges from 60 to 760 Torr, but preferably from 100 to 300 Torr to obtain a wide width for the island-shaped III-nitride semiconductor layer, the growth temperature ranges from 900 to 1,200°C, the V / III ratio ranges from 10 to 30,000, the TMG is 2 to 20 sccm, the NH3 ranges from 0.1 to 10 slm, and the carrier gas is hydrogen gas only or both hydrogen and nitrogen gas. To obtain a smooth surface, the growth conditions for each plane need to be optimized by conventional methods.

[0107] After growth for about 2-8 hours, the III-nitride ELO layer 105 has a thickness of about 1-50 μm and a bar width of about 50-150 μm.

[0108] (Manufacturing elements) Device 110 is fabricated in planar surface region 108 by conventional methods, and various device 110 designs are possible. For example, μLEDs can be fabricated where front-end processing alone is sufficient to realize device 110, e.g., p-pads and n-pads can be fabricated along either the length or width of the wings of III-nitride ELO layer 105, as shown in FIG. 4A. Preferably, either a vertical configuration or pads along the length of the wings is chosen to avoid more growth times.

[0109] (Forming a structure for separating element units) The aim of this step is to prepare the III-nitride ELO layer 105 and III-nitride device layer 107 for isolation from the host substrate 101. By applying a selective etching mask, the III-nitride device layer 107 is separated from the host substrate 101 by etching regions 201, 202 to expose at least the growth limit mask 102.

[0110] The division can also be performed by scribing with a diamond-tipped scriber or a laser scriber (e.g., tools such as RIE (reactive ion etching) or ICP (inductively coupled plasma)), but is not limited to these methods, and other methods can also be used to isolate the element units.

[0111] To keep the isolated III-nitride device layer 107 on the host substrate 101 while performing regrowth, an epitaxial bridge 301 is proposed in the present invention. It is also possible to ensure that the isolated III-nitride device layer 107 remains on the host substrate 101 by modifying the etching mask. The region 201 directly connecting the III-nitride ELO layer 105 with the host substrate 101 has been modified in such a way that a non-epitaxial bridge 303 with the host substrate 101 still remains after exposing the growth limit mask 102 in the region 202, as shown in Figures 4H and 5E.

[0112] Furthermore, the epitaxial bridge 301 can help position the light-emitting aperture 111 away from the open area 103, which can reduce the number of defects contained in the light-emitting aperture 111. Aiming to keep the light-emitting aperture 111 away from the open area 103, the bridges 301, 303 can be made of any other material, such as a dielectric layer, a metal, a semiconductor, or an insulator. By using a side from the epitaxial bridge 301, the element 110 can be completely separated from the III-nitride layers 105, 107. In other words, the element 110 is placed on the growth-limiting mask 102. At this point, the III-nitride layers 105, 107 on the open area 103 still remain. In addition, the element 110 is connected to the III-nitride layers 105, 107 on the open area 103. In this way, the element 110 can be held on the growth-limiting mask 102. This allows the elements 110 to be fabricated away from the open area 103. This is preferable as it uses a low defect area for the elements 110.

[0113] (Regrowth of crystalline layer with epitaxial bridge) The present invention follows two approaches for regrowth: in one approach, only a thin p-layer is grown, and in another approach, the complete device structure layers are regrown on the isolated wings of the n-type III-nitride ELO layer 105.

[0114] These approaches have their own advantages. (a) Regrowth can repair plasma damage associated with forming light emitting structure 404 because regrowth temperatures are generally higher. (b) Crystalline layers damaged during plasma etching are exposed to a crystalline environment, thus allowing the damage to be repaired or the etched defects to be repaired. (c) When the regrowth is for the p-type layer 107b only, the active region 107a formation is uniform, which can lead to uniform wavelength emission across the wafer. (d) When regrowth is performed for the entire device layer 107, the growth temperature may be higher, thus leading to reduced crystal defects. (e) When regrowth is performed for only the p-type layer 107b, the layer 107b must be very thin; for example, a thin Mg-doped GaN layer 107b with a higher doping concentration can be grown using pulsed sputtering deposition. (f) The epitaxial bridge 301 can be stable at high temperatures. (g) Device 110 can be extracted from host substrate 101 by mechanically severing epitaxial bridges 301.

[0115] (The ELO III-nitride device layers are removed from the substrate) The epitaxial bridge 301 is very fragile, so ultrasound or a small impact is sufficient to sever the bridge 301. The completed suspension element 110 can be transferred from its host substrate 101 using the following method. 1. Elastomeric (PDMS) stamp: As shown in Figure 4M, the PDMS stamp 414 is sufficiently flexible to release the isolated III-nitride device layer 107 from its host substrate 101. Furthermore, it can be selectively released for transfer of the layer onto a target back panel 416, as shown in Figure 4M. 2. Vacuum Chuck: The present invention proposes a new method for detaching the isolated III-nitride device layer 107 from its host substrate 101. Because the III-nitride device layer 107 has a very weak connection to the host substrate 101, it is straightforward to use a vacuum-controlled chuck 701, as shown in schematic diagrams 700a1 and 700a2 in FIG. 7 , to remove the III-nitride device layer 107, as described in more detail below. In addition, localized repairs can be performed on the back panel 416 using the vacuum chuck 701 for selective detachment. Alternatively, a PDMS stamp 414 can also be used for selective detachment.

[0116] (The element is mounted on the display panel) The separated / isolated elements 110 are lifted off using the approaches described above, i.e., (1) PDMS stamp 414 or (2) vacuum chuck 701, and then mounted onto a display panel 416.

[0117] Use of a vacuum chuck to remove ELO III-nitride device layers and localized repair methods The present invention provides a solution to the problem of mass transfer of smaller light-emitting apertures 111, alternatively referred to as emissive inorganic pixels, when the targeted size is below 50 μm. μLEDs fabricated on the wings of the III-nitride ELO layer 105 can be removed as described above. In particular, these devices 110 preferably have larger wing areas of the III-nitride ELO layer 105 and smaller open areas 201; that is, the ratio between the wing area and the open area 201 of the III-nitride ELO layer 105 should be greater than 1, more preferably 5-10, and in particular, the open area 201 should be approximately 1-5 μm. Therefore, the devices 110 can be more easily removed from the III-nitride substrate 101 and transferred to an external carrier or processed in further steps in an easy manner.

[0118] The vacuum chuck 701 is a combination of at least two plates 702a, 702b, where the top plate 702a has a large vacuum hole 703a and the bottom plate 702b has a vacuum hole 703b with a dimension d1, which is slightly smaller than the element 110 to be lifted off from the host substrate 101, and the dimension d1 can be electrically or magnetically controlled to physically extract the isolated element 110 out of the host substrate 101.

[0119] A vacuum chuck 701 is placed over the isolated device 110 on the host substrate 101, and the device 110 is extracted out of the host substrate 101 by turning on the vacuum using a valve.

[0120] The device layer contained by chuck 701 is then placed onto a processed carrier plate 704 or attached directly onto the display back panel 416 .

[0121] (Definition of terms) (Group III nitride substrate) The III-nitride substrate 101 may comprise any type of III-nitride substrate, as long as the III-nitride substrate allows for the growth of the III-nitride semiconductor layers 105, 107, 108, 109 through the growth-limiting mask 102, and may comprise any GaN substrate 101 sliced ​​from a bulk GaN or AlN crystal substrate on the {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} plane, etc., or other plane.

[0122] (hetero substrate) Furthermore, the present invention can also use hetero-substrates. For example, a GaN template or other III-nitride semiconductor layer can be grown on a hetero-substrate such as sapphire, Si, GaAs, SiC, Ga2O3, etc., prior to the growth-limiting mask 102. The GaN template or other III-nitride semiconductor layer is typically grown on the hetero-substrate to a thickness of about 2-6 μm, and then the growth-limiting mask 102 is placed on the GaN template or other III-nitride semiconductor layer.

[0123] (growth restriction mask) The growth limiting mask 102 is made of a dielectric layer such as SiO2, SiN, SiON, Al2O3, AlN, AlON, MgF, ZrO2, TiN, etc., or a refractory or noble metal such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt, etc. The growth limiting mask 102 can be a layered structure selected from the above materials. It can also be a multi-stacking layer structure selected from the above materials.

[0124] In one embodiment, the thickness of the growth limiting mask 102 is approximately 0.05 to 3 μm. The width of the growth limiting mask 102 is preferably greater than 20 μm, and more preferably greater than 40 μm. The growth limiting mask 102 may be deposited by, but is not limited to, sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD), ion beam deposition (IBD), or the like.

[0125] On the m-plane freestanding GaN substrate 101, the growth limiting mask 102 has a plurality of open areas 103 extending in a second direction, periodically spaced apart, in a first direction parallel to the 11-20 direction of the substrate 101 and a second direction parallel to the 0001 direction of the substrate 101. The length of the open areas 103 is, for example, 200 to 35,000 μm, the width is, for example, 2 to 180 μm, and the spacing between the open areas 103 is, for example, 20 to 180 μm. The width of the open areas 103 is typically constant in the second direction, but can be varied in the second direction as needed.

[0126] On the c-plane freestanding GaN substrate 101, the open areas 103 are arranged in a first direction parallel to the 11-20 direction of the substrate 101 and in a second direction parallel to the 1-100 direction of the substrate 101.

[0127] On the semipolar (20-21) or (20-2-1) GaN substrate 101, the open areas 103 are oriented parallel to [-1014] and [10-14], respectively.

[0128] Alternatively, a heterosubstrate 101 can be used. When a c-plane GaN template is grown on a c-plane sapphire substrate 101, the open area 103 is in the same direction as the c-plane freestanding GaN substrate 101, and when an m-plane GaN template is grown on an m-plane sapphire substrate 101, the open area 103 is in the same direction as the m-plane freestanding GaN substrate 101. By doing this, the m-plane cleavage plane can be used to split the rod of device 110 with the c-plane GaN template, and the c-plane cleavage plane can be used to split the rod of device 110 with the m-plane GaN template, which is much more preferable.

[0129] (Group III nitride semiconductor layer) The III-nitride ELO layer 105 and the III-nitride semiconductor device layer 107 may contain In, Al, and / or B, as well as other impurities such as Mg, Si, Zn, O, C, H, and the like.

[0130] The III-nitride device layers 107 generally include three or more layers, including at least one of an n-type layer, an undoped layer, and a p-type layer. The III-nitride device layers 107 may include a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, etc. When the device 110 has multiple III-nitride semiconductor layers 105, 107, the distance between adjacent island-like III-nitride semiconductor layers 105, 107 is generally 30 μm or less, preferably 10 μm or less, but is not limited to these figures. In the semiconductor device 110, several electrodes are arranged at predetermined positions according to the type of the semiconductor device 110.

[0131] (separation length) The separation length L is formed using either an epitaxial bridge 301 or a non-epitaxial bridge 303. The separation length L keeps the light-emitting aperture 111 away from the open area 201 of the III-nitride ELO layer 105. The length L is designed to be at least 1 μm to avoid any edge damage, crystalline defects, etc. near the open area 201. A longer length ensures easy cutting of the element 110 when pressed with the PDMS stamp 414 or vacuum chuck 701 and better crystalline quality for the light-emitting aperture 111. In the case of the epitaxial bridge 301, the element 110 can be separated from the host substrate 101 using a cleavage plane of length L.

[0132] (Advantages of epitaxial lateral overgrowth) The island-shaped III-nitride semiconductor layers 105, 107 grown on the growth-limiting mask 102 from the striped open areas 103 of the growth-limiting mask 102 using the III-nitride ELO layer 105 have very high crystallinity.

[0133] Furthermore, two advantages can be obtained using III-nitride based substrates 101. One advantage is that, compared to the use of sapphire substrates 101, high quality III-nitride semiconductor layers 107, such as with very low defect densities, can be obtained on the wings of the III-nitride ELO layer 105.

[0134] The advantage of using heterosubstrates 101 such as sapphire (m-plane, c-plane), LiAlO2, SiC, Si, etc. for the growth of epilayers 105, 107 is that these substrates 101 are low-cost substrates, which is an important advantage for mass production.

[0135] In terms of the quality of the device 110, the use of a free-standing III-nitride-based substrate 101 is more preferable due to the reasons mentioned above. On the other hand, the use of a hetero-substrate 101 makes it cheaper and more scalable.

[0136] Also, because the growth limiting mask 102 and the III-nitride ELO layer 105 are not chemically bonded, the stress in the III-nitride ELO layer 105 can be relieved by sliding induced at the interface between the growth limiting mask 102 and the III-nitride ELO layer 105.

[0137] (flat surface area) The flat surface regions 108 are layers between the bent regions 109. Furthermore, the flat surface regions 108 are within the area of ​​the growth limiting mask 102.

[0138] Fabrication of the semiconductor device 110 is primarily performed on the flat surface region 108. The width of the flat surface region 108 is preferably at least 5 μm, and more preferably 10 μm or greater. The flat surface region 108 has a highly uniform thickness for each of the semiconductor layers.

[0139] (layer bending area) 2C illustrates the layer bending region 109. If the layer bending region 109, including the active layer 107a, remains within the device 110, some of the light emitted from the active layer 107a will be reabsorbed. As a result, it is preferable to remove at least a portion of the active layer 107a within the layer bending region 109 by etching.

[0140] From another perspective, the epitaxial layer in the flat surface region 108, excluding the open area 103, has a lower defect density than the epitaxial layer in the open area 103. Therefore, it is more preferable that the opening 111 be formed in the flat surface region 108, including over the wing region.

[0141] (semiconductor element) The semiconductor element 110 may be, for example, a Schottky diode, a light emitting diode, a semiconductor laser, a photodiode, a transistor, etc., but is not limited to these elements. The present invention is particularly useful for micro LEDs. The present invention is particularly useful for semiconductor laser elements, which require a smooth region for cavity formation.

[0142] (epitaxial bridge) Grown using ELO, the epitaxial bridge 301 is specially constructed to hold the III-nitride ELO and device layers 105, 107 during regrowth of the crystal layer environment. Examples of such structures are shown in Figures 3, 4F, and 5C.

[0143] Alternative Embodiments The following describes alternative embodiments of the present invention.

[0144] (First embodiment) The first embodiment discloses a method for fabricating a III-nitride based microdisplay 416 that includes a semiconductor device 110 .

[0145] In a first embodiment, as shown in FIG. 1, a base or host substrate 101 is first provided, and a growth-limiting mask 102 having a plurality of striped open areas 103 is formed on the substrate 101 .

[0146] In this embodiment, the island-shaped III-nitride ELO layer 105 is allowed to contact neighboring layers 105 to form a foundation layer for the desired devices 110. Device layers 107, such as multi-quantum well structures, waveguides, electron blocking layers, p-GaN, etc., are then grown on the III-nitride ELO layer 105. Devices 110, such as μLEDs, are fabricated on the wing regions of the III-nitride ELO layer 105, as illustrated in FIGS. 4 and 5 . Regrowth areas 408 are opened on the device layers 107, and the III-nitride ELO layer 105 and device layers 107 are then divided into individual devices 110 or groups of devices 110 by removing regions 201 and 202 and etching down to expose the underlying growth limiting mask 102. During the etching of regions 201 and 202, epitaxial bridges 301 are formed near region 201, as shown in FIG. 3 . At this stage, III-nitride ELO layer 105 and device layer 107 effectively have only epitaxial bridge 301 as their connection to host substrate 101, which prevents III-nitride ELO layer 105 and device layer 107 from separating from substrate 101 until desired.

[0147] The structure including epitaxial bridge 301 and regrowth area 408 along with protective layer 407 is sent to a regrowth chamber to form a thin highly doped p-GaN layer 409. Regrowth can help repair damage caused by etching in the plasma environment.

[0148] Because the device layer 107 has already formed below the regrowth area 408, it is recommended not to use an aggressive temperature growth environment to form the p-GaN layer 409. For example, pulsed sputtering deposition (PSD), pulsed laser deposition, or MBE can be used to grow the heavily Mg-doped p-GaN layer 409. These regrowth layers can help obtain improved current spreading within the p-GaN layer 409 and repair device damage that may occur during plasma etching.

[0149] Once regrowth is complete, the growth limiting mask 102 and protective layer 407 are etched using BHF or HF, leaving only the epitaxial layers 105, 107, as shown in Figure 4F.

[0150] A TCO layer 410 is capped over the light emitting area and annular p-pad and n-pad 411 are deposited as shown in Figure 4I.

[0151] The weakly attached III-nitride ELO layer 105 and device layer 107 are then transferred onto a desired carrier such as a display panel 416 using tools such as an elastomeric stamp 414, a vacuum chuck 701, etc. The display panel 416 can be used in several applications such as TVs, laptops, phones, AR / VR / MR headsets, HUDs, etc.

[0152] (Second embodiment) The second embodiment discloses a III-nitride based microdisplay 416 that includes the semiconductor device 110 .

[0153] In a first embodiment, as shown in FIG. 1, a base or host substrate 101 is first provided, and a growth-limiting mask 102 having a plurality of striped open areas 103 is formed on the substrate 101 .

[0154] In a second embodiment, the island-like III-nitride ELO layers 105 are allowed to contact neighboring layers 105 to form foundation or base layers for the desired devices 110. These base III-nitride ELO layers 105 are n-GaN layers. In this embodiment, device layers 107, such as multi-quantum well structures, waveguides, electron blocking layers, p-GaN, etc., are grown on or above the base III-nitride ELO layers 105 in a regrowth process.

[0155] Regrowth areas 408 are opened on the base n-GaN layer 105, and then III-nitride ELO layer 105 and device layer 107 are divided into individual devices 110 or groups of devices 110 by etching to expose the underlying growth-limiting mask 102 through removal of regions 201, 202. During the etching of regions 201, 202, epitaxial bridges 301 are formed near region 201, as shown in FIG. 3. At this stage, III-nitride ELO layer 105 and device layer 107 have only epitaxial bridges 301 as their only connection to host substrate 101, which prevents III-nitride ELO layer 105 and device layer 107 from separating from host substrate 101 until desired. The resulting pattern is shown in FIG. 5E.

[0156] The structure including the epitaxial bridge 301 with the protective layer 407 and the regrowth area 408 is sent to a regrowth chamber to regrow the device layers 107, such as the n-GaN layer, the multi-quantum well structure, the waveguide, the electron blocking layer, the p-GaN layer, etc. Regrowth can help repair damage caused by etching in the plasma environment.

[0157] In this process, since regrowth includes growing the active region 107a, higher temperatures may be used than in the process described in the first embodiment. Growth at higher temperatures enhances the crystalline quality of the layer 107, and thereby improved performance of the device 110 may be observed.

[0158] For example, MOCVD or MBE can be used for the regrowth. These regrowth layers 107 can help repair damage to the element 110 that may occur during plasma etching.

[0159] Once regrowth is complete, the growth limiting mask 102 and protective layer 407 are etched using BHF or HF, leaving only the epitaxial layers 105, 107, as shown in Figure 5I. Before removing the growth limiting mask 102, one may choose to leave the protective layer 407 by applying a TCO layer 410. The resulting bridge 301 structure of this approach is shown in Figure 5I.

[0160] The weakly attached III-nitride ELO layer 105 and device layer 107 are then transferred onto a desired carrier, which may be a display panel 416, using tools such as an elastomeric stamp 414, a vacuum chuck 701, etc. The display panel 416 can be used in several applications such as a TV, a laptop, a phone, an AR / VR / MR headset, a HUD, etc.

[0161] (Third embodiment) The third embodiment provides a structure for electrical injection. In the first and second embodiments, electrical injection is selected as a post-injection. However, the back interface 601 of the III-nitride ELO layer 105 can be used as one of the electrical injection pads, which leads to a vertical configuration of electrical injection, as shown in FIG. 6.

[0162] (Fourth embodiment) The fourth embodiment describes a method for removing isolated elements 110 from their host substrate 101 using a PDMS stamp 414. Because the isolated III-nitride ELO layer 105 has only the epitaxial bridge 301 as its connection to the host substrate 101, this connection can be easily severed using the movement of the PDMS stamp 414. As illustrated in FIG. 4M , the PDMS stamp 414 can also be designed to remove all of the isolated III-nitride ELO layer 105 and device layer 107 together, or to selectively remove only some of the isolated III-nitride ELO layer 105 and device layer 107.

[0163] (Fifth embodiment) The fifth embodiment uses a vacuum chuck 701 to remove the isolated III-nitride ELO layer 105 and device layer 107 from the host substrate 101. The vacuum chuck 701 is designed to include at least two plates 702a, 702b. The plate 702b includes a finite-size hole 703b, which is smaller than the size of the device 110. The plate 702a has a larger-size hole 703a to control the holding process of the plate 702b. The vacuum hole 703a can be controlled by either a mechanical method, an electromagnetic method, or a hydraulic method.

[0164] As shown in FIG. 7, vacuum chuck 701 can be used to remove only selected elements 110 by closing unwanted vacuum holes 703b on plate 702b.

[0165] (Sixth embodiment) In the sixth embodiment, an AlGaN layer is used as the island-like III-nitride ELO layer 105 and the III-nitride device layer 107, which can be grown on a variety of tilt substrates 101. The AlGaN layer can have a very smooth surface and can be removed from the variety of tilt substrates 101 as the island-like III-nitride ELO layer 105 and the device layer 107.

[0166] In this case, an active laser emitting UV-light (UV-A or UV-B or UV-C) can be grown on the AlGaN ELO layer 105. After removal, the AlGaN ELO layer 105 with the active layer 107a appears as a UV device 110 with a pseudo AlGaN substrate 101. By doing this, a high-quality UV-LED display panel 416 can be obtained, whose applications can lead to sterilization, lighting, etc.

[0167] (Seventh embodiment) In a seventh embodiment, III-nitride ELO layers 105 are grown on various tilt substrates 101. The tilt orientations range from 0 to +15 degrees and 0 to -28 degrees from the m-plane toward the c-plane. The present invention allows the rods of elements 110 to be removed from various tilt substrates 101. This is a major advantage of the present technique, as various tilt orientation semiconductor planar elements 110 can be realized without changing the fabrication process.

[0168] (Eighth embodiment) In an eighth embodiment, III-nitride ELO layers 105 are grown with two different miscut orientations on a c-plane substrate 101. The III-nitride ELO and device layers 105, 107 are then removed after processing the desired device 110 using the invention described herein.

[0169] (Ninth embodiment) In the ninth embodiment, a sapphire substrate 101 with a buffer layer is used as the heterosubstrate. The resulting structure is similar to the first and second embodiments, but uses a sapphire substrate 101 and a buffer layer. In this embodiment, the buffer layer may also include an additional n-GaN layer or undoped GaN layer. The buffer layer is grown at a low temperature of about 500-700°C. The n-GaN layer or undoped GaN layer is grown at a higher temperature of about 900-1,200°C. The total thickness is about 1-3 μm. A growth-limiting mask 102 is then placed on the buffer layer and the n-GaN layer or undoped GaN layer.

[0170] On the other hand, it is not necessary to use a buffer layer. For example, the growth-limiting mask 102 can be placed directly on the heterosubstrate 101. Then, the III-nitride ELO layer 105 and / or the III-nitride device layer 107 can be grown.

[0171] (Tenth embodiment) The tenth embodiment is directed to a non-epitaxial bridge 303. The processes described in the first and second embodiments can be realized without using the epitaxial bridge 301. The regions 201 and 202 separate the device layer 107 and isolate the device 110 from the host substrate 101, as shown in FIG. 3B . The non-epitaxial bridge 303 is then placed over the device layer 107 before reintroducing the device layer 107 into the crystal growth chamber. The material of the non-epitaxial bridge 303 can be similar to or different from the material of the growth-limiting mask 102. The primary function of the non-epitaxial bridge 303 is to keep the device 110 above the growth-limiting mask 102 when it is introduced into the crystal regrowth chamber. The separation length L of the bridge 303 also allows the light-emitting aperture 111 to be designed entirely on the wing region of the III-nitride ELO layer 105. The separation length L can be measured in the same way as for the epitaxial bridge 301 to avoid crystal defects from region 201. At least 1 μm must be left between region 201 and the edge of element 110.

[0172] As in the case of epitaxial bridge 301, only p-type layer 409 regrowth, as described in the first embodiment, or complete device layer 107 growth, as described in the second embodiment, can be performed even in the case of non-epitaxial bridge 303, as shown in FIG. 3B.

[0173] (Process Step) FIG. 8 is a flow chart illustrating a method for fabricating a semiconductor device in accordance with the present invention.

[0174] Block 801 represents the step of forming a III-nitride ELO layer 105, which may be coalesced or non-coalesced.

[0175] Block 802 represents the step where III-nitride ELO layer 105 comprises only n-GaN layers.

[0176] Block 803 represents the step of forming lateral electrode structures, and block 804 represents the step of forming vertical electrode structures.

[0177] Both blocks 805 and 806 represent the step of opening up an area on the surface of the wing region of III-nitride ELO layer 105 .

[0178] Block 807 represents the step of forming epitaxial or non-epitaxial bridges 301, 303.

[0179] Block 808 represents the step of performing regrowth of device layer 107 .

[0180] Block 809 represents the step of forming a TCO layer 410 on the device layer 107 .

[0181] Block 810 represents the step of placing electrical pads 411 on the resulting device 110 .

[0182] Block 811 represents the step of extracting the device 110 from the substrate 101 after severing the connection to the substrate 101 consisting of epitaxial or non-epitaxial bridges 301, 303.

[0183] Block 812 represents the step of placing the device 110 on the display panel 416 or another carrier or submount.

[0184] Block 813 represents the step of forming III-nitride device layer 107 on III-nitride ELO layer 105 .

[0185] Block 814 represents the step of forming lateral electrode structures, and block 815 represents the step of forming vertical electrode structures.

[0186] Both blocks 816 and 817 represent the step of opening an area on the surface of device layer 107 above the wing regions of III-nitride ELO layer 105 .

[0187] Block 818 represents the step of forming epitaxial or non-epitaxial bridges 301, 303.

[0188] Block 819 represents the step of performing regrowth of the highly doped p-GaN layer 409 .

[0189] Block 820 represents the step of forming a TCO layer 410 on the device layer 107 .

[0190] Block 821 represents the step of placing electrical pads 411 on the resulting device 110 .

[0191] Block 822 represents the step of extracting the device 110 from the substrate 101 after severing the connection to the substrate 101 consisting of the epitaxial or non-epitaxial bridges 301, 303.

[0192] Block 823 represents the step of mounting the device 110 on the display panel 416 or another carrier or submount.

[0193] (Conclusion) This concludes the description of the preferred embodiments of the invention. The foregoing description of one or more embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be limited not by the detailed description provided herein, but rather by the claims appended hereto.

Claims

[Claim 1] The invention described in this specification.

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