Methods for fabricating nonpolar and semipolar devices using epitaxial lateral overgrowth.

Abstract

A method for fabricating a semiconductor device includes forming a growth-limiting mask on or above a group III nitride substrate, and growing one or more island-shaped group III nitride semiconductor layers on the group III nitride substrate using the growth-limiting mask. The group III nitride substrate has an in-plane off-angle orientation distribution of more than 0.1°, and the off-angle orientation of the m-plane oriented crystalline surface plane is within a range of about +28° to about -47° toward the c-plane. At least one long side and one short side of the island-shaped group III nitride semiconductor layer is perpendicular to the a-axis of the island-shaped group III nitride semiconductor layer. The island-shaped group III nitride semiconductor layer is not merged with neighboring island-shaped group III nitride semiconductor layers.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit under 35 U.S.C. §119(e) of pending and commonly assigned U.S. Provisional Patent Application No. 62 / 650,487, filed March 30, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled "METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES BY USING LATERAL OVERGROWTH," and bearing attorney docket number G&C30794.0680USP1 (UC2018-427-1), which is incorporated herein by reference.

[0002] FIELD OF THE INVENTION The present invention relates to a method for fabricating non-polar and semi-polar devices using epitaxial lateral overgrowth. [Background technology]

[0003] Several device manufacturers have been using nonpolar and semipolar GaN substrates to produce laser diodes (LDs) and light-emitting diodes (LEDs) for lighting, optical storage, etc. The use of nonpolar and semipolar GaN substrates can avoid strong pyroelectric and piezoelectric fields, which can lead to significant improvements in radiation efficiency. However, epitaxial growth of III-nitrides along nonpolar and semipolar directions is more difficult than growth along the polar c-plane direction.

[0004] According to Patent Document 1, numerous pyramidal hillocks (small hillocks) have been observed on the surface of epitaxially grown nonpolar m-plane III-nitride films. Furthermore, wavy surfaces appear, worsening the surface roughness. This surface roughness poses a severe problem for fabricating laser structures on such surfaces, as it can cause optical gain uniformity and device process fluctuations, which can reduce the yield of the device process. Furthermore, the reliability of the laser is affected by hillocks and large surface roughness. For example, see Non-Patent Document 1.

[0005] According to this paper, the growth conditions for obtaining a smooth surface are very narrow and strictly limited. One problem is that the surface morphology is affected by the off-axis orientation, and as is well known, GaN wafers have a wide in-plane distribution of the off-axis orientation. Therefore, the surface morphology varies significantly within the wafer. In this case, the yield is low, which is a major problem. See, for example, Non-Patent Document 2.

[0006] Furthermore, according to this paper, the facet dependence of hillock leakage current was observed under reverse bias conditions, indicating that the facet dependence of hillocks on carrier and oxygen concentrations caused leakage current distribution. This leakage current distribution is problematic when fabricating devices such as LEDs, laser diodes, and power devices such as Schottky barrier diodes (SBDs) or metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0007] Another problem is that epilayers grown on nonpolar and semipolar III-nitride substrates over growth-limiting masks can coalesce in the center of the open areas of the mask, resulting in concave regions or depressions in the epilayer islands near their centers. Under other growth conditions, convex regions or bumps can appear in the epilayer islands near their centers. In either case, problems arise when attempting to obtain epilayers with flat surfaces. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] US Patent Application Publication No. 2017 / 0092810 [Non-patent literature]

[0009] [Non-Patent Document 1] Applied Physics Letters 91, 191906 (2007) [Non-patent document 2] Physica Status Solidi (a), Volume 214, Issue 8, 1600829 (2047) [Non-patent document 3] Phys. Rev. B 79, 241308(R) Summary of the Invention [Problem to be solved by the invention]

[0010] Thus, there is a need in the art for an improved method for planarizing epilayers on non-polar and semi-polar substrates using epitaxial lateral overgrowth (ELO), which the present invention fulfills. [Means for solving the problem]

[0011] To overcome the limitations of the prior art described above, as well as other limitations that will become apparent upon reading and understanding this specification, the present invention discloses a method for fabricating a semiconductor device, comprising forming a growth constraining mask on or over a III-nitride substrate, wherein the III-nitride substrate has an in-plane off-angle orientation distribution greater than 0.1° and an off-angle orientation of an m-plane crystalline surface plane within a range of about +28° to about −47° toward the c-plane, and growing one or more island-shaped III-nitride semiconductor layers on the III-nitride substrate using the growth constraining mask, and then removing the island-shaped III-nitride semiconductor layers from the III-nitride substrate.

[0012] The resulting island-shaped III nitride semiconductor layer has an m-plane orientation crystalline surface plane with just orientation and off-angle orientation, the off-angle orientation of the m-plane orientation crystalline surface plane being within a range of about +28° to about −47° relative to the c-plane direction, at least one long side and one short side of the island-shaped III nitride semiconductor layer having the long side perpendicular to the a-axis of the island-shaped III nitride semiconductor layer, and not merging with neighboring island-shaped III nitride semiconductor layers.

[0013] The III-nitride semiconductor island has an emitting region, and the emitting region is located at least 1 μm from an edge of the layer camber region of the III-nitride semiconductor island, and the emitting region is located more than 5 μm from an edge of the top surface of the III-nitride semiconductor island.

[0014] The island-shaped III-nitride semiconductor layer has an edge growth region, and its height is less than 0.2 μm and its width is less than 5 μm.

[0015] The island-shaped III-nitride semiconductor layer also has an isolation region, where an n-electrode is formed.

[0016] The present invention also discloses a method for growing smooth III-nitride epilayers on semipolar and nonpolar III-nitride substrates using ELO to reduce or eliminate pyramidal hillocks, wavy surfaces, and concave or convex regions.

[0017] In some embodiments, it will be appreciated that edges in a substrate can degrade the surface roughness, making it necessary to separate growth regions (e.g., open areas in a growth-limiting mask) from the substrate edges. In the present invention, growth regions are separated by a growth-limiting mask.

[0018] Furthermore, rough surfaces can occur after epitaxial growth using metal-organic chemical vapor deposition (MOCVD) as a result of pits and defects appearing on the substrate surface. This has been known for some time. Even a single pit can affect the surface roughness over a large area. However, isolating each growth region prevents the surface roughness from worsening in neighboring regions. For semipolar and nonpolar epitaxial growth, it is important to isolate the growth region from the edge of the substrate to avoid affecting a large area.

[0019] In other words, the growth region is isolated by surrounding it with a growth restriction mask. For example, the growth restriction mask may be a dielectric film such as SiO2, SiN, HfO2, Al2O3, MgF, W, Mo, or a metal. Furthermore, multiple layers selected from these materials may be used as the growth restriction mask.

[0020] A group III nitride layer grown using the ELO method is called an ELO-group III nitride layer. When growing this ELO-group III nitride layer using MOCVD or HVPE, hydrogen gas is included in the carrier gas flow.

[0021] When ELO-III nitride layers coalesce, fluctuations in their surface roughness occur, and many stacking faults and misfit dislocations are generated in the coalescence region.

[0022] Therefore, in the present invention, the growth of an ELO-III nitride layer is stopped before neighboring islands coalesce, resulting in a planar region of the ELO-III nitride layer that is substantially hillock-free. III-nitride semiconductor device layers are then grown on the ELO-III nitride layer, and the III-nitride semiconductor device layers are then removed from the III-nitride substrate. Because the MOCVD growth was stopped before coalescence occurred, they become separated from each other. This method produces planar surface and device layers with high yield.

[0023] The present invention can be used with III-nitride substrates or hetero-substrates. The use of III-nitride substrates is more preferred in the present invention, as it allows for obtaining high-quality III-nitride-based semiconductor layers and avoids substrate warping or bending during epitaxial growth. The present invention also allows for low-defect density devices.

[0024] Any III-nitride based substrate or heterosubstrate, such as sapphire, SiC, LiAlO2, Si, etc., can be used as long as it allows growth of III-nitride based semiconductor layers through a growth-limiting mask.

[0025] Furthermore, the III-nitride based semiconductor layers and III-nitride based substrates may also contain Al, In, and B as well as other impurities such as Mg, Si, O, C, H, and the like.

[0026] ELO-III nitride layers are epitaxially grown on III-nitride substrates in open areas and / or via intermediate layers in the open areas. The quality of the ELO-III nitride layers and III-nitride semiconductor device layers is exceptionally high, and devices comprising these island-like III-nitride-based semiconductor layers are exceptionally high quality. Furthermore, unlike hillocks that often appear on the epilayer surface after epilayer growth on nonpolar and semipolar substrates, these island-like III-nitride semiconductor layers have a smooth surface morphology without hillocks.

[0027] In MOCVD and HVPE, it is recommended to use a carrier gas containing hydrogen gas. Hydrogen plays a crucial role in the initial growth stage. Prior art has shown that hydrogen carrier gas can deteriorate the surface morphology during GaN layer growth by MOCVD. However, the situation is different if the growth area is surrounded by a growth confinement mask.

[0028] The hydrogen-containing carrier gas effectively etches the edges of the epilayer in the open areas, preventing the epilayer from beginning to grow on either side of the open area.

[0029] If the carrier gas does not contain hydrogen, multiple epilayer cores will form on either side of the open area. Further growth will cause these epilayer cores to coalesce at or near the center of the open area, resulting in the appearance of recessed regions in the ELO-III nitride layer. This growth has occurred on a variety of nonpolar and semipolar planes.

[0030] Alternatively, a carrier gas containing hydrogen gas may be used, so that the epilayer core is formed at or near the center of the open area in the early growth stage, resulting in an ELO-III nitride layer without any recessed regions or pyramidal hillocks, and with a very flat and smooth surface.

[0031] For the reasons stated above, it is advisable to use a hydrogen-containing carrier gas when growing ELO-III nitride layers, at least in the initial stages of growth. Furthermore, the carrier gas can be hydrogen gas alone or a mixture of hydrogen and nitrogen gases.

[0032] The present invention also allows the island layers to be removed from their substrates. Homoepitaxial layers are difficult to remove from substrates because there is no heterointerface between the homoepitaxial layer and the substrate surface. However, the present invention allows the homoepitaxial island layers to be removed from substrates quickly and easily.

[0033] For example, the substrate can be removed by using a growth-limiting mask, such as a dielectric film or metal, such as SiO2, SiN, HfO2, Al2O3, MgF, etc. The interface between the growth-limiting mask and any subsequent III-nitride layers grown on the mask by ELO has low bonding strength. The bond area (open area width) can be controlled to be larger or smaller than the chip size. Moreover, the ELO method provides a cleavage point and cleavage interface. Therefore, it is easy to peel the homoepitaxial layer from the substrate.

[0034] Furthermore, these methods use cleavage on the m-plane, which is the easiest cleavage plane among GaN planes. This method also allows for easy determination of the cleavage point. For example, the cleavage point can be located at the edge of the growth-limiting mask. One improvement is to dissolve the mask using hydrofluoric acid (HF), buffered HF (BHF), or other etchants before removing the substrate.

[0035] The wafer is then bonded to a support substrate using low-temperature melting metal and / or solder, and the metal is dissolved with an etchant. The bond is a III-nitride layer on a III-nitride substrate. The support substrate can have a different thermal expansion than the III-nitride substrate. After bonding, the two substrates are heated or removed. The difference in thermal expansion imparts stress to the III-nitride layer bonded to the support substrate. This stress is applied to the portion of the III-nitride layer between the III-nitride layer and the substrate. Cleavage begins at the cleavage point at the edge of the growth limiting mask. Eventually, the cleavage ends up on the opposite side of the cleavage point. However, a trigger is required to initiate the cleavage.

[0036] As in the above case, stress due to differential thermal expansion may be used to trigger cleavage. However, there are cases where the use of such stress is unnecessary. For example, ultrasonic waves may be used to trigger cleavage. When mechanical removal, such as ultrasonic cleavage, is possible, the substrate can be removed quickly and with very little stress due to the m-plane cleavage. Furthermore, the wedge-shaped cleavage point makes it easy to identify the cleavage point. Furthermore, this shape of the cleavage point is important for achieving high yields.

[0037] Using these methods, device layers can be easily removed from wafers and III-nitride-based substrates, including large wafers, for example, wafers larger than 2 inches (1 inch = approximately 2.5 cm).

[0038] In addition, the island-shaped III-nitride-based semiconductor layers do not coalesce with each other, and internal strain is released, thereby avoiding the occurrence of any cracks.

[0039] As is the main object of the present invention, even when the III-nitride-based substrate or hetero-substrate has a wide in-plane distribution of off-angle orientations, a large-area smooth surface free from hillocks and wavy roughness can be obtained.

[0040] In the present invention, the island III-nitride layer is not necessarily removed from the substrate, but the above-described process can be used to remove the island III-nitride layer from the substrate.

[0041] In the drawings referred to below, like reference numerals designate corresponding parts throughout. [Brief explanation of the drawings]

[0042] [Figure 1] 1 is a schematic diagram of a structure according to one embodiment of the present invention, comprising a substrate and various layers deposited thereon; [Figure 2a] 1A-1C are schematic diagrams depicting the creation of a structure according to one embodiment of the present invention. [Figure 2b] 1A-1C are schematic diagrams depicting the creation of a structure according to one embodiment of the present invention. [Figure 2c] 1A-1C are schematic diagrams depicting the creation of a structure according to one embodiment of the present invention. [Figure 2d] 1A-1C are schematic diagrams depicting the creation of a structure according to one embodiment of the present invention. [Figure 2e] 1A-1C are schematic diagrams depicting the creation of a structure according to one embodiment of the present invention. [Figure 2f] 1A-1C are schematic diagrams depicting the creation of a structure according to one embodiment of the present invention. [Figure 3] 1A and 1B are schematic diagrams illustrating the growth of a semiconductor layer on a growth-limiting mask according to an embodiment of the present invention. [Figure 4] 1A and 1B are schematic diagrams depicting a growth-limiting mask according to one embodiment of the present invention; [Figure 5] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 6a] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 6b] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 6c] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 6d] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 6e] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 6f] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 6g] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 6h] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 6i] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 7a] FIG. 1 is a schematic diagram depicting a growth limiting mask in accordance with an embodiment of the present invention. [Figure 7b] FIG. 1 is a schematic diagram depicting a growth limiting mask in accordance with an embodiment of the present invention. [Figure 7c] FIG. 1 is a schematic diagram depicting a growth limiting mask in accordance with an embodiment of the present invention. [Figure 8a] 1A-1D are schematic diagrams depicting a device structure and its fabrication according to one embodiment of the present invention. [Figure 8b] 1A-1D are schematic diagrams depicting a device structure and its fabrication according to one embodiment of the present invention. [Figure 9a] 1A-1C are schematic diagrams depicting a structure removal process according to one embodiment of the present invention. [Figure 9b] 1A-1C are schematic diagrams depicting a structure removal process according to one embodiment of the present invention. [Figure 9c] 1 is a photograph of a structure removed in accordance with one embodiment of the present invention; [Figure 10a] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 10b] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 10c] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 10d] 1 is a photograph in place of a drawing illustrating experimental results according to an embodiment of the present invention. [Figure 11a] FIG. 1 is a schematic diagram depicting crystal orientation according to an embodiment of the present invention. [Figure 11b] FIG. 1 is a schematic diagram depicting crystal orientation according to an embodiment of the present invention. [Figure 12] 1 is a schematic diagram depicting a device structure according to one embodiment of the present invention; [Figure 13] 1 is a series of photographs illustrating experimental results according to the present invention. [Figure 14a] 1A and 1B are schematic diagrams and photographs used as substitutes for drawings illustrating crystal orientations according to one embodiment of the present invention. [Figure 14b] 1A and 1B are schematic diagrams and photographs used as substitutes for drawings illustrating crystal orientations according to one embodiment of the present invention. [Figure 15]15(a) and (b) are schematic diagrams depicting a semiconductor growth structure according to one embodiment of the present invention, and (c) is a photograph of the structure of FIG. 15(b) according to one embodiment of the present invention. [Figure 16] 1A and 1B are schematic diagrams and photographs illustrating experimental results according to an embodiment of the present invention. [Figure 17] 1(a) to 1(c) are schematic diagrams illustrating the growth of a semiconductor layer on a growth limiting mask according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0043] The following description of the preferred embodiment refers to specific embodiments in which the present invention may be practiced, and it is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0044] [Overview] The method for fabricating semiconductor devices described in this invention provides a smooth, planar surface for epitaxial III-nitride layers grown on a non-polar or semi-polar III-nitride substrate, and then fabricates semiconductor devices on that surface.

[0045] In one embodiment, the method comprises: forming a growth-limiting mask having a plurality of striped open areas directly or indirectly on a substrate, for example, a group III nitride substrate or a hetero substrate; The in-plane off-angle orientation distribution of the substrate is greater than 0.1°, and the off-angle orientation of the m-plane oriented crystalline surface plane is within the range of +28° to -47° toward the c-plane, and A process in which the long side of the long and short sides of the open areas is perpendicular to the a-axis; a step of growing one or more island-shaped group III nitride semiconductor layers on the substrate using the growth-limiting mask; the island-shaped III-nitride-based semiconductor layer is grown in a hydrogen atmosphere; and the direction of growth is parallel to the stripe-shaped open areas of the growth limiting mask so that the islands of III-nitride-based semiconductor layer do not coalesce; removing the island-shaped III-nitride semiconductor layer from the III-nitride substrate; It has.

[0046] The resulting island-shaped III nitride semiconductor layer has an m-plane oriented crystalline surface plane with just-oriented and off-angle orientations, the off-angle orientation of the m-plane oriented crystalline surface plane being within a range of about +28° to about −47° relative to the c-plane direction, at least one long side and one short side of the island-shaped III nitride semiconductor layer having the long side perpendicular to the a-axis of the island-shaped III nitride semiconductor layer, and not merging with neighboring island-shaped III nitride semiconductor layers.

[0047] The III-nitride semiconductor island has an emitting region that is at least 1 μm from an edge of the layer warp region of the III-nitride semiconductor island and more than 5 μm from an edge of the top surface of the III-nitride semiconductor island.

[0048] The island-shaped III-nitride semiconductor layer has an edge growth region, and the edge growth region has a height of less than 0.2 μm and a width of less than 5 μm.

[0049] The island-shaped III nitride semiconductor layer also has an isolation region, on which an n-electrode is formed.

[0050] Devices fabricated using the island-shaped III-nitride semiconductor layer can be light-emitting diodes (LEDs), laser diodes (LDs), Schottky barrier diodes (SBDs), or metal-oxide-semiconductor field-effect transistors (MOSFETs), which are processed on the flat surface regions and / or open areas.

[0051] [Semiconductor structure and manufacturing method] FIG. 1 is a schematic diagram illustrating a semiconductor structure according to one embodiment of the present invention, the structure including a substrate 101, a growth-limiting mask 102, an open area 103, a no-growth region 104, an ELO-III-nitride layer 105, a III-nitride semiconductor device layer 106, a flat surface region 107, a layer bow region 108, and a III-nitride semiconductor island 109 (formed on the flat surface region 107 and the layer bow region 108), e.g., having a light-emitting region 110.

[0052] The method for fabricating this semiconductor structure includes the following steps.

[0053] 1. ELO + Group III nitride semiconductor layer As shown in FIG. 2(a), a III-nitride layer 105, such as a GaN layer, is grown by ELO on a substrate 101 that is patterned with a growth-limiting mask 102 made of SiO 2 .

[0054] The substrate 101 may be, for example, a GaN substrate, an AlN substrate, an m-plane sapphire substrate, etc. One embodiment uses a GaN substrate 101, and the growth plane is an m-plane having an off-angle of −47° to +47° toward the c-plane (0001).

[0055] The width of the patterned SiO2 constituting the growth limiting mask 102 is 20 μm, and the spacing is 150 μm. The SiO2 stripes of the growth limiting mask 102 are <0001> The ELO-III nitride layers 105 are aligned along the axis so as not to coalesce on top of the SiO2 of the growth limiting mask 102. Then, epitaxial layers including III nitride semiconductor device layers 106 are grown, and flat surface regions 107 and layer bow regions 108 appear, generating island-shaped III nitride semiconductor layers 109, such as GaN layers, AlGaN layers, AlInGaN layers, etc.

[0056] Then, an LD device can be formed by performing a ridge formation process on the flat surface region 107 of the island-shaped III nitride semiconductor layer 109. Alternatively, an LED device or other device may be fabricated.

[0057] 2. Dissolve the growth limiting mask by wet etching As shown in Figure 2(b), the SiO2 growth limiting mask 102 is removed by dissolving it using a chemical solution such as hydrofluoric acid (HF), buffered HF (BHF), etc. This facilitates cleaving the device from the GaN substrate 101. It is best to remove the epitaxial layers from the substrate 101 after this process.

[0058] 3. TCOp pad deposition + ridge formation process 2(c), a ZrO layer 201 is patterned and a top p-contact 202, such as a TCO (transparent conductive oxide), is deposited on the devices, followed by a p-pad 203. Additionally, p-AlGaN cladding layers and electrodes can be used, although the invention is not limited to these structures.

[0059] 4. Bonding the support substrate As shown in FIG. 2(d), the devices are flip-chip bonded to a carrier wafer (Si, Cu, Cu-W, etc.) as a support substrate 204 using metal-to-metal bonding or soldering techniques.

[0060] 5. Heat the support substrate 2(e), the support substrate 204 is heated to detach the devices from the substrate 101 at the cleave point 205 and across the cleave plane 206. Alternatively, removing the heat from the support substrate 204 can accomplish this function.

[0061] 6.N electrode deposition As shown in Figure 2(f), a backside n-contact 207 is deposited on the devices, such as TCO, Ti / Al, Ti / Au, Hf / Al / Mo / Au, etc., although the n-contact 207 is not limited to these materials.

[0062] 6. Chip scribing As shown in Figures 3(a) and 3(b), chip scribing can be performed to separate the devices; Figure 3(a) shows a top view of the flat surface region 107, the layer bow region 108, the island-like III-nitride-based semiconductor layer 109, and the separating non-growth region 104, while Figure 3(b), a partial enlargement of Figure 3(a), shows additional features of the LD device, such as the ridge stripe structure 301, the etched mirror region 302, and the chip scribe line 303.

[0063] [Term definition] (III-nitride-based substrate) Any III-nitride substrate 101 sliced ​​from a bulk GaN or AlN crystal along the {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} plane, or other planes can be used, as long as it allows growth of a III-nitride-based semiconductor layer through the growth-limiting mask 102. The off-angle orientation of the bulk GaN substrate is 0° to ±47° from the m-plane toward the c-plane.

[0064] The III-nitride based substrate 101 and bulk GaN may contain Al, In, B, etc.

[0065] (III-nitride-based semiconductor layer) Within the III-nitride based semiconductor layers are ELO-III-nitride layers 105, III-nitride semiconductor device layers 106, and island-like III-nitride based semiconductor layers 109. These III-nitride based semiconductor layers may contain In, Al, and / or B, as well as other impurities such as Mg, Si, Zn, O, C, H, etc.

[0066] The ELO-III nitride layer 105 is generally composed of a GaN layer, although other III nitride layers may also be used.

[0067] The III-nitride semiconductor device layers 106 generally include two or more layers, including at least one of an n-type layer, an undoped layer, and a p-type layer, and may include one or more GaN layers, AlGaN layers, InGaN layers, AlGaInN layers, etc.

[0068] The island-shaped III-nitride-based semiconductor layer 109 is typically formed with side surfaces along the (1-10a) plane (where a is any integer), the (11-2b) plane (where b is any integer), or a crystallographically equivalent plane thereto, or the side surfaces of the island-shaped III-nitride semiconductor layer 109 include the (1-10a) plane (where a is any integer).

[0069] The distance between adjacent island-shaped group III nitride semiconductor layers 109 is generally 30 μm or less, preferably 10 μm or less, but is not limited to these values. The distance between the island-shaped group III nitride semiconductor layers 109 preferably becomes the width of the non-growth region 104.

[0070] As shown in FIGS. 4(a) and 4(b), the island-shaped group III nitride semiconductor layer 109 has short sides 401 and long sides 402, and the long sides 402 are perpendicular to the a-axis.

[0071] According to various embodiments, the island-shaped III-nitride semiconductor layers 109 are used to fabricate devices such as, but not limited to, light emitting diodes, laser diodes, Schottky diodes, photodiodes, transistors, etc. The present invention is particularly useful for micro-LEDs and LDs, such as edge-emitting lasers (EELs) and vertical-cavity surface-emitting lasers (VCSELs).

[0072] The number and arrangement of the electrodes depend on the type of semiconductor device, and the electrodes are usually arranged in predetermined locations.

[0073] (growth restriction mask) The growth limiting mask 102 is composed of a dielectric layer such as SiO2, SiN, SiON, Al2O3, AlN, AlON, or MgF, or a refractory or noble metal such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, or Pt. The growth limiting mask 102 may have a laminate structure selected from the above-listed materials. It may also have a multi-layer laminate structure selected from the above-listed materials.

[0074] In one embodiment, the growth limiting mask 102 has a thickness of about 0.05 to 3 μm. The mask width is preferably greater than 20 μm, and more preferably greater than 40 μm.

[0075] (Effect of hydrogen etching) In the present invention, the carrier gas can contain hydrogen gas. Hydrogen gas has the effect of etching the GaN layer or slowing down its growth rate. The width of the growth limiting mask 102 affects this effect. Because the GaN layer does not grow on the growth limiting mask 102, hydrogen consumption for etching the GaN layer in that area is very low.

[0076] Therefore, the number of hydrogen atoms reaching the edge of the open area 103 increases, and the edge of the open area 103 is therefore more strongly affected by hydrogen etching. On the other hand, the number of hydrogen atoms reaching the center of the open area 103 is less than that at the edge.

[0077] This effect can be seen in Figure 5. For simplicity, the open areas are wide, approximately 100 μm, in the patterned substrate 101. As shown in Figure 5, the edge area 501 of the open area 103 is narrower than the center area of ​​the open area, illustrating the effect of hydrogen etching.

[0078] This effect also affects the initial growth of the layer, as shown in Figures 6(a)-6(i). For example, as shown in Figure 6(b), the hydrogen etching effect forms a core 601 in the center of the open area 103, thereby avoiding the formation of a recessed region in the center of the ELO-III nitride layer 105.

[0079] For the reasons mentioned above, a wider growth-limiting mask 102 will result in a stronger effect of hydrogen etching at the edges of the open areas 103. Therefore, it is desirable to have a width of the mask 102 greater than 20 μm, and more preferably greater than 40 μm. On the other hand, because debris may appear on the growth-limiting mask 102, it is desirable to have a width of the growth-limiting mask 102 less than 180 μm.

[0080] Furthermore, it is desirable to make the width of the open area 103 greater than 2 μm. If the width of the open area 103 is less than 2 μm, it is difficult to grow a GaN layer in the open area 103 under hydrogen carrier gas conditions due to the effect of hydrogen etching.

[0081] (Growth restriction mask direction) 7(a) to 7(c), the growth limiting mask 102 according to one example has a plurality of stripe-shaped open areas 103. The stripe-shaped open areas 103 are periodically arranged at first intervals along a first direction parallel to the 11-20 direction of the III nitride-based semiconductor layer and at second intervals along a second direction parallel to the 0001 direction of the III nitride-based semiconductor layer, and extend in the second direction.

[0082] The width of the striped open area 103 is typically constant along the second direction, but may vary along the second direction as required.

[0083] The growth limiting mask 102 comprises a plurality of stripe-shaped open areas 103, which are periodically arranged along a first direction parallel to the 11-20 direction of the ELO-III nitride layer 105 and extend in a second direction parallel to the 1-100 direction of the ELO-III nitride layer 105. The growth limiting mask 102 further comprises a plurality of stripe-shaped open areas 103, which are periodically arranged along the first direction at the same intervals as the previous stripe-shaped open areas 103 and extend in the second direction shifted by half the interval relative to the previous stripe-shaped open areas 103, so that the multiple stripe-shaped open areas 103 overlap the ends of the previous stripe-shaped open areas 103 over a predetermined distance along the second direction. The width of the stripe-shaped open areas 103 is typically constant along the second direction, but may vary along the second direction if necessary.

[0084] In the example shown in Figure 7(c), the substrate 101 does not have overlapping areas. The pitch c is the distance between islands along a direction parallel to the 1-100 direction. In this example, a smooth surface without hillocks can be easily obtained.

[0085] (flat surface area) The flat surface regions 107 are located between the layer warpage regions 108. Furthermore, the flat surface regions 107 are located on the growth limiting mask 102.

[0086] The fabrication of semiconductor devices is mainly carried out on the flat surface region 107. The width of the flat surface region 107 is preferably at least 5 μm, and more preferably 10 μm or more. In the flat surface region 107, the thickness of each semiconductor layer is highly uniform.

[0087] (Layer warpage area) 8(a) and 8(b), layer warpage region 108 and warpage active region 801 may remain within the device. By definition, layer warpage region 108 is the region outside of and including warpage active region 801.

[0088] The fabrication of the device may be partially performed on the layer warp region 108. More preferably, the layers in the layer warp region 108 are removed by etching. For example, at least the portion of the active layer within the layer warp region 108 may be removed using an etching process, such as dry etching or wet etching.

[0089] When a non-polar or semi-polar substrate 101 is used, two or three facets 802, 803, 804 appear on one side of the island-shaped group III nitride semiconductor layer 109. When there are three facets, the first facet 802 serves as the main area for forming the ridge structure, while the second facet 803 and the third facet 804 are within the layer warpage region 108.

[0090] If the layer warp region 108 remains in the LED device along with the active layer, a portion of the emitted light from the active layer will be reabsorbed. As a result, it is desirable to etch away at least the portion of the active layer within the layer warp region 108.

[0091] If the layer warpage region 108 remains in the LD device along with the active layer, the laser mode may be affected by the layer warpage region 108 due to the low refractive index (e.g., InGaN layer). As a result, it is desirable to remove at least the portion of the active layer within the layer warpage region 108 by etching. More preferably, etching is performed twice: one etching to remove the active layer within the second facet 803 region prior to removing the epitaxial layer from the substrate 101, and a second etching to remove the active layer within the third facet 804 region after removing the epitaxial layer from the substrate 101. If the layer warpage region 108 remains in the LD device, the edges of the ridge-like stripe structure should be at least 1 μm from the edge of the layer warpage region 108.

[0092] The emitting region is the current injection region. In the LD example, the emitting region is a ridge structure. In the LED example, the emitting region is the region where the p-contact electrode is formed. The edge of the emitting region in both the LD and LED examples should be at least 1 μm, and more preferably 5 μm, from the edge of the layer bow region 108.

[0093] From another perspective, the epitaxial layer in the flat surface region 107 other than the open area 103 has a lower defect density than the epitaxial layer in the open area 103. Therefore, it is desirable to form a ridge-like stripe structure on the flat surface region 107 including both wings thereof.

[0094] (First and second support substrates) If necessary, the semiconductor device manufacturing method may further include a step of bonding a first support substrate to the exposed surface side of the island-shaped III-nitride semiconductor layer 109 and the exposed surface side of the III-nitride substrate 101, and then peeling the island-shaped III-nitride semiconductor layer 109 from the III-nitride substrate 101. The first and second support substrates may be made of elemental semiconductors, compound semiconductors, metals, alloys, nitride-based ceramics, oxide-based ceramics, diamond, carbon, plastics, etc., and may have a single-layer structure or a multi-layer structure made of these materials. A metal, such as solder, or an organic adhesive may be used to bond the first and second support substrates, and the choice is arbitrary.

[0095] (Support membrane) 9(a) and 9(b), the device can be removed from the substrate 101 using a support film 901. The support film 901 can be adhesive tape, UV tape, polyimide tape, etc., but is not limited to these materials.

[0096] In one embodiment, the support film 901 comprises a layer of polyimide tape (20-50 μm) that is rolled onto the metal layer surface of the p-pad 203. The tape 901 is gently pulled away from the surface of the substrate 101 along the cleavage plane 206, causing a cleavage at the cleavage point 205. An image of a device bar removed in this manner is shown in Figure 9(c).

[0097] To prevent excessive thin film warping after spalling, the outer portions of tape 901 can be used to securely fasten the sample to the frame.

[0098] [How to create] The present semiconductor device manufacturing method may further include a step of forming a growth limiting mask 102 on the III-nitride substrate 101 .

[0099] For example, an m-plane (1-100) freestanding GaN substrate 101 may be used in combination with a growth limiting mask 102 made of SiO2. As shown in Figures 7(a) to 7(c), the open areas 103 are aligned parallel to the <1-100> plane. If a semipolar (20-21) or (20-2-1) substrate 101 is used, the open areas 103 are aligned parallel to the [-1014] and [10-14] planes, respectively. By setting the width b of the open areas 103 to 2 μm to 180 μm, more preferably 4 μm to 50 μm, a smooth surface can be easily obtained.

[0100] Metal organic chemical vapor deposition (MOCVD) is used for the epitaxial growth. The group III element sources are trimethylgallium (TMGa), trimethylindium (TMIn), and triethylaluminum (TMAl). Ammonia (NH3) is used as the raw gas to supply nitrogen. Hydrogen (H2) and nitrogen (N2) are used as carrier gases for the group III element sources. It is important to include hydrogen in the carrier gas to obtain a smooth surface for the epilayer.

[0101] Salt and bis(cyclopentadienyl)magnesium (Cp2Mg) are used as n-type and p-type dopants. The pressure is set to 50 to 760 Torr. The GaN growth temperature is set to the range of 1050 to 1250°C.

[0102] After a growth time of about 2 to 8 hours, the island-shaped group III nitride semiconductor layer 109 has a size of Thickness: 20~60μm Bar width: 40 to 150 μm (this bar width is the width of the island-shaped group III nitride semiconductor layer 109) This becomes:

[0103] In this method, after growing a Group III nitride-based semiconductor layer on the substrate 101, a first support substrate may be bonded to the upper surface side of the Group III nitride-based semiconductor layer, and then the first support substrate and the Group III nitride-based semiconductor layer may be peeled off from the Group III nitride-based substrate 101.

[0104] In addition, this method may further include a step of forming one or more electrodes on the surface of island-shaped group III nitride semiconductor layer 109 that is exposed by peeling off the first support substrate and island-shaped group III nitride semiconductor layer 109 from substrate 101.

[0105] Optionally, the semiconductor device fabrication method may further include the step of forming one or more electrodes on the top surface of the island-shaped III-nitride semiconductor layer 109 after growing the island-shaped III-nitride semiconductor layer 109 on the substrate 101. The n-electrode may be formed after the III-nitride-based semiconductor layer is removed using a cleavage technique.

[0106] The method may further include a step of removing at least a portion, preferably most, and more preferably all of the growth limiting mask 102 using a wet etchant, although this process is not always necessary to remove the substrate 101. Also, if necessary, a conductor thin film or conductor line may be formed on the main surface of the first support substrate on the side bonded to the III-nitride-based semiconductor layer.

[0107] According to the present invention, the island-shaped group III nitride semiconductor layer 109 that grows laterally on the growth-limiting mask 102 from the stripe-shaped open areas 103 of the growth-limiting mask 102 has an extremely high degree of crystallinity, making it possible to obtain a group III nitride-based semiconductor layer made of high-quality semiconductor crystals.

[0108] Furthermore, the use of a III-nitride-based substrate 101 can provide two advantages. One advantage is that a high-quality island-shaped III-nitride semiconductor layer 109 can be obtained, for example, with a much lower defect density than would be obtained using a sapphire substrate 101. Another advantage is that the use of similar or identical materials for both the epitaxial layer and the substrate 101 reduces strain within the epitaxial layer. Furthermore, due to similar or identical thermal expansion, this method can reduce the amount of warping of the substrate 101 during epitaxial growth. As mentioned above, this has the effect of increasing production yield and improving temperature uniformity. However, heterogeneous substrates 101, such as sapphire (m-plane), LiAlO, SiC, Si, etc., can also be used. More preferably, a free-standing III-nitride substrate 101 can be used for the reasons mentioned above. If a heterogeneous substrate 101 is used, the bond strength at the cleavage point is weak, making it easier to remove.

[0109] Thus, the present invention discloses a substrate 101 made of a group III nitride-based semiconductor, a growth-limiting mask 102 disposed directly or indirectly on the substrate 101 and having one or more stripe-shaped open areas 103, and one or more island-shaped group III nitride semiconductor layers 109 grown on the substrate 101 using the growth-limiting mask 102 in the (1-100) plane orientation, wherein the stripe-shaped open areas 103 of the growth-limiting mask 102 have long and short sides, and the long sides are aligned in a direction perpendicular to the a-axis direction of the island-shaped group III nitride semiconductor layers 109, as shown in Figures 7(a), 7(b), and 7(c).

[0110] The growth limiting mask 102 according to one embodiment is deposited by, but not limited to, sputtering or electron beam evaporation or PECVD (plasma enhanced chemical vapor deposition).

[0111] Furthermore, when growing a plurality of island-shaped Group III nitride semiconductor layers 109, the layers 109 are separated from one another, i.e., formed in a separated state, so that the tensile or compressive stress generated in each island-shaped Group III nitride semiconductor layer 109 is limited and remains within that island-shaped Group III nitride-based semiconductor layer 109, and the effect of that tensile or compressive stress does not extend to other Group III nitride-based semiconductor layers.

[0112] Furthermore, since the growth-limiting mask 102 and the ELO-III nitride layer 105 are not chemically bonded to each other, the internal stress of the ELO-III nitride layer 105 can be alleviated by sliding at the interface between the growth-limiting mask 102 and the ELO-III nitride layer 105.

[0113] Furthermore, as shown by the non-growth regions 104 in FIG. 1 and FIGS. 4(a) and 4(b), by providing gaps between the island-shaped group III nitride semiconductor layers 109, it is possible to obtain a substrate 101 in which the island-shaped group III nitride semiconductor layers 109 form rows, and since this substrate has flexibility, it can be easily deformed and warped when an external force is applied.

[0114] Therefore, even if slight distortion, bending, or deformation occurs in the substrate 101, it can be easily corrected by a slight external force, thereby preventing the occurrence of cracks. As a result, handling of the substrate 101 by vacuum chucking becomes possible, and the manufacturing process of these semiconductor devices can be carried out more easily.

[0115] As already explained, by suppressing bending of the substrate 101, it is possible to grow island-shaped Group III nitride semiconductor layers 109 made of high-quality semiconductor crystals, and further, even if the Group III nitride-based semiconductor layer is very thick, it is possible to suppress the occurrence of cracks and the like, making it easy to realize large-area semiconductor devices.

[0116] (First embodiment) A group III nitride-based semiconductor device according to a first embodiment and a method for manufacturing the same will be described.

[0117] In the first embodiment, first, a substrate 101 is prepared, and a growth-limiting mask 102 having a plurality of striped open areas 103 is formed on the substrate 101. In this embodiment, the substrate 101 is made of a group III nitride semiconductor, for example, GaN.

[0118] Several substrates 101 may be prepared with different off-angle orientations. The four SEM (scanning electron microscope) images in Figure 6(d) are surface images of island-shaped group III nitride semiconductor layers 109 on substrates 101 with different off-angle orientations, as indicated by the misorientation "(towards the c-axis and a-axis)." Here, the carrier gas is H2. The off-angle orientations range from -1° from the m-plane toward the c-axis (i.e., the c-plane) to 0° (i.e., less than 0.02°) toward the a-axis (i.e., the a-plane). In this embodiment, the substrate 101 has an just orientation of less than 0.2°.

[0119] (Fabricating a patterned substrate) The thickness of the III-nitride-based semiconductor layer grown on the GaN substrate is, for example, about 5 to 80 μm, but is not limited to this value. As described herein, the thickness of the III-nitride-based semiconductor layer is measured from the surface of the growth limiting mask 102 to the upper surface of the III-nitride-based semiconductor layer.

[0120] The growth limiting mask 102 can be formed of an insulating film, for example, by depositing an SiO2 film on the substrate 101 by plasma-enhanced chemical vapor deposition (CVD), sputtering, ion beam deposition (IBD), or the like, and then patterning the SiO2 film by photolithography and etching using a predetermined photomask. In this embodiment, the thickness of the SiO2 film is 0.3 μm, but is not limited to this value.

[0121] Using the growth limiting mask 102, an ELO-III nitride layer 105 is grown in an island shape with a (1-100) orientation by a vapor deposition method, such as metal organic chemical vapor deposition (MOCVD). In this case, since the surface of the substrate 101 is exposed in the open areas 103, the ELO-III nitride layer 105 first grows thereon, and then grows laterally on the growth limiting mask 102. This growth is stopped before the ELO-III nitride layer 105 coalesces with neighboring ELO-III nitride layers 105.

[0122] The thickness of the ELO-III nitride layer 105 is important because it determines the width of the flat surface region 107. Preferably, the width of the flat surface region 107 is 20 μm or more.

[0123] The thickness of the ELO-III nitride layer 105 should be as thin as possible to reduce the process time and to make the open areas 103 easier to etch.

[0124] The ELO growth ratio is the ratio of the lateral growth rate parallel to the 11-20 axis of the GaN substrate 101 to the vertical growth rate parallel to the 1-100 axis of the GaN substrate 101. The higher the ELO ratio, i.e., ELO ratio = lateral growth rate / vertical growth rate, the better. By optimizing the growth conditions, the ELO ratio can be controlled between 0.4 and 4.

[0125] III-nitride device layers 106 are then grown on ELO-III-nitride layers 105. The III-nitride device layers 106 comprise a plurality of III-nitride-based layers.

[0126] (growth restriction mask) The growth limiting mask 102 is placed directly on the substrate 101 containing a group III nitride-based semiconductor. Specifically, the growth limiting mask 102 is placed directly on the substrate 101 in contact with the substrate, or is placed indirectly via an intermediate layer made of a group III nitride-based semiconductor grown by MOCVD, sputtering, etc. Two examples of the growth limiting mask 102 are shown in Figures 7(a) and 7(b).

[0127] 7(a) has a plurality of open areas 103, which are periodically arranged at intervals p1 and p2 along a first direction parallel to the 11-20 direction of the (1-100) plane-oriented Group III nitride semiconductor substrate 101 and a second direction parallel to the 0001 direction of the Group III nitride semiconductor substrate 101, respectively, and extend in the second direction. Each pair of open areas 103 is adjacent to each other over a length q along the second direction. The length a of the open areas 103 is, for example, 200 to 3500 μm, the width b is, for example, 2 to 180 μm, the interval p1 between the open areas 103 is, for example, 20 to 180 μm, and the interval p2 is, for example, 200 to 2000 μm.

[0128] The island-shaped III-nitride semiconductor layer 109 has long and short sides. Preferably, the long sides are perpendicular to the a-axis direction. In this case, as shown in the right image of FIG. 6(b), the epitaxial layer core 601 is aligned in the center of the open area 103 along a direction perpendicular to the a-axis direction. This allows the initial growth stage to be controlled, making it easy to obtain a smooth surface within the flat surface region 107 of the ELO-III-nitride layer 105.

[0129] (Typical dimensions of growth restriction masks) The growth limiting mask 102 used in the present invention typically has the following dimensions. In one embodiment, an m-plane GaN substrate 101 is used. The growth limiting mask 102 is formed as shown in FIG. 7(c) using a 0.3 μm thick SiO2 film. The open areas 103 have a length a of 1200 μm, a width b of 20 μm, a spacing p1 between the open areas 103 of 80 μm, a spacing p2 of 1300 μm, a width of the mask 102 stripes between the open areas 103 of 60 μm, and a distance between the open areas 103 in the 1-100 direction of 100 μm.

[0130] (Growth restriction mask open area) 7(b) has a plurality of open areas 103, which are periodically arranged at intervals p1 along a first direction parallel to the 11-20 direction of the (1-100) plane-orientation III nitride semiconductor substrate 101, and extend along a second direction parallel to the 0001 direction of the III nitride semiconductor substrate 101. In order to prevent lifting of both end portions of the III nitride semiconductor substrate 101 along the 0001 direction as will be described later, the growth-limiting mask 102 further has a plurality of open areas 103, which are periodically arranged along the first direction at the same intervals p1 as the previous opening windows 103, are shifted by half the interval p1 with respect to the previous open areas 103, and extend in the second direction, so that the multiple open areas 103 overlap with the ends of the previous open areas 103 along a length q.

[0131] The length a of the open area 103 is, for example, 200 to 3500 μm, the width b is, for example, 4 to 60 μm, the spacing p1 of the open areas 103 is, for example, 20 to 120 μm, the width L of the mask 102 stripes, i.e., p1-b, is, for example, 50 μm when p1=55 μm and b=5 μm, and the overlap length r of the end portions of the open areas 103 is 35 to 40 μm.

[0132] (Advantages of open areas) There are many advantages to growing the ELO III-nitride layer 105 and the island-shaped III-nitride semiconductor layer 109 using the growth-limiting mask 102 shown in FIG.

[0133] 4 and 7, the longitudinal direction of the open areas 103 is along the 0001 direction, so the growth rate of the III nitride-based semiconductor is low at both ends of the open areas 103, and the island-shaped III nitride semiconductor layers 109 facing each other along the 0001 direction do not coalesce, making it possible to separate the island-shaped III nitride semiconductor layers 109 from each other. In this case, the size of the island-shaped III nitride semiconductor layers 109 along the 0001 direction is approximately equal to the length a of the open areas 103.

[0134] In the case of island-shaped group III nitride semiconductor layers 109 that are surrounded by flat surfaces, for example, low-growth-rate surfaces, the following problem occurs when the distance between adjacent group III nitride semiconductor layers 109 in the opposite low-growth-rate surfaces is large: raw gas is not consumed in the stripes of the growth-limiting mask 102 between neighboring island-shaped group III nitride semiconductor layers 109, so the gas concentration increases, generating a concentration gradient along the direction connecting the neighboring group III nitride semiconductor layers 109, and a large amount of raw gas is supplied to the edge portions of the island-shaped group III nitride semiconductor layers 109 due to diffusion caused by this concentration gradient. As a result, the edge portions of the island-shaped group III nitride-based semiconductor layers 109 become thicker than the other portions, resulting in a protruding shape. More specifically, since raw gas is not consumed in the stripes of the growth limit mask 102 between neighboring island-shaped III-nitride-based semiconductor layers 109 along the 0001 direction where the growth rate is slow, the gas concentration rises, generating a concentration gradient along the 0001 direction, and diffusion due to this concentration gradient supplies a large amount of raw gas to the edge portion of the island-shaped III-nitride semiconductor layer 109 along the 0001 direction. As a result, the edge portion of the island-shaped III-nitride semiconductor layer 109 along the 0001 direction becomes thicker than the other portions, resulting in a protruding shape. Depending on the specific protruding shape of the edge portion of the island-shaped III-nitride semiconductor layer 109, not only may structural problems be caused in the III-nitride-based semiconductor device, but problems may also arise in subsequent manufacturing processes such as photolithography.

[0135] To prevent the thickness uniformity of the island-shaped group III nitride semiconductor layer 109 from being affected by the specific protruding shape of its edge portion, it is necessary to place neighboring island-shaped group III nitride semiconductor layers 109 as close as possible and to prevent in-plane uniformity of raw gas from occurring from the early stage of growth. For this reason, the growth limiting mask 102 shown in Fig. 7(b) is formed on the bisector of the region between a pair of adjacent open areas 103 along the 11-20 direction, such that each open area 103 overlaps the opposing ends of the adjacent open area 103 along the 0001 direction for a length q.

[0136] As a result, in-plane uniformity of the gas concentration can be obtained due to raw gas consumption caused by growing the island-shaped group III nitride semiconductor layer 109. Ultimately, uniformity in the thickness of the island-shaped group III nitride semiconductor layer 109 can be obtained.

[0137] (Growth conditions of ELO-III nitride layer) The growth conditions for the island-shaped III-nitride semiconductor layer 109 can be the same as those for the ELO-III-nitride layer 105, which are MOCVD growth conditions. For example, the growth temperature for the GaN layer is 950 to 1200°C, and the pressure is 15 kPa. For the growth of the GaN layer, trimethylgallium (TMG) and ammonia (NH3) are used as raw gases, and hydrogen (H 2 ) alone and silane (SiH4) as the dopant gas. The growth time is 4 hours.

[0138] The growth gas flow rates are 12 sccm for TMG, 8 slm for NH3, 3 slm for carrier gas, and 1.0 sccm for SiH4 (sccm: standard cm 3 / min, slm: standard liters per minute), and the V / III ratio is about 7700. In this case, a 20 μm thick ELO-III nitride layer 105 can be obtained.

[0139] (Effect of region isolation from growth) Also, as shown in FIGS. 4(a) and 4(b), the III-nitride-based semiconductor layer is separated from the edge of the substrate 101.

[0140] Figure 10(a) is a photograph of a GaN layer on an unpatterned semipolar (20-21) substrate, showing that the edge of the substrate 101, i.e., the area enclosed by the dashed line, is not uniform in shape. Therefore, the growth rate and shape of the core are unstable, resulting in a rough surface appearing in the edge region of the substrate 101.

[0141] Nonpolar III-nitride substrates 101, such as m-plane III-nitride substrates 101, exhibit similar results. As shown in the two left images of Figure 10(b), the unpatterned substrate 101 has numerous randomly shaped cores 1001, resulting in a large amount of surface roughness. On the other hand, as shown in the two right images of Figure 10(b), the substrate 101 patterned with a growth-limiting mask 102 made of SiO2 has a smooth surface due to area separation.

[0142] At a minimum, open area 103 should be separated from facets of substrate 101 that are enclosed by dashed lines in Figure 10(a). These facets are perpendicular to the a-axis. Preferably, open area 103 should be separated from facets that are perpendicular to the projected c-axis.

[0143] Therefore, to obtain a smooth surface in the planar surface region 107 , the III-nitride based semiconductor layers should be separated from the edge of the substrate 101 .

[0144] Another example is shown in the images of Figures 10(c) and 10(d), where the substrate in Figure 10(c) is (10-1-1) and the substrate in Figure 10(d) is (1-100), with no off-angle orientation. Both Figures 10(c) and 10(d) contain images of an unpatterned 1002 substrate 101 and a patterned 1003 substrate 101 grown simultaneously by MOCVD. The unpatterned 1002 substrate 101 has a rough surface morphology, with uneven edges and pits on its surface. On the other hand, the patterned 1003 substrate 101 exhibits a very smooth surface. As shown in the enlarged partial view of the patterned 1003 substrate 101, there is some debris on the growth-limiting mask 102, but the surface of the ELO-III nitride layer 105 is very smooth. Furthermore, when the growth conditions are optimized, no debris is present. Generally, a (10-1-1) plane tends to result in a rough surface, but the use of a patterned 1003 substrate 101 can produce a smooth surface.

[0145] (Various carrier gas conditions) To compare carrier gas dependent effects, two samples were grown under hydrogen and nitrogen carrier gas conditions.

[0146] 6(a), which reflect growth on the (1-100), (20-21), and (20-2-1) planes, under nitrogen carrier gas conditions, a recessed region develops on the surface at the center of the ELO-III nitride layer 105. As mentioned earlier, the reason is the lack of hydrogen etching at the edges of the open areas 103.

[0147] As shown in the two images in Figure 6(c), the same problem does not appear under hydrogen carrier gas conditions.

[0148] As shown in the two images in Figure 6(b), the core 601 formed in the initial stage of growth is formed at the center of the open region 103. This growth prevents the core 601 from coalescing at the center, and therefore the recessed region disappears from the ELO-III nitride layer 105.

[0149] 6(a), 6(b) and 6(c) show the results when the width of the open area 103 is 8 to 9 μm.

[0150] On the other hand, the twelfth image in Figure 6(h) shows the results when the width of the open area 103 is 25 μm. In these cases, too, using hydrogen carrier gas alone or in combination with nitrogen carrier gas resulted in a smooth surface, while using nitrogen carrier gas alone resulted in a surface with a large amount of surface roughness and lacking flat areas.

[0151] Furthermore, by separating the growth region from the edge of the substrate 101, hillocks do not appear on the surface.

[0152] (Various off-angle orientations) In addition to the just-oriented substrates, substrates 101 with various off-axis orientations were prepared. These off-axis orientations were with respect to m-plane oriented crystalline surface planes, i.e., planes whose off-axis orientations were within the range of approximately +47° to -47° relative to the c-plane. ELO-III nitride layers 105 were simultaneously grown on the substrates 101 under hydrogen carrier gas conditions.

[0153] The four images in Figure 6(d) are images of the surface of the ELO-III nitride layer 105, with the substrate 101 angled from left to right at 0, -0.45, -0.6, and -1° from the m-plane toward the (0001) c-plane. As expected, these off-angle orientations will affect the surface morphology, which is especially true when using unpatterned substrates 101. Some substrates 101 will exhibit pyramidal hillocks, wavy surfaces, etc.

[0154] However, as shown in Figure 6(d), all specimens simultaneously exhibit excellent surface morphology, even with different off-axis orientations, a result that has not been reported previously for m-plane growth.

[0155] Furthermore, as shown in the eighth image of Figure 6(f), the same technique can be used to achieve smooth surfaces on substrates 101 having different surfaces, such as (10-10), (20-2-1), (10-1-1), (10-1-2), (20-21), (10-11), and (10-12) surfaces with on-axis (0° off-angle orientation) or misorientation (-15, -28, -47, +15, +28, +47° off-angle orientation), using H2 alone as a carrier gas.

[0156] These specimens have very smooth surfaces. The (10-1-2) and (10-11) planes have somewhat rough surfaces, but flat areas appear in some parts of the planes. The surface roughness can be improved by optimizing various growth conditions, such as the hydrogen-nitrogen ratio of the carrier gas, the V / III ratio, and the growth temperature. Therefore, these flat surfaces can also be used in the present invention. On the other hand, the (10-12) plane has a triangular shape and lacks flat areas.

[0157] As shown in the image in Figure 6(i), the present invention can employ such a substrate 101, particularly one having an off-angle orientation in the range of -47° to +28° from the m-plane to the c-plane, and more preferably, the off-angle orientation in the range of -28° to +15° from the m-plane to the c-plane.

[0158] Additionally, growth may be carried out under mixed gas conditions using hydrogen and nitrogen carrier gases, with both gas flows at 1.5 slm for a total carrier gas flow of 3.0 slm.

[0159] The results using a H₂·N₂ mixed carrier gas are shown in the images in Figure 6(g) and Figure 6(e). In these cases, essentially identical results were obtained for the (10-10), (20-2-1), (10-1-1), (10-10), and (20-21) surfaces at angles of 0, -15, -28, 0, and +15°, respectively. That is, the hydrogen content of the carrier gas is important for obtaining smooth surfaces.

[0160] Therefore, even when different off-angle orientations and planes are used, a very smooth surface can be obtained. This is particularly true for off-angles less than 0.6°, where it has been difficult to obtain a smooth surface until now. Conversely, by using the present invention, a smooth surface can be obtained even for off-angles less than 0.6°.

[0161] Generally, the GaN substrate 101 has a wide in-plane distribution of off-axis angles. However, in the past, this wide in-plane distribution of off-axis angles caused a rough surface, which reduced yields and became a major problem.

[0162] As shown in Figures 11(a) and 11(b), the off-angle orientation is different at points A, B, and C. Considering an example where point A is the m-plane and has no off-angle orientation, i.e., is on-axis, the off-angle orientation at point B is 0.1° as viewed from the m-plane, and the off-angle orientation at point c is 0.2° as viewed from the m-plane. In this example, the surface morphology is different at points A, B, and C.

[0163] On the other hand, the present invention avoids this problem and provides smooth surfaces at all points A, B and C, thus making mass production more efficient and less expensive.

[0164] That is, the present invention is very useful when the in-plane off-angle orientation distribution of the substrate 101 has fluctuations of more than 0.1°, more preferably more than 0.2°.

[0165] (III-nitride semiconductor device layer) In the next step, III-nitride semiconductor device layers 106 are grown on the ELO-III-nitride layer 105. Triethylaluminum (TMA) is used as the raw gas for growing the AlGaN layer, and trimethylindium (TMI) is used as the raw gas for growing the InGaN layer. Under these conditions, the following layers were grown on the ELO-III-nitride layer 105:

[0166] FIG. 12 is a cross-sectional view of a nitride semiconductor laser bar taken along the direction perpendicular to the optical cavity, and the optical cavity is configured with a ridge-like stripe structure.

[0167] This nitride semiconductor laser includes, in the order mentioned, an ELO-III nitride layer 105 (here, a GaN layer), an InGaN / GaN 5MQW active layer 1201 (8 nm × 8 nm: 5MQW), an AlGaN-EBL layer (electron blocking layer) 1202, a p-GaN guiding layer 1203, a ZrO current limiting layer 1204, and a p-electrode 1205. Note that these III nitride semiconductor layers may be formed by growing any nitride-based III-V compound semiconductor in the above-mentioned order.

[0168] The ridged stripe structure is composed of a p-GaN cladding layer 1203, a ZrO current limiting layer 1204, and a p-electrode 1205, which provides optical confinement in the horizontal direction. The width of the ridged stripe structure is on the order of 1.0 to 20 μm, typically 10 μm.

[0169] In some embodiments, the p-electrode 1205 may be composed of one or more of the following materials: Pd, Ni, Ti, Pt, Mo, W, Ag, Au, etc. For example, the p-electrode 1205 may be composed of Pd-Ni-Au (3-30-300 nm thick), which may be deposited by electron beam evaporation, sputtering, thermal evaporation, etc.

[0170] Additionally, as shown in FIG. 2(c), an ITO cladding layer may be added between the p-GaN cladding layer 1203 and the p-electrode 1205.

[0171] (initial growth) To obtain a smooth surface on a non-polar or semi-polar substrate 101, a different initial growth mechanism from that of a polar c-plane substrate must be considered. As shown in the image in Figure 13, the initial growth on a polar c-plane substrate 101 with a (0001) surface is isotropic, exhibiting, for example, a hexagonal shape 1301. On the other hand, the initial growth on a non-polar substrate 101 with an off-axis orientation tilting from the m-plane (10-10) to the c-plane exhibits anisotropic growth, as also shown in Figure 13.

[0172] This phenomenon has been explained by several researchers. For example, Lymperakis and Neugebauer calculated highly anisotropic diffusion barriers for Ga adatoms on m-plane GaN surfaces along the c and a directions, finding them to be 0.93 eV and 0.21 eV, respectively. See Non-Patent Document 3. Their investigations suggest that the anisotropic diffusion barriers associated with Ga adatoms cause anisotropic initial growth. Furthermore, this anisotropic initial growth leads to a large amount of surface roughness in the absence of growth area restriction, as shown in Figure 14(a) for the maskless m-plane initial growth and in Figure 14(b) for the growth with mask 102.

[0173] For the reasons stated above, a nonpolar substrate 101 with an off-axis orientation tilted from the m-plane toward the c-plane experiences rapid initial growth with its longitudinal dimension aligned along the a-axis rather than the c-axis. In this case, the growth-limiting mask 102 can be used to form an opening 103 with its long side aligned along the a-direction rather than the c-axis. As shown in Figures 16 and 17, this allows for control of the initial growth position and prevents the initial growth from merging from unexpected directions, resulting in a smooth surface. The nonpolar substrate 101 has an off-axis orientation of its m-plane oriented crystalline surface plane within a range of approximately +28° to -47° toward the c-plane. For the reasons stated above, a smooth surface can be obtained using the growth-limiting mask 102 for such a substrate.

[0174] FIG. 13 shows similar results for semi-polar (20-21) substrate 101 and (20-2-1) substrate 101 as for non-polar (10-10) substrate 101.

[0175] (Edge growth) The ELO-III nitride layer 105 has an just-oriented and an off-axis orientation relative to the m-plane crystalline surface plane, and the off-axis orientation is within a range of about +28° to about -47° relative to the c-plane. A III nitride semiconductor device layer 106 is grown on the ELO-III nitride layer 105. In this case, the edge growth is limited.

[0176] 15(a) to 15(c), in the case of a c-plane substrate 101, edge growth regions 1501 appear at the edges of the island-shaped III nitride semiconductor layer 109. The width W of the edge growth regions 1501 is approximately 10 to 15 μm, and the height T of the edge growth regions 1501 is approximately 0.3 to 0.4 μm. Because the growth rate of the edge growth regions 1501 is high, the thickness of each layer differs from that at the center of the island-shaped III nitride semiconductor layer 109.

[0177] In this case, the thickness variations of the layers would reduce the production yield, and it is best to avoid the formation of ridge-like stripes originating from the edge growth region 1501. In the case of a c-plane substrate 101, the edge growth region 1501 is wide and tall. In contrast, in the present invention, the height T is less than 0.2 μm and the width W is approximately 5 μm.

[0178] It is very important to limit the edge growth region 1501 in the fabrication of the device, and by optimizing the growth conditions, the edge growth region 1501 can be substantially eliminated.

[0179] (Create a ridged stripe structure) After MOCVD growth, a ridge-like stripe structure 301 is fabricated using conventional techniques, such as photolithography and dry etching, as shown in Figures 3(a) and 3(b). The ridge depth (from the surface to the ridge bottom) is aligned with the p-GaN guide layer. The ridge depth is determined before dry etching based on simulations or previous experimental data.

[0180] (Method of creating facets) As shown in Figures 3(a) and 3(b), the location of the etched mirror region 302 is determined based on the optical cavity length. The etching process for GaN etching uses an Ar ion beam and Cl2 ambient gas. The etching depth is approximately 1 μm to approximately 4 μm. The etched mirror facets may be coated with a dielectric film selected from the group consisting of SiO2, Al2O3, AlN, AlON, SiN, SiON, TiO2, Ta2O5, Nb2O5, Zr2O, etc.

[0181] (Bonding III-nitride-based device layers to a support substrate) 2(d), the first support substrate 204 is bonded to the island-shaped group III nitride semiconductor layer 109. A conventional bonding technique can be used for this bonding.

[0182] Generally, the most commonly used types of flip-chip bonding are thermocompression bonding and wafer fusion bonding. Wafer fusion bonding is widely used in InP-based devices. However, thermocompression bonding is generally much simpler than wafer fusion bonding because it uses metal-to-metal bonding, and it also has the advantage of significantly improved thermal conductivity.

[0183] Au-Au compression bonding is by far the simplest bonding method and produces a fairly strong bond. Au-Sn eutectic bonding offers the potential for significantly stronger bonding strength.

[0184] In one embodiment, a Cu substrate is used as the support substrate 204. A patterned Ti / Au electrode is formed on the Cu substrate by electron beam evaporation or sputtering, with the electrode thickness being Ti (10 nm) and Au (500 nm).

[0185] Before the compression bonding, it is desirable to perform surface activation in preparation for wafer bonding. This surface activation is achieved using an Ar and / or O2 plasma process. The island-shaped III-nitride semiconductor layer 109 is then bonded to a support substrate 204 under pressure at 150 to 300°C.

[0186] (Removes the substrate due to thermal expansion) The bonded wafers are immersed in a wet etching solvent to remove the substrate 101. In embodiments where the growth limiting mask 102 used is SiO2, it is dissolved in an HF or BHF solvent. The advantage of this technique is that the substrate 101 is removed without mechanical damage (very gently), and that large areas of SiO2 are dissolved very easily and quickly by HF.

[0187] Thereafter, the wafer bonded to the group III nitride substrate 101 and the support substrate 204 is heated. The Cu support substrate 204 has a larger CTE (coefficient of thermal expansion) than the GaN substrate 101. As shown in FIG. 2( e), the expansion of the support substrate 204 due to heating applies a strong stress to the cleavage point 205. Then, cleavage begins at the cleavage point 205 and proceeds toward the opposite side of the cleavage plane 206.

[0188] (N electrode) 2(f), an n-electrode 207 is disposed on the back surface of the island-shaped group III nitride semiconductor layer 109. The n-electrode 207 is typically made of a material such as Ti, Hf, Cr, Al, Mo, W, Pt, or Au.

[0189] For example, the n-electrode 207 may be made of Ti-Al-Pt-Au (thickness: 30-100-30-500 nm), but is not limited to these materials. The deposition of these materials may be performed by electron beam evaporation, sputtering, thermal evaporation, etc. Preferably, the p-electrode 207 is deposited on ITO.

[0190] 16, an n-electrode (not shown) is preferably formed on the back surface of the island-shaped III nitride semiconductor layer 109, in a separation area 1601, after the island-shaped III nitride semiconductor layer 109 is removed from the substrate 101. By making the surface condition of this separation area 1601 favorable for an n-electrode, contact resistance can be reduced. Specifically, in the present invention, this separation area 1601 is kept clean until the island-shaped III nitride semiconductor layer 109 is removed.

[0191] (Chip division method) The chip division method has two steps. The first step is to scribe the island-shaped group III nitride semiconductor layer 109. The second step is to divide the support substrate 204 using laser scribing or the like.

[0192] 3(a) and 3(b), a chip scribe line 303 is formed using a diamond scribing machine or a laser scribing machine on the back surface of the island-shaped group III nitride semiconductor layer 109. The chip scribe line 303 may be a solid line or a dashed line.

[0193] Next, the support substrate 204 is divided by laser scribing to obtain LD devices. When forming the chip scribe lines 303, it is better to avoid a ridge-like stripe structure.

[0194] (Second embodiment) The second embodiment is almost the same as the first embodiment, except that the island-shaped III nitride semiconductor layer 109 is not removed. The steps of this fabrication method are the same as those of the first embodiment up to step 3 (TCOp pad deposition + ridge formation process). In the second embodiment, the island-shaped III nitride semiconductor layer 109 is not bonded to the support substrate 204. The subsequent processes are the same as those of the conventional device process.

[0195] 4. The substrate 101 is polished to a thickness of 80 to 100 μm.

[0196] 5. Form an n-electrode on the back surface of the substrate 101.

[0197] 6. Separate the substrate 101 into bars as shown in Figures 17(a) and 17(b), where Figure 17(a) shows the flat surface regions 107, layer bow regions 108, and island-like III-nitride-based semiconductor layers 109, the no-growth regions 104 separating them, and scribe lines 1701, and Figure 17(b) shows the devices separated into bars 1702 along the scribe lines 1701.

[0198] 7. Facet coating (using the same method as mentioned in the first embodiment).

[0199] 8. Separate the bars 1702 into individual devices or chips 1703 as shown in Figures 17(b) and 17(c).

[0200] In this way, the device 1703 can be obtained without removing the island-shaped group III nitride semiconductor layer 109 from the substrate 101. The same effects as those of the first embodiment can be obtained by using the method of the second embodiment.

[0201] [Variant and Alternative] Numerous modifications and substitutions can be made without departing from the spirit and scope of the present invention.

[0202] For example, the present invention may be used with other III-nitride substrates. Specifically, the substrate may be a basal nonpolar m-plane {10-10} family substrate, or a semipolar plane family substrate, such as the {20-2-1} plane, with at least two nonzero h, i, or k Miller indices and a nonzero l Miller index. (20-2-1) semipolar substrates are particularly useful due to their large flat ELO growth area.

[0203] Also for example, the present invention has been described as being used in fabricating various optoelectronic device structures, such as light emitting diodes (LEDs), laser diodes (LDs), Schottky barrier diodes (SBDs), or metal oxide semiconductor field effect transistors (MOSFETs). The present invention may also be used in fabricating other optoelectronic devices, such as microLEDs, vertical cavity surface emitting lasers (VCSELs), edge emitting laser diodes (EELDs), and solar cells.

[0204] [Conclusion] This concludes the description of the preferred embodiments of the present invention. The foregoing description of one or more embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed or to be exhaustive. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be defined by the appended claims, rather than by this detailed description.

Claims

1. A device having a plurality of island-shaped Group III nitride semiconductor layers having just-oriented and off-angle-oriented m-plane oriented crystalline surface planes, the island-shaped III-nitride semiconductor layer is formed by epitaxial lateral overgrowth on an open area of ​​a growth-limiting mask deposited on a substrate and on the growth-limiting mask without merging with neighboring island-shaped III-nitride semiconductor layers; the just orientation of the m-plane crystalline surface plane of the island-shaped Group III nitride semiconductor layer is the a-axis direction of the island-shaped Group III nitride semiconductor layer; an off-angle orientation of an m-plane oriented crystalline surface plane of the island-shaped Group III nitride semiconductor layer is within a range of +28° to −47° toward a c-plane direction of the island-shaped Group III nitride semiconductor layer; the island-shaped Group III nitride semiconductor layer has at least one long side and one short side, the long side being perpendicular to the a-axis of the island-shaped Group III nitride semiconductor layer; the island-shaped group III nitride semiconductor layer has an edge growth region having a height of less than 0.2 μm on a short side of the island-shaped group III nitride semiconductor layer so that growth of the island-shaped group III nitride semiconductor layer is restricted; The island-shaped III-nitride semiconductor layer has a flat surface region that is free of hillocks.

2. 2. The device of claim 1, wherein the open areas of the growth-limiting mask are separated from the edges of the substrate.

3. 3. The device of claim 2, wherein said island-shaped III-nitride semiconductor layer is detached from said substrate.

4. 2. The device of claim 1, wherein the island-shaped III-nitride semiconductor layer comprises an emitting region.

5. 5. The device of claim 4, wherein the emitting region is at least 1 [mu]m from a bowed region of the island-shaped III-nitride semiconductor layer.

6. 5. The device of claim 4, wherein the emitting region is more than 5 [mu]m from the edge of the top surface of the island-shaped III-nitride semiconductor layer.

7. 10. The device of claim 1, wherein the edge growth region has a width of less than 5 [mu]m.

8. 4. The device of claim 3, wherein the island-shaped III-nitride semiconductor layer has an isolated area detached from the substrate, and an n-electrode is formed in the isolated area.

9. Forming a growth limiting mask on or above the substrate, The in-plane off-angle orientation distribution of the substrate is set to a magnitude of more than 0.1°, and the off-angle orientation of the m-plane oriented crystalline surface plane of the substrate is within the range of +28° to −47° toward the c-plane; 1. A method for forming a semiconductor device, comprising growing a plurality of III-nitride semiconductor island layers on the substrate and over the open areas of the growth-limiting mask by epitaxial lateral overgrowth, without coalescing with neighboring III-nitride semiconductor island layers; the island-shaped group III nitride semiconductor layer has the m-plane oriented crystalline surface plane directed toward the a-axis, the island-shaped III-nitride semiconductor layer has an off-angle orientation of the m-plane oriented crystalline surface plane in the range of +28° to −47° with respect to the c-plane; the island-shaped group III nitride semiconductor layer has at least one long side and one short side, the long side being perpendicular to the a-axis; the island-shaped group III nitride semiconductor layer has an edge growth region having a height of less than 0.2 μm on a short side of the island-shaped group III nitride semiconductor layer so that growth of the island-shaped group III nitride semiconductor layer is restricted; The method, wherein the island-shaped III-nitride semiconductor layer has flat surface regions that are free of hillocks.

10. 10. The method of claim 9, wherein the open areas of the growth-limiting mask are separated from the edge of the substrate.

11. 10. The method of claim 9, wherein the island-shaped III-nitride semiconductor layer is removed from the substrate.

12. 10. The method of claim 9, wherein the island-shaped III-nitride semiconductor layer comprises an emissive region.

13. 13. The method of claim 12, wherein the emitting region is at least 1 μm from a bow region of the island-shaped III-nitride semiconductor layer.

14. 13. The method of claim 12, wherein the emitting region is more than 5 μm from the edge of the top surface of the island-shaped III-nitride semiconductor layer.

15. 10. The method of claim 9, wherein the edge growth region has a width of less than 5 microns.

16. 12. The method of claim 11, wherein the island-shaped III-nitride semiconductor layer has an isolated area detached from the substrate, and an n-electrode is formed in the isolated area.

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