METHOD FOR MANUFACTURING A STACKED STRUCTURE OF THE TYPE SILICON CONSTRAINED ON INSULATOR USING A 2D MATERIAL-BASED LAYER TRANSFER TECHNIQUE

Abstract

The invention relates to a method of manufacturing a stacked structure comprising a layer of semiconductor material bonded to a substrate, comprising: the fabrication of a heterostructure by: forming an intermediate layer made of a two-dimensional material on a growth substrate (1); shaping the intermediate layer with a plurality of openings to form a shaped intermediate layer (3); growing a semiconductor material on the shaped intermediate layer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the shaped intermediate layer; the formation of a first assembly by bonding the heterostructure to a manipulation substrate (6), the continuous epitaxial layer being located at the bonding interface;the separation of the first set at the level of the modeled intermediate layer (3) so as to obtain a second set resulting from the transfer of the continuous epitaxial layer (4) from the heterostructure to the manipulation substrate (6). Figure for the abstract: Figure 7;

Description

Title of the invention: METHOD FOR MANUFACTURING A STACKED STRUCTURE OF THE TYPE CONSTRAINED SILICON ON INSULATOR USING A 2D MATERIAL-BASED LAYER TRANSFER TECHNIQUE technical field

[0001] The field of the invention is that of methods for manufacturing a stacked structure comprising a layer of semiconductor material adhering to a substrate. More particularly, the invention relates to processes that implement a 2D material-based layer transfer technique in order, for example, to fabricate a stacked structure of the strained silicon-on-insulator type. DESCRIPTION OF THE ASSOCIATED TECHNIQUE

[0002] Remote epitaxy is an emerging technology for the production of self-supporting single-crystal films and thin structures. The method uses 2D van der Waals materials as semi-transparent intermediate layers that allow epitaxy and exfoliation of epitaxial layers at the 2D layer interface by mechanical delamination, this technique being known as 2D material-based layer transfer (2DLT).

[0003] As described, for example, in WO 2019 / 099461 A1, the 2DLT process can use a 2D molded layer with a plurality of openings within it, and the layer transfer is carried out, firstly, by depositing a nickel stress layer onto the epitaxial layer, which has been previously grown on the 2D molded material layer, and then by applying a ribbon layer onto the stress layer. The stack consisting of the ribbon layer, the stress layer, and the epitaxial layer can then be exfoliated after detachment of the 2D molded layer by mechanical energy. After exfoliation, the ribbon layer and the stress layer are respectively detached and removed by etching with a Fe-C13 solution. However, iron is generally an undesirable contaminant for the fabrication of semiconductor devices. BRIEF DESCRIPTION OF THE INVENTION

[0004] The invention aims to provide a 2DLT technique that would not require the use of a stress layer and would therefore be free from associated contamination. To this end, a method for fabricating a stacked structure comprising a layer of semiconductor material adhering to a substrate is proposed, comprising: - the fabrication of a heterostructure by: • formation of an intermediate layer consisting of a two-dimensional material on a growth substrate; • modeling of the intermediate layer with a plurality of openings to form a modeled intermediate layer; • growth of a semiconductor material on the modeled intermediate layer by epitaxial lateral overgrowth to form a continuous epitaxial layer on the modeled intermediate layer; - the formation of a first assembly by bonding the heterostructure to a manipulation substrate, the continuous epitaxial layer being located at the bonding interface; - the separation of the first set at the level of the intermediate layer modeled so as to obtain a second set resulting from the transfer of the continuous epitaxial layer from the heterostructure to the manipulation substrate.

[0005] The modeling of the intermediate layer is carried out so that 1% to 10% of a surface of the growth substrate on which the modeled intermediate layer is located is uncovered, the remainder being covered by the two-dimensional material.

[0006] The bonding of the heterostructure to the manipulation substrate includes one of a surface activation bonding, an atomic diffusion bonding and a hydrophilic bonding accompanied by an annealing to strengthen the bonding strength.

[0007] Some preferred, but not limiting, aspects of the method are as follows: - the manipulation substrate has a top oxide layer which is located at the bonding interface during the formation of the first assembly; - the manipulation substrate also includes a layer rich in traps under the upper oxide layer; - it also includes the planarization of the upper oxide layer before the formation of the first assembly; - the continuous epitaxial layer is a relaxed layer and the fabrication of the heterostructure further includes the epitaxial deposition of a constrained layer on the continuous epitaxial layer; - it also includes the removal of the continuous epitaxial layer of the second set; - the strained layer is a strained silicon layer; - the growth substrate includes a gradient buffer and a layer of relaxed growth on the gradient buffer, the gradient buffer having a mesh parameter with a gradient between a first mesh parameter and a second mesh parameter, and the relaxed growth layer having the second mesh parameter; - it further includes, after the separation of the first set at the level of the molded intermediate layer, the recycling of the growth substrate, in which said recycling includes the polishing of the relaxed growth layer; - the continuous epitaxial layer is a relaxed layer; - it also includes the planarization of the continuous epitaxial layer before the formation of the first set; - the shaping of the intermediate layer leaves a peripheral ring of the material in two dimensions on the growth substrate; - two adjacent openings of the molded intermediate layer are separated by a distance that is less than 40 micrometers, preferably less than 20 micrometers. Brief description of the drawings

[0008] Other aspects, purposes, advantages and features of the invention will become more apparent upon reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and implemented with reference to the accompanying drawings, in which: Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. 9 illustrate a possible embodiment of a method according to the invention; - Fig. 10 and Fig. 11 represent two different embodiments of a heterostructure that can be used in a method according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] The invention relates to a method for manufacturing a stacked structure comprising a layer of semiconductor material adhering to a substrate, which method implements a 2DLT process. More particularly, the 2DLT process uses a 2D material layer shaped with a plurality of openings within it.

[0010] This method includes the fabrication of a heterostructure. With reference to [Fig. 1], this fabrication begins with the provision of a growth substrate 1.

[0011] Next, with reference to [Fig. 2], the fabrication of the heterostructure comprises the formation of an intermediate layer 2 made of a two-dimensional material on the growth substrate 1. This formation can be carried out after planarizing the surface of the growth substrate 1, for example, by means of chemical-mechanical polishing. This formation can include the deposition of the material in two dimensions. Dimensions on the growth substrate 1. In a non-exhaustive manner, this deposition can be carried out by MBE (molecular beam epitaxy), CVD (chemical vapor deposition) or ALD (atomic layer epitaxy).

[0012] The two-dimensional material can be hexagonal boron nitride h-BN, graphene, or, more generally, any 2D van der Waals material that allows long-range epitaxy. The intermediate layer 2 of the two-dimensional material is thus made up of single-atom sheets having weak interactions with each other, and whose number is limited to allow long-range epitaxy of a layer of semiconductor material.

[0013] With reference to [Fig.3], the fabrication of the heterostructure further includes the shaping of the intermediate layer 2 with a plurality of openings to form a shaped intermediate layer 3.

[0014] The shaping of the intermediate layer offers several advantages, such as those discussed, for example, in Kim, H., Lee, S., Shin, J. et al., Graphene nanopattern as a universal epitaxy platform for single-crystal membrane production and defect reduction. Nat. Nanotechnol. 17, 1054-1059 (2022). https: / / doi.org / 10.1038 / s41565-022-01200-6. In particular, the shaping of the intermediate layer can reduce the interface toughness between the growth substrate 1 and a continuous epitaxial layer 4 brought to grow on the shaped intermediate layer as discussed below.

[0015] The openings can be created by etching the 2D material using a lithographic process. The openings can be trenches that delimit bands of 2D material. The trenches can be parallel to each other. The width of the trenches can range from several tens of nanometers to several micrometers. Two openings adjacent to the molded intermediate layer are separated by a distance (the width of the bands in the case of parallel trenches) that is less than 40 micrometers, preferably less than 20 micrometers. This distance between the openings is calibrated with respect to a difference between the lateral growth rate and the vertical growth rate and the corresponding coefficients of thermal expansion of the materials so as to avoid the occurrence of curvature, warping, or cracking.

[0016] In a preferred embodiment, the modeling of the intermediate layer is carried out such that the modeled intermediate layer 3 has an openness ratio of between 1% and 10%, that is, 1% to 10% of the surface of the growth substrate on which the modeled intermediate layer is located is uncovered, the remainder being covered by the material in two dimensions. In other words, the growth substrate has a 2D material coverage percentage of between 90% and 99%.

[0017] The lower limit of 1% is calibrated for a preferred embodiment described later (where a stressed Si layer is grown on a continuous epitaxial layer 4 made of relaxed SiGe, which is itself grown on a 2D material shaped with parallel trenches) and allows coalescence to be achieved for thicknesses that do not present any problems of mismatch in the coefficients of thermal expansion. The upper limit of 10% allows operation in the exfoliation regime, and not in the other two regimes, namely scaling or delamination.

[0018] In one possible embodiment, the shaping of the intermediate layer is carried out so as to leave a peripheral ring of the two-dimensional material on the growth substrate. The presence of such a peripheral ring facilitates the initiation of subsequent separation at the level of the shaped intermediate layer.

[0019] With reference to [Fig. 4], the fabrication of the heterostructure further comprises the growth of a semiconductor material on the molded intermediate layer by epitaxial lateral overgrowth to form a continuous epitaxial layer 4 on the molded intermediate layer 3. More specifically, the growth of the semiconductor material begins with the localized growth of seeds in the molded openings in the 2D material. The lateral growth of these seeds is then activated, resulting in lateral growth of the seeds on the 2D material and, finally, coalescence to produce the continuous epitaxial layer 4.

[0020] In a preferred embodiment, the continuous epitaxial layer 4 is then planarized, for example, by means of a chemical-mechanical polishing CMP, to improve its morphological quality and more particularly to obtain a uniform and controllable thickness and fewer coalescence defects.

[0021] In another embodiment shown in [Fig.5], the fabrication of the heterostructure can further include the epitaxial deposition of one (or more) additional layer(s) 5 on the continuous epitaxial layer 4. It is thus possible to form a bilayer which is separated from the growth substrate 1 by the molded intermediate layer 3. The additional layer 5 can be a constrained layer, as will be illustrated below.

[0022] Once the heterostructure has been fabricated, with reference to [Fig. 6], the method of the invention comprises forming a first assembly by bonding the heterostructure to a manipulation substrate 6, the continuous epitaxial layer 4 being located at the bonding interface. In the case where an additional layer 5 has been previously formed on the continuous epitaxial layer, the bilayer comprising the continuous epitaxial layer 4 is located at the bonding interface.

[0023] In a preferred embodiment, the handling substrate 6 comprises a top oxide layer 7 which is located at the bonding interface during the formation of the first set. The manipulation substrate 6 may further include a trap-rich layer under the upper oxide layer.

[0024] The upper oxide layer 7 can be planarized, for example, by means of chemical-mechanical polishing (CMP), before the formation of the first assembly. In particular, such planarization proves advantageous with regard to reducing the surface toughness of the upper oxide layer when it is grown on a trap-rich layer.

[0025] In an embodiment given by way of example, the manipulation substrate 6 is a silicon substrate and the upper oxide layer 7 may have been formed by thermal oxidation of the silicon manipulation substrate.

[0026] The bonding of the heterostructure to the manipulation substrate 6 is carried out in such a way as to obtain an interface bonding energy at the bonding interface between the heterostructure and the manipulation substrate which is greater than the interface toughness, through the modeled interface 3, between the growth substrate 1 and the continuous epitaxial layer 4. In other words, the bonding force is such that, with respect to the modeled interface toughness, the subsequent application of mechanical disassembly forces to the first assembly results in the separation of the first assembly at the modeled interface rather than at the bonding interface.

[0027] When the growth of the continuous epitaxial layer 4 takes place in the openings, the resulting interface energy is quite high, since it is related to the bond energy between the atoms of the 2D material and the layer subjected to overgrowth, whereas, when the growth of the continuous epitaxial layer 4 takes place on the 2D material between the openings, the resulting interface energy is quite low, since no bond is formed between the 2D material and the layer subjected to overgrowth, only a weak van der Waals interaction occurring.Therefore, the aperture ratio is a compromise between the overall interface energy required to allow subsequent separation and the processing time needed to achieve lateral epitaxial overgrowth of the continuous epitaxial layer (this processing time being all the more important as the apertures are larger, and of course, the larger the apertures, the greater the growth thickness must be to achieve coalescence).

[0028] In one possible embodiment, the bonding of the heterostructure to the manipulation substrate includes either surface activation bonding (SAB) or atomic diffusion bonding (ADB). In this way, a high bond strength is obtained without the need for bond-strengthening annealing. This proves advantageous compared to the Smart Cut™ process implemented with trap-rich layers, for which, during heat treatment (such as that used to strengthen hydrophilic bonding), grains are rearranged, resulting in a deformation of the substrate. Localized formation occurs at the bonding interface, resulting in low localized bonding energy. Subsequently, during separation, the separation wave tends to pass through the weakly bonded area, and no layer transfer occurs around these regions. By using a 2D layer, there is no separation wave. Furthermore, no heat treatment is required for SAB and ADB techniques.

[0029] In another possible embodiment, the bonding of the heterostructure to the manipulation substrate includes a hydrophilic bond, and the formation of the first assembly further includes performing an annealing to enhance the bond strength, for example between 900 °C and 1100 °C. Plasma treatment of surfaces not yet bonded can also be implemented, which allows for increased bond strength.

[0030] Once the first assembly is formed by bonding the heterostructure to the bonding substrate 6, as shown in [Fig. 7], the method of the invention comprises separating the first assembly at the level of the molded intermediate layer 3 so as to obtain a second assembly (shown in [Fig. 8]) resulting from the transfer of the continuous epitaxial layer 4 from the heterostructure to the manipulation substrate 6. This separation can be a mechanical detachment at the level of the molded intermediate layer induced by separating the heterostructure and the manipulation substrate, for example by inserting a blade at the interface. Advantageously, this separation can be carried out at room temperature.

[0031] When the heterostructure comprises a bilayer, with reference to [Fig. 9], the method may further include the removal of the continuous epitaxial layer 4 from the second set. This removal may include a wet or dry etching of the continuous epitaxial layer 4 in which the additional layer 5 acts as an etching stop layer.

[0032] Figures 10 and 11 represent two possible embodiments of a heterostructure comprising a bilayer 4, 5 in which the additional layer 5 is a constrained layer grown by heteroepitaxy on the continuous epitaxial layer 4. The additional layer can be a constrained layer for the following reasons: - the continuous epitaxial layer 4 is a relaxed layer, its thickness is greater than a critical thickness which is the thickness up to which relaxation does not occur and beyond which relaxation occurs by plastic deformation; - the additional layer 5 is made of a material which has a different mesh parameter than the material of the epitaxial layer and its thickness is less than the critical thickness.

[0033] These two embodiments allow the transfer of such a constrained layer onto the manipulation substrate by detachment at the level of the modeled 2D interface 3. The transferred layer remains constrained after its transfer onto the manipulation substrate.

[0034] As shown in [Fig. 10], the growth substrate 1 can be a silicon substrate on which a 2D intermediate layer, for example made of graphene, is formed. The 2D intermediate layer is shaped, and the continuous epitaxial layer 4 is formed on the shaped 2D intermediate layer 3. The continuous epitaxial layer 4 can be a relaxed layer having a constant lattice parameter plateau, such as a relaxed SiGe layer with, for example, a Ge content of 20%. The additional layer 5 can be a strained silicon layer.

[0035] As shown in Figure 11, the growth substrate 1 can be a silicon substrate on which a gradient buffer 8 and a relaxed growth layer 9 are formed on the gradient buffer 8. The gradient buffer has a lattice parameter with a gradient between a first lattice parameter and a second lattice parameter, and the relaxed growth layer has the second lattice parameter. The gradient buffer can be a SiGe gradient buffer whose Ge content increases as the distance from the growth substrate 1 increases, for example, from a Ge content of 0% to 20%. The relaxed growth layer 9 can be a SiGe layer with a Ge content of 20%. A 2D intermediate layer, for example made of graphene, is formed on the relaxed growth layer 9. The 2D intermediate layer is molded, and the continuous epitaxial layer 4 is formed on the molded 2D intermediate layer 3.The continuous epitaxial layer 4 can be a relaxed layer with a constant lattice parameter plateau, such as a relaxed SiGe layer with, for example, a Ge content of 20%. The additional layer 5 can be a strained silicon layer.

[0036] Once separated at the level of the molded 2D intermediate layer, the heterostructure can be recycled as follows, for reuse in the method of the invention. First, remaining portions of the molded intermediate layer can be removed, for example, by oxygen treatment in the case of graphene. Then, in the case of [Fig. 10], the growth substrate can be ground and polished before it can be used in a new cycle beginning with the formation of a new 2D intermediate layer. In the case of [Fig. 11], the relaxed growth layer 9 can be polished before a new 2D intermediate layer is formed on it. In a preferred embodiment, the initial thickness of the relaxed growth layer 9 is several micrometers, thus allowing for several recycling cycles.Indeed, the polishing of the relaxed growth layer 9 in a cycle. Recycling can remove a thickness of between 3 µm and 4 µm. Performing multiple recycling cycles may require CTE compensation, as disclosed, for example, in US 2008 / 017952 Al, by including a constrained transition layer in the gradient buffer.

[0037] In addition to enabling the transfer of the continuous epitaxial layer onto the manipulation substrate without requiring a stress layer, the invention is also advantageous in that it provides a method for transferring a stress layer onto a manipulation substrate that overcomes the disadvantages of prior art solutions.

[0038] Considering the transfer of the strained silicon layer, a prior art solution using the Smart Cut™ process to fabricate a strained silicon-on-insulator structure is, for example, disclosed in WO 2007 / 019260 A1. It comprises the formation of a donor substrate by growing a strained Si layer on a relaxed SiGe layer and the formation of a cleavage plane in the relaxed SiGe layer by implanting ionic species. The donor substrate is then bonded to a manipulation substrate before being separated at the cleavage plane, thus transferring the strained Si layer to the manipulation substrate. Subsequently, the transferred strained Si layer is annealed to repair the damage caused by the implantation, thereby improving its crystallinity. However, a high number of dislocations are still observed, and it becomes difficult to reduce the through-dislocation density below 10⁵ / cm².Furthermore, numerous macroscopic defects are present in the final structure, particularly within the buried thin oxide layer. It should also be noted that this prior art solution hinders the integration of a trap-rich layer into the manipulation substrate due to the sensitivity of the transfer to the nanotopology / roughness of the bonded substrates.

[0039] Unlike this prior art solution, the present invention offers the following advantages. The number of dislocations in the strained Si film is reduced by performing epitaxy through the molded intermediate layer. Furthermore, since the detachment of the heterostructure at the 2D interface layer is completely different from Smart Cut™ separation, the defect in the transferred layer is improved. Another advantage is that the 2D material covers the entire surface of the substrate ([Fig. 2]), thus enabling full-slice layer transfer without an unbonded edge ring, which also simplifies the recycling process. A further advantage is its compatibility with the presence of a trap-rich layer.And finally, since the invention is not based on the implantation of ionic species, an annealing treatment is not necessary to repair the damage caused by the implantation and the invention can be. achieved with a very low thermal budget.

Claims

Demands

1. Method of manufacturing a stacked structure comprising a layer of semiconductor material bonded to a substrate, comprising: - the fabrication of a heterostructure by: • formation of an intermediate layer (2) consisting of a two-dimensional material on a growth substrate (1); • modeling of the intermediate layer with a plurality of openings to form a modeled intermediate layer (3); • growth of a semiconductor material on the molded intermediate layer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the molded intermediate layer; - the formation of a first assembly by gluing of the heterostructure to a manipulation substrate (6), the continuous epitaxial layer being located at the level of the bonding interface; - the separation of the first set at the level of the modeled intermediate layer (3) so as to obtain a second set resulting from the transfer of the continuous epitaxial layer (4) from the heterostructure to the manipulation substrate (6); in which the shaping of the intermediate layer (2) is carried out so that 1% to 10% of a surface of the growth substrate on which the shaped intermediate layer is located is uncovered, the remainder being covered by the two-dimensional material; in which the bonding of the heterostructure to the manipulation substrate includes one of surface activation bonding, atomic diffusion bonding and hydrophilic bonding accompanied by annealing to enhance bond strength.

2. Method according to claim 1, wherein the substrate of mani- pulation includes a top oxide layer (7) which is located at the bonding interface during the formation of the first assembly.

3. Method according to claim 2, wherein the manipulation substrate further comprises a trap-rich layer below the upper oxide layer.

4. Method according to claim 3, further comprising planarizing the upper oxide layer (7) before the formation of the first assembly.

5. Method according to any one of claims 1 to 4, wherein the continuous epitaxial layer (4) is a relaxed layer and wherein the fabrication of the heterostructure further comprises the epitaxial deposition of a constrained layer (5) on the continuous epitaxial layer (4).

6. Method according to claim 5, further comprising the removal of the continuous epitaxial layer (4) from the second set.

7. Method according to any one of claims 5 and 6, wherein the constrained layer is a constrained silicon layer.

8. Method according to any one of claims 1 to 7, wherein the growth substrate comprises a gradient buffer (8) and a relaxed growth layer (9) on the gradient buffer, the gradient buffer having a gradient mesh parameter between a first mesh parameter and a second mesh parameter and the relaxed growth layer having the second mesh parameter.

9. Method according to claim 8, further comprising, after separation of the first set at the level of the molded intermediate layer (3), recycling of the growth substrate, wherein said recycling comprises polishing of the relaxed growth layer (9).

10. Method according to any one of claims 1 to 9, wherein the continuous epitaxial layer (4) is a relaxed layer.

11. Method according to any one of claims 1 to 10, further comprising planarization of the continuous epitaxial layer (4) prior to the formation of the first set.

12. Method according to any one of claims 1 to 11, wherein the shaping of the intermediate layer (2) leaves a peripheral ring of the material in two dimensions on the growth substrate.

13. A method according to any one of claims 1 to 12, wherein two adjacent openings in the molded intermediate layer are separated by a distance of less than 40 micrometers, preferably in- less than 20 micrometers.

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