Nitride semiconductor device

Abstract

To suppress the decrease in reliability of connection in a drain electrode pad, a source electrode pad, and a gate electrode pad.SOLUTION: A nitride semiconductor device includes a nitride transistor, a first surface 21 where a drain pad 71, a source pad 72, and a gate pad 73 are provided, and an organic insulating layer 90 that covers the first surface 21. The organic insulating layer 90 includes a drain opening part 91, a source opening part 92, and a gate opening part 93. Each of the pads 71 to 73 includes a first metal layer 81 provided on the first surface 21, and a second metal layer 82 that is formed of a material that is oxidized less easily than the first metal layer 81 and that covers the first metal layer 81. A part of the gate pad 73 that is exposed by the gate opening part 93, a part of the source pad 72 that is exposed by the source opening part 92, and a part of the drain pad 71 that is exposed by the drain opening part 91 correspond to the second metal layer 82.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a transistor that is a HEMT (High Electron Mobility Transistor) using a nitride semiconductor, a lead frame on which the transistor is mounted, and a sealing resin that seals the transistor. Five drain electrode pads, four source electrode pads, and one gate electrode pad are provided on the surface of the transistor. The drain electrode pad is electrically connected to a drain frame of the lead frame. The source electrode pad is electrically connected to a source frame of the lead frame. The gate electrode pad is electrically connected to a gate frame of the lead frame. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6827776

[0004] [overview] It is desirable to suppress a decrease in the reliability of connections in the drain electrode pad, source electrode pad, and gate electrode pad.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes a nitride semiconductor chip including a nitride transistor having a drain electrode, a source electrode, and a gate electrode, and a first surface on which a drain pad electrically connected to the drain electrode, a source pad electrically connected to the source electrode, and a gate pad electrically connected to the gate electrode are provided, and an organic insulating layer covering the first surface, wherein the organic insulating layer has a drain opening exposing the drain pad, a source opening exposing the source pad, and a gate opening exposing the gate pad, and is provided between the drain opening and the source opening; and a first insulating portion insulating the drain pad and the source pad, wherein each of the drain pad, the source pad, and the source pad includes a first metal layer provided on the first surface and a second metal layer made of a material less susceptible to oxidation than the first metal layer and covering the first metal layer, wherein the portion of the drain pad exposed by the drain opening is the second metal layer, the portion of the source pad exposed by the source opening is the second metal layer, and the portion of the gate pad exposed by the gate opening is the second metal layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing the internal configuration of an exemplary nitride semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is a schematic perspective view of a nitride semiconductor chip in the nitride semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic plan view of the nitride semiconductor chip of FIG. [Figure 5] FIG. 5 is a schematic plan view showing the internal wiring configuration of the nitride semiconductor chip of FIG. [Figure 6] FIG. 6 is a schematic plan view of a transistor cell of the nitride semiconductor chip of FIG. [Figure 7] FIG. 7 is a schematic plan view showing an enlarged view of a part of the transistor cell and a part of the wiring in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the nitride semiconductor chip taken along line F8-F8 in FIG. [Figure 9] FIG. 9 is an enlarged schematic cross-sectional view of the gate pad and its periphery in the nitride semiconductor chip of FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of the nitride semiconductor chip taken along line F10-F10 in FIG. [Figure 11] FIG. 11 is an enlarged schematic cross-sectional view of the drain pad and its periphery in the nitride semiconductor chip of FIG. [Figure 12] FIG. 12 is an enlarged schematic cross-sectional view of the source pad and its periphery in the nitride semiconductor chip of FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view of the nitride semiconductor chip taken along line F13-F13 in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of the nitride semiconductor chip taken along line F10-F10 in FIG. 9 with the clip joined thereto. [Figure 15] FIG. 15 is an enlarged schematic cross-sectional view of the drain clip and its periphery shown in FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view illustrating an exemplary manufacturing process of a nitride semiconductor device according to an embodiment. [Figure 17] FIG. 17 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view of a modified nitride semiconductor chip with a clip joined thereto. [Figure 22]FIG. 22 is a schematic plan view showing an enlarged view of a drain pad, a source pad, and their surroundings in a nitride semiconductor chip according to a modified example. [Figure 23] FIG. 23 is a schematic plan view showing an enlarged view of a drain pad, a source pad, and the periphery thereof in a nitride semiconductor chip according to a modified example. [Figure 24] FIG. 24 is a schematic plan view showing an enlarged view of a drain pad, a source pad, and the periphery thereof in a nitride semiconductor chip according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] [Overall configuration of nitride semiconductor device] The overall configuration of the nitride semiconductor device 10 will be described with reference to FIGS. Fig. 1 schematically shows the planar structure of the interior of the nitride semiconductor device 10. Fig. 2 schematically shows the cross-sectional structure of the nitride semiconductor device 10 taken along line F2-F2 in Fig. 1. Note that Fig. 1 shows a see-through view of a sealing resin 240, which will be described later, so that the interior of the nitride semiconductor device 10 can be seen.

[0012] As shown in Figures 1 and 2, the nitride semiconductor device 10 has a flat plate shape with its thickness direction aligned in the Z direction. In one example, the nitride semiconductor device 10 has a rectangular shape having long and short sides when viewed from the Z direction. In the example shown in Figure 1, the nitride semiconductor device 10 is arranged so that its long sides extend along the X direction and its short sides extend along the Y direction. Hereinafter, viewing the nitride semiconductor device 10 from the Z direction will be referred to as a "planar view."

[0013] The nitride semiconductor device 10 includes a nitride semiconductor chip 20, a die pad 200, a drain terminal 210, a source terminal 220, a gate terminal 230, and a sealing resin 240. The nitride semiconductor device 10 includes a drain clip 110, a source clip 120, and a gate wire 130.

[0014] The sealing resin 240 forms the exterior of the nitride semiconductor device 10. For this reason, the sealing resin 240 has a rectangular plate shape. The sealing resin 240 seals the nitride semiconductor chip 20, the drain clip 110, the source clip 120, and the gate wire 130. The sealing resin 240 seals the die pad 200, the drain terminal 210, the source terminal 220, and the gate terminal 230, leaving them partially exposed. The sealing resin 240 is made of a material containing an insulating material. In one example, the sealing resin 240 is made of a material containing a black epoxy resin.

[0015] The sealing resin 240 includes a first sealing surface 241, a second sealing surface 242 opposite the first sealing surface 241, and first to fourth sealing side surfaces 243 to 246 as four side surfaces connecting the first sealing surface 241 and the second sealing surface 242. The first sealing side surface 243 and the second sealing side surface 244 constitute both end surfaces of the sealing resin 240 in the X direction. The third sealing side surface 245 and the fourth sealing side surface 246 constitute both end surfaces of the sealing resin 240 in the Y direction. The die pad 200, the drain terminal 210, the source terminal 220, and the gate terminal 230 are each exposed from the second sealing surface 242. Therefore, the nitride semiconductor device 10 has a surface-mount package structure. The package structure of the nitride semiconductor device 10 can be changed as desired.

[0016] The nitride semiconductor chip 20 is a semiconductor chip provided with a nitride transistor 30 (see FIG. 6). The nitride semiconductor chip 20 has a flat plate shape with its thickness direction aligned in the Z direction. In one example, the nitride semiconductor chip 20 has a rectangular shape having long and short sides in a plan view. In the example shown in FIG. 1, the nitride semiconductor chip 20 is arranged so that its long sides extend along the X direction and its short sides extend along the Y direction.

[0017] The nitride semiconductor chip 20 includes a first surface 21, a second surface 22 opposite to the first surface 21, and first to fourth side surfaces 23 to 26 as four side surfaces connecting the first surface 21 and the second surface 22. The first side surface 23 and the second side surface 24 constitute both end surfaces of the nitride semiconductor chip 20 in the X direction, and the third side surface 25 and the fourth side surface 26 constitute both end surfaces of the nitride semiconductor chip 20 in the Y direction. The first surface 21 is provided with a plurality of drain pads 71 ​​(three in this embodiment), a plurality of source pads 72 (two in this embodiment), and a gate pad 73. The detailed configuration of the nitride semiconductor chip 20 will be described later.

[0018] The nitride semiconductor chip 20 is mounted on a die pad 200. In one example, the nitride semiconductor chip 20 is bonded to the die pad 200 by a conductive bonding material SD. The die pad 200 has a flat plate shape with its thickness direction aligned in the Z direction. The die pad 200 has a rectangular shape with long and short sides in a plan view. In the example shown in FIG. 1, the die pad 200 is arranged so that its long sides extend along the X direction and its short sides extend along the Y direction.

[0019] The drain terminal 210 is disposed closer to the third sealing side surface 245 than the die pad 200. The drain terminal 210 is disposed apart from the die pad 200 in the Y direction. The drain terminal 210 is provided in a strip shape extending in the X direction in a plan view.

[0020] The source terminal 220 and the gate terminal 230 are arranged closer to the fourth sealing side surface 246 with respect to the die pad 200. In other words, the source terminal 220 and the gate terminal 230 are arranged on the opposite side of the die pad 200 from the drain terminal 210. The source terminal 220 and the gate terminal 230 are arranged spaced apart from the die pad 200 in the Y direction. The source terminal 220 and the gate terminal 230 are arranged at the same position as each other in the Y direction and spaced apart from each other in the X direction. The gate terminal 230 is arranged closer to the second sealing side surface 244 than the source terminal 220.

[0021] The source terminal 220 is provided in a strip shape extending in the X direction in a plan view. The dimension of the source terminal 220 in the X direction is shorter than the dimension of the drain terminal 210 in the X direction. The gate terminal 230 is provided in a rectangular shape in a plan view. The dimension of the gate terminal 230 in the X direction is shorter than the dimension of the source terminal 220 in the X direction.

[0022] The die pad 200, the drain terminal 210, the source terminal 220, and the gate terminal 230 are exposed from the second sealing surface 242. Therefore, the drain terminal 210, the source terminal 220, and the gate terminal 230 constitute external electrode terminals that are electrically connected to wiring on a circuit board (not shown) when the nitride semiconductor device 10 is mounted on the circuit board, for example.

[0023] The die pad 200, the drain terminal 210, the source terminal 220, and the gate terminal 230 are made of a conductive material such as aluminum (Al), copper (Cu), etc. The die pad 200, the drain terminal 210, the source terminal 220, and the gate terminal 230 are made of a material containing Cu, for example.

[0024] The nitride semiconductor chip 20 is connected to the drain terminal 210, the source terminal 220, and the gate terminal 230 using a drain clip 110, a source clip 120, and a gate wire 130, respectively. The drain clip 110 and the source clip 120 are conductive. The drain clip 110 and the source clip 120 are provided by bending a metal plate such as Al or Cu. The gate wire 130 is made of a conductive material such as Al, Cu, silver (Ag), or gold (Au). The gate wire 130 is, for example, a bonding wire.

[0025] Since the nitride semiconductor chip 20 and the drain terminal 210 are connected by the drain clip 110, the drain of the nitride transistor 30 is electrically connected to the drain terminal 210. Since the nitride semiconductor chip 20 and the source terminal 220 are connected by the source clip 120, the source of the nitride transistor 30 is electrically connected to the source terminal 220. Since the nitride semiconductor chip 20 and the gate terminal 230 are connected by the gate wire 130, the gate of the nitride transistor 30 is electrically connected to the gate terminal 230.

[0026] [Detailed structure of nitride semiconductor chip] Next, the detailed configuration of the nitride semiconductor chip 20 will be described with reference to FIGS. 3 to 8. FIG. 3 schematically shows a perspective structure of the nitride semiconductor chip 20. FIG. 4 schematically shows a planar structure of the nitride semiconductor chip 20. FIG. 5 schematically shows an example of a planar structure inside the nitride semiconductor chip 20. FIG. 6 schematically shows an example of a planar structure of the nitride transistor 30 in the nitride semiconductor chip 20. FIG. 7 schematically shows an enlarged planar structure of a portion of the nitride transistor 30. FIG. 8 schematically shows an example of a cross-sectional structure of the nitride semiconductor chip 20 taken along line F8-F8 in FIG. 7.

[0027] 3 and 4, the nitride semiconductor chip 20 includes a plurality of (three in this embodiment) drain pads 71, a plurality of (two in this embodiment) source pads 72, and a gate pad 73. The drain pads 71, the source pads 72, and the gate pad 73 are used as external electrode terminals of the nitride semiconductor chip 20.

[0028] The drain pads 71 ​​and the source pads 72 are alternately arranged one by one in the X direction. In plan view, each drain pad 71 and each source pad 72 extends in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the drain pads 71 ​​and the source pads 72. In plan view, each drain pad 71 and each source pad 72 has a rectangular shape with its long side extending in the Y direction and its short side extending in the X direction. Here, the X direction is an example of a "first direction."

[0029] The gate pad 73 is disposed in a corner portion of the nitride semiconductor chip 20 that is closer to the second side surface 24 and the fourth side surface 26. The gate pad 73 has a rectangular shape in a plan view. In one example, the gate pad 73 has a square shape in a plan view. The arrangement and shape of the gate pad 73 in a plan view can be changed as desired.

[0030] The gate pad 73 is disposed adjacent to one of the plurality of drain pads 71 ​​in the Y direction. Here, the drain pad 71 adjacent to the gate pad 73 among the plurality of drain pads 71 ​​is referred to as an "end drain pad 71E." The dimension in the Y direction of the end drain pad 71E is shorter than the dimension in the Y direction of the other drain pads 71. In addition, the gate pad 73 is disposed adjacent to one of the plurality of source pads 72 in the X direction. Here, the Y direction is an example of a "second direction."

[0031] 6, the nitride semiconductor chip 20 includes a nitride transistor 30. The nitride transistor 30 is configured as a high electron mobility transistor (HEMT) using a nitride semiconductor.

[0032] The nitride transistor 30 of the nitride semiconductor chip 20 includes a plurality of first transistor cells TA, a plurality of second transistor cells TB, and a plurality of third transistor cells TC. The plurality of first transistor cells TA are arranged along the X direction. The plurality of second transistor cells TB are arranged along the X direction. The plurality of second transistor cells TB are arranged adjacent to the plurality of first transistor cells TA in the Y direction. The plurality of third transistor cells TC are arranged along the X direction. The plurality of third transistor cells TC are arranged on the opposite side of the plurality of second transistor cells TB from the plurality of first transistor cells TA in the Y direction. In other words, the plurality of second transistor cells TB are arranged between the plurality of first transistor cells TA and the plurality of third transistor cells TC in the Y direction.

[0033] Corner regions 27, in which no transistor cells are formed, are provided adjacent to both the second transistor cells TB and the third transistor cells TC. The corner regions 27 can also be said to be provided in corner portions of the nitride semiconductor chip 20 that are closer to the second side surface 24 and the fourth side surface 26. The corner regions 27 are regions where gate pads 73 (see FIG. 4) are provided in a plan view.

[0034] Each of the first to third transistor cells TA, TB, and TC includes a drain electrode 41, a source electrode 42, and a gate electrode 43. Both the drain electrode 41 and the source electrode 42 may be strip-shaped extending in the Y direction in plan view. The gate electrode 43 may be annular in shape surrounding the drain electrode 41 in plan view.

[0035] The drain electrodes 41 and source electrodes 42 of the multiple first transistor cells TA are arranged alternately and spaced apart from each other in the X direction. The annular gate electrode 43 of each of the multiple first transistor cells TA includes a portion that is arranged between the drain electrode 41 and source electrode 42 of each of the multiple first transistor cells TA in the X direction.

[0036] The arrangement of the drain electrodes 41, source electrodes 42, and gate electrodes 43 of the second transistor cells TB is the same as that of the first transistor cells TA. The drain electrodes 41, source electrodes 42, and gate electrodes 43 of the second transistor cells TB are arranged at the same positions in the X direction as the drain electrodes 41, source electrodes 42, and gate electrodes 43 of the first transistor cells TA adjacent to them in the Y direction. The gate electrodes 43 of the second transistor cells TB are integrated with the gate electrodes 43 of the first transistor cells TA adjacent to them in the Y direction.

[0037] The arrangement of the drain electrodes 41, source electrodes 42, and gate electrodes 43 of the multiple third transistor cells TC is the same as that of the multiple second transistor cells TB. The drain electrodes 41, source electrodes 42, and gate electrodes 43 of the multiple third transistor cells TC are arranged at the same positions in the X direction as the drain electrodes 41, source electrodes 42, and gate electrodes 43 of the second transistor cells TB adjacent to them in the Y direction. The gate electrodes 43 of the multiple third transistor cells TC are integrated with the gate electrodes 43 of the second transistor cells TB adjacent to them in the Y direction.

[0038] 5, the nitride semiconductor device 10 includes a plurality of (three in this embodiment) drain wirings 61A to 61C, a plurality of (three in this embodiment) source wirings 62A to 62C, and a gate wiring 63. The drain wirings 61A to 61C, the source wirings 62A to 62C, and the gate wiring 63 are provided on a first insulating layer 54, which will be described later, that covers the nitride transistor 30.

[0039] The plurality of drain wirings 61A to 61C are arranged to be spaced apart from one another in the Y direction. Each of the drain wirings 61A to 61C has a strip shape extending in the X direction in a plan view. The drain wiring 61A is a wiring that electrically connects the drain electrode 41 of each first transistor cell TA to the drain pad 71 (see FIG. 4). The drain wiring 61A is arranged at a position that overlaps with the first transistor cell TA in a planar view. The drain wiring 61A is arranged so as to overlap with both the drain electrode 41 and the source electrode 42 of the multiple first transistor cells TA in a planar view. The drain wiring 61A extends over the entire multiple first transistor cells TA in the X direction in a planar view. The drain wiring 61A is electrically connected to the drain electrodes 41 of the multiple first transistor cells TA by multiple drain vias 66 (see FIG. 7).

[0040] The drain wiring 61B is a wiring that electrically connects the drain electrode 41 of each second transistor cell TB and the drain pad 71. The drain wiring 61B is arranged at a position that overlaps with the second transistor cell TB in a planar view. The drain wiring 61B is arranged so as to overlap with both the drain electrode 41 and the source electrode 42 of the second transistor cells TB in a planar view. The drain wiring 61B extends over the entire X-direction of the second transistor cells TB in a planar view. The dimension of the drain wiring 61B in the X-direction is equal to the dimension of the drain wiring 61A in the X-direction. The drain wiring 61B is electrically connected to the drain electrodes 41 of the second transistor cells TB by a plurality of drain vias 66.

[0041] The drain wiring 61C is a wiring that electrically connects the drain electrode 41 of each third transistor cell TC and the drain pad 71. The drain wiring 61C is arranged at a position that overlaps with the third transistor cell TC in a planar view. The drain wiring 61C is arranged so as to overlap with both the drain electrode 41 and the source electrode 42 of the plurality of third transistor cells TC in a planar view. The drain wiring 61C extends over the entirety of the plurality of third transistor cells TC in the X direction in a planar view. The dimension of the drain wiring 61C in the X direction is smaller than the dimension of the drain wiring 61A in the X direction. The drain wiring 61C is electrically connected to the drain electrodes 41 of the plurality of third transistor cells TC by a plurality of drain vias 66.

[0042] The plurality of source wirings 62A to 62C are arranged to be spaced apart from one another in the Y direction. Each of the source wirings 62A to 62C has a strip shape extending in the X direction in a plan view. The source wiring 62A is a wiring that electrically connects the source electrode 42 of each first transistor cell TA and the source pad 72 (see FIG. 4). The source wiring 62A is arranged at a position that overlaps with the first transistor cell TA in a planar view. The source wiring 62A is arranged so as to overlap with both the drain electrode 41 and the source electrode 42 of the plurality of first transistor cells TA in a planar view. The source wiring 62A is arranged at a position adjacent to the drain wiring 61A in the Y direction. The source wiring 62A extends over the entirety of the plurality of first transistor cells TA in the X direction in a planar view. The source wiring 62A is electrically connected to the source electrodes 42 of the plurality of first transistor cells TA by a plurality of source vias 67 (see FIG. 7).

[0043] The source wiring 62B is a wiring that electrically connects the source electrode 42 of each second transistor cell TB and the source pad 72. The source wiring 62B is arranged at a position overlapping the second transistor cell TB in a planar view. The source wiring 62B is arranged so as to overlap both the drain electrode 41 and the source electrode 42 of the second transistor cells TB in a planar view. The source wiring 62B is arranged at a position adjacent to the drain wiring 61B in the Y direction. The source wiring 62B extends over the entire X direction of the second transistor cells TB in a planar view. The dimension of the source wiring 62B in the X direction is equal to the dimension of the source wiring 62A in the X direction. The source wiring 62B is electrically connected to the source electrodes 42 of the second transistor cells TB by a plurality of source vias 67.

[0044] The source wiring 62C is a wiring that electrically connects the source electrode 42 of each third transistor cell TC to the source pad 72. The source wiring 62C is arranged at a position overlapping the third transistor cell TC in a planar view. The source wiring 62C is arranged so as to overlap both the drain electrode 41 and the source electrode 42 of the third transistor cells TC in a planar view. The source wiring 62C is arranged at a position adjacent to the drain wiring 61C in the Y direction. The source wiring 62C extends over the entire X direction of the third transistor cells TC in a planar view. The dimension of the source wiring 62C in the X direction is smaller than the dimension of the source wiring 62A in the X direction. The source wiring 62C is electrically connected to the source electrodes 42 of the third transistor cells TC by a plurality of source vias 67.

[0045] The gate wiring 63 is a wiring electrically connected to the gate pad 73 (see FIG. 4). The gate wiring 63 includes a peripheral gate wiring 64 and an intermediate gate wiring 65. The peripheral gate wiring 64 is provided on the periphery of the nitride semiconductor chip 20 in a plan view. The peripheral gate wiring 64 is wiring that surrounds the first to third transistor cells TA, TB, and TC. The peripheral gate wiring 64 includes a pad connection portion 64A and a peripheral wiring portion 64B. The pad connection portion 64A is provided in the corner region 27. The peripheral wiring portion 64B is connected to the pad connection portion 64A and is provided in a ring shape that surrounds the first to third transistor cells TA, TB, and TC, the drain wirings 61A to 61C, and the source wirings 62A to 62C.

[0046] The intermediate gate wiring 65 is disposed between the first transistor cell TA and the second transistor cell TB in the Y direction and between the second transistor cell TB and the third transistor cell TC in the Y direction. The intermediate gate wiring 65 is disposed at a position where it does not overlap with the drain wiring 61A to 61C and the source wiring 62A to 62C in a plan view. The intermediate gate wiring 65 has a strip shape extending in the X direction in a plan view. In one example, the width of the intermediate gate wiring 65 is smaller than the width of the drain wiring 61A to 61C and the width of the source wiring 62A to 62C. The intermediate gate wiring 65 is connected to the peripheral wiring portion 64B of the peripheral gate wiring 64. The intermediate gate wiring 65 disposed between the second transistor cell TB and the third transistor cell TC in the Y direction is connected to the pad connection portion 64A. The intermediate gate wiring 65 is electrically connected to the gate electrodes 43 of the first to third transistor cells TA, TB, and TC by a plurality of gate vias 68 (see FIG. 7).

[0047] (Schematic cross-sectional structure of nitride semiconductor chip) 8, the nitride semiconductor chip 20 includes a semiconductor substrate 31 and a semiconductor layer 32 provided on the semiconductor substrate 31. A part of the nitride transistor 30 is provided on the semiconductor layer 32.

[0048] The semiconductor substrate 31 may be made of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 31 is a Si substrate. The thickness of the semiconductor substrate 31 may be, for example, 200 μm or more and 1500 μm or less. The Z direction corresponds to the thickness direction of the semiconductor substrate 31.

[0049] The semiconductor layer 32 includes a buffer layer 33 formed on the semiconductor substrate 31, an electron transit layer 34 formed on the buffer layer 33, and an electron supply layer 35 formed on the electron transit layer 34.

[0050] The buffer layer 33 may be made of any material capable of suppressing wafer warpage and cracking due to mismatch in thermal expansion coefficients between the semiconductor substrate 31 and the electron transit layer 34. The buffer layer 33 may include one or more nitride semiconductor layers. The buffer layer 33 may include, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 33 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0051] The electron transit layer 34 is made of a nitride semiconductor. The electron transit layer 34 is made of a material containing GaN. In one example, the electron transit layer 34 may be, for example, a GaN layer. The thickness of the electron transit layer 34 may be, for example, 0.1 μm or more and 2 μm or less. The electron transit layer 34 may include one or more nitride semiconductor layers. Furthermore, in order to suppress leakage current in the electron transit layer 34, impurities may be introduced into a portion of the electron transit layer 34 to make the electron transit layer 34 semi-insulating except for the surface region. In this case, the impurity is, for example, carbon (C). The impurity concentration of the carbon may be, for example, 1×10 19 cm -3 It may be more than that.

[0052] The electron supply layer 35 is composed of a nitride semiconductor having a larger band gap than the electron transport layer 34. The electron supply layer 35 may be, for example, an AlGaN layer. Since the larger the Al composition, the larger the band gap, the electron supply layer 35 which is an AlGaN layer has a larger band gap than the electron transport layer 34 which is a GaN layer. In one example, the electron supply layer 35 is Al x Ga 1-x N. In this case, x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the electron supply layer 35 can be, for example, 5 nm or more and 20 nm or less.

[0053] The electron transport layer 34 and the electron supply layer 35 have different lattice constants in the bulk region. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 34 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 35 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 34 and the electron supply layer 35 and the piezo-polarization caused by the compressive stress received by the hetero-junction portion of the electron transport layer 34, the energy level of the conduction band of the electron transport layer 34 near the hetero-junction interface between the electron transport layer 34 and the electron supply layer 35 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 36 is formed in the electron transport layer 34 at a position close to the hetero-junction interface between the electron transport layer 34 and the electron supply layer 35 (for example, at a distance of about several nm from the interface).

[0054] The nitride semiconductor chip 20 includes a gate layer 37 formed on a part of the electron supply layer 35. The gate layer 37 is composed of a nitride semiconductor. In one example, the gate layer 37 is composed of a nitride semiconductor having a smaller band gap than the electron supply layer 35 and containing acceptor-type impurities. In one example, the gate layer 37 is GaN (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurity may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurity in the gate layer 37 is, for example, 7×10 18 cm -3More than 1×10 20 cm -3 The following is the result.

[0055] A gate electrode 43 is provided on the gate layer 37. The gate electrode 43 includes one or more metal layers. For example, the gate electrode 43 may be a titanium nitride (TiN) layer. For example, the gate electrode 43 may be formed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 43 may be formed of, for example, a material that forms a Schottky junction with the gate layer 37. An example of such a material is TiN. The thickness of the gate electrode 43 may be, for example, 50 nm or more and 200 nm or less.

[0056] The nitride semiconductor chip 20 includes a passivation layer 51. The passivation layer 51 covers the electron supply layer 35, the gate layer 37, and the gate electrode 43. The passivation layer 51 may be composed of one or any combination of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 51 may be, for example, 50 nm to 200 nm, preferably 80 nm to 150 nm. The passivation layer 51 includes a source opening 52 and a drain opening 53, each of which exposes a portion of the upper surface 35A of the electron supply layer 35.

[0057] A source electrode 42 is provided in the source opening 52. A drain electrode 41 is provided in the drain opening 53. The source electrode 42 includes a source contact portion that contacts the electron supply layer 35 through the source opening 52. The drain electrode 41 includes a drain contact portion that contacts the electron supply layer 35 through the drain opening 53.

[0058] The drain electrode 41 and the source electrode 42 include one or more metal layers. In one example, the drain electrode 41 and the source electrode 42 may be made of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, the drain electrode 41 and the source electrode 42 are made of a first metal layer in contact with the electron supply layer 35, a second metal layer stacked on the second metal layer, a third metal layer stacked on the second metal layer, and a fourth metal layer stacked on the third metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

[0059] The drain contact portion of the drain electrode 41 is filled in the drain opening 53. The drain contact portion is in ohmic contact with the 2DEG 36 immediately below the electron supply layer 35 through the drain opening 53. The source contact portion of the source electrode 42 is filled in the source opening 52. The source contact portion is in ohmic contact with the 2DEG 36 immediately below the electron supply layer 35 through the source opening 52. Although not shown in the figure, the semiconductor substrate 31 is electrically connected to the source electrode 42. As a result, a voltage having the same potential as that of the source electrode 42 is applied to the semiconductor substrate 31.

[0060] In a structure in which the gate layer 37 is formed of a nitride semiconductor containing acceptor-type impurities, the conduction path (channel) is blocked by depletion of the 2DEG 36 in the region directly below the gate layer 37 at zero bias when no voltage is applied to the gate electrode 43. This realizes a normally-off HEMT in which the gate threshold voltage is a positive value.

[0061] In the example shown in FIG. 8 , the gate layer 37 includes a ridge portion 37A and a drain-side extension portion 37B and a source-side extension portion 37C that are thinner than the ridge portion 37A. The ridge portion 37A corresponds to a relatively thick portion of the gate layer 37. The gate electrode 43 is in contact with the ridge portion 37A. The ridge portion 37A may have a rectangular or trapezoidal shape in a cross section along the XZ plane. The thickness of the ridge portion 37A may be, for example, 100 nm or more and 200 nm or less. The thickness of the ridge portion 37A can be defined by the distance in the Z direction between the upper surface 37AA of the ridge portion 37A and the upper surface 35A of the electron supply layer 35. The thickness of the ridge portion 37A is determined in consideration of various parameters such as the gate breakdown voltage.

[0062] The drain-side extension portion 37B and the source-side extension portion 37C extend in opposite directions relative to the ridge portion 37A. More specifically, the drain-side extension portion 37B extends from the ridge portion 37A toward the drain opening 53 in the passivation layer 51. It can also be said that the drain-side extension portion 37B extends from the ridge portion 37A toward the drain electrode 41. The source-side extension portion 37C extends from the ridge portion 37A toward the source opening 52 in the passivation layer 51. It can also be said that the source-side extension portion 37C extends from the ridge portion 37A toward the source electrode 42.

[0063] The thickness of the drain side extension portion 37B can be, for example, 60 nm or less. The thickness of the drain side extension portion 37B can be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness of the drain side extension portion 37B can be, for example, 10 nm or more. The thickness of the source side extension portion 37C can be, for example, 60 nm or less. The thickness of the source side extension portion 37C can be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness of the source side extension portion 37C can be, for example, 10 nm or more. In one example, the thickness of the drain side extension portion 37B and the thickness of the source side extension portion 37C are equal to each other. Here, the thickness of the drain side extension portion 37B can be defined by the distance in the Z direction between the upper surface 37BA of the drain side extension portion 37B and the upper surface 35A of the electron supply layer 35. The thickness of the source-side extension portion 37C can be defined by the distance in the Z direction between an upper surface 37CA of the source-side extension portion 37C and an upper surface 35A of the electron supply layer 35. At least one of the drain-side extension portion 37B and the source-side extension portion 37C may be omitted from the gate layer 37.

[0064] The nitride semiconductor chip 20 includes a field plate electrode 44 provided on the passivation layer 51. The field plate electrode 44 is electrically connected to the source electrode 42. In the example shown in FIG. 8 , the field plate electrode 44 is formed integrally with the source electrode 42. That is, a portion of the source electrode 42 is provided as the field plate electrode 44. Therefore, a voltage having the same potential as that of the source electrode 42 is applied to the field plate electrode 44. The field plate electrode 44 is also called a source field plate. The field plate electrode 44 covers the entire gate layer 37 in a plan view. The field plate electrode 44 may be provided separately from the source electrode 42. In this case, the field plate electrode 44 may be disposed apart from the source electrode 42.

[0065] The nitride semiconductor chip 20 includes a first insulating layer 54 provided on the passivation layer 51. The first insulating layer 54 covers the drain electrode 41, the source electrode 42, and the field plate electrode 44. The first insulating layer 54 may be made of, for example, one or any combination of SiO2, SiN, SiON, Al2O3, AlN, and AlON. In one example, the first insulating layer 54 is made of a material containing SiO2.

[0066] Drain wirings 61A to 61C, source wirings 62A to 62C, and gate wiring 63 (all see FIG. 4) are provided on the first insulating layer 54. Drain vias 66, source vias 67, and gate vias 68 (all see FIG. 7) are each provided to penetrate the first insulating layer 54 in the Z direction.

[0067] [Pad Configuration] The configurations of the drain pad 71, the source pad 72, and the gate pad 73 will be described with reference to FIG. 4 and FIGS. 9 to 13. FIG. 9 schematically shows an enlarged planar structure of the gate pad 73 and its periphery in the nitride semiconductor chip 20. FIG. 10 schematically shows a cross-sectional structure of the nitride semiconductor chip 20 taken along line F10-F10 in FIG. 9. FIG. 11 schematically shows an enlarged cross-sectional structure of the drain pad 71 and its periphery in FIG. 10. FIG. 12 schematically shows an enlarged cross-sectional structure of the source pad 72 and its periphery in FIG. 10. FIG. 13 schematically shows a cross-sectional structure of the nitride semiconductor chip 20 taken along line F13-F13 in FIG. 10.

[0068] As shown in FIG. 10, the nitride semiconductor chip 20 includes a second insulating layer 55 provided on the first insulating layer 54. The second insulating layer 55 is provided on the first insulating layer 54. The second insulating layer 55 covers the drain wirings 61A-61C, the source wirings 62A-62C, and the gate wiring 63 (see FIG. 4 for all of these). The second insulating layer 55 may be made of, for example, one or any combination of SiO2, SiN, SiON, Al2O3, AlN, and AlON. In one example, the second insulating layer 55 is made of a material containing SiO2. Here, in this embodiment, the second insulating layer 55 forms the first surface 21 of the nitride semiconductor chip 20. The second insulating layer 55 is a protective layer for the nitride semiconductor chip 20.

[0069] The drain pad 71, the source pad 72, and the gate pad 73 (see FIG. 9) are each provided on the second insulating layer 55. The drain pad 71 is electrically connected to the drain wirings 61A to 61C by a plurality of drain vias 74. The plurality of drain vias 74 are arranged at positions overlapping both the drain wirings 61A to 61C and the drain pad 71 in a plan view. The source pad 72 is electrically connected to the source wirings 62A to 62C by a plurality of source vias 75. The plurality of source vias 75 are arranged at positions overlapping both the source wirings 62A to 62C and the source pad 72 in a plan view. The gate pad 73 is electrically connected to the gate wiring 63 by a plurality of gate vias 76 (see FIG. 13). The plurality of gate vias 76 are arranged at positions overlapping both the pad connection portion 64A of the gate wiring 63 (see FIG. 5) and the gate pad 73 in a plan view.

[0070] The nitride semiconductor device 10 includes an organic insulating layer 90 covering the first surface 21 of the nitride semiconductor chip 20. It can also be said that the nitride semiconductor chip 20 includes the organic insulating layer 90 covering the first surface 21. In this embodiment, the organic insulating layer 90 covers the entire first surface 21. The organic insulating layer 90 is made of, for example, a photosensitive resin. An example of a photosensitive resin is a polyimide (PI) resin. Therefore, it can be said that the organic insulating layer 90 is made of a material containing PI.

[0071] As shown in FIG. 9, the organic insulating layer 90 includes a drain opening 91, a source opening 92, and a gate opening 93. The drain opening 91 exposes the drain pad 71. A plurality of drain openings 91 are provided corresponding to the number of drain pads 71. The source opening 92 exposes the source pad 72. As shown in FIG. 4, a plurality of source openings 92 are provided corresponding to the number of source pads 72. The plurality of drain openings 91 and the plurality of source openings 92 are alternately arranged one by one in the X direction. The gate opening 93 exposes the gate pad 73.

[0072] (Drain pad) As shown in FIG. 11 , the drain pad 71 includes a first metal layer 81 provided on the first surface 21 of the nitride semiconductor chip 20 and a second metal layer 82 covering the first metal layer 81. The first metal layer 81 is made of a material containing at least one of Al and Cu. In this embodiment, the first metal layer 81 is made of a material containing Cu. The second metal layer 82 is made of a material that is less susceptible to oxidation than the first metal layer 81. The second metal layer 82 is made of a material containing nickel (Ni) and gold (Au), for example. In one example, the second metal layer 82 has a stacked structure of a Ni layer and an Au layer. The Ni layer is provided on the upper surface 81A of the first metal layer 81. The Au layer is provided on the Ni layer.

[0073] A plurality of drain vias 74 are provided on a lower surface 81B of the first metal layer 81 of the drain pad 71. Here, the lower surface 81B of the first metal layer 81 is the surface of the first metal layer 81 that is in contact with the upper surface of the second insulating layer 55. The plurality of drain vias 74 are provided integrally with, for example, the first metal layer 81. Therefore, the plurality of drain vias 74 are made of, for example, the same material as the first metal layer 81. Note that the plurality of drain vias 74 may be provided separately from the first metal layer 81. Furthermore, the plurality of drain vias 74 may be made of a material different from that of the first metal layer 81.

[0074] 9 and 11, the organic insulating layer 90 includes a drain wrap portion 94 provided at a position overlapping the periphery of the first metal layer 81 of the drain pad 71 in a plan view. In this embodiment, the drain wrap portion 94 is provided around the entire periphery of the first metal layer 81. As a result, the drain wrap portion 94 defines a drain opening 91. In other words, the drain opening 91 is smaller than the first metal layer 81 of the drain pad 71 in a plan view. The drain wrap portion 94 has a rectangular frame shape with its long sides extending in the Y direction and its short sides extending in the X direction in a plan view.

[0075] A second metal layer 82 is provided on a drain exposed portion 71A, which is a portion of the upper surface 81A of the first metal layer 81 exposed by the drain opening 91. The second metal layer 82 is in contact with the upper surface 81A (drain exposed portion 71A) of the first metal layer 81. In this embodiment, the second metal layer 82 covers the entire surface of the drain exposed portion 71A. Therefore, the second metal layer 82 is in contact with a side surface 91A that constitutes the drain opening 91. In this embodiment, the side surface 91A of the drain opening 91 extends perpendicular to the upper surface 81A of the first metal layer 81. Because the second metal layer 82 is provided within the drain opening 91, the area of ​​the second metal layer 82 is smaller than the area of ​​the first metal layer 81 in a plan view.

[0076] The thickness T2 of the second metal layer 82 is thinner than the thickness T1 of the first metal layer 81. In one example, the thickness T2 of the second metal layer 82 is thinner than ½ the thickness T1 of the first metal layer 81. In one example, the thickness T2 of the second metal layer 82 is thinner than ⅓ the thickness T1 of the first metal layer 81.

[0077] The thickness T2 of the second metal layer 82 is thinner than the thickness TD of the drain wrap portion 94. In one example, the thickness T2 of the second metal layer 82 is thinner than half the thickness TD of the drain wrap portion 94. Therefore, the side surface 91A of the drain opening 91 includes a portion exposed from the second metal layer 82. The thickness TD of the drain wrap portion 94 is thinner than the thickness T1 of the first metal layer 81. The thickness TD of the drain wrap portion 94 is thicker than half the thickness T1 of the first metal layer 81.

[0078] As shown in FIG. 9 , the drain wrap portion 94 includes a first drain wrap portion 94A and a second drain wrap portion 94B. The first drain wrap portion 94A covers both ends of the first metal layer 81 of the drain pad 71 in the X direction. The first drain wrap portion 94A forms the long sides of the rectangular frame-shaped drain wrap portion 94. The second drain wrap portion 94B covers both ends of the first metal layer 81 of the drain pad 71 in the Y direction. The second drain wrap portion 94B forms the short sides of the rectangular frame-shaped drain wrap portion 94. In this embodiment, the width WD1 of the first drain wrap portion 94A is equal to the width WD2 of the second drain wrap portion 94B. Here, the width WD1 of the first drain wrap portion 94A is the dimension in a direction perpendicular to the extension direction of the first drain wrap portion 94A in a plan view. The width WD1 of the first drain wrap portion 94A can be said to be the dimension of the first drain wrap portion 94A in the X direction. The width WD2 of the second drain wrap portion 94B is the dimension in a direction perpendicular to the extension direction of the second drain wrap portion 94B in a plan view. The width WD2 of the second drain wrap portion 94B can be said to be the dimension of the second drain wrap portion 94B in the Y direction.

[0079] (Source Pad) 12, the source pad 72 includes a first metal layer 81 provided on the first surface 21 of the nitride semiconductor chip 20, and a second metal layer 82 covering the first metal layer 81. The configurations of the first metal layer 81 and the second metal layer 82 of the source pad 72 are the same as the configurations of the first metal layer 81 and the second metal layer 82 of the drain pad 71 (see FIG. 11).

[0080] A plurality of source vias 75 are provided on the lower surface 81B of the first metal layer 81 of the source pad 72. The plurality of source vias 75 are provided integrally with, for example, the first metal layer 81. Therefore, the plurality of source vias 75 are made of, for example, the same material as the first metal layer 81. Note that the plurality of source vias 75 may be provided separately from the first metal layer 81. Furthermore, the plurality of source vias 75 may be made of a material different from that of the first metal layer 81.

[0081] 9 and 12, the organic insulating layer 90 includes a source wrap portion 95 provided at a position that overlaps the periphery of the first metal layer 81 of the source pad 72 in a plan view. In this embodiment, the source wrap portion 95 is provided around the entire periphery of the first metal layer 81 of the source pad 72. As a result, the source wrap portion 95 defines a source opening 92. In other words, the source opening 92 is smaller than the first metal layer 81 of the source pad 72 in a plan view. The source wrap portion 95 has a rectangular frame shape with its long sides extending in the Y direction and its short sides extending in the X direction in a plan view.

[0082] A second metal layer 82 is provided on a source exposed portion 72A, which is a portion of an upper surface 81A of a first metal layer 81 of the source pad 72 exposed by the source opening 92. The second metal layer 82 is in contact with the upper surface 81A (source exposed portion 72A) of the first metal layer 81. In this embodiment, the second metal layer 82 covers the entire surface of the source exposed portion 72A. Therefore, the second metal layer 82 is in contact with a side surface 92A that constitutes the source opening 92. In this embodiment, the side surface 92A of the source opening 92 extends perpendicular to the upper surface 81A of the first metal layer 81 of the source pad 72. Because the second metal layer 82 is provided in the source opening 92, the area of ​​the second metal layer 82 is smaller than the area of ​​the first metal layer 81 in a plan view.

[0083] The thickness T2 of the second metal layer 82 of the source pad 72 is thinner than the thickness TS of the source wrap portion 95. In one example, the thickness T2 of the second metal layer 82 is thinner than half the thickness TS of the source wrap portion 95. Therefore, the side surface 92A of the source opening 92 includes a portion exposed from the second metal layer 82. The thickness TS of the source wrap portion 95 is thinner than the thickness T1 of the first metal layer 81. The thickness TS of the source wrap portion 95 is thicker than half the thickness T1 of the first metal layer 81. In one example, the thickness TS of the source wrap portion 95 is equal to the thickness TD of the drain wrap portion 94 (see FIG. 11 ). In this embodiment, the thickness T1 of the first metal layer 81 of the source pad 72 is equal to the thickness T1 of the first metal layer 81 of the drain pad 71. The thickness T2 of the second metal layer 82 of the source pad 72 is equal to the thickness T2 of the second metal layer 82 of the source pad 72.

[0084] As shown in FIG. 9 , the source wrap portion 95 includes a first source wrap portion 95A and a second source wrap portion 95B. The first source wrap portion 95A covers both end portions of the first metal layer 81 of the source pad 72 in the X direction. The first source wrap portion 95A forms the long sides of the rectangular frame-shaped source wrap portion 95. The second source wrap portion 95B covers both end portions of the first metal layer 81 of the source pad 72 in the Y direction. The second source wrap portion 95B forms the short sides of the rectangular frame-shaped source wrap portion 95. In this embodiment, the width WS1 of the first source wrap portion 95A is equal to the width WS2 of the second source wrap portion 95B. In this embodiment, the width WS1 of the first source wrap portion 95A is equal to the width WD1 of the first drain wrap portion 94A. Here, the width WS1 of the first source wrap portion 95A is the dimension in a direction perpendicular to the extension direction of the first source wrap portion 95A in a plan view. The width WS1 of the first source wrap portion 95A can be considered to be the dimension of the first source wrap portion 95A in the X direction. The width WS2 of the second source wrap portion 95B can be considered to be the dimension of the second source wrap portion 95B in the Y direction in a plan view.

[0085] (Gate Pad) 13, the gate pad 73 includes a first metal layer 81 provided on the first surface 21 of the nitride semiconductor chip 20, and a second metal layer 82 covering the first metal layer 81. The configurations of the first metal layer 81 and the second metal layer 82 of the gate pad 73 are the same as the configurations of the first metal layer 81 and the second metal layer 82 of the drain pad 71 (see FIG. 11).

[0086] A plurality of gate vias 76 are provided on the lower surface 81B of the first metal layer 81 of the gate pad 73. The plurality of gate vias 76 are provided integrally with, for example, the first metal layer 81. Therefore, the plurality of gate vias 76 are made of, for example, the same material as the first metal layer 81. Note that the plurality of gate vias 76 may be provided separately from the first metal layer 81. Furthermore, the plurality of gate vias 76 may be made of a material different from that of the first metal layer 81.

[0087] 9 and 13, the organic insulating layer 90 includes a gate wrap portion 96 provided at a position overlapping the periphery of the first metal layer 81 of the gate pad 73 in a plan view. In this embodiment, the gate wrap portion 96 is provided around the entire periphery of the first metal layer 81 of the gate pad 73. As a result, the gate wrap portion 96 defines a gate opening 93. In other words, the gate opening 93 is smaller than the first metal layer 81 of the gate pad 73 in a plan view. The gate wrap portion 96 has a rectangular frame shape with its long sides extending in the X direction and its short sides extending in the Y direction in a plan view.

[0088] A second metal layer 82 is provided on a gate exposed portion 73A, which is a portion of an upper surface 81A of a first metal layer 81 of the gate pad 73 that is exposed by the gate opening 93. The second metal layer 82 is in contact with the upper surface 81A (gate exposed portion 73A) of the first metal layer 81. In this embodiment, the second metal layer 82 covers the entire surface of the gate exposed portion 73A. Therefore, the second metal layer 82 is in contact with a side surface 93A that constitutes the gate opening 93. In this embodiment, the side surface 93A of the gate opening 93 extends perpendicular to the upper surface 81A of the first metal layer 81 of the gate pad 73. Because the second metal layer 82 is provided within the gate opening 93, the area of ​​the second metal layer 82 is smaller than the area of ​​the first metal layer 81 in a plan view.

[0089] The thickness T2 of the second metal layer 82 of the gate pad 73 is thinner than the thickness TG of the gate wrap portion 96. In one example, the thickness T2 of the second metal layer 82 is thinner than half the thickness TG of the gate wrap portion 96. Therefore, the side surface 93A of the gate opening 93 includes a portion exposed from the second metal layer 82. The thickness TG of the gate wrap portion 96 is thinner than the thickness T1 of the first metal layer 81. The thickness TG of the gate wrap portion 96 is thicker than half the thickness T1 of the first metal layer 81. The thickness TG of the gate wrap portion 96 is equal to the thickness TD of the drain wrap portion 94 (see FIG. 11 ). In this embodiment, the thickness T1 of the first metal layer 81 of the gate pad 73 is equal to the thickness T1 of the first metal layer 81 of the drain pad 71. The thickness T2 of the second metal layer 82 of the gate pad 73 is equal to the thickness T2 of the second metal layer 82 of the source pad 72.

[0090] As shown in FIG. 9 , the gate wrap portion 96 includes a first gate wrap portion 96A and a second gate wrap portion 96B. The first gate wrap portion 96A covers both ends of the first metal layer 81 of the gate pad 73 in the X direction. The first gate wrap portion 96A forms the short sides of the rectangular frame-shaped gate wrap portion 96. The second gate wrap portion 96B covers both ends of the first metal layer 81 of the gate pad 73 in the Y direction. The second gate wrap portion 96B forms the long sides of the rectangular frame-shaped gate wrap portion 96. In this embodiment, the width WG1 of the first gate wrap portion 96A is smaller than the width WD1 of the first drain wrap portion 94A. The width WG1 of the first gate wrap portion 96A is smaller than the width WD2 of the second drain wrap portion 94B. The width WG1 of the first gate wrap portion 96A is smaller than the width WS1 of the first source wrap portion 95A. The width WG1 of the first gate wrap portion 96A is smaller than the width WS2 of the second source wrap portion 95B. The width WG2 of the second gate wrap portion 96B is smaller than the width WD1 of the first drain wrap portion 94A. The width WG2 of the second gate wrap portion 96B is smaller than the width WD2 of the second drain wrap portion 94B. The width WG2 of the second gate wrap portion 96B is smaller than the width WS1 of the first source wrap portion 95A. The width WG2 of the second gate wrap portion 96B is smaller than the width WS2 of the second source wrap portion 95B. In this embodiment, the width WG1 of the first gate wrap portion 96A is equal to the width WG2 of the second gate wrap portion 96B.

[0091] Here, the width WG1 of the first gate wrap portion 96A is the dimension in a direction perpendicular to the extension direction of the first gate wrap portion 96A in a plan view. The width WG1 of the first gate wrap portion 96A can be said to be the dimension of the first gate wrap portion 96A in the X direction. The width WG2 of the second gate wrap portion 96B is the dimension in a direction perpendicular to the extension direction of the second gate wrap portion 96B in a plan view. The width WG2 of the second gate wrap portion 96B can be said to be the dimension of the second gate wrap portion 96B in the Y direction.

[0092] (Planar structure of nitride semiconductor chip) 9, the organic insulating layer 90 includes a first chip wrap portion 97A. The first chip wrap portion 97A is provided between the drain wrap portion 94 and the source wrap portion 95 in the X direction. In one example, the first chip wrap portion 97A is disposed between the first metal layer 81 of the drain pad 71 and the first metal layer 81 of the source pad 72 in the X direction. The first chip wrap portion 97A connects the drain wrap portion 94 and the source wrap portion 95. More specifically, the first chip wrap portion 97A connects the first drain wrap portion 94A of the drain wrap portion 94 and the first source wrap portion 95A of the source wrap portion 95.

[0093] 10, the first chip lap portion 97A contacts the first surface 21 of the nitride semiconductor chip 20. The first chip lap portion 97A contacts both the side surface of the drain pad 71 and the side surface of the source pad 72.

[0094] In this embodiment, with respect to the drain pad 71 and source pad 72 adjacent to each other in the X direction, a first insulating portion 98A is formed by a first drain wrap portion 94A of the drain pad 71 closer to the source pad 72, a first source wrap portion 95A of the source pad 72 closer to the drain pad 71, and a first chip wrap portion 97A. In other words, the organic insulating layer 90 includes the first insulating portion 98A that insulates the drain pad 71 from the source pad 72. The first insulating portion 98A is provided between the drain opening 91 and the source opening 92. The first insulating portion 98A extends in the Y direction in a plan view. Here, the first insulating portion 98A is formed by a portion of the organic insulating layer 90 between the drain opening 91 and the source opening 92 in the X direction. For this reason, a plurality of first insulating portions 98A are provided spaced apart in the X direction.

[0095] The first insulating portion 98A has a recessed shape with the chip wrap portion 97A as its bottom. Although not shown, the recessed portion of the first insulating portion 98A is filled with sealing resin 240 (see FIG. 1). The sealing resin 240 is provided so as to contact the upper surface of the chip wrap portion 97A, the surface of the first drain wrap portion 94A, and the surface of the first source wrap portion 95A.

[0096] The organic insulating layer 90 is provided on the outer periphery of the nitride semiconductor chip 20 in a plan view, and includes a peripheral connecting portion 99 that connects the plurality of first insulating portions 98A. The peripheral connecting portion 99 has a rectangular frame shape that surrounds the plurality of drain pads 71, the plurality of source pads 72, and the gate pad 73. In this way, the drain pads 71 ​​and the source pads 72 are insulated in the X direction by the first insulating portions 98A and the peripheral connecting portion 99.

[0097] 9, the organic insulating layer 90 includes a second chip wrap portion 97B. The second chip wrap portion 97B is provided between the drain wrap portion 94 and the gate wrap portion 96 in the Y direction. In one example, the second chip wrap portion 97B is disposed between the first metal layer 81 of the drain pad 71 and the first metal layer 81 of the gate pad 73 in the Y direction. The second chip wrap portion 97B connects the drain wrap portion 94 and the gate wrap portion 96. More specifically, the second chip wrap portion 97B connects the second drain wrap portion 94B of the drain wrap portion 94 and the second gate wrap portion 96B of the gate wrap portion 96.

[0098] The second chip lap portion 97B contacts the first surface 21 of the nitride semiconductor chip 20. The second chip lap portion 97B contacts both the side surface of the drain pad 71 and the side surface of the gate pad 73.

[0099] In this embodiment, for a drain pad 71 and a gate pad 73 adjacent to each other in the Y direction, a second insulating portion 98B is formed by a second drain wrap portion 94B of the drain pad 71 closer to the gate pad 73, a second source wrap portion 95B of the gate pad 73 closer to the drain pad 71, and a second chip wrap portion 97B. That is, the organic insulating layer 90 includes the second insulating portion 98B that insulates the drain pad 71 from the gate pad 73. The second insulating portion 98B is provided between the drain opening 91 and the gate opening 93. The second insulating portion 98B extends in the X direction in a plan view. Here, the second insulating portion 98B is formed by a portion of the organic insulating layer 90 between the drain opening 91 and the gate opening 93 in the Y direction. The second insulating portion 98B is connected to the outer periphery connecting portion 99 and the first insulating portion 98A.

[0100] 9 and 13, the second insulating portion 98B has a recessed shape with the chip wrap portion 97B as its bottom. Although not shown, the recessed portion of the second insulating portion 98B is filled with sealing resin 240 (see FIG. 1). The sealing resin 240 is provided so as to contact the upper surface of the chip wrap portion 97B, the surface of the second drain wrap portion 94B, and the surface of the second gate wrap portion 96B. The sealing resin 240 is also provided so as to cover the outer periphery connecting portion 99.

[0101] 9, a first inter-pad distance PD1, which is the distance between the drain pad 71 and the source pad 72 in the X direction, is equal to or less than the width WPD of the drain pad 71. The first inter-pad distance PD1 is equal to or less than the width WPS of the source pad 72. In this embodiment, the first inter-pad distance PD1 is smaller than the width WPD of the drain pad 71. The first inter-pad distance PD1 is smaller than the width WPS of the source pad 72. Furthermore, the width WPD of the drain pad 71 is equal to the width WPS of the source pad 72.

[0102] Here, the width WPD of the drain pad 71 can be defined by the dimension in a direction perpendicular to the extension direction of the drain pad 71 in a plan view. In this embodiment, the width WPD of the drain pad 71 can be defined by the dimension of the drain pad 71 in the X direction. The width WPS of the source pad 72 can be defined by the dimension in a direction perpendicular to the extension direction of the source pad 72 in a plan view. In this embodiment, the width WPS of the source pad 72 can be defined by the dimension of the source pad 72 in the X direction.

[0103] In this embodiment, the first pad distance PD1 is greater than the sum (WD1+WS1) of the width WD1 of one first drain wrap portion 94A and the width WS1 of one first source wrap portion 95A. The first pad distance PD1 can also be referred to as the width (dimension in the X direction) of the first chip wrap portion 97A. Therefore, the width of the first chip wrap portion 97A can be said to be greater than the sum (WD1+WS1) of the width WD1 of one first drain wrap portion 94A and the width WS1 of one first source wrap portion 95A.

[0104] The opening width W1 of the drain opening 91 is equal to or greater than the first pad-to-pad distance PD1. The opening width W2 of the source opening 92 is equal to or greater than the first pad-to-pad distance PD1. In this embodiment, the opening width W1 of the drain opening 91 is greater than the first pad-to-pad distance PD1. The opening width W2 of the source opening 92 is greater than the first pad-to-pad distance PD1. The opening width W1 of the drain opening 91 is equal to the opening width W2 of the source opening 92.

[0105] Here, the opening width W1 of the drain opening 91 can be defined by the dimension in a direction perpendicular to the direction in which the drain opening 91 extends in a plan view. In this embodiment, the opening width W1 of the drain opening 91 can be defined by the dimension of the drain opening 91 in the X direction. The opening width W2 of the source opening 92 can be defined by the direction perpendicular to the direction in which the source opening 92 extends in a plan view. In this embodiment, the opening width W2 of the source opening 92 can be defined by the dimension of the source opening 92 in the X direction.

[0106] The first inter-opening distance D1, which is the distance between the drain opening 91 and the source opening 92 adjacent to each other in the X direction, is larger than the first inter-pad distance PD1. The first inter-pad distance PD1 is, for example, 200 μm or less. In one example, the first inter-pad distance PD1 is 150 μm or less. In one example, the first inter-pad distance PD1 is 100 μm or less. In one example, the first inter-pad distance PD1 is 50 μm or more. On the other hand, the first inter-pad distance PD1 is, for example, 200 μm or more. In one example, the first inter-opening distance D1 is 250 μm or more. In one example, the first inter-opening distance D1 is 300 μm or more. In one example, the first inter-opening distance D1 is 350 μm or more. In one example, the first inter-opening distance D1 is 400 μm or less.

[0107] The second inter-pad distance PD2, which is the distance between the drain pad 71 and the gate pad 73 in the Y direction, is, for example, 200 μm or less. In one example, the second inter-pad distance PD2 is 150 μm or less. In one example, the second inter-pad distance PD2 is 100 μm or less. In one example, the second inter-pad distance PD2 is 50 μm or more. The second inter-pad distance PD2 is not more than the first inter-pad distance PD1. In this embodiment, the second inter-pad distance PD2 is smaller than the first inter-pad distance PD1. In addition, in this embodiment, the second inter-pad distance PD2 is not less than the sum (WD2 + WG2) of the width WD2 of one second drain wrap portion 94B and the width WG2 of one second gate wrap portion 96B.

[0108] (Thickness of chip lap) 12, the thickness TC1 of the first chip wrap portion 97A is thinner than the thickness T1 of the first metal layer 81 of the drain pad 71. The thickness TC1 of the first chip wrap portion 97A is equal to the thickness TD of the drain wrap portion 94. The thickness TC1 of the first chip wrap portion 97A is equal to the thickness TS of the source wrap portion 95.

[0109] 13, the thickness TC2 of the second chip wrap portion 97B is thinner than the thickness T1 of the first metal layer 81 of the drain pad 71. The thickness TC2 of the second chip wrap portion 97B is equal to the thickness TD of the drain wrap portion 94. The thickness TC2 of the second chip wrap portion 97B is equal to the thickness TS of the source wrap portion 95. The thickness TC2 of the second chip wrap portion 97B is equal to the thickness TC1 of the first chip wrap portion 97A.

[0110] Both the thickness TC1 of the first chip lap portion 97A and the thickness TC2 of the second chip lap portion 97B can be changed as desired. For example, the thickness TC1 of the first chip lap portion 97A can be equal to or greater than the thickness T1 of the first metal layer 81. The thickness TC2 of the second chip lap portion 97B can be equal to or greater than the thickness T1 of the first metal layer 81. For example, the thickness TC1 of the first chip lap portion 97A and the thickness TC2 of the second chip lap portion 97B can be different from each other.

[0111] [Clip joint structure] 14 and 15, the bonding structure between the drain clip 110 and the source clip 120 and the drain pad 71 and the source pad 72 will be described. Fig. 14 schematically shows a cross-sectional structure in which the drain clip 110 and the source clip 120 are bonded to the drain pad 71 and the source pad 72, respectively. Fig. 15 shows an enlarged view of the drain clip 110, the drain pad 71, and the surrounding areas of Fig. 14.

[0112] 14, the drain clip 110 is bonded to the second metal layer 82 of the drain pad 71. More specifically, the drain clip 110 is bonded to the second metal layer 82 of the drain pad 71 by a first conductive bonding material 101. The first conductive bonding material 101 may be, for example, a silver (Ag) paste or a solder paste.

[0113] The thickness TCD of the drain clip 110 is greater than the thickness TD of the drain wrap portion 94 of the organic insulating layer 90. Therefore, the upper surface 111 of the drain clip 110 is located on the opposite side of the upper surface 94S of the drain wrap portion 94 from the second metal layer 82. On the other hand, in this embodiment, the lower surface 112 of the drain clip 110 is located closer to the second metal layer 82 than the upper surface 94S of the drain wrap portion 94. Here, the lower surface 112 of the drain clip 110 is an example of a "facing surface" that faces the second metal layer 82.

[0114] The thickness TCD of the drain clip 110 is, for example, equal to or greater than the first inter-pad distance PD1. In this embodiment, the thickness TCD of the drain clip 110 is greater than the first inter-pad distance PD1.

[0115] The first conductive bonding material 101 is interposed between the lower surface 112 of the drain clip 110 and the second metal layer 82 of the drain pad 71. Furthermore, the first conductive bonding material 101 contacts a side surface 113 of the drain clip 110. The first conductive bonding material 101 contacts a side surface 91A that constitutes the drain opening 91. Thus, the first conductive bonding material 101 includes an interposed portion 103, a fillet 104, and a contact end portion 105. The interposed portion 103 is a portion of the first conductive bonding material 101 that is interposed between the lower surface 112 of the drain clip 110 and the second metal layer 82. The fillet 104 is a portion of the first conductive bonding material 101 that contacts the side surface 113 of the drain clip 110. The contact end portion 105 is a portion of the first conductive bonding material 101 that contacts the side surface 91A that constitutes the drain opening 91.

[0116] 15, the thickness TP of the intermediate portion 103 is thinner than the thickness TD of the drain wrap portion 94. The thickness TQ of the contact end portion 105 is thinner than the thickness TD of the drain wrap portion 94. The thickness TQ of the contact end portion 105 is equal to or greater than the thickness TP of the intermediate portion 103. In this embodiment, the thickness TQ of the contact end portion 105 is thicker than the thickness TP of the intermediate portion 103. The sum (TQ+T2) of the thickness TQ of the contact end portion 105 and the thickness T2 of the second metal layer 82 is, for example, equal to or less than the thickness TD of the drain wrap portion 94. In this embodiment, the sum (TQ+T2) of the thickness TQ of the contact end portion 105 and the thickness T2 of the second metal layer 82 is equal to the thickness TD of the drain wrap portion 94.

[0117] 15, the fillet 104 contacts the side surface 113 of the drain clip 110 in the Z direction from the lower surface 112 along about half the Z-direction dimension of the side surface 113. In one example, the fillet 104 may contact the side surface 113 of the drain clip 110 in the Z direction from the lower surface 112 along more than half the Z-direction dimension of the side surface 113.

[0118] 14, the source clip 120 is bonded to the second metal layer 82 of the source pad 72. More specifically, the source clip 120 is bonded to the second metal layer 82 of the source pad 72 by a second conductive bonding material 102. The second conductive bonding material 102 may be, for example, an Ag paste or a solder paste.

[0119] The thickness TCS of the source clip 120 is thicker than the thickness TS of the source wrap portion 95 of the organic insulating layer 90. Therefore, the upper surface 121 of the source clip 120 is located on the opposite side of the upper surface 95S of the source wrap portion 95 from the second metal layer 82. On the other hand, in this embodiment, the lower surface 122 of the source clip 120 is located closer to the second metal layer 82 than the upper surface 94S of the drain wrap portion 94. Here, the lower surface 122 of the source clip 120 is an example of a "facing surface" that faces the second metal layer 82.

[0120] The thickness TCS of the source clip 120 is, for example, equal to or greater than the first inter-pad distance PD1. In this embodiment, the thickness TCS of the source clip 120 is greater than the first inter-pad distance PD1.

[0121] The second conductive bonding material 102 is interposed between the lower surface 122 of the source clip 120 and the second metal layer 82 of the source pad 72. Furthermore, the second conductive bonding material 102 contacts a side surface 123 of the source clip 120. The second conductive bonding material 102 contacts a side surface 92A that defines the source opening 92. Similarly to the first conductive bonding material 101, the second conductive bonding material 102 includes an interposed portion 106, a fillet 107, and a contact end portion 108. The interposed portion 106 is a portion of the second conductive bonding material 102 that is interposed between the lower surface 122 of the source clip 120 and the second metal layer 82. The fillet 107 is a portion of the second conductive bonding material 102 that contacts the side surface 123 of the source clip 120. The contact end portion 108 is a portion of the second conductive bonding material 102 that contacts the side surface 92A (see FIG. 12 ) that defines the source opening 92. The dimensions of the intervening portion 106, the fillet 107, and the contact end portion 108 are equal to the dimensions of the intervening portion 103, the fillet 104, and the contact end portion 105 of the first conductive bonding material 101, respectively.

[0122] [Method of manufacturing a nitride semiconductor device] An exemplary method for manufacturing the nitride semiconductor device 10 of this embodiment will be described with reference to Figures 16 to 20. Figures 16 to 20 mainly show manufacturing steps for the drain pad 71, the source pad 72, and the organic insulating layer 90.

[0123] 16, the method for manufacturing the nitride semiconductor device 10 includes preparing a nitride semiconductor chip 820. The nitride semiconductor chip 820 is a semiconductor chip obtained by omitting the drain pad 71, the source pad 72, the gate pad 73, and the organic insulating layer 90 (all of which are shown in FIG. 9) from the nitride semiconductor chip 20. The nitride semiconductor chip 820 includes a first surface 821 formed by the second insulating layer 55.

[0124] As shown in FIG. 17, this process includes forming a first metal layer 81 of a drain pad 71, a source pad 72, and a gate pad 73 (see FIG. 13) on a first surface 821 of a nitride semiconductor chip 820. The drain pad 71, the source pad 72, and the gate pad 73 are formed by, for example, electrolytic plating. More specifically, in this process, first, through-holes penetrating the second insulating layer 55 are formed. Then, electrolytic plating is performed. At this time, a metal material (Cu) is embedded in the through-holes. As a result, drain vias 74, source vias 75, and gate vias 76 (see FIG. 13) are formed together with the drain pad 71, the source pad 72, and the gate pad 73. Note that the formation of the drain vias 74, the source vias 75, and the gate vias 76 may be performed in separate processes from the formation of the drain pad 71, the source pad 72, and the gate pad 73.

[0125] As shown in FIGS. 18 and 19, the method for manufacturing the nitride semiconductor device 10 includes forming an organic insulating layer 90 that covers a first surface 821 of a nitride semiconductor chip 820. In this step, as shown in FIG. 18, first, a resin layer 890 is formed on the first surface 821. The resin layer 890 is made of, for example, a resin material containing PI. The resin layer 890 is formed, for example, by applying the resin material to the first surface 821. The resin layer 890 covers the entire surface of the first surface 821. The resin layer 890 covers the entire surface of each of the upper surface 81A of the first metal layer 81 of the drain pad 71, the upper surface 81A of the first metal layer 81 of the source pad 72, and the upper surface 81A of the first metal layer 81 of the gate pad 73 (see FIG. 13). Next, as shown in FIG. 19, portions of the resin layer 890 corresponding to the drain opening 91, the source opening 92, and the gate opening 93 (see FIG. 13) are removed. This forms a drain opening 91, a source opening 92, and a gate opening 93, as well as a drain exposed portion 71A exposed from the drain opening 91, a source exposed portion 72A exposed from the source opening 92, and a gate exposed portion 73A exposed from the gate opening 93 (see FIG. 13). Furthermore, a drain wrap portion 94 covering the periphery of the drain pad 71, a source wrap portion 95 covering the periphery of the source pad 72, and a gate wrap portion 96 covering the periphery of the gate pad 73 (see FIG. 13) are formed. Through the above steps, an organic insulating layer 90 is formed.

[0126] 18 and 19 may be, for example, a process of applying a resin material after forming a mask at positions corresponding to the drain opening 91, the source opening 92, and the gate opening 93. In this way, the organic insulating layer 90 is formed by removing the mask after the resin material is applied.

[0127] As shown in FIG. 20, the method for manufacturing the nitride semiconductor device 10 includes forming a second metal layer 82. The second metal layer 82 is made of a material containing, for example, Ni and Au. In one example, first, a Ni layer is formed by sputtering on the drain exposed portion 71A, the source exposed portion 72A, and the gate exposed portion 73A (see FIG. 13). Then, an Au layer is formed on these Ni layers by sputtering. This forms the second metal layer 82. Through the above steps, the nitride semiconductor chip 20 is manufactured.

[0128] Although not shown, the method for manufacturing the nitride semiconductor device 10 includes mounting the nitride semiconductor chip 20 on the die pad 200, bonding the drain clip 110 and the source clip 120 to the drain pad 71 and the source pad 72, respectively, forming the gate wire 130, and forming the sealing resin 240. Through these steps, the nitride semiconductor device 10 is manufactured.

[0129] [Operation of the embodiment] The operation of the nitride semiconductor device 10 of this embodiment will be described. Generally, the pads exposed on the surface of a nitride semiconductor chip are made of metal materials such as Cu and Al. In this case, the pad surface oxidizes when exposed to the atmosphere. That is, an oxide film forms on the pad surface. This makes it difficult to bond the conductive adhesive to the pad when a clip is bonded to the pad using the conductive adhesive. As a result, the reliability of the connection between the clip and the pad decreases.

[0130] In this embodiment, the exposed drain portion 71A, the exposed source portion 72A, and the exposed gate portion 73A of the first metal layer 81 in the drain pad 71, the source pad 72, and the gate pad 73 provided on the first surface 21 of the nitride semiconductor chip 20, which are exposed from the organic insulating layer 90, are made of the second metal layer 82, which is less susceptible to oxidation than the first metal layer 81. Therefore, when the drain clip 110 is bonded to the drain pad 71 using the first conductive bonding material 101, the second metal layer 82 of the drain pad 71 is less susceptible to oxidation than the first metal layer 81, and therefore the first conductive bonding material 101 and the second metal layer 82 are more easily bonded to each other. This allows the drain pad 71 and the drain clip 110 to be suitably connected by the first conductive bonding material 101. Furthermore, when the source clip 120 is bonded to the source pad 72 using the second conductive bonding material 102, the second metal layer 82 of the source pad 72 is less susceptible to oxidation than the first metal layer 81, and therefore the second conductive bonding material 102 and the second metal layer 82 are easily bonded together. This allows the source pad 72 and the source clip 120 to be suitably connected by the second conductive bonding material 102. Furthermore, when the gate wire 130 is bonded to the gate pad 73, the second metal layer 82 of the gate pad 73 is less susceptible to oxidation than the first metal layer 81, and therefore the gate pad 73 and the gate wire 130 can be suitably connected together.

[0131] [Effects of the embodiment] The nitride semiconductor device 10 of this embodiment provides the following effects. (1) The nitride semiconductor device 10 includes a nitride semiconductor chip 20 including a nitride transistor 30 having a drain electrode 41, a source electrode 42, and a gate electrode 43, a first surface 21 on which a drain pad 71 electrically connected to the drain electrode 41, a source pad 72 electrically connected to the source electrode 42, and a gate pad 73 electrically connected to the gate electrode 43 are provided, and an organic insulating layer 90 covering the first surface 21. The organic insulating layer 90 includes a drain opening 91 exposing the drain pad 71, a source opening 92 exposing the source pad 72, a gate opening 93 exposing the gate pad 73, and a first insulating portion 98A provided between the source opening 92 and the drain opening 91 and insulating the source pad 72 from the drain pad 71. Each of the gate pad 73, the source pad 72, and the drain pad 71 includes a first metal layer 81 provided on the first surface 21, and a second metal layer 82 made of a material that is less susceptible to oxidation than the first metal layer 81 and covering the first metal layer 81. The portion of the gate pad 73 exposed by the gate opening 93 is the second metal layer 82. The portion of the source pad 72 exposed by the source opening 92 is the second metal layer 82. The portion of the drain pad 71 exposed by the drain opening 91 is the second metal layer 82.

[0132] According to this configuration, the portion of the drain pad 71 exposed from the drain opening 91, the portion of the source pad 72 exposed from the source opening 92, and the portion of the gate pad 73 exposed from the gate opening 93 are each less susceptible to oxidation. As a result, when connecting members such as clips or wires are connected to the portion of the drain pad 71 exposed from the drain opening 91, the portion of the source pad 72 exposed from the source opening 92, and the portion of the gate pad 73 exposed from the gate opening 93, for example, the bonding strength is increased compared to when the connecting members are connected to the first metal layer 81. Therefore, it is possible to suppress a decrease in the reliability of the connections between the drain pad 71, the source pad 72, and the gate pad 73 and the connecting members.

[0133] In addition, because the first surface 21 is covered with the organic insulating layer 90, the thickness of the insulating layer covering the first surface 21 can be easily increased compared to when the first surface 21 is covered with an inorganic insulating layer. This improves the mechanical properties of the insulating layer covering the first surface 21. Therefore, the nitride semiconductor device 10 can be suitably mounted in, for example, equipment that may experience relatively large vibrations (e.g., in-vehicle equipment).

[0134] In addition, by providing the first insulating portion 98A between the source pad 72 and the drain pad 71, insulation between the source pad 72 and the drain pad 71 can be ensured even when the source pad 72 and the drain pad 71 are arranged close to each other in the X direction, compared to a configuration in which the first insulating portion 98A is not provided between the source pad 72 and the drain pad 71. Therefore, the nitride semiconductor chip 20 can be made smaller while ensuring insulation between the source pad 72 and the drain pad 71.

[0135] (2) In a plan view, the source opening 92 is smaller than the first metal layer 81 of the source pad 72. The organic insulating layer 90 is provided at a position overlapping the periphery of the first metal layer 81 of the source pad 72 and includes a source wrap portion 95 that defines the source opening 92. In a plan view, the second metal layer 82 of the source pad 72 is smaller than the first metal layer 81 of the source pad 72. In a plan view, the drain opening 91 is smaller than the first metal layer 81 of the drain pad 71. The organic insulating layer 90 is provided at a position overlapping the periphery of the first metal layer 81 of the drain pad 71 and includes a drain wrap portion 94 that defines the drain opening 91. In a plan view, the second metal layer 82 of the drain pad 71 is smaller than the first metal layer 81 of the drain pad 71.

[0136] With this configuration, the distance between the second metal layer 82 of the source pad 72 and the second metal layer 82 of the drain pad 71 is greater than the distance between the first metal layer 81 of the source pad 72 and the first metal layer 81 of the drain pad 71. In other words, the distance between the source pad 72 exposed from the organic insulating layer 90 and the drain pad 71 is greater than the distance between the source pad 72 and the drain pad 71 covered by the organic insulating layer 90. Therefore, even if the source pad 72 and the drain pad 71 are arranged close to each other in the X direction, it is easy to ensure insulation between the source pad 72 and the drain pad 71.

[0137] (3) The nitride semiconductor device 10 includes a conductive source clip 120 bonded to the second metal layer 82 of the source pad 72 and a conductive drain clip 110 bonded to the second metal layer 82 of the drain pad 71.

[0138] This configuration can reduce the inductance caused by the wires compared to a configuration in which wires are connected to the source pad 72 and the drain pad 71. Therefore, the inductance in the nitride semiconductor device 10 can be reduced.

[0139] (4) The nitride semiconductor device 10 includes a first conductive bonding material 101 that bonds the second metal layer 82 of the drain pad 71 to the drain clip 110, and a second conductive bonding material 102 that bonds the second metal layer 82 of the source pad 72 to the source clip 120. The thickness TS of the source wrap portion 95 is greater than the thickness T2 of the second metal layer 82 of the source pad 72. The thickness TD of the drain wrap portion 94 is greater than the thickness T2 of the second metal layer 82 of the drain pad 71.

[0140] This configuration can prevent the first conductive bonding material 101 from leaking out of the drain opening 91 in a plan view. It can also prevent the second conductive bonding material 102 from leaking out of the source opening 92 in a plan view. This can prevent the insulation distance between the first conductive bonding material 101 and the second conductive bonding material 102 from becoming small.

[0141] (5) The thickness TCS of the source clip 120 is greater than the thickness TS of the source wrap portion 95. The thickness TCD of the drain clip 110 is greater than the thickness TD of the drain wrap portion 94.

[0142] According to this configuration, the electrical resistance of both the source clip 120 and the drain clip 110 can be limited, making it easier to pass a large current through the source clip 120 and the drain clip 110.

[0143] (6) The first conductive bonding material 101 contacts the side surface 113 of the drain clip 110. The second conductive bonding material 102 contacts the side surface 123 of the source clip 120. This configuration increases the bonding area between the first conductive bonding material 101 and the drain clip 110. This increases the bonding strength between the drain clip 110 and the second metal layer 82 of the drain pad 71, due to the first conductive bonding material 101. This increases the bonding area between the second conductive bonding material 102 and the source clip 120. This increases the bonding strength between the source clip 120 and the second metal layer 82 of the source pad 72, due to the second conductive bonding material 102.

[0144] (7) The thickness of the portion of the first conductive bonding material 101 that contacts the side surface 113 of the drain clip 110 is greater than the thickness TD of the drain wrap portion 94. The thickness of the portion of the second conductive bonding material 102 that contacts the side surface 123 of the source clip 120 is greater than the thickness TS of the source wrap portion 95.

[0145] This configuration can further increase the bonding area between the first conductive bonding material 101 and the drain clip 110. This can further increase the bonding strength between the drain clip 110 and the second metal layer 82 of the drain pad 71 by the first conductive bonding material 101. This can further increase the bonding area between the second conductive bonding material 102 and the source clip 120. This can further increase the bonding strength between the source clip 120 and the second metal layer 82 of the source pad 72 by the second conductive bonding material 102.

[0146] (8) The first conductive bonding material 101 contacts a side surface 91A of the organic insulating layer 90 that constitutes the drain opening 91. The second conductive bonding material 102 contacts a side surface 92A of the organic insulating layer 90 that constitutes the source opening 92.

[0147] According to this configuration, the bonding area between the first conductive bonding material 101 and the second metal layer 82 of the drain pad 71 can be increased, and the first conductive bonding material 101 is also bonded to the organic insulating layer 90. Therefore, the reliability of the connection between the drain pad 71 and the drain clip 110 by the first conductive bonding material 101 can be improved. Furthermore, the bonding area between the second conductive bonding material 102 and the second metal layer 82 of the source pad 72 can be increased, and the second conductive bonding material 102 is also bonded to the organic insulating layer 90. Therefore, the reliability of the connection between the source pad 72 and the source clip 120 by the second conductive bonding material 102 can be improved.

[0148] (9) The thickness of the portion of the first conductive bonding material 101 that contacts the side surface 91A of the drain opening 91 is equal to or less than the thickness TD of the drain wrap portion 94. The thickness of the portion of the second conductive bonding material 102 that contacts the side surface 92A of the source opening 92 is equal to or less than the thickness TS of the source wrap portion 95.

[0149] According to this configuration, in plan view, the first conductive bonding material 101 does not protrude from the drain opening 91. In plan view, the second conductive bonding material 102 does not protrude from the source opening 92. This makes it possible to prevent the insulation distance between the first conductive bonding material 101 and the second conductive bonding material 102 from becoming small.

[0150] (10) A plurality of drain pads 71 ​​and a plurality of source pads 72 are provided. The plurality of drain pads 71 ​​and the plurality of source pads 72 are alternately arranged one by one in the X direction. Both the thickness TCS of the source clip 120 and the thickness TCD of the drain clip 110 are thicker than a first inter-pad distance PD1, which is the distance between the drain pad 71 and the source pad 72 adjacent to each other in the X direction.

[0151] According to this configuration, the first inter-pad distance PD1 can be reduced, and the drain pad 71 and the source pad 72 can be arranged closer to each other in the X direction while ensuring insulation between the drain pad 71 and the source pad 72. In addition, the electrical resistance of the drain clip 110 and the source clip 120 is reduced, allowing the use of drain clips 110 and source clips 120 that are compatible with large currents. In other words, the nitride semiconductor chip 20 can be made smaller in size in the X direction, and a large current can be supplied to the nitride semiconductor chip 20. Therefore, the nitride semiconductor device 10 that is compatible with large currents can be made smaller.

[0152] (11) The first pad distance PD1 is 200 μm or less. According to this configuration, the first inter-pad distance PD1 can be reduced, and therefore the drain pad 71 and the source pad 72 can be arranged close to each other in the X direction while ensuring insulation between the drain pad 71 and the source pad 72. This makes it possible to reduce the size of the nitride semiconductor chip 20 while suppressing deterioration in the insulation performance of the nitride semiconductor chip 20.

[0153] (12) In a plan view, the gate opening 93 is smaller than the first metal layer 81 of the gate pad 73. The organic insulating layer 90 is provided at a position overlapping the periphery of the first metal layer 81 of the gate pad 73 and includes a gate wrap portion 96 that defines the gate opening 93. In a plan view, the second metal layer 82 of the gate pad 73 is smaller than the first metal layer 81 of the gate pad 73.

[0154] With this configuration, the distance between the second metal layer 82 of the gate pad 73 and the second metal layer 82 of the drain pad 71 is greater than the distance between the first metal layer 81 of the gate pad 73 and the first metal layer 81 of the drain pad 71. In other words, the distance between the gate pad 73 exposed from the organic insulating layer 90 and the drain pad 71 is greater than the distance between the gate pad 73 and the drain pad 71 covered by the organic insulating layer 90. Therefore, insulation between the gate pad 73 and the drain pad 71 can be easily ensured even if the gate pad 73 and the drain pad 71 are arranged close to each other in the Y direction.

[0155] (13) The organic insulating layer 90 includes a second insulating portion 98B that is provided between the drain pad 71 and the gate pad 73 that are adjacent to each other in the Y direction and that insulates the drain pad 71 from the gate pad 73. This configuration can improve the insulation between the drain pad 71 and the gate pad 73.

[0156] (14) The second inter-pad distance PD2, which is the distance between the drain pad 71 and the gate pad 73 adjacent to each other in the Y direction, is 200 μm or less. According to this configuration, the second inter-pad distance PD2 can be reduced, and therefore the drain pad 71 and the gate pad 73 can be arranged close to each other in the X direction while ensuring insulation between the drain pad 71 and the gate pad 73. This makes it possible to reduce the size of the nitride semiconductor chip 20 while suppressing deterioration in the insulation performance of the nitride semiconductor chip 20.

[0157] (15) The first pad distance PD1 is smaller than both the dimension of the source clip 120 in the X direction and the dimension of the drain clip 110 in the X direction. According to this configuration, the first inter-pad distance PD1 can be reduced, and therefore the drain pad 71 and the source pad 72 can be arranged close to each other in the X direction while ensuring insulation between the drain pad 71 and the source pad 72. This makes it possible to reduce the size of the nitride semiconductor chip 20 while suppressing deterioration in the insulation performance of the nitride semiconductor chip 20.

[0158] (16) The first pad distance PD1 is smaller than the dimension of the source opening 92 in the X direction and the dimension of the drain opening 91 in the X direction. According to this configuration, the first inter-pad distance PD1 can be reduced, and therefore the drain pad 71 and the source pad 72 can be arranged close to each other in the X direction while ensuring insulation between the drain pad 71 and the source pad 72. This makes it possible to reduce the size of the nitride semiconductor chip 20 while suppressing deterioration in the insulation performance of the nitride semiconductor chip 20.

[0159] (17) The drain clip 110 and the source clip 120 each include a lower surface 112, 122 as an opposing surface facing the second metal layer 82. The lower surface 112 of the drain clip 110 is positioned closer to the second metal layer 82 than the upper surface 94S of the drain wrap portion 94. The lower surface 122 of the source clip 120 is positioned closer to the second metal layer 82 than the upper surface 95S of the source wrap portion 95.

[0160] With this configuration, the drain wrap portion 94 can limit the movement of the drain clip 110 in the X direction. The source wrap portion 95 can limit the movement of the source clip 120 in the X direction. Therefore, the drain clip 110 and the source clip 120 can be prevented from coming too close in the X direction, making it easier to ensure an insulating distance between the drain clip 110 and the source clip 120.

[0161] <Example of change> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0162] As shown in FIG. 21 , the drain wrap portion 94, the source wrap portion 95, and the first chip wrap portion 97A may be individually provided in the first insulating portion 98A of the organic insulating layer 90. In one example, the first chip wrap portion 97A is flat and provided between the drain pad 71 and the source pad 72. The thickness of the first chip wrap portion 97A is thinner than the thickness T1 (see FIGS. 11 and 12 ) of the first metal layer 81 of the drain pad 71 and the source pad 72. The first chip wrap portion 97A covers a portion of the side surface in the Z direction of the first metal layer 81 of the drain pad 71 and the source pad 72. The drain wrap portion 94 includes a first portion covering the upper surface 81A of the first metal layer 81 of the drain pad 71 and a second portion covering the side surface of the first metal layer 81. The second portion is in contact with the first chip wrap portion 97A. The source wrap portion 95 includes a first portion that covers the upper surface 81A of the first metal layer 81 of the source pad 72, and a second portion that covers the side surface of the first metal layer 81. The second portion is in contact with the first chip wrap portion 97A. The type of organic insulating layer 90 that constitutes the first chip wrap portion 97A may be different from the type of organic insulating layer 90 that constitutes the drain wrap portion 94 and the source wrap portion 95.

[0163] Although not shown, the drain wrap portion 94, the gate wrap portion 96, and the second chip wrap portion 97B may be provided separately in the second insulating portion 98B of the organic insulating layer 90. Even in this case, the type of organic insulating layer 90 constituting the second chip wrap portion 97B may be different from the type of organic insulating layer 90 constituting the drain wrap portion 94 and the gate wrap portion 96.

[0164] The relationship between the widths WD1 and WD2 of the drain wrap portion 94 and the widths WS1 and WS2 of the source wrap portions 95 and the first inter-pad distance PD1 can be changed as desired. As an example, as shown in FIG. 22 , the sum (WD1+WS1) of the width WD1 of the first drain wrap portion 94A of one drain wrap portion 94 and the width WS1 of the first source wrap portion 95A of one source wrap portion 95 may be greater than the first inter-pad distance PD1. This configuration ensures insulation between the drain pad 71 and the source pad 72 while miniaturizing the nitride semiconductor chip 20 in the X direction.

[0165] Furthermore, the first pad-to-pad distance PD1 may be smaller than the opening width W1 of the drain opening 91. The first pad-to-pad distance PD1 may be smaller than the opening width W2 of the source opening 92. This configuration allows the nitride semiconductor chip 20 to be miniaturized in the X direction while ensuring the bonding area between the drain pad 71 and the drain clip 110 and the bonding area between the source pad 72 and the source clip 120.

[0166] The configuration of the drain wrap portion 94 and the configuration of the source wrap portion 95 can each be changed as desired. For example, the width WD1 of the first drain wrap portion 94A of the drain wrap portion 94 and the width WD2 of the second drain wrap portion 94B may be different from each other. As shown in FIG. 23, the width WD2 of the second drain wrap portion 94B may be smaller than the width WD1 of the first drain wrap portion 94A. For example, the width WS1 of the first source wrap portion 95A of the source wrap portion 95 and the width WS2 of the second source wrap portion 95B may be different from each other. As shown in FIG. 23, the width WS2 of the second source wrap portion 95B may be smaller than the width WS1 of the first source wrap portion 95A.

[0167] This configuration makes it possible to increase the bonding area between the drain clip 110 and the second metal layer 82 of the drain pad 71 while ensuring insulation between the drain pad 71 and the source pad 72. It also makes it possible to increase the bonding area between the source clip 120 and the second metal layer 82 of the source pad 72 while ensuring insulation between the drain pad 71 and the source pad 72.

[0168] In another example, the widths WD1 of the two first drain wrap portions 94A of the drain wrap portion 94 in the drain pad 71 provided at the end portion in the X direction of the nitride semiconductor chip 20 may be different from each other. As shown in Fig. 24, the width WD3 of the first drain wrap portion 94A that is closer to the end edge in the X direction of the nitride semiconductor chip 20 may be smaller than the width WD1 of the remaining first drain wrap portion 94A. This configuration makes it possible to reduce the size of the nitride semiconductor chip 20 in the X direction while ensuring insulation between the drain pad 71 and the source pad 72.

[0169] The width WG1 of the first gate wrap portion 96A and the width WG2 of the second gate wrap portion 96B of the gate wrap portion 96 can each be changed as desired. For example, the width WG1 of the first gate wrap portion 96A and the width WG2 of the second gate wrap portion 96B may be equal to the width WD1 of the first drain wrap portion 94A of the drain wrap portion 94. For example, the width WG1 of the first gate wrap portion 96A and the width WG2 of the second gate wrap portion 96B may be equal to the width WD2 of the second drain wrap portion 94B of the drain wrap portion 94. For example, the width WG1 of the first gate wrap portion 96A and the width WG2 of the second gate wrap portion 96B may be different from each other.

[0170] The material that constitutes the organic insulating layer 90 is not limited to PI, and may be other organic insulating materials such as epoxy resin, phenolic resin, etc. The first gate wrap portion 96A of the gate wrap portion 96 may be omitted from the organic insulating layer 90. Also, the second gate wrap portion 96B of the gate wrap portion 96, which is provided on the opposite side of the drain pad 71 in the Y direction, may be omitted from the organic insulating layer 90. Also, the pair of second gate wrap portions 96B of the gate wrap portion 96 may be omitted. Also, the gate wrap portion 96 may be omitted from the organic insulating layer 90.

[0171] The second source wrap portion 95B of the source wrap portion 95 may be omitted from the organic insulating layer 90. Also, the first source wrap portion 95A of the source wrap portion 95 may be omitted. Also, the source wrap portion 95 may be omitted from the organic insulating layer 90. When the source wrap portion 95 is omitted, the second metal layer 82 of the source pad 72 may be provided over the entire upper surface 81A of the first metal layer 81.

[0172] The second drain wrap portion 94B of the drain wrap portion 94 may be omitted from the organic insulating layer 90. Also, the first drain wrap portion 94A of the drain wrap portion 94 may be omitted. Also, the drain wrap portion 94 may be omitted from the organic insulating layer 90. When the drain wrap portion 94 is omitted, the second metal layer 82 of the drain pad 71 may be provided over the entire upper surface 81A of the first metal layer 81.

[0173] The second insulating portion 98B may be omitted from the organic insulating layer 90. The peripheral connecting portion 99 may be omitted from the organic insulating layer 90. The thickness TD of the drain wrap portion 94 may be equal to or smaller than the thickness T2 of the second metal layer 82 of the drain pad 71.

[0174] The thickness TS of the source wrap portion 95 may be equal to or less than the thickness T2 of the second metal layer 82 of the source pad 72. The thickness TG of the gate wrap portion 96 may be equal to or less than the thickness T2 of the second metal layer 82 of the gate pad 73.

[0175] The number of drain pads 71 ​​and source pads 72 can be changed arbitrarily. For example, there may be only one drain pad 71 and one source pad 72. The nitride semiconductor chip 20 may also be provided with pads other than the drain pad 71, the source pad 72, and the gate pad 73. For example, the nitride semiconductor chip 20 may be provided with a Kelvin source pad. The Kelvin source pad is electrically connected to, for example, the source electrode 42 of the nitride transistor 30.

[0176] The thickness TCD of the drain clip 110 can be changed as desired. In one example, the thickness TCD of the drain clip 110 may be equal to or less than the first pad distance PD1. In one example, the thickness TCD of the drain clip 110 may be equal to or less than the thickness TD of the drain wrap portion 94.

[0177] The thickness TCS of the source clip 120 can be changed as desired. For example, the thickness TCS of the source clip 120 may be equal to or less than the first pad distance PD1. For example, the thickness TCS of the source clip 120 may be equal to or less than the thickness TS of the source wrap portion 95.

[0178] The position of the lower surface 112 of the drain clip 110 in the Z direction can be changed as desired. In one example, the lower surface 112 of the drain clip 110 may be located at the same position in the Z direction as the upper surface 94S of the drain wrap portion 94. In another example, the lower surface 112 of the drain clip 110 may be located on the opposite side of the upper surface 94S of the drain wrap portion 94 from the second metal layer 82 in the Z direction.

[0179] The position of the lower surface 122 of the source clip 120 in the Z direction can be changed as desired. In one example, the lower surface 122 of the source clip 120 may be located at the same position in the Z direction as the upper surface 95S of the source wrap portion 95. In another example, the lower surface 122 of the source clip 120 may be located on the opposite side of the upper surface 95S of the source wrap portion 95 from the second metal layer 82 in the Z direction.

[0180] The first conductive bonding material 101 does not need to have a fillet 104. In other words, the first conductive bonding material 101 does not need to be in contact with the side surface 113 of the drain clip 110. The second conductive bonding material 102 does not need to have the fillet 107. In other words, the second conductive bonding material 102 does not need to be in contact with the side surface 123 of the source clip 120.

[0181] The first conductive bonding material 101 does not need to be in contact with the side surface 91A of the drain opening 91. In other words, the first conductive bonding material 101 may be provided at a position spaced apart from the side surface 91A of the drain opening 91.

[0182] The second conductive bonding material 102 does not need to be in contact with the side surface 92A of the source opening 92. In other words, the second conductive bonding material 102 may be provided at a position spaced apart from the side surface 92A of the source opening 92.

[0183] The first inter-pad distance PD1 can be changed arbitrarily. In one example, the first inter-pad distance PD1 may be greater than 200 μm. The second inter-pad distance PD2 can be changed arbitrarily. In one example, the second inter-pad distance PD2 may be greater than 200 μm.

[0184] The material constituting the first metal layer 81 can be changed arbitrarily as long as the first metal layer 81 is made of a conductive material. The material constituting the second metal layer 82 can be changed arbitrarily. The second metal layer 82 may be made of a conductive material that is less susceptible to oxidation than the first metal layer 81.

[0185] The drain clip 110 may be bonded to the drain pad 71 without using the first conductive bonding material 101. In one example, the drain clip 110 may be bonded to the drain pad 71 by ultrasonic welding.

[0186] The source clip 120 may be bonded to the source pad 72 without using the second conductive bonding material 102. In one example, the source clip 120 may be bonded to the source pad 72 by ultrasonic welding.

[0187] The nitride semiconductor device 10 may be configured such that the drain pad 71 of the nitride semiconductor chip 20 and the drain terminal 210 are electrically connected by a drain wire instead of the drain clip 110 .

[0188] The nitride semiconductor device 10 may be configured such that the source pad 72 of the nitride semiconductor chip 20 and the source terminal 220 are electrically connected by a source wire instead of the source clip 120 .

[0189] The sealing resin 240 may be omitted from the nitride semiconductor device 10. The nitride semiconductor device 10 may include a semiconductor chip made of a material containing, for example, silicon (Si) or silicon carbide (SiC) instead of the nitride semiconductor chip 20. In this case, the semiconductor chip includes a transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET) instead of a nitride transistor. Here, a lateral transistor is used as the transistor. When including such a semiconductor chip, the nitride semiconductor device 10 can be called a semiconductor device.

[0190] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0191] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this disclosure being "up" and "down" of the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0192] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0193] [Appendix 1] a nitride semiconductor chip (20) including a nitride transistor (30) having a drain electrode (41), a source electrode (42), and a gate electrode (43), and a first surface (21) provided with a drain pad (71) electrically connected to the drain electrode (41), a source pad (72) electrically connected to the source electrode (42), and a gate pad (73) electrically connected to the gate electrode (43); an organic insulating layer (90) covering the first surface (21); Including, The organic insulating layer (90) is a drain opening (91) exposing the drain pad (71); a source opening (92) exposing the source pad (72); a gate opening (93) exposing the gate pad (73); a first insulating portion (98A) provided between the drain opening (91) and the source opening (92) and insulating the drain pad (71) from the source pad (72); Including, Each of the drain pad (71), the source pad (72), and the source pad (73) is a first metal layer (81) provided on the first surface (21); a second metal layer (82) made of a material less susceptible to oxidation than the first metal layer (81) and covering the first metal layer (81); Including, The portion of the drain pad (71) exposed by the drain opening (91) is the second metal layer (82), The portion of the source pad (72) exposed by the source opening (92) is the second metal layer (82); The portion of the gate pad (73) exposed by the gate opening (93) is the second metal layer (82). Nitride semiconductor device (10).

[0194] [Appendix 2] In a plan view seen from a thickness direction (Z) of the nitride semiconductor chip (20), the drain opening (91) is smaller than the first metal layer (81) of the drain pad (72); the organic insulating layer (90) is provided at a position overlapping the periphery of the first metal layer (81) of the drain pad (71), and includes a drain lap portion (94) that defines the drain opening (91); In the plan view, the second metal layer (82) of the drain pad (71) is smaller than the first metal layer (81) of the drain pad (71), In the plan view, the source opening (92) is smaller than the first metal layer (81) of the source pad (72); the organic insulating layer (90) is provided at a position overlapping the periphery of the first metal layer (81) of the source pad (72), and includes a source wrap portion (95) that defines the source opening (92); In the plan view, the second metal layer (82) of the source pad (72) is smaller than the first metal layer (81) of the source pad (72). 2. The nitride semiconductor device according to claim 1.

[0195] [Appendix 3] The thickness (TD) of the drain wrap portion (94) is greater than the thickness (T2) of the second metal layer (82) of the drain pad (71), The thickness (TS) of the source wrap portion (95) is greater than the thickness (T2) of the second metal layer (82) of the source pad (72). 3. The nitride semiconductor device according to claim 2.

[0196] [Appendix 4] a conductive drain clip (110) bonded to the second metal layer (82) of the drain pad (71); a conductive source clip (120) bonded to the second metal layer (82) of the source pad (72); Contains 4. The nitride semiconductor device according to claim 2 or 3.

[0197] [Appendix 5] The thickness (TCD) of the drain clip (110) is greater than the thickness (TD) of the drain wrap portion (94), The thickness (TCS) of the source clip (120) is greater than the thickness (TS) of the source wrap portion (95). 5. The nitride semiconductor device according to claim 4.

[0198] [Appendix 6] a first conductive bonding material (101) that bonds the second metal layer (82) of the drain pad (71) to the drain clip (110); a second conductive bonding material (102) that bonds the second metal layer (82) of the source pad (72) to the source clip (120); Including, The first conductive bonding material (101) is in contact with a side surface (113) of the drain clip (110), The second conductive adhesive (102) is in contact with the side surface (123) of the source clip (120). 6. The nitride semiconductor device according to claim 5.

[0199] [Appendix 7] The thickness of a portion (104) of the first conductive bonding material (101) that contacts the side surface (113) of the drain clip (110) is thicker than the thickness (TD) of the drain wrap portion (94), The thickness of the portion (107) of the second conductive bonding material (102) that contacts the side surface (123) of the source clip (120) is greater than the thickness (TS) of the source wrap portion (95). 7. The nitride semiconductor device according to claim 6.

[0200] [Appendix 8] the first conductive bonding material (101) is in contact with a side surface (91A) of the organic insulating layer (90) that forms the drain opening (91); The second conductive bonding material (102) is in contact with a side surface (92A) of the organic insulating layer (90) that forms the source opening (92). 8. The nitride semiconductor device according to claim 6 or 7.

[0201] [Appendix 9] a thickness of a portion (105) of the first conductive bonding material (101) that contacts the side surface (91A) of the drain opening (91) is equal to or less than a thickness (TD) of the drain wrap portion (94); The thickness of a portion (108) of the second conductive bonding material (102) that contacts the side surface (92A) of the source opening (92) is equal to or less than the thickness (TS) of the source wrap portion (95). 9. The nitride semiconductor device according to claim 8.

[0202] [Appendix 10] The drain pad (71) and the source pad (72) are each provided in plurality, The plurality of drain pads (71) and the plurality of source pads (72) are alternately arranged one by one in a first direction (X), Both the thickness (TCD) of the drain clip (110) and the thickness (TCS) of the source clip (120) are thicker than a first pad distance (PD1) between the drain pad (71) and the source pad (72) adjacent to each other in the first direction (X). 10. The nitride semiconductor device according to any one of appendixes 4 to 9.

[0203] [Appendix 11] The drain pad (71) and the source pad (72) are each provided in plurality, The plurality of drain pads (71) and the plurality of source pads (72) are alternately arranged one by one in a first direction (X), A first pad distance (PD1), which is a distance between the drain pad (71) and the source pad (72) adjacent to each other in the first direction (X), is 200 μm or less. 11. The nitride semiconductor device according to any one of claims 1 to 10.

[0204] [Appendix 12] In the plan view, the gate opening (93) is smaller than the first metal layer (81) of the gate pad (73), the organic insulating layer (90) is provided at a position overlapping the periphery of the first metal layer (81) of the gate pad (73), and includes a gate wrap portion (96) that defines the gate opening (93); In the plan view, the second metal layer (82) of the gate pad (73) is smaller than the first metal layer (81) of the gate pad (73). 11. The nitride semiconductor device according to any one of claims 2 to 10.

[0205] [Appendix 13] The thickness (TG) of the gate wrap portion (96) is greater than the thickness (T2) of the second metal layer (82) of the gate pad (73). 13. The nitride semiconductor device according to claim 12.

[0206] [Appendix 14] The drain pad (71) and the source pad (72) are each provided in plurality, The plurality of drain pads (71) and the plurality of source pads (72) are alternately arranged one by one in a first direction (X), A direction perpendicular to the first direction (X) as viewed from the thickness direction (Z) of the nitride semiconductor chip (20) is defined as a second direction (Y), The gate pad (73) is arranged in the second direction (Y) next to one drain pad (71E) of the plurality of drain pads (71), The organic insulating layer (90) includes a second insulating portion (98B) that is provided between the drain pad (71E) and the gate pad (73) adjacent to each other in the second direction (Y) and that insulates the drain pad (71E) from the gate pad (73). 14. The nitride semiconductor device according to claim 12 or 13.

[0207] [Appendix 15] A second pad distance (PD2), which is a distance between the drain pad (71E) and the gate pad (73) adjacent to each other in the second direction (Y), is 200 μm or less. 15. The nitride semiconductor device according to claim 14.

[0208] [Appendix 16] The nitride semiconductor chip (20) an electron transit layer (34); an electron supply layer (35) provided on the electron transit layer (34); a gate layer (37) partially provided on the electron supply layer (35); Including, the source electrode (42) and the drain electrode (41) are provided on the electron supply layer (35) and spaced apart from each other; The gate electrode (43) is provided on the gate layer (37). 16. The nitride semiconductor device according to any one of claims 1 to 15.

[0209] [Appendix 17] the electron transit layer (34) is made of a material containing GaN, The electron supply layer (35) has a band gap larger than that of the electron transit layer (34), and is Al x Ga 1-x It is made of materials containing N, and 0.1 <x<0.3であり、 The gate layer (37) contains acceptor-type impurities and is made of a material containing GaN. 17. The nitride semiconductor device according to claim 16.

[0210] [Appendix 18] The first metal layer (81) is made of a material containing Cu. 18. The nitride semiconductor device according to any one of claims 1 to 17.

[0211] [Appendix 19] The second metal layer (82) is made of a material containing Ni and Au. 19. The nitride semiconductor device according to any one of appendices 1 to 18.

[0212] [Appendix 20] A plurality of vias (74 / 75 / 76) are connected to the lower surface (81B) of the first metal layer (81). 20. The nitride semiconductor device according to any one of claims 1 to 19.

[0213] [Appendix 21] The organic insulating layer (90) is made of a material containing polyimide. 21. The nitride semiconductor device according to any one of claims 1 to 20.

[0214] [Appendix 22] the organic insulating layer (90) includes a tip wrap portion (97A) that is provided between the drain wrap portion (94) and the source wrap portion (95) and connects the drain wrap portion (94) and the source wrap portion (95), The drain wrap portion (94), the source wrap portion (95), and the tip wrap portion (97A) are provided individually. 11. The nitride semiconductor device according to any one of claims 2 to 10.

[0215] [Appendix 23] The type of the organic insulating layer (90) constituting the tip lap portion (97A) is different from the type of the organic insulating layer (90) constituting the drain lap portion (94) and the source lap portion (95). 23. The nitride semiconductor device according to claim 22.

[0216] [Appendix 24] The drain pad (71) and the source pad (72) are each provided in plurality, The plurality of drain pads (71) and the plurality of source pads (72) are alternately arranged one by one in a first direction (X), A first pad distance (PD1), which is a distance between the drain pad (71) and the source pad (72) adjacent to each other in the first direction (X), is smaller than both the dimension of the source clip (120) in the first direction (X) and the dimension of the drain clip (110) in the first direction (X). 10. The nitride semiconductor device according to any one of appendixes 4 to 9.

[0217] [Appendix 25] The drain pad (71) and the source pad (72) are aligned in a first direction (X), A first pad distance (PD1), which is the distance between the drain pad (71) and the source pad (72) in the first direction (X), is smaller than a dimension (W1) of the drain opening (91) in the first direction (X) and a dimension (W2) of the source opening (92) in the first direction (X). 10. The nitride semiconductor device according to any one of appendices 1 to 9.

[0218] [Appendix 26] The drain pad (71) and the source pad (72) are aligned in a first direction (X), Each of the drain pad (71) and the source pad (72) extends in a second direction (Y) perpendicular to the first direction (X) in the plan view, The drain wrap portion (94) a first drain wrap portion (94A) covering both end portions of the drain pad (71) in the first direction (X); a second drain wrap portion (94B) covering both end portions of the drain pad (71) in the second direction (Y); Including, The sauce wrap portion (95) is a first source wrap portion (95A) covering both end portions of the source pad (72) in the first direction (X); a second source wrap portion (95B) covering both end portions of the source pad (72) in the second direction (Y); Including, a dimension (WD2) of the second drain wrap portion (94B) in the second direction (Y) is smaller than a dimension (WD1) of the first drain wrap portion (94A) in the first direction (X); The dimension (WS2) of the second sauce wrap portion (95B) in the second direction (Y) is smaller than the dimension (WS1) of the first sauce wrap portion (95A) in the first direction (X). 11. The nitride semiconductor device according to any one of claims 2 to 10.

[0219] [Appendix 27] The drain pad (71) and the source pad (72) are arranged in a first direction (X), A direction perpendicular to the first direction (X) as viewed from the thickness direction (Z) of the nitride semiconductor chip (20) is defined as a second direction (Y), The gate pad (73) is arranged next to the drain pad (71E) in the second direction (Y), The dimension (WG2) of the gate wrap portion (96) in the second direction (Y) is smaller than the dimension (WD1) of the drain wrap portion (94) in the first direction (X) and the dimension (WS1) of the source wrap portion (95) in the first direction (X). 16. The nitride semiconductor device according to any one of claims 12 to 15.

[0220] [Appendix 28] The drain pad (71) and the source pad (72) are arranged in a first direction (X), The drain wrap portion (94) includes first drain wrap portions (94A) that respectively cover both end portions of the drain pad (71) in the first direction (X), The source wrap portion (95) includes first source wrap portions (95A) that respectively cover both end portions of the source pad (72) in the first direction (X), a sum of the dimensions (WD1) of the two first drain wrap portions (94A) of the drain pad (71) in the first direction (X) is equal to or greater than a first pad distance (PD1) that is a distance between the drain pad (71) and the source pad (72) in the first direction (X); The sum of the dimensions (WS1) of the two first source wrap portions (95A) in the first direction (X) of the source pad (72) is equal to or greater than the first pad distance (PD1). 11. The nitride semiconductor device according to any one of claims 2 to 10.

[0221] [Appendix 29] each of the drain clip (110) and the source clip (120) including an opposing surface (112 / 122) facing the second metal layer (82); The opposing surface (112) of the drain clip (110) is disposed closer to the second metal layer (82) than the upper surface (94S) of the drain wrap portion (94), The opposing surface (122) of the source clip (120) is disposed closer to the second metal layer (82) than the upper surface (95S) of the source wrap portion (95). 11. The nitride semiconductor device according to any one of claims 4 to 10.

[0222] [Appendix 30] The nitride semiconductor chip (20) is sealed with a sealing resin (240). 30. The nitride semiconductor device according to any one of appendices 1 to 29.

[0223] [Appendix 31] a die pad (200) on which the nitride semiconductor chip (20) is mounted; a drain terminal (210) electrically connected to the drain pad (71) of the nitride semiconductor chip (20); a source terminal (220) electrically connected to the source pad (72) of the nitride semiconductor chip (20); a gate terminal (230) electrically connected to the gate pad (73) of the nitride semiconductor chip (20); Contains 31. The nitride semiconductor device according to claim 30.

[0224] [Appendix 32] The sealing resin (240) includes a first sealing surface (241) and a second sealing surface (242) opposite to the first sealing surface (241), The die pad (200), the drain terminal (210), the source terminal (220), and the gate terminal (230) are each exposed from the second sealing surface (242). 32. The nitride semiconductor device according to claim 31.

[0225] [Appendix 33] forming a first metal layer (81) on a first surface (821) of a nitride semiconductor chip (820) including a nitride transistor (30) having a drain electrode (41), a source electrode (42), and a gate electrode (43), for each of a drain pad (71) electrically connected to the drain electrode (41), a source pad (72) electrically connected to the source electrode (42), and a gate pad (73) electrically connected to the gate electrode (43); forming a resin layer (890) covering the first surface (821); forming a drain opening (91) exposing the drain pad (71), a source opening (92) exposing the source pad (72), and a gate opening (93) exposing the gate pad (73) in the resin layer (890); forming a second metal layer (82) made of a material less susceptible to oxidation than the first metal layer (81) on each of the drain pad (71), the source pad (72), and the gate pad (73) so as to cover the first metal layer (81); Including, The portion of the drain pad (71) exposed by the drain opening (91) is the second metal layer (82), The portion of the source pad (72) exposed by the source opening (92) is the second metal layer (82); The portion of the gate pad (73) exposed by the gate opening (93) is the second metal layer (82). A method for manufacturing a nitride semiconductor device.

[0226] [Appendix 34] a semiconductor chip including a transistor having a drain electrode, a source electrode, and a gate electrode, and a first surface (21) provided with a drain pad (71) electrically connected to the drain electrode, a source pad (72) electrically connected to the source electrode, and a gate pad (73) electrically connected to the gate electrode; an organic insulating layer (90) covering the first surface (21); Including, The organic insulating layer (90) is a drain opening (91) exposing the drain pad (71); a source opening (92) exposing the source pad (72); a gate opening (93) exposing the gate pad (73); a first insulating portion (98A) provided between the drain opening (91) and the source opening (92) and insulating the drain pad (71) from the source pad (72); Including, Each of the drain pad (71), the source pad (72), and the gate pad (73) is a first metal layer (81) provided on the first surface (21); a second metal layer (82) made of a material less susceptible to oxidation than the first metal layer (81) and covering the first metal layer (81); Including, The portion of the drain pad (71) exposed by the drain opening (91) is the second metal layer (82), The portion of the source pad (72) exposed by the source opening (92) is the second metal layer (82); The portion of the gate pad (73) exposed by the gate opening (93) is the second metal layer (82). Semiconductor device.

[0227] [Appendix 35] In a plan view seen from a thickness direction (Z) of the semiconductor chip, the drain opening (91) is smaller than the first metal layer (81) of the drain pad (71); the organic insulating layer (90) is provided at a position overlapping the periphery of the first metal layer (81) of the drain pad (71), and includes a drain lap portion (94) that defines the drain opening (91); In the plan view, the second metal layer (82) of the drain pad (71) is smaller than the first metal layer (81) of the drain pad (71), In the plan view, the source opening (92) is smaller than the first metal layer (81) of the source pad (72); the organic insulating layer (90) is provided at a position overlapping the periphery of the first metal layer (81) of the source pad (72), and includes a source wrap portion (95) that defines the source opening (92); In the plan view, the second metal layer (82) of the source pad (72) is smaller than the first metal layer (81) of the source pad (72); The thickness (TD) of the drain wrap portion (94) is greater than the thickness (T2) of the second metal layer (82) of the drain pad (71), The thickness (TS) of the source wrap portion (95) is greater than the thickness (T2) of the second metal layer (82) of the source pad (72). 35. The semiconductor device according to claim 34.

[0228] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0229] 10...Nitride semiconductor device 20...Nitride semiconductor chip 21...Side 1 22…Second side 23~26…1st~4th side 27...Corner area 30...Nitride transistor 31...Semiconductor substrate 32...Semiconductor layer 33...Buffer layer 34...Electron transit layer 35...electron supply layer 35A…Top surface 36...Two-dimensional electron gas (2DEG) 37...Gate layer 37A...Ridge 37AA…Top surface 37B...Drain side extension 37BA…Top surface 37C…Source side extension part 37CA…Top surface 41...Drain electrode 42...Source electrode 43...Gate electrode 44...Field plate electrode 51...passivation layer 52...Source opening 53...Drain opening 54...First insulating layer 55...Second insulating layer 61A~61C...Drain wiring 62A~62C...Source wiring 63...Gate wiring 64...Outer gate wiring 64A...Pad connection part 64B...Peripheral wiring section 65...Intermediate gate wiring 66...Drain via 67...Sauce Beer 68...Gate Via 71...Drain pad 71A...Exposed drain 71E...End drain pad 72...Sauce Pad 72A...Exposed source 73...Gate pad 73A...Exposed gate 74...Drain via 75...Sauce Beer 76...Gate Via 81...first metal layer 81A…Top surface 81B…Bottom surface 82…Second metal layer 90...Organic insulating layer 91...Drain opening 91A...Side 92...Source opening 92A…Side 93...Gate opening 93A…Side 94...Drain wrap section 94A...First drain wrap section 94B...Second drain wrap section 94S…Top surface 95...Sauce wrap section 95A...First sauce wrap section 95B...Second sauce wrap section 95S…Top surface 96...Gate wrap section 96A...First gate wrap section 96B...Second gate wrap section 97A...First tip lap section 97B...Second tip lap section 98A...First insulating section 98B...Second insulating part 99...Outer periphery connection part 101...First conductive bonding material 102...Second conductive bonding material 103...intervening part 104...Fillet 105...Contact end 106...intervening part 107...Fillet 108...Contact end 110...Drain clip 111…Top surface 112…Bottom surface 113...Side 120...Source clip 121…Top surface 122…Bottom surface 123...Side 130...Gate wire 200...Die pad 210...Drain terminal 220...Source terminal 230...Gate terminal 240…Sealing resin 241...first sealing surface 242…Second sealing surface 243~246...1st~4th sealing side 820...Nitride semiconductor chip 821...Side 1 890...Resin layer SD: Conductive adhesive TA...first transistor cell TB: Second transistor cell TC: Third transistor cell T1: Thickness of the first metal layer T2: Thickness of the second metal layer TP: Thickness of the interposed part TQ: Thickness of the contact edge TC1: Thickness of the first chip lap TC2: Thickness of the second chip lap TD: Thickness of drain wrap TS: Thickness of the sauce wrap TG: Gate wrap thickness TCD: Drain clip thickness TCS: Source clip thickness WD1: Width of first drain wrap WD2: Width of second drain wrap WD3: Width of first drain wrap WS1: Width of the first sauce wrap WS2: Width of second sauce wrap WG1: Width of first gate wrap WG2: Width of second gate wrap WPD: Width of drain pad WPS: Source pad width W1: Opening width of drain opening W2: Source opening width PD1: Distance between first pads PD2: Distance between second pads D1: Distance between first openings

Claims

1. a nitride semiconductor chip including: a nitride transistor having a drain electrode, a source electrode, and a gate electrode; and a first surface provided with a drain pad electrically connected to the drain electrode, a source pad electrically connected to the source electrode, and a gate pad electrically connected to the gate electrode; an organic insulating layer covering the first surface; Including, The organic insulating layer is a drain opening exposing the drain pad; a source opening exposing the source pad; a gate opening exposing the gate pad; a first insulating portion provided between the drain opening and the source opening and insulating the drain pad from the source pad; Including, Each of the drain pad, the source pad, and the source pad comprises: a first metal layer provided on the first surface; a second metal layer made of a material less susceptible to oxidation than the first metal layer and covering the first metal layer; Including, a portion of the drain pad exposed by the drain opening is the second metal layer; a portion of the source pad exposed by the source opening is the second metal layer; The portion of the gate pad exposed by the gate opening is the second metal layer. Nitride semiconductor devices.

2. In a plan view seen from a thickness direction of the nitride semiconductor chip, the drain opening is smaller than the first metal layer of the drain pad; the organic insulating layer includes a drain lap portion that is provided at a position that overlaps a periphery of the first metal layer of the drain pad and that defines the drain opening; In the plan view, the second metal layer of the drain pad is smaller than the first metal layer of the drain pad; In the plan view, the source opening is smaller than the first metal layer of the source pad; the organic insulating layer includes a source wrap portion that is provided at a position that overlaps a periphery of the first metal layer of the source pad and that defines the source opening; In the plan view, the second metal layer of the source pad is smaller than the first metal layer of the source pad. The nitride semiconductor device according to claim 1 .

3. The thickness of the drain wrap portion is greater than the thickness of the second metal layer of the drain pad, The thickness of the source wrap portion is greater than the thickness of the second metal layer of the source pad. The nitride semiconductor device according to claim 2 .

4. a conductive drain clip bonded to the second metal layer of the drain pad; a conductive source clip bonded to the second metal layer of the source pad; Contains The nitride semiconductor device according to claim 2 .

5. The thickness of the drain clip is greater than the thickness of the drain wrap portion, The thickness of the source clip is greater than the thickness of the source wrap portion. The nitride semiconductor device according to claim 4 .

6. a first conductive bonding material that bonds the second metal layer of the drain pad and the drain clip; a second conductive bonding material that bonds the second metal layer of the source pad and the source clip; Including, the first conductive bonding material is in contact with a side surface of the drain clip, The second conductive bonding material is in contact with a side surface of the source clip. The nitride semiconductor device according to claim 5 .

7. a thickness of a portion of the first conductive bonding material that contacts the side surface of the drain clip is greater than a thickness of the drain wrap portion; The thickness of the portion of the second conductive bonding material that contacts the side surface of the source clip is greater than the thickness of the source wrap portion. The nitride semiconductor device according to claim 6 .

8. the first conductive bonding material is in contact with a side surface of the organic insulating layer that forms the drain opening, The second conductive bonding material is in contact with a side surface of the organic insulating layer that forms the source opening. The nitride semiconductor device according to claim 6 .

9. a thickness of a portion of the first conductive bonding material that contacts the side surface of the drain opening is equal to or less than a thickness of the drain wrap portion; The thickness of the portion of the second conductive bonding material that contacts the side surface of the source opening is equal to or less than the thickness of the source wrap portion. The nitride semiconductor device according to claim 8 .

10. a plurality of the drain pads and a plurality of the source pads are provided; the plurality of drain pads and the plurality of source pads are alternately arranged one by one in a first direction; Both the thickness of the drain clip and the thickness of the source clip are thicker than a first inter-pad distance, which is a distance between the drain pad and the source pad adjacent to each other in the first direction. The nitride semiconductor device according to claim 4 .

11. a plurality of the drain pads and a plurality of the source pads are provided; the plurality of drain pads and the plurality of source pads are alternately arranged one by one in a first direction; A first pad distance, which is a distance between the drain pad and the source pad adjacent to each other in the first direction, is 200 μm or less. The nitride semiconductor device according to claim 1 .

12. In the plan view, the gate opening is smaller than the first metal layer of the gate pad; the organic insulating layer includes a gate wrap portion that is provided at a position that overlaps a periphery of the first metal layer of the gate pad and that defines the gate opening; In the plan view, the second metal layer of the gate pad is smaller than the first metal layer of the gate pad. The nitride semiconductor device according to claim 2 .

13. The thickness of the gate wrap portion is greater than the thickness of the second metal layer of the gate pad. The nitride semiconductor device according to claim 12 .

14. a plurality of the drain pads and a plurality of the source pads are provided; the plurality of drain pads and the plurality of source pads are alternately arranged one by one in a first direction; a direction perpendicular to the first direction when viewed from the thickness direction of the nitride semiconductor chip is defined as a second direction; the gate pad is arranged next to one of the plurality of drain pads in the second direction, The organic insulating layer includes a second insulating portion provided between the drain pad and the gate pad adjacent to each other in the second direction and insulating the drain pad and the gate pad. The nitride semiconductor device according to claim 12 .

15. A second pad distance, which is a distance between the drain pad and the gate pad adjacent to each other in the second direction, is 200 μm or less. The nitride semiconductor device according to claim 14.

16. The nitride semiconductor chip comprises: an electron transit layer; an electron supply layer provided on the electron transit layer; a gate layer partially disposed on the electron supply layer; Including, the source electrode and the drain electrode are provided on the electron supply layer and spaced apart from each other, The gate electrode is provided on the gate layer. The nitride semiconductor device according to claim 1 .

17. the electron transit layer is made of a material containing GaN, The electron supply layer has a band gap larger than that of the electron transit layer, and ｘ Ga １－ｘ The material is made of a material containing N, and 0.1<x<0.3; The gate layer contains an acceptor-type impurity and is made of a material containing GaN. The nitride semiconductor device according to claim 16.

18. The first metal layer is made of a material containing Cu. The nitride semiconductor device according to claim 1 .

19. The second metal layer is made of a material containing Ni and Au. The nitride semiconductor device according to claim 1 .

20. A plurality of vias are connected to the lower surface of the first metal layer. The nitride semiconductor device according to any one of claims 1 to 19.

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