Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device that can reduce contact resistance.SOLUTION: A semiconductor device according to an embodiment comprises: a semiconductor part that has a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, and a third semiconductor layer provided in a first trench of the second semiconductor layer; a first electrode that is provided on a rear face of the first semiconductor layer; a first metal film that is in contact with the second semiconductor layer in the first trench; a second metal film that is in contact with the third semiconductor layer and the first metal film in the first trench; and a second electrode that is in contact with the second metal film in the first trench. The first metal film includes a high work function metal, and the second metal film includes a low work function metal having a lower work function than the first metal film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] 2. Description of the Related Art In semiconductor devices such as MOSFETs having trench gates, a structure in which a source electrode and a semiconductor layer are electrically connected by a trench contact is known.

[0003] In a semiconductor device having the trench contact structure described above, a reduction in contact resistance is required in order to reduce the on-resistance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5792701 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of reducing contact resistance and a method for manufacturing the same. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment includes a semiconductor portion having a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, and a third semiconductor layer provided in a first trench in the second semiconductor layer, a first electrode provided on a back surface of the first semiconductor layer, a first metal film in contact with the second semiconductor layer in the first trench, a second metal film in contact with the third semiconductor layer and the first metal film in the first trench, and a second electrode in contact with the second metal film in the first trench. The first metal film includes a high work function metal, and the second metal film includes a low work function metal having a work function lower than that of the first metal film. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 10 is a cross-sectional view illustrating a step of forming a gate electrode, a third electrode, and an insulating film in the second trench. FIG. [Figure 3] FIG. 10 is a cross-sectional view illustrating a step of forming a first trench in a second semiconductor layer. [Figure 4] 10 is a cross-sectional view illustrating a process for forming a PSG film on the inner surface of the first trench. [Figure 5] FIG. 10 is a cross-sectional view illustrating a step of forming a third semiconductor layer. [Figure 6] FIG. 10 is a cross-sectional view illustrating a step of removing the PSG film. [Figure 7] FIG. 10 is a cross-sectional view illustrating a step of etching the first trench to a deeper position. [Figure 8] FIG. 10 is a cross-sectional view illustrating a step of forming a first metal film on the inner surface of the first trench. [Figure 9] FIG. 10 is a cross-sectional view illustrating a step of filling the first trench with an insulating film. [Figure 10] FIG. 10 is a cross-sectional view illustrating a step of etching back an insulating film. [Figure 11] FIG. 10 is a cross-sectional view illustrating a step of removing a part of the first metal film. [Figure 12] FIG. 10 is a cross-sectional view illustrating a step of removing an insulating film. [Figure 13] 10 is a cross-sectional view illustrating a step of forming a second metal film 60 and a third semiconductor layer containing silicide. FIG. [Figure 14] FIG. 10 is a cross-sectional view illustrating a step of embedding a third electrode in the first trench. [Figure 15] FIG. 10 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 16] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 17]FIG. 10 is a cross-sectional view illustrating a step of forming a first metal film in the first trench. [Figure 18] FIG. 10 is a cross-sectional view illustrating a step of etching back the first metal film. [Figure 19] FIG. 10 is a cross-sectional view illustrating a step of forming a second metal film. [Figure 20] FIG. 10 is a cross-sectional view illustrating a step of forming a third semiconductor layer containing silicide. [Figure 21] FIG. 10 is a cross-sectional view illustrating a step of embedding a third electrode in the first trench. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0009] (First embodiment) FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. In the following description, the arrangement and configuration of each part of the semiconductor device may be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually orthogonal and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward. In this embodiment, the X-direction and Y-direction correspond to the first and third directions and represent in-plane directions parallel to the front (or back) surface of the semiconductor device 1. The Z-direction corresponds to the second direction and represents the out-of-plane direction orthogonal to the front (or back) surface of the semiconductor device 1.

[0010] Also, p, p + The notation means that the p-type impurity concentration increases in this order. - , n, n + The notation indicates that the n-type impurity concentration increases in this order.

[0011] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the semiconductor region, can also be determined by, for example, SIMS.

[0012] 1 is a Schottky-type low-voltage MOSFET. The semiconductor device 1 includes a semiconductor portion 10, a first electrode 20, a second electrode 30, a gate electrode 40, a third electrode 41, a first metal film 50, and a second metal film 60.

[0013] The semiconductor portion 10 is made of, for example, silicon. A first electrode 20 is provided on the back surface of the semiconductor portion 10, while a second electrode 30 is provided on the front surface of the semiconductor portion 10. The first electrode 20 is a drain electrode. The second electrode 30 is a source electrode. The first electrode 20 is made of a metal material containing, for example, nickel (Ni), aluminum (Al), etc. On the other hand, the second electrode 30 is made of a metal material containing, for example, tungsten (W) and aluminum (Al).

[0014] The semiconductor section 10 includes a first semiconductor layer 11, a second semiconductor layer 12, and a third semiconductor layer 13. The conductivity type of each semiconductor layer is n-type. Each semiconductor layer will be described below.

[0015] The first semiconductor layer 11 is n + The back surface of the first semiconductor layer 11 is in contact with the first electrode 20. The front surface of the first semiconductor layer 11 is in contact with the second semiconductor layer 12.

[0016] The second semiconductor layer 12 is n -The second semiconductor layer 12 is an n-type drift layer. The concentration of n-type impurities contained in the second semiconductor layer 12 is lower than the concentration of n-type impurities contained in the first semiconductor layer 11. The second semiconductor layer 12 includes a third semiconductor layer 13, a first trench TR1, a second trench TR2, a first metal film 50, and a second metal film 60.

[0017] The third semiconductor layer 13 is n + The third semiconductor layer 13 is a n-type source layer. The concentration of n-type impurities contained in the third semiconductor layer 13 is higher than the concentration of n-type impurities contained in the second semiconductor layer 12. The third semiconductor layer 13 also contains silicide. In this embodiment, titanium silicide (TiSi) is contained in the third semiconductor layer 13. However, the silicide contained in the third semiconductor layer 13 is not limited to titanium silicide. The third semiconductor layer 13 is in contact with the second metal film 60.

[0018] The first trench TR1 is a so-called contact trench. In this embodiment, the first trench TR1 is disposed between two second trenches TR2 arranged in the X direction. The depth of the first trench TR1 from the surface of the semiconductor portion 10 is smaller than the depth of the second trench TR2 from the surface of the semiconductor portion 10. A third semiconductor layer 13, a first metal film 50, a second metal film 60, and a second electrode 30 are provided in the first trench TR1.

[0019] The first metal film 50 contacts the second semiconductor layer 12 at the bottom of the first trench TR1. The material of the first metal film 50 is a high work function metal. In this embodiment, the first metal film 50 is formed of platinum (Pt). However, the material of the first metal film 50 is not limited to platinum, and may be other high work function metals such as Ni or Co.

[0020] The second metal film 60 extends from the top to the bottom of the first trench TR1. The second electrode 30 also extends from the top to the bottom of the first trench TR1. Therefore, at the bottom of the first trench TR1, the second metal film 60 is interposed between the first metal film 50 and the second electrode 30. The second metal film 60 is also interposed between the third semiconductor layer 13 and the second electrode 30 on the side of the first trench TR1.

[0021] The second metal film 60 has, for example, a two-layer structure including a metal layer and a barrier metal layer. This metal layer contacts the first metal film 50 and the third semiconductor layer 13. This barrier metal layer is stacked on the metal layer. The material of the metal layer is, for example, titanium (Ti). On the other hand, the material of the barrier metal layer is titanium nitride (TiN). However, the materials of the metal layer and the barrier metal layer are not limited to titanium and titanium nitride, and may be any low-work function metal having a work function lower than that of the first metal film 50.

[0022] The second trench TR2 is provided with a gate electrode 40, a third electrode 41, and an insulating film 42. The internal structure of the second trench TR2 will be described below.

[0023] The gate electrode 40 and the third electrode 41 are arranged apart in the Z direction. Specifically, the gate electrode 40 is arranged in an upper part of the second trench TR2, while the third electrode 41 is arranged in a lower part of the second trench TR2.

[0024] The third electrode 41 is a so-called field plate. The third electrode 41 is electrically connected to the second electrode 30. The third electrode 41 is electrically insulated from the gate electrode 40 by an insulating film 42. The insulating film 42 is, for example, a silicon oxide film (SiO2).

[0025] The insulating film 42 also functions as a gate insulating film that electrically insulates the gate electrode 40 from the semiconductor portion 10. The second semiconductor layer 12 is provided so as to face the gate electrode 40 via this gate insulating film. The third semiconductor layer 13 is in contact with this gate insulating film.

[0026] A method for manufacturing the semiconductor device 1 according to this embodiment will now be described with reference to Figures 2 to 14. Here, the main manufacturing steps will be described.

[0027] 2, a second trench TR2 is formed in the second semiconductor layer 12 stacked on the first semiconductor layer 11, and a gate electrode 40, a third electrode 41, and an insulating film 42 are formed in the second trench TR2. The gate electrode 40 and the third electrode 41 are formed using, for example, polysilicon.

[0028] 3, a first trench TR1 is formed in the second semiconductor layer 12. The first trench TR1 is formed by, for example, RIE (Reactive Ion Etching). However, in this process, the formation of the first trench TR1 is interrupted when it reaches a depth at which the third semiconductor layer 13 is to be formed, in other words, when it reaches the same height as the upper surface of the gate electrode 40.

[0029] 4, a PSG (Phosphorous Silicate Glass) film 70 is formed on the inner surface of the first trench TR1. The PSG film 70 can be formed by, for example, CVD (Chemical Vapor Deposition).

[0030] Next, the PSG film 70 is heat-treated. This heat treatment causes the n-type impurities contained in the PSG film 70 to thermally diffuse into the second semiconductor layer 12. As a result, as shown in FIG. 5, a third semiconductor layer 131 is formed in a portion in contact with the PSG film 70, i.e., on the inner surface of the first trench TR1.

[0031] 6, the PSG film 70 is removed, thereby exposing the third semiconductor layer 131. The method for forming the third semiconductor layer 131 is not limited to the thermal diffusion from the PSG film 70 described above. The third semiconductor layer 131 may be formed, for example, by ion implantation of n-type impurities into the second semiconductor layer 12.

[0032] 7, the first trench TR1 is etched to a deeper position by, for example, RIE. In this process, the depth of the first trench TR1 reaches the depth at which the first metal film 50 is formed, in other words, the same height level as the bottom surface of the gate electrode 40.

[0033] 8, a first metal film 50 is formed on the inner surface of the first trench TR1. At this time, the third semiconductor layer 131 is covered with the first metal film 50.

[0034] 9, an insulating film 80 is buried in the first trench TR1. The insulating film 80 is formed using, for example, silicon nitride or TEOS (Tetra Ethoxy Silane). The insulating film 80 is desirably formed by a low-temperature film formation method such as plasma CVD, plasma ALD (Atomic Layer Deposition), or SOG (Spin On Glass). By using these film formation methods, it is possible to avoid the formation of platinum silicide (PtSi) in the third semiconductor layer 131.

[0035] 10, the insulating film 80 is etched back. In this step, the insulating film 80 is etched back so that the upper surface of the insulating film 80 is at the same height level as the bottom surface of the third semiconductor layer 131 in the first trench TR1.

[0036] 11, the portions of the first metal film 50 formed on the side surfaces of the first trenches TR1, in other words, the portions not in contact with the insulating film 80, are removed. The first metal film 50 is etched using a chemical solution such as aqua regia.

[0037] 12, the insulating film 80 is removed, thereby exposing the first metal film 50.

[0038] 13, a second metal film 60 is formed in the first trench TR1 to cover the third semiconductor layer 131 and the first metal film 50. Subsequently, the second metal film 60 is heat-treated to form a third semiconductor layer 13 containing silicide.

[0039] 14, the second electrode 30 is buried in the first trench TR1. Separately from this process, the first electrode 20 is formed on the back surface of the first semiconductor layer 11.

[0040] Here, a comparative example to be compared with this embodiment will be described.

[0041] Fig. 15 is a cross-sectional view of a semiconductor device according to a comparative example. In Fig. 15, the same components as those in the semiconductor device 1 described above are denoted by the same reference numerals, and redundant explanations will be omitted.

[0042] In the semiconductor device 100 according to this comparative example, a first metal film 50 containing a high work function metal is interposed between the third semiconductor layer 131 and the second metal film 60. That is, a Schottky junction is formed in both an upper mesa region, which is a contact region between the third semiconductor layer 131 and the first metal film 50, and a lower mesa region, which is a contact region between the first metal film 50 and the second semiconductor layer 12.

[0043] In the semiconductor device 100 having the above-described structure, the contact resistance decreases as the n-type impurity concentration of the third semiconductor layer 131 increases. However, as shown in Fig. 15 , the third semiconductor layer 131 is formed thinly on the sidewall of the first trench TR1. Therefore, locally implanting a high concentration of n-type impurities into the third semiconductor layer 131 is a difficult process.

[0044] Therefore, in this embodiment, the third semiconductor layer 13 is in contact with the second metal film 60 containing a low work function metal. As a result, an ohmic junction is formed between the third semiconductor layer 13 and the second metal film 60 in the upper mesa region, and a Schottky junction is formed between the first metal film 50 containing a high work function metal and the second semiconductor layer 12 in the lower mesa region.

[0045] Therefore, according to this embodiment, it is possible to reduce the contact resistance by a method other than increasing the n-type impurity concentration of the third semiconductor layer 131.

[0046] Furthermore, when the third semiconductor layer 131 containing a high concentration of n-type impurities is formed by thermal diffusion of the PSG film 70 as in this embodiment, a local ion implantation process becomes unnecessary.

[0047] (Second embodiment) 16 is a cross-sectional view of a semiconductor device according to the second embodiment. In FIG. 16, components similar to those in the semiconductor device 1 according to the first embodiment described above are denoted by the same reference numerals, and redundant explanations will be omitted. In the semiconductor device 1 according to the first embodiment described above, the second metal film 60 and the second electrode 30 extend from the top to the bottom of the first trench TR1.

[0048] 16, in the semiconductor device 2 according to the second embodiment, the first metal film 50 is buried in the lower part of the first trench TR1, so that the second metal film 60 and the second electrode 30 terminate at the upper part of the first trench TR1.

[0049] 17 to 21, a method for manufacturing the semiconductor device 2 according to this embodiment will be described. Note that the steps up to forming the third semiconductor layer 131 by thermal diffusion of the PSG film 70 (see FIGS. 2 to 7) are the same as those in the first embodiment, and therefore will not be described here.

[0050] In this embodiment, after the third semiconductor layer 131 is formed and the first trench TR1 is etched to a deeper position, a first metal film 50 is formed in the first trench TR1 as shown in FIG. 17. At this time, the first trench TR1 is filled with the first metal film 50.

[0051] 18, the first metal film 50 is etched back. In this embodiment, the first metal film 50 is etched back so that the upper surface of the first metal film 50 in the first trench TR1 is at the same height level as the upper surface of the gate electrode 40.

[0052] Next, as shown in FIG. 19, a second metal film 60 is formed so as to cover the third semiconductor layer 131 and the first metal film 50 in the first trench TR1.

[0053] Next, the second metal film 60 is heat-treated, thereby forming a third semiconductor layer 13 containing silicide, as shown in FIG.

[0054] 21, the second electrode 30 is buried in the first trench TR1. Separately from this process, the first electrode 20 is formed on the back surface of the first semiconductor layer 11.

[0055] In the present embodiment described above, as in the first embodiment, an ohmic junction is formed between the third semiconductor layer 13 and the second metal film 60 in the upper mesa region, and a Schottky junction is formed between the first metal film 50 and the second semiconductor layer 12 in the lower mesa region.

[0056] Therefore, according to this embodiment, similarly to the first embodiment, it is possible to reduce the contact resistance by a method other than increasing the n-type impurity concentration in the third semiconductor layer 131. Also in this embodiment, if the third semiconductor layer 131 containing a high concentration of n-type impurities is formed by thermal diffusion of the PSG film 70, the local ion implantation process becomes unnecessary.

[0057] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0058] 1, 2: Semiconductor device 10: Semiconductor Department 11: First semiconductor layer 12: Second semiconductor layer 13: Third semiconductor layer 20: 1st electrode 30:Second electrode 40: Gate electrode 41:Third electrode 42: insulating film 50: First metal film 60:Second metal film 70:PSG membrane 131: Third semiconductor layer TR1: First trench TR2: Second trench

Claims

1. a semiconductor portion including a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, and a third semiconductor layer provided in a first trench of the second semiconductor layer; a first electrode provided on a rear surface of the first semiconductor layer; a first metal film in contact with the second semiconductor layer in the first trench; a second metal film in contact with the third semiconductor layer and the first metal film in the first trench; a second electrode in contact with the second metal film in the first trench; the first metal film includes a high work function metal; The second metal film includes a low work function metal having a work function lower than that of the first metal film.

2. The semiconductor device according to claim 1 , wherein the third semiconductor layer includes a silicide.

3. the third semiconductor layer is provided on an upper portion of the first trench; 3. The semiconductor device according to claim 1, wherein the first metal film is provided in a lower portion of the first trench.

4. The semiconductor device according to claim 3 , wherein the first metal film and the second electrode extend from the upper portion to the lower portion of the first trench.

5. the first metal film and the second electrode terminate at the top of the first trench; The semiconductor device according to claim 3 , wherein said first metal film is buried in said lower portion of said first trench.

6. the first trench is disposed between two second trenches arranged in the second semiconductor layer; 3. The semiconductor device according to claim 1, wherein a gate electrode, a third electrode electrically connected to the second electrode, and an insulating film electrically insulating the gate electrode and the second electrode are provided in the second trench.

7. 3. The semiconductor device according to claim 2, wherein said silicide is titanium silicide (TiSi), said high work function metal is platinum (Pt), and said low work function metal is titanium (Ti).

8. 3. The semiconductor device according to claim 1, wherein each of the second semiconductor layer and the third semiconductor layer contains an n-type impurity, and a concentration of the n-type impurity contained in the third semiconductor layer is higher than a concentration of the n-type impurity contained in the second semiconductor layer.

9. forming a first trench in a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer, a first metal film in contact with the second semiconductor layer and containing a high work function metal, and a second metal film in contact with the third semiconductor layer and the first metal film and containing a low work function metal having a work function lower than that of the first metal film, are sequentially formed in the first trench; forming a first electrode on the rear surface of the first semiconductor layer, and forming a second electrode in contact with the second metal film in the first trench; A method for manufacturing a semiconductor device.

10. forming a PSG (Phosphorous Silicate Glass) film on the inner surface of the first trench TR1; 10. The method for manufacturing a semiconductor device according to claim 9, wherein the third semiconductor layer is formed by heat-treating the PSG film.

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