Method for manufacturing semiconductor device

Abstract

To prevent oxidation of a back electrode of a semiconductor chip.SOLUTION: After grinding a backside SB2 of a semiconductor substrate SB so that a thickness of a central portion CT of the semiconductor substrate SB becomes smaller than a thickness of a peripheral portion PR, a metal film ME containing a silver film or a copper film is formed on the backside SB2 of the semiconductor substrate SB. Thereafter, a dicing tape DT is attached to the backside SB2 of the semiconductor substrate SB through the metal film ME. A base material layer of the dicing tape DT is made of polyvinyl chloride. Subsequently, the peripheral portion PR is separated from the central portion CT and the dicing tape DT, and then, the semiconductor substrate SB attached to the dicing tape DT is diced. The semiconductor substrate SB attached to the dicing tape DT is then transported.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and can be suitably used, for example, in a method for manufacturing a semiconductor device that includes a step of dicing a semiconductor wafer having a backside metal film. [Background technology]

[0002] After a dicing tape is attached to the rear surface of the semiconductor wafer, the semiconductor wafer is diced, thereby dividing the semiconductor wafer into a plurality of semiconductor chips.

[0003] Japanese Patent Application Laid-Open No. 2016-192450 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2011-222843 (Patent Document 2) describe polishing the back surface of a semiconductor wafer so that the thickness of the central part of the semiconductor wafer is smaller than the thickness of the peripheral part of the semiconductor wafer, and then attaching a dicing tape to the back surface of the semiconductor wafer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-192450 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-222843 Summary of the Invention [Problem to be solved by the invention]

[0005] A gold (Au) film is generally used as the back electrode of a semiconductor chip. However, the inventors of the present application are considering using a material that is more easily oxidized than a gold film, such as a silver (Ag) film, as the back electrode of a semiconductor chip. The price of silver is lower than that of gold. Therefore, if a silver film is used instead of a gold film as the back electrode of a semiconductor chip, the manufacturing cost of the semiconductor chip can be reduced.

[0006] However, as mentioned above, silver oxidizes more easily than gold. If the silver film oxidizes, the performance and reliability of the semiconductor device assembled using the semiconductor chip may be reduced. Therefore, it is desirable to take some measures to prevent the oxidation of the back electrode, which is made of a material that oxidizes more easily than gold.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] According to one embodiment, a method for manufacturing a semiconductor device includes the steps of: grinding the second main surface of a semiconductor wafer so that the thickness of the central portion of the semiconductor wafer is smaller than the thickness of the peripheral portion; forming a metal film on the second main surface of the semiconductor wafer, the metal film including a first metal film made of a silver film or a copper film; and attaching a dicing tape to the second main surface of the semiconductor wafer via the metal film. The method for manufacturing a semiconductor device further includes the steps of separating the peripheral portion from the central portion and the dicing tape, then dicing the semiconductor wafer attached to the dicing tape, and then transporting the diced semiconductor wafer attached to the dicing tape. The dicing tape has a base layer and an adhesive layer on the base layer. The base layer is made of polyvinyl chloride. [Effects of the Invention]

[0009] According to one embodiment, it is possible to prevent oxidation of the back electrode of the semiconductor chip. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a process flow diagram showing a manufacturing process of a semiconductor device according to an embodiment. [Figure 2] 1 is a plan view showing a semiconductor substrate used in a manufacturing process of a semiconductor device according to an embodiment of the present invention; [Figure 3]3 is a cross-sectional view of the semiconductor substrate taken along line A1-A1 in FIG. 2. [Figure 4] 1 is a cross-sectional view of a semiconductor substrate after a wiring structure forming step has been performed; [Figure 5] FIG. 2 is a plan view showing the back surface of the wafer after the back surface grinding process. [Figure 6] FIG. 6 is a cross-sectional view taken along the line A1-A1 in FIG. 5. [Figure 7] 10 is a cross-sectional view of the vicinity of an edge of a semiconductor substrate after a backside grinding process has been performed. [Figure 8] FIG. [Figure 9] FIG. 10 is a cross-sectional view of a wafer that has undergone a backside metal film forming step. [Figure 10] 10 is a cross-sectional view of the vicinity of an edge of a semiconductor substrate after a backside metal film forming step has been performed. [Figure 11] 2 is a partially enlarged cross-sectional view showing a rear surface layer portion of a semiconductor substrate and a metal film formed thereon. FIG. [Figure 12] FIG. 10 is a plan view showing a wafer that has undergone a dicing tape application step. [Figure 13] FIG. 13 is a cross-sectional view taken along the line A1-A1 in FIG. [Figure 14] 10 is a cross-sectional view of the vicinity of an end portion of a semiconductor substrate after a dicing tape application step has been performed. [Figure 15] 2 is a partially enlarged cross-sectional view showing a rear surface layer portion of a semiconductor substrate, a metal film formed thereon, and a dicing tape formed thereon. FIG. [Figure 16] FIG. 10 is an explanatory diagram of a dicing tape attaching step. [Figure 17] FIG. 17 is a partially enlarged cross-sectional view of a part of FIG. 16. [Figure 18] FIG. 10 is an explanatory diagram of a dicing tape attaching step. [Figure 19] FIG. 10 is an explanatory diagram of a peripheral edge separating step. [Figure 20] FIG. 20 is a partially enlarged cross-sectional view of a part of FIG. 19. [Figure 21] FIG. 10 is an explanatory diagram of a peripheral edge separating step. [Figure 22]FIG. 10 is a plan view of the wafer at the stage where a peripheral edge separation process has been completed. [Figure 23] FIG. [Figure 24] FIG. [Figure 25] FIG. 10 is a plan view of the wafer at the stage where the dicing process is completed. [Figure 26] 26 is a cross-sectional view taken along the line A1-A1 in FIG. 25. [Figure 27] FIG. 10 is a cross-sectional view showing an example of a semiconductor device assembled using the obtained semiconductor chip. [Figure 28] 10A and 10B are explanatory diagrams of a pick-up process for obtaining a semiconductor chip from a structure. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following embodiments, the description will be divided into multiple sections or embodiments for convenience, as necessary. However, unless otherwise specified, they are not unrelated to one another, and one is a partial or complete modification, detail, supplementary explanation, etc., of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited to a specific number in principle. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of components, etc. are mentioned, it is intended to include those that are substantially similar to or similar to the shape, etc., unless otherwise specified or clearly considered not to be essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to make the drawings easier to see, and hatching may be added even in plan views to make the drawings easier to see.

[0014] (Embodiment) The manufacturing process of the semiconductor device of this embodiment will be described below. Fig. 1 is a process flow diagram showing the manufacturing process of the semiconductor device of this embodiment.

[0015] <Semiconductor substrate preparation process> Fig. 2 is a plan view showing a semiconductor substrate SB used in the manufacturing process of the semiconductor device of this embodiment, Fig. 3 is a cross-sectional view of the semiconductor substrate SB taken along line A1-A1 of Fig. 2.

[0016] 2 and 3, a semiconductor substrate (semiconductor wafer) SB made of single crystal silicon or the like is prepared (step S1 in FIG. 1). The semiconductor substrate SB prepared in step S1 is a substantially disk-shaped semiconductor wafer. The semiconductor substrate SB may have a notch NT for identifying the planar orientation of the semiconductor substrate SB.

[0017] As shown in FIG. 2, the semiconductor substrate SB has a plurality of chip regions 1A, which are regions from which semiconductor chips are to be obtained, and scribe regions 1B between adjacent chip regions 1A, and in a planar view, each chip region 1A is surrounded by the scribe region 1B. That is, in the semiconductor substrate SB, a plurality of chip regions 1A are arranged in an array, and the region between adjacent chip regions 1A corresponds to the scribe region 1B. In a dicing process described below, the semiconductor substrate SB is cut (diced) along the scribe regions 1B, thereby dividing each chip region 1A into individual chip regions 1A and obtaining semiconductor chips. Note that, at the stage when the semiconductor substrate SB is prepared in step S1, the chip region 1A and the scribe region 1B are virtual regions, and there is no boundary or the like between the chip region 1A and the scribe region 1B.

[0018] 3, the semiconductor substrate SB has a front surface SB1 which is one main surface, and a back surface SB2 which is the main surface opposite to the front surface SB1. The semiconductor substrate SB prepared in step S1 has a uniform thickness. In the semiconductor substrate SB prepared in step S1, the entire front surface SB1 is flat, and the entire back surface SB2 is flat.

[0019] <Semiconductor element formation process> Next, semiconductor elements are formed in each of the plurality of chip regions 1A of the semiconductor substrate SB (step S2 in FIG. 1). Examples of the semiconductor elements include MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and bipolar transistors. For example, trench-gate MISFETs, LDMOSFETs (Lateral Diffused Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), etc. can be formed on the semiconductor substrate SB.

[0020] <Wiring structure formation process> Next, as shown in Fig. 4, a wiring structure WR is formed on the surface SB1 of the semiconductor substrate SB (step S3 in Fig. 1). Fig. 4 is a cross-sectional view of the semiconductor substrate SB after the wiring structure formation process of step S3 has been performed, and shows a cross section corresponding to Fig. 3 above.

[0021] The wiring structure WR includes one or more insulating layers, one or more wiring layers, and a top-layer protective film (protective insulating film, passivation film). The top-layer wiring layer included in the wiring structure WR includes a plurality of pads (pad electrodes). In the wiring structure WR, each pad is exposed through an opening in the protective film. In each chip area 1A, a predetermined circuit (integrated circuit) is formed by semiconductor elements formed in or on the surface of the semiconductor substrate SB and wiring formed in the wiring structure WR.

[0022] Hereinafter, the semiconductor substrate SB and the wiring structure WR on the surface SB1 of the semiconductor substrate SB will be referred to as a wafer (semiconductor wafer) WF. The back surface of the wafer WF corresponds to the back surface SB2 of the semiconductor substrate SB. The front surface of the wafer WF corresponds to the surface of the wiring structure WR on the surface SB1 of the semiconductor substrate SB. The front surface and the back surface of the wafer WF are located on opposite sides of each other.

[0023] <Back grinding process> Next, the back surface of the wafer WF (back surface SB2 of the semiconductor substrate SB) is ground (step S4 in FIG. 1). By performing the back surface grinding step of step S4, the thickness of the semiconductor substrate SB is reduced.

[0024] In the above steps S2 and S3, from the viewpoint of preventing damage to the semiconductor substrate SB, it is desirable to make the thickness of the semiconductor substrate SB thick to a certain extent. On the other hand, from the viewpoint of miniaturizing the semiconductor device, it is desirable to make the thickness of the semiconductor chips obtained after the dicing process described below thin. In this embodiment, the thickness of the semiconductor substrate SB is thinned by performing the backside grinding process of step S4 after steps S2 and S3. Therefore, in steps S2 and S3, the thickness of the semiconductor substrate SB can be ensured to prevent damage to the semiconductor substrate SB, and the thickness of the semiconductor chips obtained after the dicing process described below can be thinned.

[0025] However, in the backside grinding step of step S4, if the entire backside surface SB2 of the semiconductor substrate SB shown in Fig. 4 is simply ground uniformly to uniformly reduce the thickness of the entire semiconductor substrate SB, as opposed to the present embodiment, the handleability of the wafer WF after the backside grinding step of step S4 will be reduced. In that case, there is also a concern that warpage will occur in the wafer WF, and the occurrence of warpage will cause a decrease in processing accuracy in the dicing step.

[0026] Therefore, in this embodiment, as shown in Figures 5 to 7, in the back surface grinding process of step S4, the peripheral portion PR of the semiconductor substrate SB is hardly ground, and the central portion CT surrounded by the peripheral portion PR is selectively ground to make it thinner.

[0027] FIG. 5 is a plan view showing the back surface (back surface SB2 of the semiconductor substrate SB) of the wafer that has undergone the back surface grinding process of step S4. FIG. 6 is a cross-sectional view taken along line A1-A1 in FIG. 5. In FIG. 6, the wafer WF is shown with its back surface (back surface SB2 of the semiconductor substrate SB) facing upward. Although FIG. 5 is a plan view, for ease of understanding, the central portion CT and the peripheral portion PR are hatched in different directions. Also, in FIG. 5, multiple chip regions 1A of the semiconductor substrate SB are indicated by dotted lines. FIG. 7 is a cross-sectional view of the vicinity of the edge of the semiconductor substrate SB that has undergone the back surface grinding process of step S4. The wiring structure WR is not shown in FIG. 7. FIG. 8 is an explanatory diagram of the back surface grinding process.

[0028] In a plan view, the semiconductor substrate SB has a central portion CT and a peripheral portion PR that continuously surrounds the periphery of the central portion CT (see FIG. 5). In the semiconductor substrate SB, a plurality of chip regions 1A are located in the central portion CT, and no chip regions 1A are arranged in the peripheral portion PR.

[0029] Before the backside grinding process of step S4 is performed, the entire backside surface SB2 of the semiconductor substrate SB is flat, and the thickness of the semiconductor substrate SB is approximately uniform. Therefore, before the backside grinding process of step S4 is performed, the thickness of the central portion CT of the semiconductor substrate SB is the same as the thickness of the peripheral portion PR.

[0030] In the backside grinding process of step S4, the backside SB2 of the semiconductor substrate SB is ground so that the thickness T2 of the central portion CT is thinner than the thickness T1 of the peripheral portion PR (T1>T2), as shown in Figures 6 and 7. The planar shape of the central portion CT is preferably circular. The planar shape of the peripheral portion PR is preferably annular.

[0031] Here, the thickness of the central portion CT of the semiconductor substrate SB after the backside grinding process of step S4 is referred to as thickness T2, and the thickness of the peripheral portion PR of the semiconductor substrate SB after the backside grinding process of step S4 is referred to as thickness T1. The thickness T2 of the central portion CT corresponds to the distance from the front surface SB1 to the back surface SB2 of the semiconductor substrate SB at the central portion CT. The thickness T1 of the peripheral portion PR corresponds to the distance from the front surface SB1 to the back surface SB2 of the semiconductor substrate SB at the peripheral portion PR. The thickness T2 of the central portion CT is thinner than the thickness T1 of the peripheral portion PR (T1>T2). The thickness T2 of the central portion CT is, for example, not less than 50 micrometers and not more than 150 micrometers, and the thickness T1 of the peripheral portion PR is, for example, not less than 700 micrometers and not more than 775 micrometers. The difference between the thickness T1 of the peripheral portion PR and the thickness T2 of the central portion CT of the semiconductor substrate SB is, for example, not less than 550 micrometers and not more than 725 micrometers.

[0032] 5, the width W1 of the peripheral portion PR is substantially constant regardless of the position of the peripheral portion PR except for the portion where the notch NT is formed. The width W1 of the peripheral portion PR is, for example, not less than 4000 micrometers and not more than 6000 micrometers.

[0033] In this way, by increasing the thickness T1 of the peripheral portion PR surrounding the central portion CT, the peripheral portion PR can function as a reinforcing member that suppresses warpage of the semiconductor substrate SB. This improves the handleability of the wafer WF after the backside grinding process of step S4, and suppresses or prevents warpage of the wafer WF. On the other hand, by decreasing the thickness T2 of the central portion CT where the multiple chip regions 1A are located, the thickness of the semiconductor chips obtained after the dicing process described below can be reduced.

[0034] A specific example of the back grinding process in step S4 will be described below with reference to FIG.

[0035] First, as shown in the upper part of Figure 8, a backgrinding tape BT is attached to the surface of the wafer WF. The backgrinding tape BT has the function of preventing semiconductor elements formed in the semiconductor substrate SB or on the surface SB1 of the semiconductor substrate SB, or the wiring layer of the wiring structure WR, from being contaminated by grinding debris from the semiconductor substrate SB or cleaning water during the backgrinding process. The backgrinding tape BT has a resin film as a base material and an adhesive layer formed on one main surface of the resin film. The backgrinding tape BT is attached to the surface of the wafer WF so that the adhesive layer of the backgrinding tape BT contacts the surface of the wafer WF (the surface of the wiring structure WR).

[0036] Next, although not shown in Figure 8, the entire back surface of the wafer WF is ground with the backgrind tape BT attached to the wafer WF (pre-grinding step). This reduces the thickness of the entire semiconductor substrate SB. This pre-grinding step may be omitted.

[0037] 8, with the backgrind tape BT attached to the wafer WF, a grinding jig KG1 such as a grindstone is used to grind the back surface of the wafer WF (the back surface SB2 of the semiconductor substrate SB) (rough grinding step). At this time, the central portion CT of the semiconductor substrate SB is selectively ground until the thickness of the central portion CT of the semiconductor substrate SB reaches a predetermined thickness.

[0038] Next, as shown in the lower part of Figure 8, with the backgrind tape BT attached to the wafer WF, a grinding jig KG2 such as a grindstone is used to grind the back surface of the wafer WF (the back surface SB2 of the semiconductor substrate SB) (finish grinding process). At this time, the central portion CT of the semiconductor substrate SB is selectively ground until the thickness of the central portion CT of the semiconductor substrate SB reaches the design target thickness. The grain size of the abrasive grains in the grinding jig KG2 is smaller than the grain size of the abrasive grains in the grinding jig KG1.

[0039] By performing grinding using a grinding jig KG1 having abrasive grains with a large grain size in the rough grinding process, the total time required for the grinding process can be shortened. Then, by performing grinding using a grinding jig KG2 having abrasive grains with a small grain size in the subsequent finish grinding process, the flatness of the back surface SB2 at the center portion CT of the semiconductor substrate SB can be improved. This makes it possible to achieve both a reduction in the time required for the grinding process and an improvement in the flatness of the back surface SB2 at the center portion CT of the semiconductor substrate SB.

[0040] By selectively grinding the central portion CT of the semiconductor substrate SB in the back surface grinding process of step S4, a step surface (step side surface, step portion) DS1 is formed at the boundary between the central portion CT and the peripheral portion PR of the semiconductor substrate SB, and the thickness T2 of the central portion CT of the semiconductor substrate SB becomes thinner than the thickness T1 of the peripheral portion PR of the semiconductor substrate SB.

[0041] As described above, when the rough grinding process and the subsequent finish grinding process are performed in the back grinding process of step S4, a small step portion DS2 connected to the step surface DS1 is also formed at the boundary between the central portion CT and the peripheral portion PR, as shown in FIG. 7. The height difference between the step portion DS2 and the central portion CT is smaller than the height difference between the peripheral portion PR and the central portion CT and is also smaller than the thickness of the central portion CT. The height difference between the step portion DS2 and the central portion CT corresponds to the difference between the thickness T3 of the step portion DS2 and the thickness T2 of the central portion CT. The thickness T3 of the step portion DS2 is, for example, approximately 100 micrometers or more and 250 micrometers or less. The height difference of the step portion DS2 is, for example, approximately 50 micrometers or more and 100 micrometers or less.

[0042] The step surface DS1 and the step portion DS2 are located at the boundary (between) the central portion CT and the peripheral portion PR, and the back surface of the peripheral portion PR is continuous with the step surface DS1, and the back surface of the central portion CT is continuous with the step portion DS2. The step portion DS2 is interposed between the step surface DS1 and the back surface of the central portion CT. In other words, the step portion DS2 exists below the step surface DS1.

[0043] Thereafter, the wafer WF is subjected to a cleaning process to remove grinding debris and grinding fluid adhering to the wafer WF. At this time, the backgrind tape BT is peeled off from the wafer WF, and the surface of the wafer WF is also cleaned.

[0044] In this manner, the back grinding step of step S4 is carried out.

[0045] Unlike the present embodiment, if the entire semiconductor substrate SB is uniformly thin, warping of the wafer WF is likely to occur when the backgrinding tape BT is peeled off from the wafer WF. However, in the present embodiment, as shown in Figures 5 to 7, a peripheral portion PR that is thicker than the central portion CT exists around the central portion CT where the multiple chip regions 1A are arranged. Therefore, even when the backgrinding tape BT is peeled off from the wafer WF, warping of the wafer WF can be prevented.

[0046] Furthermore, from the viewpoint of suppressing warpage of the wafer WF, it is desirable that the thickness T1 of the peripheral portion PR be large. On the other hand, while increasing the width W1 of the peripheral portion PR can also suppress warpage of the wafer WF, increasing the width W1 of the peripheral portion PR reduces the number of semiconductor chips that can be obtained from one wafer WF. For this reason, in order to suppress warpage of the wafer WF, it is preferable to increase the thickness T1 of the peripheral portion PR rather than increasing the width W1 of the peripheral portion PR. Therefore, from the viewpoint of increasing the number of semiconductor chips that can be obtained from one wafer WF and improving manufacturing efficiency, it is preferable that the thickness T1 of the peripheral portion PR be at least twice the thickness T2 of the central portion CT. Furthermore, when the thickness T2 of the central portion CT is 100 micrometers or less, it is even more preferable that the thickness T1 of the peripheral portion PR be at least five times the thickness T2 of the central portion CT.

[0047] <Back metal film formation process> Next, as shown in FIGS. 9 to 11, a metal film ME is formed on the back surface of the wafer WF (back surface SB2 of the semiconductor substrate SB) (step S5 in FIG. 1). FIG. 9 is a cross-sectional view of the wafer after the back surface metal film formation process of step S5 has been performed, and shows a cross section corresponding to FIG. 6 above. FIG. 10 is a cross-sectional view of the vicinity of the edge of the semiconductor substrate SB after the back surface metal film formation process of step S5 has been performed, and shows a cross section corresponding to FIG. 7 above. The wiring structure WR is not shown in FIG. 10. FIG. 11 is a partially enlarged cross-sectional view showing an enlarged view of the back surface layer portion of the semiconductor substrate SB and the metal film ME formed thereon.

[0048] A metal film (back surface metal film, metal layer) ME is formed on almost the entire back surface (back surface SB2 of semiconductor substrate SB) of wafer WF. There may be cases where the metal film ME is not formed on the step surface DS1, but in any case, the metal film ME is formed on the entire back surface of the central portion CT of semiconductor substrate SB. The metal film ME is also formed on the back surface of peripheral portion PR, but it is not essential that the metal film ME be formed on the back surface of peripheral portion PR.

[0049] By forming the metal film ME on the back surface of the wafer WF in step S5, the semiconductor chips obtained after the dicing step described below have back electrodes made of the metal film ME.

[0050] The inventors of the present application are considering using a silver (Ag) film instead of a gold (Au) film as the back electrode of a semiconductor chip. If a silver (Ag) film is used instead of a gold (Au) film as the back electrode of a semiconductor chip, the manufacturing cost of the semiconductor chip can be reduced.

[0051] The semiconductor chip obtained after the dicing process described below has a back electrode made of a metal film ME. Therefore, in this embodiment, the metal film ME does not include a gold (Au) film but includes a silver (Ag) film.

[0052] Specifically, the metal film ME is composed of a laminated film of multiple metal films, and includes a silver (Ag) film as the uppermost layer. The layer of the metal film ME that contacts the back surface SB2 of the semiconductor substrate SB is the lowermost layer of the metal film ME, and the layer of the metal film ME that is farthest from the back surface SB2 of the semiconductor substrate SB is the uppermost layer of the metal film ME, which in this embodiment is made of silver (Ag). In other words, the silver (Ag) film ME3 included in the metal film ME forms the surface (exposed surface) of the metal film ME.

[0053] For example, as shown in FIG. 11, the metal film ME is a laminated film including a titanium (Ti) film ME1 formed on the back surface SB2 of the semiconductor substrate SB so as to be in contact with the back surface SB2 of the semiconductor substrate SB, a nickel (Ni) film ME2 formed on the titanium film ME1, and a silver (Ag) film ME3 formed on the nickel film ME2. The titanium film ME1 and the nickel film ME2 are interposed between the back surface SB2 of the semiconductor substrate SB and the silver (Ag) film ME3. The titanium film ME1 is interposed between the back surface SB2 of the semiconductor substrate SB and the nickel film ME2, and the nickel film ME2 is interposed between the titanium film ME1 and the silver (Ag) film ME3. The metal film ME can be formed, for example, by a sputtering method. When the metal film ME is formed by a sputtering method, the metal film ME is hardly formed on the step surface DS1 as shown in FIG. 10. In this case, the metal film ME on the back surface of the central portion CT and the metal film on the back surface of the peripheral portion PR are not connected to each other.

[0054] Furthermore, after forming the metal film ME in step S5, the surface of the metal film ME (the surface of the silver film ME3) can be roughened, which can improve the adhesion between the metal film ME and the dicing tape DT in the dicing tape attachment process in step S6 described later.

[0055] Hereinafter, the wafer WF and the metal film ME formed on the back surface of the wafer WF are collectively referred to as the wafer (semiconductor wafer) WF1. That is, the semiconductor substrate SB, the wiring structure WR on the front surface SB1 of the semiconductor substrate SB, and the metal film ME on the back surface SB2 of the semiconductor substrate SB are collectively referred to as the wafer WF1. The back surface of the wafer WF1 corresponds to the surface of the metal film ME formed on the back surface SB2 of the semiconductor substrate SB. The front surface of the wafer WF1 corresponds to the surface of the wiring structure WR on the front surface SB1 of the semiconductor substrate SB. The front surface of the wafer WF1 and the back surface of the wafer WF1 are located on opposite sides of each other. The surface of the metal film ME corresponds to the surface (main surface) opposite to the surface in contact with the back surface SB2 of the semiconductor substrate SB.

[0056] In the following description, the entire combination of the peripheral portion PR of the semiconductor substrate SB, the wiring structure WR on the surface of the peripheral portion PR, and the metal film ME on the back surface of the peripheral portion PR will be referred to as the peripheral portion PR1. The back surface of the peripheral portion PR1 corresponds to the surface of the metal film ME on the back surface of the peripheral portion PR of the semiconductor substrate SB.

[0057] In the following description, the central portion CT of the semiconductor substrate SB, the wiring structure WR on the central portion CT, and the metal film ME on the back surface of the central portion CT will be referred to as the central portion CT1. The back surface of the central portion CT1 corresponds to the surface of the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB. In a plan view, the boundary between the central portion CT1 and the peripheral portion PR1 coincides with the boundary between the central portion CT and the peripheral portion PR.

[0058] <Dicing tape application process> 12 to 15, a dicing tape (protective tape) DT is attached to the back surface of the wafer WF1 (step S6 in FIG. 1). In other words, in step S6, the dicing tape DT is attached to the back surface SB2 of the semiconductor substrate SB via the metal film ME.

[0059] FIG. 12 is a plan view showing a wafer that has undergone the dicing tape application step of step S6. In FIG. 12, the boundary between the central portion CT1 and the peripheral portion PR1 of the wafer WF1 is indicated by a dotted line. FIG. 13 is a cross-sectional view taken along line A1-A1 in FIG. 12. In FIG. 13, the wafer WF1 is shown with its back surface facing upward. FIG. 14 is a cross-sectional view of the vicinity of the edge of the semiconductor substrate SB that has undergone the dicing tape application step of step S6, and shows a cross-section corresponding to FIG. 10 above. In FIG. 14, the wiring structure WR is omitted. FIG. 15 is a partially enlarged cross-sectional view showing the back surface layer of the semiconductor substrate SB, the metal film ME formed thereon, and the dicing tape DT formed thereon.

[0060] As shown in FIG. 15, the dicing tape DT has a base layer (base layer) BS and an adhesive layer (bonding layer) NL formed on one main surface of the base layer BS. That is, the dicing tape DT has a laminated structure of the base layer BS and the adhesive layer NL. In this embodiment, the base layer BS is made of polyvinyl chloride (PVC). The adhesive layer NL is made of acrylic resin. The thickness of the base layer BS is preferably 70 micrometers or more and 100 micrometers or less. The thickness of the adhesive layer NL is preferably 5 micrometers or more and 10 micrometers or less. The dicing tape DT is attached to the back surface (surface of the metal film ME) of the wafer WF1 so that the adhesive layer NL of the dicing tape DT faces (contacts) the back surface (surface of the metal film ME) of the wafer WF1.

[0061] A specific example of the dicing tape application process in step S6 will be described below with reference to FIGS. 16 to 18. FIGS. 16 and 18 are explanatory views of the dicing tape application process. FIG. 17 is a partially enlarged cross-sectional view of a portion of FIG. 16, showing a cross section corresponding to FIG. 14. In FIG. 17, the wiring structure WR and the stage STG1 are not shown.

[0062] First, the wafer WF1 is placed in a vacuum vessel (vacuum chamber) VC (wafer WF1 placement process). The vacuum vessel VC has a stage STG1 and a vessel part CB placed on the stage STG1. The wafer WF1 is placed on the stage STG1 so that the surface of the wafer WF1 (the surface of the wiring structure WR) faces the upper surface of the stage STG1. The back surface of the wafer WF1 placed on the stage STG1 faces upward. The wafer WF1 placed on the stage STG1 is covered by the vessel part CB, but the wafer WF1 is separated from the inner surface of the vessel part CB. The wafer WF1 is placed in the space surrounded by the stage STG1 and the vessel part CB.

[0063] Next, with the wafer WF1 placed in the vacuum container VC, the vacuum container VC is depressurized (depressurization step). This depressurization step can be performed by evacuating the vacuum container VC with an exhaust vacuum pump (not shown). This puts the vacuum container VC into a depressurized state (vacuum state).

[0064] 16, the dicing tape DT is placed on the back surface of the wafer WF1 placed on the stage STG1 (dicing tape DT placement process). At this time, the dicing tape DT is placed on the back surface of the wafer WF1 so that the adhesive layer NL (see FIG. 15) of the dicing tape DT faces the back surface of the wafer WF1 (the surface of the metal film ME). To make the dicing tape DT easier to handle, the outer periphery of the dicing tape DT can be held by a ring-shaped support member (not shown), and the dicing tape DT held by the support member can be placed on the back surface of the wafer WF1.

[0065] As shown in Figures 16 and 17, when the dicing tape DT is placed on the backside of the wafer WF1, the dicing tape DT contacts the backside of the wafer WF1 at the peripheral portion PR1, but does not contact the backside of the wafer WF1 at the central portion CT1, and the backside of the wafer WF1 is separated from the dicing tape DT. That is, the dicing tape DT contacts the backside of the peripheral portion PR1 (the surface of the metal film ME on the backside of the peripheral portion PR), but does not contact the backside of the central portion CT1 (the surface of the metal film ME on the backside of the central portion CT), and is separated from the backside of the central portion CT1. Therefore, the step surface DS1 and the step portion DS2 are not in contact with the dicing tape DT. Between the backside of the wafer WF1 and the dicing tape DT, there is a space SP1 surrounded by the backside of the central portion CT1 (the surface of the metal film ME on the backside of the central portion CT), the step surface DS1, the surface of the metal film ME on the step portion DS2, and the dicing tape DT.

[0066] The dicing tape DT placement process is performed in a reduced pressure state (vacuum state) inside the vacuum container VC, so the space SP1 is also in a reduced pressure state (vacuum state). At this stage, the pressure inside the space SP1 is the same as the pressure around the wafer WF1 on which the dicing tape DT is placed (space SP2).

[0067] Next, the vacuum container VC is opened to the atmosphere (atmospheric release step). Figure 18 shows the state after the atmospheric release step has been performed. This atmospheric release step can be performed by stopping the exhaust from the vacuum container VC by the exhaust vacuum pump (not shown) and opening a valve (not shown) connected to the opening of the vacuum container VC to introduce atmospheric air into the vacuum container VC from outside the vacuum container VC. As a result, the inside of the vacuum container VC becomes atmospheric pressure, and the area around the wafer WF1 on which the dicing tape DT is placed (space SP2) quickly becomes atmospheric pressure. However, the space SP1 does not easily transition to atmospheric pressure and tends to maintain a reduced pressure state. This is because the back surface of the peripheral portion PR1 (the surface of the metal film ME on the back surface of the peripheral portion PR) is in contact with the dicing tape DT, so the space SP1 is close to a closed space. Therefore, when atmospheric air flows into the vacuum container VC, it is difficult for the air to flow into the space SP1.

[0068] When the atmosphere release step is performed, the dicing tape DT is deformed due to the pressure difference between the inside of the vacuum container VC (atmospheric pressure state) and the inside of the space SP1 (reduced pressure state), and the space SP1 is compressed (reduced). That is, when the atmosphere release step is performed, the pressure around the wafer WF1 on which the dicing tape DT is placed (space SP2) becomes greater than the pressure in space SP1, and due to the difference in pressure between space SP2 and space SP1, a force in the direction of arrow YG shown in Figure 18 (a force that presses the dicing tape DT toward the wafer WF1) is applied to the dicing tape DT. As a result, as shown in Figure 18, the dicing tape DT deforms to fit the shape of the back surface of the wafer WF1, and the dicing tape DT comes into close contact with the entire back surface of the wafer WF1. Specifically, the dicing tape DT adheres to the back surface of the peripheral portion PR1 (the surface of the metal film ME on the back surface of the peripheral portion PR), the step surface DS1, the metal film ME on the step portion DS2, and the back surface of the central portion CT1 (the surface of the metal film ME on the back surface of the central portion CT) (see FIGS. 14 and 18). In other words, the dicing tape DT adheres to the surface of the metal film ME on the back surface of the peripheral portion PR, the surface of the metal film ME on the back surface of the central portion CT, the step surface DS1, and the surface of the metal film ME on the step portion DS2 (see FIGS. 14 and 18). This allows the dicing tape DT to be attached to the entire back surface of the wafer WF1 so that no gap is created between the back surface of the wafer WF1 and the tape DT.

[0069] Thereafter, the wafer WF1 with the dicing tape DT attached thereto is taken out from the vacuum vessel VC.

[0070] <Peripheral separation process> Next, the wafer WF1 is cut along the boundary between the central portion CT (CT1) and the peripheral portion PR (PR1), thereby separating the central portion CT1 from the peripheral portion PR1 (step S7 in FIG. 1).

[0071] A specific example of the peripheral edge separation process of step S7 will be described below with reference to FIGS. 19 to 22. FIGS. 19 and 21 are explanatory views of the peripheral edge separation process. FIG. 20 is a partially enlarged cross-sectional view of a portion of FIG. 19, showing a cross section corresponding to FIG. 14. The wiring structure WR and stage STG2 are omitted from FIG. 20. FIG. 22 is a plan view of the wafer WF1 at the stage where the peripheral edge separation process of step S7 has been completed. In FIG. 22, multiple chip regions 1A on the wafer WF1 are indicated by dotted lines.

[0072] 19, the wafer WF1 with the dicing tape DT attached thereto is placed on the stage STG2 of the cutting device. At this time, the wafer WF1 with the dicing tape DT attached thereto is placed on the stage STG2 so that the front surface of the wafer WF1 faces upward and the dicing tape DT is in contact with the upper surface of the stage STG2. The upper surface of the stage STG2 has a shape that matches the rear surface of the wafer WF1 and has a step at a position corresponding to the step surface DS1.

[0073] 19 and 20, the blade (cutting blade) BR1 of the cutting device cuts the wafer WF1 from the front surface side of the wafer WF1 along the boundary between the central portion CT (CT1) and the peripheral portion PR (PR1) (cutting process). In this cutting process, the wafer WF1 is cut so that the cutting line traces a circular orbit. In addition, in this cutting process, it is preferable to cut the wafer WF1 slightly inside the boundary between the central portion CT (CT1) and the peripheral portion PR (PR1). In a plan view, the side closer to the center of the central portion CT (CT1) corresponds to the inside, and the side farther from the center of the central portion CT (CT1) corresponds to the outside.

[0074] The rotating blade BR1 cuts the wafer WF1, separating the central portion CT1 and the peripheral portion PR1, but the dicing tape DT is not completely cut. Therefore, the dicing tape DT located below the central portion CT1 and the dicing tape DT located below the peripheral portion PR1 remain connected together even after the cutting process.

[0075] Next, as shown in Fig. 21, the peripheral edge portion PR1 is separated from the dicing tape DT. For example, the peripheral edge portion PR1 can be separated from the dicing tape DT by peeling it off from the dicing tape DT using a pickup tool (not shown).

[0076] Because the peripheral portion PR1 was separated from the central portion CT1 in the cutting process described above, the central portion CT remains attached to the dicing tape DT even after the peripheral portion PR1 is separated from the dicing tape DT, which allows the peripheral portion PR1 to be selectively separated from the dicing tape DT.

[0077] Furthermore, by cutting the wafer WF1 slightly inside the boundary between the central portion CT1 and the peripheral portion PR1 during the cutting process, when the peripheral portion PR1 is separated from the dicing tape DT, a portion (outer periphery) of the central portion CT1 can also be separated from the dicing tape DT together with the peripheral portion PR1.

[0078] In this way, in step S7, the peripheral portion PR1 can be separated from the central portion CT1 and the dicing tape DT.

[0079] After the peripheral edge separation process of step S7 is completed, as shown in Figure 22, the central portion CT1 of the wafer WF1 is attached to the dicing tape DT, but the peripheral edge portion PR1 is not present on the dicing tape DT. Therefore, before the peripheral edge separation process of step S7 is performed, the wafer WF1 integrally has the peripheral edge portion PR1 and the central portion CT1, but after the peripheral edge separation process of step S7 is completed, the wafer WF1 does not have the peripheral edge portion PR1 and is composed only of the central portion CT1. The central portion CT1 has multiple chip regions 1A.

[0080] <Dicing process> Next, the wafer WF1 (center portion CT1) attached to the dicing tape DT is diced (cut) (step S8 in FIG. 1).

[0081] A specific example of the dicing process in step S8 will be described below with reference to FIGS. 23 to 25. FIGS. 23 and 24 are explanatory views of the dicing process in step S8. FIG. 25 is a plan view of the wafer WF1 at the stage after the dicing process in step S8 has been completed. FIG. 26 is a cross-sectional view taken along line A1-A1 in FIG. 25.

[0082] First, as shown in Fig. 23, the wafer WF1 to which the dicing tape DT is attached is placed on the stage STG3 of the dicing device. At this time, the wafer WF1 to which the dicing tape DT is attached is placed on the stage STG3 so that the surface of the wafer WF1 faces upward and the dicing tape DT faces (contacts) the upper surface of the stage STG3.

[0083] 24 and 25, the wafer WF1 is cut from the front surface side of the wafer WF1 along the scribe area 1B (see FIG. 2) by a rotating blade (cutting blade) BR2 of a dicing device. As a result, the wafer WF1 is separated and singulated into a plurality of semiconductor chips CP. Each singulated chip area 1A corresponds to a semiconductor chip CP.

[0084] Each semiconductor chip CP is composed of a chip area 1A of the semiconductor substrate SB, a wiring structure WR on the chip area 1A, and a metal film ME on the back surface of the chip area 1A. The cut surface of the wafer WF1 in the dicing process corresponds to the side surface of each semiconductor chip CP. The metal film ME of each semiconductor chip CP functions as a back electrode of the semiconductor chip CP.

[0085] The rotating blade BR2 cuts the wafer WF1 and separates it into multiple semiconductor chips CP, but the dicing tape DT is not completely cut, so the dicing tapes DT located under each semiconductor chip CP remain connected together even after the dicing process.

[0086] Therefore, before the dicing process of step S8 is performed, one wafer WF1 (center portion CT1) is attached to one dicing tape DT, but after the dicing process of step S8 is completed, the diced wafer WF1 is attached to one dicing tape DT, that is, multiple semiconductor chips CP are attached to one dicing tape DT. The diced wafer WF1 is an aggregate of multiple semiconductor chips CP.

[0087] Hereinafter, the dicing tape DT and the plurality of semiconductor chips CP (diced wafer WF1) attached to the dicing tape DT will be referred to as a structure KB.

[0088] <Storage process> Next, the structure KB shown in FIGS. 25 and 26 is stored (step S9 in FIG. 1) until the transport step of step S10, which will be described later, is carried out.

[0089] <Transportation (shipping) process> Next, the structure KB is transported (shipped) to a customer or the like (step S10 in FIG. 1). If the structure KB is transported to a customer in step S10, the assembly process in step S12, which will be described later, is carried out at the customer's factory or the like. If the assembly process in step S12, which will be described later, is carried out at another factory of the same company, the structure KB is transported to the other factory of the same company in step S10.

[0090] <Storage process> The structure KB transported in the transport step of step S10 is stored until the assembly step of step S12, which will be described later, is carried out (step S11 in FIG. 1).

[0091] <Semiconductor device assembly process> Using the semiconductor chip CP obtained from the structure KB, a semiconductor device (semiconductor package) is assembled (step S12 in FIG. 1).

[0092] FIG. 27 is a cross-sectional view showing an example of a semiconductor device (semiconductor package) PKG assembled using semiconductor chips CP obtained from the structure KB.

[0093] The semiconductor device PKG shown in Figure 27 has a die pad (chip mounting portion) DP, a semiconductor chip CP mounted on the die pad DP via a conductive bonding material BD1 such as solder, leads LD, bonding wires BW, a metal plate MP, and a sealing portion MR that seals these.

[0094] As described above, the semiconductor chip CP comprises a semiconductor substrate SB, a wiring structure WR formed on the front surface of the semiconductor substrate SB, and a metal film ME formed on the lower surface of the semiconductor substrate SB. The back surface of the semiconductor chip CP is formed by the front surface of the metal film ME, which functions as a back electrode of the semiconductor chip CP. The wiring structure WR of the semiconductor chip CP has multiple pads (bonding pads) PD. In the case of FIG. 27, a trench-gate MISFET or LDMOSFET is formed on the main surface of the semiconductor substrate SB of the semiconductor chip CP or in the semiconductor substrate SB, and the multiple pads PD of the semiconductor chip CP include a gate pad PDG and a source pad PDS. The gate pad PDG is electrically connected to the gate electrode of the trench-gate MISFET or LDMOSFET via wiring in the wiring structure WR. The source pad PDS is electrically connected to the source region of the trench-gate MISFET or LDMOSFET via wiring in the wiring structure WR. The metal film ME is electrically connected to the drain region of the trench-gate MISFET or LDMOSFET and can function as a back electrode for the drain.

[0095] The semiconductor chip CP is mounted on the die pad DP via a conductive bonding material BD1 such as solder, with the metal film ME facing the die pad DP. Therefore, the metal film ME of the semiconductor chip CP is electrically connected to the die pad DP via the conductive bonding material BD1.

[0096] The gate pad PDG of the semiconductor chip CP is electrically connected to the lead LD via a bonding wire BW. The die pad DP and the lead LD are made of a metal material, for example, copper (Cu) or a copper alloy. A part of the lead LD is exposed from the encapsulation portion MR and can function as an external terminal (external terminal for gate). The back surface of the die pad DP is exposed from the back surface of the encapsulation portion MR and can function as an external terminal (external terminal for drain).

[0097] One end of the metal plate MP is electrically connected to the source pad PDS of the semiconductor chip CP via a conductive bonding material BD2 such as solder. The other end of the metal plate MP protrudes from the sealing portion MR, and this protrusion can function as a source external terminal. The other end of the metal plate MP can also be electrically connected to a source lead via a conductive bonding material, in which case the source lead functions as a source external terminal.

[0098] The sealing portion MR is made of a resin material and may contain a filler or the like.

[0099] Next, an example of the assembly process (step S12 in FIG. 1) of the semiconductor device PKG shown in FIG. 27 will be described.

[0100] To manufacture the semiconductor device PKG, a lead frame having a die pad DP and leads LD is prepared.

[0101] Next, the semiconductor chip CP is obtained from the structure KB, and the obtained semiconductor chip CP is placed on the die pad DP of the lead frame via the conductive bonding material BD1. At this time, the semiconductor chip CP is placed on the die pad DP via the conductive bonding material BD1, with the metal film ME of the semiconductor chip CP facing the die pad DP. Thereafter, the bonding material BD1 is hardened. In this manner, the die bonding process is performed.

[0102] FIG. 28 is an explanatory diagram of a pickup process for obtaining semiconductor chips CP from a structure KB. As described above, in the structure KB, multiple semiconductor chips CP are attached to a single dicing tape DT. For example, after ultraviolet light is irradiated onto the adhesive layer NL of the dicing tape DT of the structure KB, the structure KB is placed on a stage STG4 as shown in FIG. 28. Thereafter, as shown in FIG. 28, the semiconductor chips CP are peeled off from the dicing tape DT and picked up using a pickup jig (not shown) such as a collet. The picked-up semiconductor chips CP are then placed on a die pad DP of a lead frame via a conductive bonding material BD1 as described above.

[0103] After the die bonding process, a metal plate connecting process and a wire bonding process are performed. In the metal plate connecting process, one end of the metal plate MP is electrically connected to the source pad PDS of the semiconductor chip CP via a conductive bonding material BD2 such as solder. In the wire bonding process, the gate pad PDG of the semiconductor chip CP is electrically connected to the lead LD via a bonding wire BW. Either the metal plate connecting process or the wire bonding process may be performed first.

[0104] After the metal plate connecting step and the wire bonding step, a sealing portion forming step is carried out to form the sealing portion MR.

[0105] After the sealing part formation process, a lead frame cutting process is performed to separate the leads LD and die pad DP from the lead frame. Thereafter, if necessary, processes such as bending the leads LD and plating the exposed parts of the leads LD and die pad DP are performed.

[0106] In this manner, the semiconductor device PKG can be assembled.

[0107] <Background of the review> As described above, the inventors of the present application have been considering using a silver (Ag) film instead of a gold (Au) film as the back electrode of a semiconductor chip. Therefore, they have been considering forming a metal film containing a silver (Ag) film when forming a back metal film on the back surface of a semiconductor substrate. Using a silver (Ag) film instead of a gold (Au) film can reduce the manufacturing cost of semiconductor chips. However, a silver (Ag) film is more susceptible to oxidation than a gold (Au) film. If the silver film constituting the back electrode is oxidized, there is a risk that the performance and reliability of a semiconductor device assembled using a semiconductor chip having an oxidized back electrode will be reduced. For this reason, the following two countermeasures have been taken.

[0108] As a first measure, a semiconductor wafer with a metal film formed on its backside is diced to obtain multiple semiconductor chips, and then the obtained multiple semiconductor chips are stored in a chip tray or carrier tape, and the chip tray or carrier tape containing the multiple semiconductor chips is vacuum-packed in an aluminum bag for transportation (shipment). Vacuum packaging in an aluminum bag prevents oxidation of the silver film contained in the backside metal film.

[0109] As a second measure, semiconductor wafers with a metal film formed on the backside are stored in wafer cassettes without dicing, and the wafer cassettes containing the semiconductor wafers are vacuum-packed in aluminum bags before being transported (shipped). Vacuum packing in aluminum bags prevents oxidation of the silver film contained in the backside metal film.

[0110] However, when the first measure is taken, it is necessary to extract multiple semiconductor chips from the diced semiconductor wafer and store the multiple semiconductor chips in a chip tray or carrier tape, which is a time-consuming process and may increase costs.

[0111] Furthermore, when the first measure is taken, it is necessary to prepare in advance a dedicated device (for example, a die bonding device compatible with chip trays or carrier tapes) at the transport destination (shipping destination) of the chip tray or carrier tape containing multiple semiconductor chips. Also, when the second measure is taken, it is necessary to prepare in advance a dedicated device (for example, a dicing device) at the transport destination (shipping destination) of the wafer cassette containing semiconductor wafers.

[0112] Furthermore, when the first measure and the second measure are taken, the cost of packaging materials such as aluminum bags is high, which may increase costs.

[0113] For this reason, in recent years, there has been an increasing need (customer demand) to transport (ship) the diced semiconductor wafer to a customer, etc., in a state where the diced semiconductor wafer is adhered and fixed to a dicing tape after the dicing process has been performed. This allows the semiconductor chips to be picked up from the diced semiconductor wafer adhered to the dicing tape at the transport destination (shipping destination) of the diced semiconductor wafer, and to be used promptly in the die bonding process.

[0114] However, it is difficult to vacuum-pack dicing tape with diced semiconductor wafers in aluminum bags. Furthermore, as mentioned above, silver (Ag) films are more susceptible to oxidation than gold (Au) films. Therefore, when transporting dicing tape with diced semiconductor wafers, new measures are needed to prevent oxidation of the silver film contained in the metal film on the backside of the semiconductor wafer.

[0115] <Main features and effects> In this embodiment, in step S4, the back surface SB2 of the semiconductor substrate (semiconductor wafer) SB is ground so that the thickness of the central portion CT of the semiconductor substrate SB is smaller than the thickness of the peripheral portion PR surrounding the central portion CT of the semiconductor substrate SB. Then, in step S5, a metal film ME including a silver film ME3 is formed on the back surface SB2 of the semiconductor substrate SB, and then, in step S6, a dicing tape DT is attached to the metal film ME on the back surface SB2 of the semiconductor substrate SB. Then, in step S7, the semiconductor substrate SB (wafer WF1) is cut to separate the peripheral portion PR (PR1) from the central portion CT (CT1) and the dicing tape DT. Then, in step S8, the semiconductor substrate SB (wafer WF1) attached to the dicing tape DT is diced. Then, in step S10, the semiconductor substrate SB (wafer WF1) attached to the dicing tape DT and diced is transported to a customer or the like. That is, the above-mentioned structure KB is transported to a customer or the like in step S10.

[0116] After the dicing step of step S8, in the storage step of step S9, the transport step of step S10, and the storage step of step S11, it is effective to increase the degree of adhesion between the dicing tape DT and the metal film ME to prevent oxidation of the silver film ME3 contained in the metal film ME. If the degree of adhesion between the dicing tape DT and the metal film ME is high, air is less likely to exist between the metal film ME and the dicing tape DT, and the metal film ME is less likely to be exposed to air, preventing oxidation of the metal film ME and therefore preventing oxidation of the silver film ME3 contained in the metal film ME.

[0117] In this embodiment, in step S4, the back surface SB2 of the semiconductor substrate SB is ground so that the thickness of the central portion CT of the semiconductor substrate SB is smaller than the thickness of the peripheral portion PR of the semiconductor substrate SB. This improves the handleability of the wafer WF after the back surface grinding process in step S4, suppresses or prevents warpage of the wafer WF, and reduces the thickness of the semiconductor chips CP obtained after the dicing process.

[0118] However, if the back surface SB2 of the semiconductor substrate SB is ground so that the thickness of the central portion CT of the semiconductor substrate SB is smaller than the thickness of the peripheral portion PR, it is difficult to increase the degree of adhesion between the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB and the dicing tape DT in the dicing tape application process unless some kind of ingenuity is implemented. This is because a step is formed at the boundary between the central portion CT and the peripheral portion PR on the back surface of the semiconductor substrate SB, and a gap is likely to occur between the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB and the dicing tape DT. If the degree of adhesion between the dicing tape DT and the metal film ME is low and a gap occurs between the dicing tape DT and the metal film ME, air will be present between the metal film ME and the dicing tape DT, and the metal film ME will be prone to oxidation.

[0119] Therefore, in this embodiment, a dicing tape DT having a base layer BS made of polyvinyl chloride is used. A soft polyvinyl chloride is preferably used as the polyvinyl chloride for the base layer BS. This allows the dicing tape DT to be adhered to the entire back surface of the wafer WF1 in the dicing tape application process of step S6, thereby increasing the degree of adhesion between the dicing tape DT and the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB. This will be explained in more detail below.

[0120] As described above, the dicing tape application process of step S6 includes the steps of placing the wafer WF1 in a vacuum container VC, reducing the pressure inside the vacuum container VC, placing the dicing tape DT on the wafer WF1, and opening the vacuum container VC to the atmosphere. The dicing tape DT placed on the wafer WF1 is separated from the metal film ME on the central portion CT of the semiconductor substrate SB until the vacuum container VC is opened to the atmosphere. After that, by opening the vacuum container VC to the atmosphere, the dicing tape DT is pressed toward the wafer WF1 due to the difference in air pressure between the dicing tape DT and the wafer WF1 and the air pressure around the wafer WF1. As a result, the dicing tape DT deforms to fit the back surface of the wafer WF1, and the dicing tape DT is applied to the entire back surface of the wafer WF1. This causes the dicing tape DT to come into contact with and adhere to the metal film ME on the back surface of the central portion of the semiconductor substrate SB.

[0121] Unlike the present embodiment, if a polyolefin film is used as the base layer BS of the dicing tape DT, when the vacuum container VC is opened to the atmosphere, the dicing tape DT will not be able to deform to the shape of the back surface of the wafer WF1, even if it tries to deform to fit the back surface of the wafer WF1, and a gap will likely form between the dicing tape DT and the back surface of the wafer WF1. This is because the polyolefin film has lower elasticity than, for example, a polyvinyl chloride film. Therefore, when a polyolefin film is used as the base layer BS of the dicing tape DT, not only is a gap likely to form between the dicing tape DT and the wafer WF1, but this gap will also likely widen.

[0122] In contrast, in this embodiment, a polyvinyl chloride film is used as the base layer BS of the dicing tape DT, and therefore the base layer BS is more easily deformed than when a polyolefin film is used as the base layer BS. From another perspective, a polyvinyl chloride film has higher elasticity than a polyolefin film. Therefore, in this embodiment, when the vacuum chamber VC is opened to the atmosphere, the dicing tape DT is more likely to deform to conform to the shape of the back surface of the wafer WF1. Therefore, the dicing tape DT comes into contact with and adheres to the entire back surface of the wafer WF1, compared to when a polyolefin film is used, thereby preventing a gap from forming between the dicing tape DT and the back surface of the wafer WF1. Even if a small gap does form between the dicing tape DT and the wafer WF1, the high elasticity of the polyvinyl chloride film prevents the gap from widening, compared to when a polyolefin film is used. Therefore, the dicing tape DT can be adhered to the entire back surface of the wafer WF1, thereby improving the adhesion between the dicing tape DT and the metal film ME on the back surface of the central portion CT of the semiconductor substrate SB. As a result, air is less likely to exist between the metal film ME and the dicing tape DT, which prevents oxidation of the silver film ME3 contained in the metal film ME during the storage step S9, the transport step S10, and the storage step S11 after the dicing step S8. It is also possible to prevent sulfurization of the silver film ME3 contained in the metal film ME during the storage step S9, the transport step S10, and the storage step S11 after the dicing step S8.

[0123] Silver films discolor when oxidized or sulfurized. The inventors confirmed that when the above structure KB was left in the atmosphere for a long period of time (for example, about 8 months), and then a semiconductor chip was removed from the structure KB and the metal film ME was observed, the silver film ME3 contained in the metal film ME did not discolor, and that there was almost no oxidation or sulfurization of the silver film ME3 contained in the metal film ME.

[0124] Therefore, even if the structure KB is left in the atmosphere for a long time in the storage step S9 after the dicing step, the transport step S10, and the storage step S11, the silver film ME3 contained in the metal film ME can be prevented from being oxidized and sulfurized, thereby improving the performance and reliability of the semiconductor device manufactured using the semiconductor chip CP.

[0125] In addition, in the assembly process of step S12, once the semiconductor chip CP is obtained from the structure KB as shown in Fig. 28, the die bonding process (placement of the semiconductor chip CP on the die pad DP) can be performed quickly (for example, within 5 minutes) using the obtained semiconductor chip CP. This makes it possible to prevent the silver film ME3 included in the metal film ME of the semiconductor chip CP picked up from the structure KB from being oxidized before the die bonding process.

[0126] Furthermore, in this embodiment, since oxidation and sulfurization of the silver film ME3 contained in the metal film ME can be prevented in the structure KB, the time required for each of the storage step S9, the transport step S10, and the storage step S11 can be set as needed without worrying about oxidation of the silver film ME3 contained in the metal film ME. Therefore, after the dicing step S8, the transport step S10 and the assembly step S12 can be performed at the desired timing.

[0127] Furthermore, it is preferable that the surface of the metal film ME, i.e., the surface of the silver film ME3, be roughened. This roughening is performed after the metal film ME is formed in step S5 and before the dicing tape application step in step S6. By roughening the surface of the metal film ME, the degree of adhesion between the metal film ME and the dicing tape DT can be further increased in the dicing tape application step in step S6. This further prevents oxidation and sulfurization of the silver film contained in the metal film ME during the storage step in step S9, the transport step in step S10, and the storage step in step S11 after the dicing step in step S8.

[0128] Furthermore, as described above, by grinding the back surface SB2 of the semiconductor substrate SB in step S4, a step (step surface DS1) is formed on the back surface SB2 of the semiconductor substrate SB at the boundary between the central portion CT and the peripheral portion PR.

[0129] In step S4, a plurality of steps may be formed on the back surface SB2 of the semiconductor substrate SB at the boundary between the central portion CT and the peripheral portion PR. In the case of Fig. 7, two steps (step surface DS1 and step portion DS2) are formed on the back surface SB2 of the semiconductor substrate SB at the boundary between the central portion CT and the peripheral portion PR.

[0130] When there is more than one step at the boundary between the central portion CT and the peripheral portion PR, a gap is more likely to form between the backside of the wafer WF1 and the dicing tape DT during the dicing tape application process of step S6. In contrast, in this embodiment, the dicing tape DT is made of polyvinyl chloride. This allows the dicing tape DT to adhere to the entire backside of the wafer WF1, preventing a gap from forming between the backside of the wafer WF1 and the dicing tape DT, not only when there is one step at the boundary between the central portion CT and the peripheral portion PR but also when there are multiple steps at the boundary between the central portion CT and the peripheral portion PR. This prevents oxidation and sulfurization of the silver film contained in the metal film ME during the storage process of step S9, the transport process of step S10, and the storage process of step S11 after the dicing process.

[0131] Like silver (Ag), copper (Cu) is cheaper than gold (Au), but is more susceptible to oxidation than gold (Au). Therefore, even when the metal film ME includes a copper (Cu) film instead of the silver film ME3, the same problems and effects as those described in this embodiment may occur. Therefore, this embodiment can also be applied when the metal film ME includes a copper (Cu) film instead of the silver film ME3. That is, in this embodiment, the metal film ME may have a copper (Cu) film instead of the silver film ME3.

[0132] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0133] 1A chip area 1B Scribe area BD1,BD2 Bonding material BR1,BR2 blades BS base material layer BW Bonding Wire CB container part CT,CT1 central part DP die pad KB Structure KG1, KG2 grinding jig PR,PR1 peripheral area DT Dicing Tape DS1 step surface DS2 step LD lead NL adhesive layer ME metal membrane ME1 Titanium Film ME2 Nickel Film ME3 silver film MP metal plate MR sealing part NT notch PD Pad PDG Gate Pad PDS source pad PR,PR1 peripheral area SB semiconductor substrate SB1 surface SB2 back side SP1,SP2 space STG1, STG2, STG3 stages T1, T2 thickness VC vacuum container W1 width WF, WF1 wafer WR wiring structure

Claims

1. (a) providing a semiconductor wafer having a first major surface and a second major surface opposite the first major surface; (b) grinding the second main surface of the semiconductor wafer so that the thickness of the central portion of the semiconductor wafer is smaller than the thickness of the peripheral portion surrounding the central portion of the semiconductor wafer; (c) after the step (b), forming a metal film including a first metal film made of a silver film or a copper film on the second main surface of the semiconductor wafer; (d) attaching a dicing tape to the second main surface of the semiconductor wafer via the metal film; (e) after the step (d), cutting the semiconductor wafer to separate the peripheral portion from the central portion and the dicing tape; (f) after the step (e), dicing the semiconductor wafer attached to the dicing tape; (g) after the step (f), a step of transporting the semiconductor wafer attached to the dicing tape and having been diced; and The step (d) (d1) placing the semiconductor wafer in a vacuum chamber; (d2) after the step (d1), a step of reducing the pressure inside the vacuum container; (d3) after the step (d2), a step of placing the dicing tape on the second main surface of the semiconductor wafer so as to be spaced apart from the metal film; (d4) after the step (d3), a step of opening the inside of the vacuum container to the atmosphere; and the dicing tape has a base layer and an adhesive layer on the base layer, The method for manufacturing a semiconductor device, wherein the base layer is made of polyvinyl chloride.

2. 2. The method of manufacturing a semiconductor device according to claim 1, At the stage where the step (d3) is performed, the dicing tape is separated from the metal film on the central portion of the semiconductor wafer, In the step (d4), the vacuum chamber is opened to the atmosphere, whereby the dicing tape comes into contact with the metal film on the central portion of the semiconductor wafer.

3. 3. The method for manufacturing a semiconductor device according to claim 2, In the step (d), the dicing tape is attached to the metal film on the second main surface of the semiconductor wafer so that the adhesive layer of the dicing tape faces the metal film on the second main surface of the semiconductor wafer.

4. 4. The method for manufacturing a semiconductor device according to claim 3, The method for manufacturing a semiconductor device, wherein the adhesive layer is made of an acrylic resin.

5. 2. The method of manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the first metal film constitutes an uppermost layer of the metal film.

6. The method for manufacturing a semiconductor device according to claim 1 further comprises: (a1) forming a semiconductor element on the first main surface of the semiconductor wafer or in the semiconductor wafer after the step (a) and before the step (b); (a2) forming a wiring structure on the first main surface of the semiconductor wafer after the step (a1) and before the step (b); The method for manufacturing a semiconductor device comprising the steps of:

7. 2. The method of manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the surface of the metal film is subjected to a roughening treatment.

8. 2. The method of manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the thickness of the base layer is 70 micrometers or more and 100 micrometers or less.

9. 2. The method of manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the metal film does not include a gold film.

10. 2. The method of manufacturing a semiconductor device according to claim 1, (g1) after the step (g), a step of obtaining a semiconductor chip from the semiconductor wafer that has been attached to the dicing tape and diced, and performing die bonding using the obtained semiconductor chip; The method for manufacturing a semiconductor device further comprises:

11. 2. The method of manufacturing a semiconductor device according to claim 1, In the step (b), the second main surface of the semiconductor wafer is ground, thereby forming a step at the boundary between the central portion and the peripheral portion on the second main surface of the semiconductor wafer.

12. 2. The method of manufacturing a semiconductor device according to claim 1, In the step (b), by grinding the second main surface, a plurality of steps are formed at the boundary between the central portion and the peripheral portion on the second main surface of the semiconductor wafer.

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