Power supply control device, DC / DC converter, and vehicle

Abstract

To provide a power supply control device that can regulate an output from a DC / DC converter when an input voltage drops, and suppress output overshoot of the DC / DC converter when the input voltage recovers.SOLUTION: A power supply control device (2A) includes a clamp circuit (20) configured to clamp a second amplifier output voltage (Vc) output from a second error amplifier (12) to a predetermined clamp voltage (Vclamp), in which a switching control unit (16) can perform a skipping operation in which a turn on operation of a low-side transistor (M2) is skipped in at least one switching cycle to maintain a high-side transistor (M1) in an on state, and the clamp circuit performs clamping during the skip operation.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device. [Background technology]

[0002] One type of DC / DC converter includes a high-side transistor and a low-side transistor connected in series, and a rectifying / smoothing circuit with an inductor and an output capacitor connected to their connection node. An input voltage is applied between the high-side and low-side transistors. The high-side and low-side transistors are alternately turned on and off to generate a rectangular voltage, which is then rectified and smoothed by the rectifying / smoothing circuit to obtain an output voltage lower than the input voltage. In this case, current-mode control based on the inductor current may be used. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-221099

[0004] [overview] In automotive battery-powered equipment, the cold crank phenomenon is a well-known phenomenon in which the internal impedance of the lead battery drops in cold regions and the battery voltage drops significantly. When recovering from the cold crank phenomenon, there is a demand from the market to suppress output overshoot of the DC / DC converter that is directly connected to the automotive battery, and to regulate the DC / DC converter output as much as possible when the battery output drops.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a power supply control device that can regulate the output of a DC / DC converter when the input voltage drops and suppress output overshoot of the DC / DC converter when the input voltage recovers.

[0006] A power supply control device according to one aspect of the present disclosure includes: a high-side transistor having a first terminal connected to an input voltage application terminal; a low-side transistor having a first terminal connected to a second terminal of the high-side transistor at a first node; an inductor connected to the first node; A power supply control device used in a DC / DC converter comprising: a first error amplifier configured to receive a feedback voltage based on the output voltage of the DC / DC converter and a first reference voltage; a second error amplifier configured to receive the output of the first error amplifier and a signal representing information on the current flowing through the inductor; a first comparator configured to receive the output of the second error amplifier and a ramp voltage; a switching control unit configured to perform switching control of the high-side transistor and the low-side transistor based on an output of the first comparator; a clamp circuit configured to clamp a second amplifier output voltage output from the second error amplifier to a predetermined clamp voltage; Equipped with the switching control unit is capable of a skip operation of skipping the turn-on of the low-side transistor in at least one switching period to maintain the on state of the high-side transistor, The clamp circuit is configured to perform clamping during the skip operation. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is an overall configuration diagram of a DC / DC converter according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a perspective view showing the appearance of the power supply IC. [Figure 3] FIG. 3 shows the configuration of a DC / DC converter having a power supply IC. [Figure 4] FIG. 4 is a diagram illustrating an example of a peripheral circuit configuration of the error amplifier and the comparator. [Figure 5] FIG. 5 is a diagram showing an example of waveforms of a ramp voltage, a clock signal, and a gate signal. [Figure 6] FIG. 6 is a flowchart showing a process related to the frequency division operation. [Figure 7] FIG. 7 is a diagram showing an example of a waveform when the amplifier output voltage is clamped to the clamp voltage. [Figure 8] FIG. 8 is a waveform diagram showing an example of behavior when the input voltage drops and then recovers. [Figure 9] FIG. 9 is a timing chart showing an example of the clamping operation of the amplifier output voltage. [Figure 10] FIG. 10 is a flowchart relating to the operation of the clamp circuit control unit. [Figure 11] FIG. 11 is a waveform diagram showing an example of the operation of the clamp circuit control section. [Figure 12] FIG. 12 is a diagram showing a modified example of the configuration for controlling the reference voltage. [Figure 13] FIG. 13 is a waveform diagram schematically showing the operation of the configuration shown in FIG. [Figure 14] FIG. 14 is a diagram showing a modification of the configuration of FIG. [Figure 15] FIG. 15 is a diagram showing a configuration that takes into account a light load. [Figure 16] FIG. 16 is a timing chart showing an example of operation under a light load. [Figure 17] FIG. 17 is a diagram showing an example of waveforms when returning from a sleep operation. [Figure 18] FIG. 18 is a diagram illustrating a configuration example of a clamp voltage generating circuit. [Figure 19] FIG. 19 is an external view showing an example of a vehicle.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <Configuration of DC / DC Converter> FIG. 1 is an overall configuration diagram of a DC / DC converter 1 according to an embodiment of the present disclosure. The DC / DC converter 1 in FIG. 1 includes a power supply IC 2 as a power supply control device and a plurality of discrete components externally connected to the power supply IC 2. The plurality of discrete components include a capacitor C1 as an output capacitor, a capacitor C2 as a bootstrap capacitor, resistors R1 and R2 as feedback resistors, and an inductor L1. The DC / DC converter 1 is configured as a step-down DC / DC converter that generates a desired output voltage Vout from an input voltage Vin supplied from the outside. An output voltage Vout occurs at the output terminal OUT. That is, the output terminal OUT is an application terminal of the output voltage Vout (a terminal to which the output voltage VoutT is applied). The output voltage Vout is supplied to a load LD connected to the output terminal OUT.

[0010] The input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. For example, when the input voltage Vin is 12V, the output voltage Vout can be stabilized at a desired target voltage (e.g., 5V) less than 12V by adjusting the resistance values of the resistors R1 and R2.

[0011] FIG. 2 shows an external perspective view of the power supply IC 2 (power supply control device). The power supply IC 2 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the power supply IC 2. The power supply IC 2 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply IC 2 shown in FIG. 2 and the type of the housing of the power supply IC 2 are merely examples, and they can be arbitrarily designed. The output stage circuit MM, the main control block 3, and the rectifying element D1 shown in FIG. 1 are included in the semiconductor integrated circuit. Note that the output stage circuit MM may be provided outside the power supply IC 2.

[0012] In FIG. 1, only the input terminal IN, switch terminal SW, feedback terminal FB, output monitoring terminal OS, boot terminal BOOT, and ground terminal GND are shown as some of the multiple external terminals provided on power supply IC2 (the same applies to FIG. 3 described later, etc.), but other external terminals (e.g., an enable terminal and a power good terminal) may also be provided on power supply IC2.

[0013] The external configuration of power supply IC2 will now be described. An input voltage Vin is supplied to input terminal IN from outside power supply IC2. An inductor L1 is connected in series between switch terminal SW and output terminal OUT. One end of inductor L1 is connected to switch terminal SW, and the other end of inductor L1 is connected to output terminal OUT. The output terminal OUT is connected to ground via capacitor C1. One end of capacitor C1 is connected to output terminal OUT, and the other end of capacitor C1 is connected to ground. The output terminal OUT is connected to one end of resistor R1, and the other end of resistor R1 is connected to ground via resistor R2. The connection node between resistors R1 and R2 is connected to feedback terminal FB. An output monitoring terminal OS is connected to output terminal OUT. Therefore, the output voltage Vout is applied to output monitoring terminal OS. The ground terminal GND is connected to ground. A capacitor C2 is connected between terminals BOOT and SW. One end of capacitor C2 is connected to boot terminal BOOT, and the other end of capacitor C2 is connected to switch terminal SW. The current flowing through inductor L1 is referred to as inductor current IL.

[0014] The following describes the internal configuration of the power supply IC 2. The power supply IC 2 includes an output stage circuit MM, a main control block 3 for controlling the output stage circuit MM, and a rectifying element D1.

[0015] The output stage circuit MM includes a high-side transistor M1 and a low-side transistor M2. Here, the transistors M1 and M2 are each an N-channel metal oxide semiconductor field effect transistor (MOSFET). The transistors M1 and M2 are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, ground). When the transistors M1 and M2 are switched, the input voltage Vin is switched and a square-wave switching voltage Vsw appears at the switch terminal SW. Specifically, the drain of the transistor M1 is connected to the input terminal IN, which is the application terminal of the input voltage Vin, and the source of the transistor M1 and the drain of the transistor M2 are commonly connected to the switch terminal SW. The source of the transistor M2 is connected to the ground terminal GND.

[0016] The high-side transistor M1 functions as an output transistor, and the low-side transistor M2 functions as a synchronous rectifier transistor. Inductor L1 and capacitor C1 form a rectifying and smoothing circuit that rectifies and smoothes the square-wave switching voltage Vsw that appears at the switch terminal SW to generate the output voltage Vout. Resistors R1 and R2 form a voltage divider circuit that divides the output voltage Vout, and a feedback voltage Vfb, which is the divided voltage of the output voltage Vout, is generated at the connection node between resistors R1 and R2. The connection node between resistors R1 and R2 is connected to the feedback terminal FB, and the feedback voltage Vfb is input to the feedback terminal FB.

[0017] Gate signals G1 and G2 are supplied to the gates of transistors M1 and M2, respectively. Transistors M1 and M2 are turned on and off in response to the gate signals G1 and G2. When the gate signal G1 is at a high level, the high-side transistor M1 is turned on, and when the gate signal G1 is at a low level, the high-side transistor M1 is turned off. Similarly, when the gate signal G2 is at a high level, the low-side transistor M2 is turned on, and when the gate signal G2 is at a low level, the low-side transistor M2 is turned off. Essentially, transistors M1 and M2 are switched in a complementary manner. However, a simultaneous off period (dead time) during which both transistors M1 and M2 are turned off may be provided.

[0018] The main control block 3 is connected to the gates of the transistors M1 and M2, the switch terminal SW, the feedback terminal FB, and the output monitoring terminal OS. The main control block 3 controls the on / off states of the transistors M1 and M2 by controlling the levels of the gate signals G1 and G2 based on the feedback voltage Vfb, thereby generating an output voltage Vout at the output terminal OUT according to the feedback voltage Vfb. As shown in FIG. 1, the main control block 3 may also be supplied with the output voltage Vout. The main control block 3 can perform overvoltage protection and the like based on the output voltage Vout, and can also generate pseudo current information (described later in detail) by referring to the output voltage Vout.

[0019] The power supply IC2 is provided with an internal power supply circuit (not shown) that generates an internal power supply voltage Vreg based on the input voltage Vin. The internal power supply voltage Vreg has a predetermined positive DC voltage value. In the example of FIG. 1, the rectifier element D1 is a diode. In this case, the anode of the rectifier element D1 is connected to the terminal to which the internal power supply voltage Vreg is applied, and the cathode is connected to the boot terminal BOOT. The rectifier element D1 may be a switching element that is turned on during the on period of the transistor M2. The rectifier element D1 and capacitor C2 form a bootstrap circuit. The voltage applied to the boot terminal BOOT is called the boot voltage Vboot. The main control block 3 can be driven based on the internal power supply voltage Vreg or the boot voltage Vboot.

[0020] When the output stage circuit MM is in the output low state (high-side transistor M1 is off and low-side transistor M2 is on), capacitor C2 is charged through rectifier element D1 based on the internal power supply voltage Vreg, and the boot voltage Vboot becomes higher than the switching voltage Vsw by the voltage across capacitor C2. Thereafter, even when the output stage circuit MM is switched to the output high state (high-side transistor M1 is on and low-side transistor M2 is off), the boot voltage Vboot remains higher than the switching voltage Vsw by the voltage across capacitor C2.

[0021] The gate signal G1 is a signal based on the potential of the switch terminal SW. Specifically, a low-level gate signal G1 has the potential of the switch terminal SW, and a high-level gate signal G1 is higher than the potential of the switch terminal SW by the difference between voltages Vboot and Vsw. The main control block 3 can generate a high-level gate signal G1 based on the boot voltage Vboot. On the other hand, the gate signal G2 is a signal based on the ground potential. Specifically, a low-level gate signal G2 has the ground potential, and a high-level gate signal G2 is higher than the ground potential by a predetermined voltage (e.g., the internal power supply voltage Vreg).

[0022] Figure 3 shows the configuration of DC / DC converter 1 including power supply IC 2A. Power supply IC 2A is an example of power supply IC 2. Unless inconsistent, all of the points made above about power supply IC 2 also apply to power supply IC 2A.

[0023] The main control block 3 in the power supply IC 2A includes an error amplifier 11, an error amplifier 12, a clock generation circuit 13, a ramp voltage generation circuit 14, a comparator 15, a logic circuit 16, a driver 17, and a current information generation circuit 18. The power supply IC 2A performs switching operations using PWM (pulse width modulation). The function and operation of each component are explained below. The main control block 3 also includes a clamp circuit CLP and a zero-cross circuit ZC, which will be described later.

[0024] The error amplifier 11 is a current output type transconductance amplifier. The error amplifier 11 has an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal. The output terminal of the error amplifier 11 is connected to the wiring WR1. The non-inverting input terminal of the error amplifier 11 is connected to the feedback terminal FB and receives the feedback voltage Vfb. A predetermined reference voltage Ref is supplied to the inverting input terminal of the error amplifier 11. The reference voltage Ref is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generation circuit (not shown) in the power supply IC2A.

[0025] The error amplifier 11 outputs a current signal I1 corresponding to the difference between the feedback voltage Vfb and the reference voltage Ref from its output terminal, thereby generating an amplifier output voltage Comp corresponding to the difference between the feedback voltage Vfb and the reference voltage Ref on a line WR1. Charge due to the current signal I1 is input to and output from the line WR1. Specifically, when the feedback voltage Vfb is higher than the reference voltage Ref, the error amplifier 11 outputs a current due to the current signal I1 from the error amplifier 11 to the line WR1 so as to increase the potential of the line WR1, and when the feedback voltage Vfb is lower than the reference voltage Ref, the error amplifier 11 draws a current due to the current signal I1 from the line WR1 to the error amplifier 11 so as to decrease the potential of the line WR1. As the absolute value of the difference between the feedback voltage Vfb and the reference voltage Ref increases, the magnitude of the current due to the current signal I1 also increases.

[0026] A phase compensation circuit (not shown in FIG. 3) is provided between the wiring WR1 and ground, and receives the input of the current signal I1 to compensate for the phase of the amplifier output voltage Comp. The phase compensation circuit includes a series circuit of a resistor and a capacitor. Specifically, one end of the resistor is connected to the wiring WR1, and the other end of the resistor is connected to one end of the capacitor. The other end of the capacitor is connected to ground. By appropriately setting the resistance value of the resistor and the capacitance value of the capacitor, the phase of the amplifier output voltage Comp can be compensated to prevent oscillation of the output feedback loop.

[0027] Like the error amplifier 11, the error amplifier 12 is also a current output type transconductance amplifier. The error amplifier 12 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The output terminal of the error amplifier 12 is connected to a wiring WR2. The inverting input terminal of the error amplifier 12 is connected to a wiring WR1 and receives the amplifier output voltage Comp. A current detection signal Visns is supplied to the non-inverting input terminal of the error amplifier 12. As will be described in detail later, the current detection signal Visns is a voltage signal that represents the detection result of the inductor current IL.

[0028] The error amplifier 12 outputs a current signal I2 corresponding to the difference between the amplifier output voltage Comp and the current detection signal Visns from its output terminal, thereby generating an amplifier output voltage Vc corresponding to the difference between the amplifier output voltage Comp and the current detection signal Visns on the wiring WR2. Charge due to the current signal I2 is input to and output from the wiring WR2. Specifically, when the amplifier output voltage Comp is lower than the current detection signal Visns, the error amplifier 12 outputs a current due to the current signal I2 from the error amplifier 12 to the wiring WR2 so as to increase the potential of the wiring WR2, and when the amplifier output voltage Comp is higher than the current detection signal Visns, the error amplifier 12 draws a current due to the current signal I2 from the wiring WR2 to the error amplifier 12 so as to decrease the potential of the wiring WR2. As the absolute value of the difference between the amplifier output voltage Comp and the current detection signal Visns increases, the magnitude of the current due to the current signal I2 also increases.

[0029] A phase compensation circuit (not shown in Figure 3) is provided between the wiring WR2 and ground, and receives the input of the current signal I2 to compensate for the phase of the amplifier output voltage Vc. The phase compensation circuit includes a series circuit of a resistor and a capacitor. Specifically, one end of the resistor is connected to the wiring WR2, and the other end of the resistor is connected to one end of the capacitor. The other end of the capacitor is connected to ground. By appropriately setting the resistance value of the resistor and the capacitance value of the capacitor, the phase of the amplifier output voltage Vc can be compensated and oscillation of the output feedback loop can be prevented.

[0030] The clock generation circuit 13 generates and outputs a clock signal CLK. The clock signal CLK is a square wave signal having a predetermined switching frequency fsw, and alternates between low and high signal levels. The clock signal CLK is output from the clock generation circuit 13 to the ramp voltage generation circuit 14 and the logic circuit 16.

[0031] The ramp voltage generating circuit 14 generates a ramp voltage Ramp. The ramp voltage Ramp has, for example, a sawtooth voltage waveform, as will be described later. The ramp voltage may also have a triangular waveform, etc. The ramp voltage Ramp depends on the clock signal CLK.

[0032] The amplifier output voltage Vc is applied to the inverting input terminal of the comparator 15. A ramp voltage Ramp is applied to the non-inverting input terminal of the comparator 15. The comparator 15 compares the amplifier output voltage Vc with the ramp voltage Ramp and outputs a reset signal Rst. The reset signal Rst is supplied to the logic circuit 16.

[0033] The logic circuit 16 controls the driver 17 based on the clock signal CLK and the reset signal RST to control the gate signals G1 and G2. Under the control of the logic circuit 16, the driver 17 supplies the gate signals G1 and G2 based on the signals CLK and RST to the transistors M1 and M2, thereby causing the output stage circuit MM to perform a switching operation. In the switching operation, the transistors M1 and M2 are alternately turned on and off based on the signals CLK and RST. The error amplifier 11 generates the current signal I1 so that the feedback voltage Vfb and the reference voltage Ref are equal. Therefore, through the switching operation, the output voltage Vout is stabilized at a predetermined target voltage that corresponds to the reference voltage Ref and the voltage division ratio defined by the resistors R1 and R2.

[0034] The comparator 19 is provided to detect a light load state. A feedback voltage Vfb is applied to the non-inverting input terminal of the comparator 19. A reference voltage Ref2 (>Ref) is applied to the inverting input terminal of the comparator 19. The comparator 19 compares the feedback voltage Vfb with the reference voltage Ref2, and outputs a detection signal DET as the comparison result. The detection signal DET is supplied to the logic circuit 16. Light load mode control will be described later.

[0035] <Current mode control> Here, the current information generating circuit 18 will be described with reference to Fig. 4. Providing the current information generating circuit 18 realizes current mode control. Fig. 4 is a diagram showing an example of a peripheral circuit configuration of the error amplifiers 11 and 12 and the comparator 15. As shown in Fig. 4, the current information generating circuit 18 has a current detecting unit 18A, a pseudo current detecting unit 18B, and a resistor 18C.

[0036] The current detection unit 18A detects the inductor current IL that flows when the low-side transistor M2 is in the ON state. During normal operation, the pseudo current detection unit 18B does not operate. However, in the frequency division operation described below, the turn-on of the low-side transistor M2 (switching from the OFF state to the ON state) is skipped in the switching cycle, so the inductor current IL cannot be detected when the low-side transistor M2 is in the ON state. Therefore, in the frequency division operation, the pseudo current detection unit 18B detects the inductor current IL in a pseudo manner.

[0037] In the frequency division operation, the turn-on of the low-side transistor M2 is skipped in the switching period, and therefore the high-side transistor M1 is maintained in the on state, thereby maintaining the output high state of the output stage circuit MM. An estimated increase in the inductor current IL while the output high state is maintained is superimposed on the detected current IA by the current detection unit 18A as a pseudo current (current IB detected by the pseudo current detection unit 18B). A method for detecting the pseudo current will now be described.

[0038] The slope ΔIL of the inductor current IL when the output stage circuit MM is in the high output state is expressed by the following equation (1). In equation (1), L1 represents the inductance (inductance value) of the inductor L1. If the slope ΔIL of the inductor current IL is known, the increase in the inductor current IL mentioned above can be determined, and the pseudo current to be superimposed can be found. ΔIL=((Vin-Vout) / L1)×Ton ···(1) However, Ton = Duty × (1 / fsw) Duty=Vout / Vin

[0039] In DC / DC converter 1, the inductance of inductor L1 is set to a predetermined value, and in power supply IC2A, the inductance of inductor L1 is known. Furthermore, power supply IC2A can recognize the input voltage Vin by detecting the voltage at input terminal IN. Additionally, power supply IC2A can recognize the output voltage Vout by detecting the voltage at output monitor terminal OS. Therefore, in power supply IC2A, the slope ΔIL can be calculated using equation (1) based on the input voltage Vin, output voltage Vout, and the inductance of inductor L1.

[0040] The pseudo current Ipseudo to be superimposed is derived for the gradient ΔIL according to the following equation (2). Ipseudo=ΔIL·k (2) where k is a coefficient. In theory, ΔIL is input to the circuit side, but it is multiplied by the coefficient to match the IF (voltage level, etc.) with the circuit side. Each time the turn-on of the low-side transistor M2 is skipped, a pseudo current Ipseudo is superimposed.

[0041] As shown in Figure 4, when the detection current IA or a current obtained by superimposing the detection current IB (pseudo current) on the detection current IA flows through resistor 18C, a voltage that is lower than the reference voltage Vref by the voltage drop across resistor 18C is generated as the current detection signal Visns.

[0042] <Division operation function> Next, we will explain the frequency division function of the power supply IC 2A. The frequency division function is performed to regulate the output voltage Vout even when the input voltage Vin drops (voltage reduction occurs).

[0043] The left side of Fig. 5 is a timing chart showing an example of operation when the input voltage Vin is at a normal value. In Fig. 5, waveform examples of the ramp voltage Ramp, clock signal CLK, and gate signal G1 are shown from the top to the bottom. The gate signal G2, not shown, is an inverted version of G1.

[0044] First, at timing t1, the rising edge of the clock signal CLK triggers the ramp voltage Ramp to rise to the bottom voltage V1, and the gate signal G1 is switched to high level. At this time, the gate signal G2 is switched to low level. This turns on the high-side transistor M1 and turns off the low-side transistor M2, causing the output stage circuit MM to output a high voltage. The bottom voltage V1 is determined by the power supply voltage Vdd. The power supply voltage Vdd is generated by a voltage generation circuit (not shown) provided in the power supply IC2A. The ramp voltage Ramp then rises from the bottom V1 at a slope ΔV. The slope ΔV depends on the input voltage Vin.

[0045] Then, when the ramp voltage Ramp reaches the amplifier output voltage Vc at timing t2, the reset signal RST is asserted and the gate signal G1 is switched to low level. At this time, the gate signal G2 is switched to high level. This causes the output stage circuit MM to enter a low output state. At this time, the ramp voltage Ramp falls. After that, the clock signal CLK falls at timing t3 and rises again at timing t4. This triggers the ramp voltage Ramp to rise to the bottom voltage V1, and the gate signal G1 is switched to high level. Thereafter, the same process is repeated.

[0046] The switching period Tsw is composed of an on-period Ton (timing t1 to t2) during which the high-side transistor M1 is in the on state and an off-period Toff (timing t2 to t4) during which the high-side transistor M1 is in the off state, whereby PWM control is performed using a duty represented by Ton / Tsw.

[0047] The right side of Figure 5 is a timing chart showing an example of the waveform when the input voltage Vin drops from its normal value. Here, the drop in input voltage Vin causes the ramp voltage Ramp to rise at a smaller slope ΔV than under normal conditions (left side of Figure 5). This lengthens the on-period Ton in the switching cycle Tsw, increasing the duty.

[0048] If the ramp voltage Ramp does not reach the amplifier output voltage Vc by the time the clock signal CLK falls (timing t3), the ramp voltage Ramp is forcibly lowered.

[0049] When the input voltage Vin decreases in this way, the off-period Toff becomes shorter. Here, since it is necessary to secure a period during which the low-side transistor M2 is in the on state for bootstrap, a minimum off-period Toffmin, which is the minimum off-period Toff, is set.

[0050] Here, the frequency division operation will be described with reference to the flowchart in Fig. 6. First, if the logic circuit 16 determines in step S1 that the off-period Toff is equal to or greater than the minimum off-period Toffmin (Y in step S1), the process proceeds to step S2, where the low-side transistor M2 is switched to the on state (the high-side transistor M1 is switched to the off state). In this case, it can be determined that the remaining off-period Toff in the switching cycle Tsw is equal to or greater than the minimum off-period Toffmin at the timing when the reset signal Rst is asserted. Fig. 5 shows an example of such a case.

[0051] On the other hand, if it is determined in step S1 that the off period Toff is shorter than the minimum off period Toffmin (N in step S1), the process proceeds to step S3. In this case, the remaining off period Toff in the switching period Tsw at the timing when the reset signal Rst is asserted is shorter than the minimum off period Toffmin, or the ramp voltage Ramp does not reach the amplifier output voltage Vc before the clock signal CLK falls, and the off period Toff=0 in the switching period Tsw.

[0052] When proceeding to step S3, the high-side transistor M1 is not turned off and remains on (the low-side transistor M2 remains off). In step S3, a frequency divider counter (not shown) starts counting, and detection of the pseudo current begins. The frequency divider counter counts the number of switching periods.

[0053] If the ramp voltage Ramp reaches the amplifier output voltage Vc in step S4 (Y in step S4), the process proceeds to step S5, where the low-side transistor M2 is switched to the ON state (the high-side transistor M1 is switched to the OFF state).

[0054] On the other hand, if the ramp voltage Ramp does not reach the amplifier output voltage Vc in step S4 (N in step S4), proceed to step S6. If the count value of the frequency division counter does not reach a predetermined value (e.g., 16) in step S6 (N in step S6), return to step S4. On the other hand, if the count value reaches the predetermined value without the ramp voltage Ramp reaching the amplifier output voltage Vc (Y in step S6), proceed to step S7, where the low-side transistor M2 is turned on (the high-side transistor M1 is turned off) for the minimum off-period Toffmin.

[0055] As a result, when the input voltage Vin continues to decrease and the off-period Toff becomes shorter than the minimum off-period Toffmin, the frequency division operation is initiated, and the turn-on of the low-side transistor M2 in the switching period is skipped in at least one switching period. The skipping is performed up to a number of switching periods that is one less than the predetermined value (for example, 15 when the predetermined value is 16). When the maximum number of switching periods is skipped, the minimum off-period Toffmin is ensured in the last switching period after the skipping. Therefore, the frequency division operation regulates the output voltage Vout by lowering the switching frequency.

[0056] <Clamp control> When the input voltage Vin drops as described above, the output voltage Vout is regulated by skipping the turn-on of the low-side transistor M2 in the switching cycle, but if the input voltage Vin drops further and regulation by the skipping becomes impossible, the amplifier output voltage Vc rises. However, since there is a possibility of the output voltage Vout overshooting when the input voltage Vin recovers from a dropped state (power reduction state), in this embodiment, control is performed to clamp the amplifier output voltage Vc.

[0057] As shown in FIG. 4, the power supply IC2 is provided with a clamp circuit 20. The clamp circuit 20 has an amplifier 20A and an NMOS transistor 20B. An amplifier output voltage Vc is applied to the non-inverting input terminal of the amplifier 20A. A predetermined clamp voltage Vclamp is applied to the inverting input terminal of the amplifier 20A. The NMOS transistor 20B is an N-channel MOSFET. The output of the amplifier 20A is applied to the gate of the NMOS transistor 20B. The drain of the NMOS transistor 20B is connected to the terminal to which the amplifier output voltage Vc is applied. The source of the NMOS transistor 20B is connected to ground.

[0058] The clamp voltage Vclamp is set higher than the level of the amplifier output voltage Vc during normal operation. When the amplifier output voltage Vc exceeds the clamp voltage Vclamp, the NMOS transistor 20B is turned on, and the amplifier output voltage Vc is clamped to the clamp voltage Vclamp. When the amplifier output voltage Vc is equal to or lower than the clamp voltage Vclamp, the NMOS transistor 20B is turned off, allowing the amplifier output voltage Vc to take any value.

[0059] Figure 7 shows an example of the waveform when the amplifier output voltage Vc is clamped to the clamp voltage Vclamp. The state shown in Figure 7 is during frequency division, so the ramp voltage Ramp cannot reach the clamp voltage Vclamp and the gate signal G1 is maintained at a high level.

[0060] Furthermore, when the input voltage Vin drops, the feedback voltage Vfb becomes lower than the reference voltage Ref, causing the output of the error amplifier 11 to saturate and fall outside its operating range. To avoid this situation, this embodiment also clamps the amplifier output voltage Comp.

[0061] Specifically, as shown in FIG. 4, the amplifier 20A outputs a control signal OUT for controlling the reference voltage Ref. The control signal OUT is a logic signal that can be either high or low. For example, when the amplifier output voltage Vc exceeds the clamp voltage Vclamp, the control signal OUT is set to high level, and when the amplifier output voltage Vc is equal to or lower than the clamp voltage Vclamp, the control signal OUT is set to low level. Note that hysteresis may be provided in the generation of the control signal OUT. When the control signal OUT is high level, the reference voltage Ref is set to a voltage value that is a predetermined value lower than the reference value. When the control signal OUT is low level, the reference voltage Ref is set to the reference value.

[0062] As a result, when the feedback voltage Vfb becomes lower than the reference voltage Ref due to a drop in the input voltage Vin, the amplifier output voltage Comp drops and the amplifier output voltage Vc rises. At this time, the amplifier output voltage Vc is clamped, and the reference voltage Ref is lowered by the control signal OUT, causing the amplifier output voltage Comp to rise. Therefore, the amplifier output voltage Comp can be clamped.

[0063] FIG. 8 is a waveform diagram showing an example of behavior when the input voltage Vin drops and then recovers. Starting from the top, FIG. 8 shows example waveforms of the input voltage Vin, the output voltage Vout, and the amplifier output voltage Vc. As shown in FIG. 8, the threshold value Vth for the output voltage Vout corresponds to the feedback voltage Vfb equivalent to the amplifier output voltage Comp at which the amplifier output voltage Vc becomes the clamp voltage Vclamp. When the output voltage Vout is equal to or lower than the threshold value Vth, the amplifier output voltage Vc is clamped. Furthermore, the voltage VL shown in FIG. 8 is the value of the output voltage Vout corresponding to the voltage value to which the reference voltage Ref is reduced by the control signal OUT.

[0064] 9 is a timing chart showing an example of the clamping operation of the amplifier output voltages Vc and Comp. From the top to bottom, Fig. 9 shows the control signal OUT, the feedback voltage Vfb (solid line), the reference voltage Ref (dashed line), the amplifier output voltage Comp, and the amplifier output voltage Vc.

[0065] 9 shows an example of operation when the input voltage Vin is reduced. The reference voltage Ref is reduced during the high-level period Th of the control signal OUT. As a result, the input differential voltage of the error amplifier 11 is maintained substantially constant, and the amplifier output voltage Comp is clamped (region A). The amplifier output voltage Vc is also clamped to the clamp voltage Vclamp (region B).

[0066] <Clamp circuit control section> 4, in this embodiment, a clamp circuit control unit 21 is provided in a power supply IC 2A. The clamp circuit control unit 21 switches the clamp circuit 20 (more specifically, the amplifier 20A) between enabled and disabled states. Here, the operation of the clamp circuit control unit 21 will be described with reference to the flowchart shown in FIG.

[0067] A high-side on / off signal Sh is input to the clamp circuit control unit 21. The high-side on / off signal Sh is a signal that indicates the on / off state of the high-side transistor M1, and is input from, for example, the logic circuit 16. For example, when the high-side on / off signal M1 is at a high level, it indicates that the high-side transistor M1 is in an on state, and when the high-side on / off signal M1 is at a low level, it indicates that the high-side transistor M1 is in an off state.

[0068] In addition, an enable signal Enb is output from the clamp circuit control unit 21. The enable signal Enb is supplied to the amplifier 20A. For example, when the enable signal Enb is at a high level, it indicates enable, and when the enable signal Enb is at a low level, it indicates disable. When the amplifier 20A is disabled, the output of the amplifier 20A turns off the NMOS transistor 20B, and the amplifier output voltage Vc can take any value.

[0069] 10, first, in step S10, it is determined whether the high-side transistor M1 is turned on based on the high-side on / off signal Sh. If it is not turned on (N in step S10), the process returns to step S10. If it is turned on (Y in step S10), the process proceeds to step S11. In step S11, time counting begins.

[0070] Then, in step S12, it is determined whether the high-side transistor M1 has been turned off based on the high-side on / off signal Sh. If it has not been turned off (N in step S12), the process proceeds to step S13, where it is determined whether a predetermined time has been counted. If the predetermined time has not been counted (N in step S13), the process returns to step S12. If the high-side transistor M1 is turned off before the predetermined time has been counted (Y in step S12), the process returns to step S10.

[0071] On the other hand, if the predetermined time has been counted without the high-side transistor M1 being turned off (Y in step S13), the process proceeds to step S14, where the enable signal Enb is changed from disabled to enabled. Thereafter, in step S15, it is determined whether the high-side transistor M1 has been turned off. If the high-side transistor M1 has not been turned off (N in step S15), the process returns to step S15. If the high-side transistor M1 has been turned off (Y in step S15), the process proceeds to step S16.

[0072] In step S16, counting of the rising edges of the high-side on / off signal Sh is started. Then, in step S17, it is determined whether the count has reached a predetermined value. Counting continues while the count has not reached the predetermined value. When the count has reached the predetermined value (Y in step S17), the enable signal Enb is changed from enable to disable in step S18. Then, the process returns to step S10.

[0073] The operation of the clamp circuit control unit 21 will be described with reference to the waveform example shown in FIG. 11. In FIG. 11, the high-side on-off signal Sh and the enable signal Enb are shown, starting from the top. When the high-side on-off signal Sh rises to a high level, i.e., when the high-side transistor M1 is turned on, a time count is started. When the high-side transistor M1 remains on for a predetermined time Tcnt, the enable signal Enb is switched to a high level, i.e., changed to enabled. After that, the high-side on-off signal Sh falls to a low level, i.e., the high-side transistor M1 is turned off. At this point, counting of rising edges of the high-side on-off signal Sh is started. In the example shown in FIG. 11, the high-side transistor M1 is turned on and then immediately turned off a predetermined number of times. As a result, the count value reaches a predetermined value, and the enable signal Enb is switched to a low level, i.e., changed to disabled. In this way, a delay time Tdly is provided between when the high-side transistor M1 is turned off and when the enable signal Enb is changed to disabled. This makes it possible to suppress overshoot of the output voltage Vout, which may occur if the enable signal Enb is immediately changed to disable.

[0074] <Variation 1> Fig. 12 shows a modified example of the configuration for controlling the reference voltage Ref. Unlike the configuration for generating the control signal OUT described above, the configuration shown in Fig. 12 includes an amplifier 22 and voltage-dividing resistors R11 and R12 in the power supply IC 2A. Note that a clamp circuit 20 is provided separately.

[0075] An amplifier output voltage Vc is applied to the inverting input terminal of the amplifier 22. A clamp voltage Vclamp is applied to the non-inverting input terminal of the amplifier 22. The amplifier 22 is a current output type transconductance amplifier. An output current IOUT output from the amplifier 22 is injected into a node N1 to which voltage dividing resistors R11 and R12 are connected. A reference voltage Ref is generated at the node N1.

[0076] The operation of the configuration of FIG. 12 will be described using the schematic waveform diagram shown in FIG. 13. FIG. 13 shows example waveforms of the output current IOUT and the reference voltage Ref. As shown in FIG. 13, when the amplifier output voltage Vc approaches the clamp voltage Vclamp, the output current IOUT decreases and the reference voltage Ref drops. When the amplifier output voltage Vc moves away from the clamp voltage Vclamp, the output current IOUT increases and the reference voltage Ref rises. In this way, the reference voltage Ref can be controlled by varying the output current IOUT.

[0077] <Variation 2> 14 is a diagram showing a modification of the configuration shown in FIG. 4. Here, a PMOS transistor 23 for clamping the amplifier output voltage Comp is provided in the power supply IC2A. The inverting amplifier output AOUT output from the amplifier 20A is applied to the gate of the PMOS transistor 23. As a result, when the amplifier output voltage Vc exceeds the clamp voltage Vclamp, the PMOS transistor 23 is turned on, and the amplifier output voltage Comp is clamped.

[0078] 14, the NMOS transistor 20B is not necessarily provided because the clamping of the amplifier output voltage Vc can be controlled by the clamping of Comp. Also, the configuration of FIG. 14 does not necessarily have to include a configuration for varying the reference voltage Ref using the control signal OUT.

[0079] Furthermore, the threshold value for the amplifier output voltage Vc for generating the inverting amplifier output AOUT may be offset from the clamp voltage Vclamp for clamping the amplifier output voltage Vc. Also, a timing difference may be set between the clamping of the amplifier output voltage Vc and the fluctuation of the reference voltage Ref.

[0080] <Light load operation> Here, we will explain the operation of power supply IC2A under light load conditions. Figure 15 shows a configuration that takes into account the operation under light load conditions compared to the configuration of Figure 4 described above. Specifically, power supply IC2A is provided with a switch 24. Switch 24 is connected between the application terminal of clamp voltage Vclamp and the application terminal of amplifier output voltage Vc. We will also explain the operation of clamp circuit CLP and zero-cross circuit ZC in Figure 3 described above.

[0081] When DC / DC operation is stable, a negative feedback state occurs, and the current detection signal Visns and the amplifier output voltage Comp are in an imaginary short state. In this state, Comp follows Visns. When the load current increases, Visns decreases, and when it decreases, Visns increases. In an imaginary short state, Comp behaves in the same way as Visns, and Comp increases under light loads. The clamp circuit CLP limits the upper level of Comp, so once the load current decreases to a certain level, Comp can no longer increase. When Comp can no longer increase, the voltage difference with Visns increases, causing the amplifier output voltage Vc to increase. As a result, the duty cycle of DC / DC operation increases, and the output voltage Vout increases.

[0082] FIG. 16 is a timing chart showing an example of operation under a light load. FIG. 16 shows example waveforms of the output voltage Vout, the switching voltage Vsw, and the inductor current IL. At the point indicated by A in FIG. 16, the switching voltage Vsw is generated based on Vc. Here, the output voltage Vout rises. When the output voltage Vout exceeds the reference voltage VREF2, the detection signal DET output from the comparator 19 is asserted. Then, the logic circuit 16 transitions to a first state in which the high-side transistor M1 is maintained in an off state and the low-side transistor M2 is maintained in an on state (timing t11 in FIG. 16).

[0083] By transitioning to the first state, switching is stopped and the voltage holding state is entered, and the output voltage Vout decreases due to the load current. Also, in the first state, the inductor current IL decreases. When transitioning to the first state, the switching voltage Vsw drops to a negative voltage (as shown in the enlarged view in Figure 16). Thereafter, as the inductor current IL decreases, the switching voltage Vsw rises toward 0V (ground level). When the switching voltage Vsw becomes 0V or higher, the zero crossing of the inductor current IL is detected by the zero crossing circuit ZC (at timing t12 in Figure 16). Then, the logic circuit 16 causes a transition to a second state (high impedance state) in which both transistors M1 and M2 are maintained in the off state.

[0084] Also, when the output voltage Vout exceeds the reference voltage VREF2, the logic circuit 16 shuts down the error amplifiers 11, 12, the clamp circuit 20, etc. for standby power reduction (transition to the sleep operation). When the output voltage Vout drops and falls below the reference voltage VREF (<VREF2), the logic circuit 16 resumes all the circuits that were shut down. However, time is required for the resumption, and particularly for the outputs of the error amplifiers 11, 12, large capacitors for phase compensation are often connected, requiring a significant resumption time. Therefore, during the resumption time, instead of generating the pulse of the switching voltage Vsw using Vc, the pulse of the switching voltage Vsw is generated using the clamp voltage Vclamp as a substitute. Note that the generation of the pulse here is performed at least once from the shutdown state until the resumption.

[0085] Specifically, the logic circuit 16 turns on the switch 24, inputting the clamp voltage Vclamp to the comparator 15. This causes the comparator 15 to compare the ramp voltage Ramp with the clamp voltage Vclamp. At this time, as shown in the waveform example of FIG. 17, the logic circuit 16 generates an on-pulse of the gate signal G1 to turn on the high-side transistor M1. After the on-pulse is generated, the logic circuit 16 turns off the switch 24, releasing the output of the error amplifier 12. In FIG. 16, a switching pulse is generated using Vclamp at a point indicated by B, after which normal operation resumes, and a switching pulse is generated using Vc at a point indicated by C. Thus, according to this embodiment, the clamp voltage Vclamp can be used both to clamp the amplifier output voltage Vc and to generate an on-pulse upon returning from sleep operation. Note that the clamp voltage Vclamp may be the same during frequency division operation and light load, or the level of the clamp voltage Vclamp during light load may be set higher than during frequency division operation, making the clamp voltage Vclamp different between frequency division operation and light load. By using this type of control, hysteresis can be provided in the transition from light load mode to PWM and from PWM to light load mode, achieving smooth switching and also reducing the number of switching operations in light load mode, thereby improving efficiency characteristics.

[0086] FIG. 18 shows a clamp voltage generation circuit 25 that generates a clamp voltage Vlamp. The clamp voltage generation circuit 25 has resistors Ra, Rb, and Rc. One end of the resistor Ra is connected to the application terminal of the output voltage Vout. One end of the resistor Rb is connected to the application terminal of the power supply voltage Vdd. The other ends of the resistors Ra and Rb are connected to one end of the resistor Rc at a node Nd. The other end of the resistor Rc is connected to ground. The clamp voltage Vclamp is generated at the node Nd.

[0087] The clamp voltage Vclamp is expressed by the following equation (3).

number

[0088] The clamp voltage Vclamp contains information about the output voltage Vout. This allows the clamp voltage Vclamp for clamping the amplifier output voltage Vc to be set according to the output voltage Vout. Furthermore, because the slope ΔV of the voltage rise of the ramp voltage Ramp depends on the input voltage Vin, the duty of the on-pulse generated when returning from sleep mode can be set according to the output voltage Vout.

[0089] During power reduction, PWM operation is performed and operation in light load mode does not occur.

[0090] <Application to vehicles> FIG. 19 is an external view of a vehicle X. The vehicle X of this configuration example is equipped with a DC / DC converter 1 including a power supply IC2A to which a battery voltage output from a battery B1 is supplied as an input voltage Vin. As shown in FIG. 19, various electronic devices X11 to X18 are mounted on the vehicle X. At least one of the electronic devices X11 to X18 operates based on an output voltage Vout output from the DC / DC converter 1. For convenience of illustration, the mounting positions of the electronic devices X11 to X18 in FIG. 19 may differ from the actual positions.

[0091] The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

[0092] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamp) and DRL (daytime running lamp).

[0093] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0094] The electronic device X14 is a braking unit that performs control related to the movement of the vehicle X (ABS (anti-lock brake system) control, EPS (electric power steering) control, electronic suspension control, etc.).

[0095] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and other devices.

[0096] The electronic device X16 is an electronic device that is installed in the vehicle X at the time of shipment from the factory as a standard equipment or a manufacturer option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0097] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0098] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0099] By providing the power supply IC2A in the vehicle X in this way, even if a cold crank phenomenon occurs in which the battery voltage drops, the output voltage Vout can be regulated by seamlessly lowering the switching frequency through frequency division operation, and when the battery voltage recovers, overshoot of the output voltage Vout can be suppressed by clamping the amplifier output voltage.

[0100] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0101] <Additional Notes> As described above, the power supply control device (2A) according to one aspect of the present disclosure has: a high-side transistor (M1) having a first terminal connected to an application terminal of an input voltage (Vin); a low-side transistor (M2) having a first terminal connected to a second terminal of the high-side transistor at a first node; an inductor (L1) connected to the first node; A power supply control device used in a DC / DC converter (1) comprising: a first error amplifier (11) configured to receive a feedback voltage (Vfb) based on an output voltage (Vout) of the DC / DC converter and a first reference voltage (Ref); a second error amplifier (12) configured to receive the output (Comp) of the first error amplifier and a signal (Visns) representing information on the current flowing through the inductor; a first comparator (15) configured to receive the output (Vc) of the second error amplifier and a ramp voltage (Ramp); a switching control unit (16) configured to perform switching control of the high-side transistor and the low-side transistor based on an output of the first comparator; a clamp circuit (20) configured to clamp a second amplifier output voltage (Vc) output from the second error amplifier to a predetermined clamp voltage (Vclamp); Equipped with the switching control unit is capable of a skip operation of skipping the turn-on of the low-side transistor in at least one switching period to maintain the on state of the high-side transistor, The clamp circuit is configured to perform clamping during the skip operation (first configuration).

[0102] In the first configuration, the clamp circuit (20) a first amplifier (20A) configured to receive the second amplifier output voltage and the clamp voltage; The second configuration may further include an NMOS transistor (20B) having a gate to which the output of the first amplifier is input and which is connected between a terminal to which the second amplifier output voltage is applied and the ground.

[0103] In the second configuration, the first reference voltage may be controlled based on a control signal (OUT) serving as a logic signal output from the first amplifier (third configuration).

[0104] In addition, the second configuration may further include a second amplifier (22) configured to receive the second amplifier output voltage and the clamp voltage, and voltage-dividing resistors (R11, R12), and an output current (IOUT) output from the second amplifier is output to a second node (N1) to which the voltage-dividing resistors are connected, and the first reference voltage is generated at the second node (fourth configuration).

[0105] In the first configuration, the clamp circuit includes a third amplifier (20A) configured to receive the second amplifier output voltage and the clamp voltage; A PMOS transistor (23) having a gate to which an output signal (AOUT) output from the third amplifier is input, a source to which an application terminal of a second reference voltage (Vref) is connected, and a drain to which an application terminal of a first amplifier output voltage (Comp) output from the first error amplifier is connected (fifth configuration).

[0106] In any one of the second to fourth configurations, the present invention further includes a clamp circuit control unit (21) configured to receive a high-side on / off signal (Sh) indicating on / off of the high-side transistor and to output an enable signal (Enb) to the first amplifier, The clamp circuit control unit may be configured to change the enable signal to enable when the high-side transistor is maintained in an on state until a predetermined time has elapsed since the high-side transistor was turned on (sixth configuration).

[0107] In addition, in the sixth configuration, the clamp circuit control unit may be configured to change the enable signal to disable when the high-side transistor is turned off after the change to enable and the high-side transistor is turned on a predetermined number of times in succession (seventh configuration).

[0108] In any one of the first to seventh configurations, a light-load mode control unit (16) configured to transition to a sleep operation when a light load is detected; a switch (24) connected between the application terminal of the clamp voltage and the input terminal of the first comparator; The light-load mode control unit may be configured to turn on the switch when a drop in the output voltage during the sleep operation is detected, thereby generating an on-pulse at least once to turn on the high-side transistor based on a comparison between the ramp voltage and the clamp voltage by the first comparator (eighth configuration).

[0109] Furthermore, the eighth configuration may further include a clamp voltage generating circuit (25) configured to generate the clamp voltage based on the output voltage (ninth configuration).

[0110] In any of the first to ninth configurations, the skip may be performed in a variable number of switching periods up to a predetermined maximum number of times (tenth configuration).

[0111] Furthermore, a DC / DC converter (1) according to an embodiment of the present disclosure includes a power supply control device (2A) of any one of the first to tenth configurations, the high-side transistor, the low-side transistor, and the inductor (eleventh configuration).

[0112] Furthermore, a vehicle (X) according to one embodiment of the present disclosure includes the DC / DC converter (1) of the eleventh configuration and a battery (B1) configured to output a battery voltage as the input voltage (twelfth configuration). [Industrial Applicability]

[0113] The present disclosure can be used, for example, in DC / DC converters for various applications. [Explanation of symbols]

[0114] 1 DC / DC converter 2,2A power IC 3 Main Control Block 11,12 Error amplifier 13 Clock generation circuit 14 Lamp voltage generation circuit 15 Comparator 16 Logic Circuits 17 Drivers 18 Current information generation circuit 18A current detection section 18B Pseudo current detection section 18C resistance 19 Comparator 20 Clamp Circuit 20A amplifier 20B NMOS transistor 21 Clamp circuit control section 22 Amplifier 23 PMOS transistor 24 Switch 25 Clamp voltage generation circuit B1 Battery C1 Output capacitor C2 capacitor CLP Clamp circuit D1 rectifier element L1 inductor LD load M1 High-side transistor M2 Low-side transistor MM output stage circuit R1, R2 resistance R11, R12 voltage dividing resistors Ra,Rb,Rc resistance WR1, WR2 wiring X vehicle X11~X18 Electronic equipment ZC Zero cross circuit

Claims

1. a high-side transistor having a first terminal connected to an input voltage application terminal; a low-side transistor having a first terminal connected to a second terminal of the high-side transistor at a first node; an inductor connected to the first node; A power supply control device used in a DC / DC converter comprising: a first error amplifier configured to receive a feedback voltage based on an output voltage of the DC / DC converter and a first reference voltage; a second error amplifier configured to receive the output of the first error amplifier and a signal representing information on the current flowing through the inductor; a first comparator configured to receive the output of the second error amplifier and a ramp voltage; a switching control unit configured to perform switching control of the high-side transistor and the low-side transistor based on an output of the first comparator; a clamp circuit configured to clamp a second amplifier output voltage output from the second error amplifier to a predetermined clamp voltage; Equipped with the switching control unit is capable of a skip operation of skipping the turn-on of the low-side transistor in at least one switching period to maintain the on state of the high-side transistor; The power supply control device, wherein the clamp circuit performs clamping during the skip operation.

2. The clamp circuit a first amplifier configured to receive the second amplifier output voltage and the clamp voltage; an NMOS transistor having a gate to which the output of the first amplifier is input and connected between an application terminal of the second amplifier output voltage and ground; The power supply control device of claim 1 , further comprising:

3. 3. The power supply control device according to claim 2, wherein the first reference voltage is controlled based on a control signal as a logic signal output from the first amplifier.

4. a second amplifier configured to receive the second amplifier output voltage and the clamp voltage; A voltage dividing resistor, Furthermore, an output current output from the second amplifier is output to a second node to which the voltage dividing resistor is connected; 3. The power supply control device of claim 2, wherein the first reference voltage is generated at the second node.

5. The clamp circuit a third amplifier configured to receive the second amplifier output voltage and the clamp voltage; a PMOS transistor having a gate to which an output signal output from the third amplifier is input, a source to which a second reference voltage is applied, and a drain to which a first amplifier output voltage output from the first error amplifier is applied; The power supply control device of claim 1 , further comprising:

6. a clamp circuit control unit configured to receive a high-side on / off signal indicating on / off of the high-side transistor and to output an enable signal to the first amplifier; 3. The power supply control device according to claim 2, wherein the clamp circuit control unit changes the enable signal to enable when the high-side transistor is maintained in an on state until a predetermined time has elapsed since the high-side transistor was turned on.

7. 7. The power supply control device according to claim 6, wherein the clamp circuit control unit changes the enable signal to disable when the high-side transistor is turned on a predetermined number of times after the high-side transistor is turned off after the change to enable.

8. a light load mode control unit configured to transition to a sleep operation when a light load is detected; a switch connected between the clamp voltage application terminal and the input terminal of the first comparator; Furthermore, 2. The power supply control device according to claim 1, wherein the light-load mode control unit turns the switch on when a drop in the output voltage during the sleep operation is detected, thereby generating an on-pulse at least once to turn the high-side transistor on based on a comparison between the ramp voltage and the clamp voltage by the first comparator.

9. The power supply control device of claim 8 , further comprising a clamp voltage generation circuit configured to generate the clamp voltage based on the output voltage.

10. 2. The power supply control device according to claim 1, wherein the skipping is performed for a variable number of the switching periods up to a predetermined maximum number of times.

11. 11. A DC / DC converter comprising: the power supply control device according to claim 1; the high-side transistor; the low-side transistor; and the inductor.

12. A vehicle comprising: the DC / DC converter according to claim 11; and a battery configured to output a battery voltage as the input voltage.

Images