Reference voltage generating circuit

Abstract

To solve a problem of a conventional reference voltage generating circuit which could not reduce an influence of a voltage drift that occurs due to prolonged use.SOLUTION: A reference voltage generating circuit of the present invention comprises: a first reference voltage source circuit 21 that operates constantly and outputs a first reference voltage VREF1; a second reference voltage source circuit 22 that operates intermittently based on an intermittent operation control signal Sint and outputs a second reference voltage VREF2; an intermittent operation control circuit 25 that outputs the intermittent operation control signal Sint; and a voltage drift correction circuit 24 that outputs an output reference voltage VREF_out which corresponds to a first reference voltage VREF1. The voltage drift correction circuit 24 corrects a difference between the first reference voltage VREF1 and the output reference voltage VREF_out so that the output reference voltage VREF_out approaches the second reference voltage VREF2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a reference voltage generating circuit, and more particularly to a reference voltage generating circuit that outputs a reference voltage having a voltage value equivalent to a bandgap voltage. [Background technology]

[0002] In electronic circuits, a reference voltage is sometimes used as a reference for operation. This reference voltage needs to be stable against temperature and power supply voltage fluctuations. Therefore, Patent Document 1 discloses a technique for obtaining a stable reference voltage.

[0003] The bandgap voltage reference circuit disclosed in Patent Document 1 is a bandgap voltage reference circuit including: a current source circuit element for supplying a first current to a first conductor and a second current to a second conductor; a plurality of diodes each having a cathode terminal coupled to a first reference voltage; a first group of switches for selectively coupling the first conductor to an anode terminal of the diode in response to a first digital control signal, respectively, to cause the first current to flow through the selected diode; and a second group of switches for selectively coupling the second conductor to an anode terminal of the diode not selectively coupled to the first conductor in response to the first digital control signal, to cause the second current to flow through the diode not selectively coupled to the first conductor and to be shared among the diodes, wherein the first control signal has a value that continuously couples the diodes to the first conductor, thereby causing the first current to flow through the diodes to a corresponding relatively high V BE a voltage is generated in the first conductor, and the second current causes the continuously coupled diode not coupled to the first conductor to generate a corresponding relatively low VBE voltage in the second conductor, and a relatively high V BE voltage and the corresponding relatively low V BE The difference between the voltages corresponds to ΔV BEa bandgap reference generating circuit that generates a reference voltage equal to the relatively high VBE voltage and the relatively low V BE sampling circuitry for sampling the voltage to generate a differential bandgap charge; and averaging circuitry coupled by first and second output conductors of the sampling circuitry to receive the differential bandgap charge for averaging successive differential gaps to generate a stable bandgap voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2013-525902 Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology described in Patent Document 1, a bandgap reference voltage is constantly generated. However, the bandgap voltage is generated due to the structure and physical properties of the semiconductor element, and voltage drift occurs, in which the voltage changes due to changes in the physical properties over time. When this voltage drift occurs, the reference voltage becomes misaligned, but Patent Document 1 does not disclose or suggest how to resolve the misalignment of the reference voltage caused by voltage drift. [Means for solving the problem]

[0006] A reference voltage generation circuit according to the present invention comprises a first reference voltage source circuit that operates constantly and outputs a first reference voltage, a second reference voltage source circuit that operates intermittently based on an intermittent operation control signal and outputs a second reference voltage, an intermittent operation control circuit that outputs the intermittent operation control signal, and a voltage drift correction circuit that outputs an output reference voltage that conforms to the first reference voltage, and the voltage drift correction circuit corrects the difference between the first reference voltage and the output reference voltage so that the output reference voltage approaches the second reference voltage.

[0007] The reference voltage generating circuit according to the present invention corrects the output reference voltage to match the second reference voltage, which has less voltage deviation due to voltage drift over time. [Effects of the Invention]

[0008] The reference voltage generating circuit according to the present invention can generate an output reference voltage that is stable over time. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram illustrating an example of a reference voltage source circuit according to the first embodiment. [Figure 3] 4 is a graph illustrating a change over time in a bandgap reference voltage according to the first embodiment. [Figure 4] 4 is a timing chart illustrating an operation of the reference voltage generating circuit according to the first embodiment. [Figure 5] FIG. 10 is a block diagram of a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a block diagram of a voltage drift correction circuit according to a second embodiment. [Figure 7] 10 is a timing chart illustrating a second operation example during a correction processing period in the reference voltage generating circuit according to the second embodiment. [Figure 8] 10 is a timing chart illustrating a second operation example during a correction processing period in the reference voltage generating circuit according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiment 1 For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In addition, the same elements in each drawing are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0011] Fig. 1 shows a block diagram of a semiconductor device 1 according to embodiment 1. Fig. 1 shows only a reference voltage generating circuit 10, which is one of the features of the semiconductor device 1 according to embodiment 1, and an analog circuit 11 to which an output reference voltage VREF_out output by the reference voltage generating circuit 10 is applied, among the circuits included in the semiconductor device, but the semiconductor device 1 also includes many other circuits.

[0012] As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a reference voltage generating circuit 10 and an analog circuit 11. The reference voltage generating circuit 10 outputs an output reference voltage VREF_out that is generated based on the bandgap voltage of a semiconductor element. The analog circuit 11 is a functional block that receives the output reference voltage VREF_out and performs a function set in the design. Since the semiconductor device 1 according to the first embodiment is characterized by the reference voltage generating circuit 10, the reference voltage generating circuit 10 will be described in detail below.

[0013] The reference voltage generating circuit 10 includes a first reference voltage source circuit 21, a second reference voltage source circuit 22, a voltage drift correction circuit 24, and an intermittent operation control circuit 25. The first reference voltage source circuit 21 operates constantly and outputs a first reference voltage VREF1. The second reference voltage source circuit 22 operates intermittently based on an intermittent operation control signal Sint and outputs a second reference voltage VREF2. In the example shown in FIG. 1, the second reference voltage source circuit 22 includes a reference voltage source circuit 23 and a switch SW. The on / off state of the switch SW is controlled by the intermittent operation control signal Sint. The second reference voltage source circuit 22 operates the reference voltage source circuit 23 only while the switch SW is in the on state, thereby causing the reference voltage source circuit 23 to operate intermittently. The first reference voltage VREF1 and the second reference voltage VREF2 are generated based on the bandgap voltage of a semiconductor element (e.g., a transistor).

[0014] The voltage drift correction circuit 24 outputs an output reference voltage VREF_out that is based on the first reference voltage VREF1. The intermittent operation control circuit 25 outputs an intermittent operation control signal Sint. During the period in which the second reference voltage source circuit 22 is controlled to be in an operating state by the intermittent operation control signal Sint, the voltage drift correction circuit 24 corrects the difference between the first reference voltage VREF1 and the output reference voltage VREF_out so that the output reference voltage VREF_out approaches the second reference voltage VREF2.

[0015] Here, the first reference voltage source circuit 21 and the second reference voltage source circuit 22 are configured as circuits having substantially the same configuration. The first reference voltage source circuit 21 and the second reference voltage source circuit 22 are bandgap reference voltage source circuits, and although many circuit configurations are possible, an example of the circuit configuration of a bandgap reference voltage source circuit will be described here. Figure 2 shows a circuit diagram illustrating an example of the reference voltage source circuit according to the first embodiment.

[0016] The reference voltage source circuit shown in FIG. 2 includes NMOS transistors NM1 to NM5, PMOS transistors PM1 to PM3, and resistors R11 and R12. The NMOS transistors NM1, NM2, and NM4 are each diode-connected transistors, with their sources connected to the ground wiring. The drain of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM3. The drain of the NMOS transistor NM2 is connected to the source of the NMOS transistor NM4 via the resistor R11. The gate of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM3. The gate of the NMOS transistor NM4 is connected to the gate of the NMOS transistor NM4.

[0017] The gate and source of the PMOS transistor PM2 are connected together. The gates of the PMOS transistors PM1 to PM3 are connected together. The sources of the PMOS transistors PM1 to PM3 are connected to a power supply wiring (for example, a wiring to which a power supply voltage VDD is supplied). The drain of the PMMOS transistor PM1 is connected to the drain of the NMOS transistor NM3. The drain of the PMMOS transistor PM2 is connected to the drain of the NMOS transistor NM4. The drain of the PMMOS transistor PM3 is connected to the drain of the NMOS transistor NM5 via a resistor R12. The reference voltage source circuit outputs a first reference voltage VREF1 or a second reference voltage VREF2 from a node connecting the drain of the PMOS transistor PM3 and the resistor R12.

[0018] In the reference voltage source circuit 23, the NMOS transistors NM1 to NM4, the resistor R11, and the PMOS transistors PM1 and PM2 generate a bandgap current I1 that flows through the PMOS transistor PM2. This bandgap current I1 is then output as a current Io that flows through the PMOS transistor PM3 by a current mirror circuit formed by the PMOS transistors PM1 and PM2. In the reference voltage source circuit, the current Io is passed through the resistor R12 and the NMOS transistor NM5 to generate the first reference voltage VREF1 or the second reference voltage VREF2.

[0019] The first reference voltage VREF1 and the second reference voltage VREF2 thus generated have the characteristic of having stable voltage values ​​against fluctuations in the power supply voltage and temperature. However, as they are continuously output, they also have the characteristic of changing in voltage value due to changes in the characteristics of the transistors that make up the reference voltage source circuit. Therefore, the voltage change over time of the bandgap reference voltage will be explained. Figure 3 shows a graph illustrating the change over time (e.g., voltage drift) of the bandgap reference voltage according to the first embodiment.

[0020] In the semiconductor device 1 according to the first embodiment, the second reference voltage source circuit 22 is operated intermittently, so that the length of the period during which the second reference voltage source circuit 22 operates is set to 1 / 10 or less of the period during which the first reference voltage source circuit 21 operates. More preferably, the length of the period during which the second reference voltage source circuit 22 operates is set to 1 / 100 or less of the period during which the first reference voltage source circuit 21 operates. Therefore, the second reference voltage VREF2 has less voltage drift than the first reference voltage VREF1. FIG. 3 is a graph comparing the first reference voltage VREF1 output by the continuously operating first reference voltage source circuit 21 and the second reference voltage VREF2 output by the intermittently operating second reference voltage source circuit 22.

[0021] As shown in Fig. 3, the bandgap reference voltage experiences voltage drift, which causes the voltage value to rise as the reference voltage source circuit operates for a longer period of time. In the semiconductor device 1 according to the first embodiment, the difference between the first reference voltage VREF1 and the output reference voltage VREF_out is corrected so that the output reference voltage VREF_out matches the second reference voltage VREF2, in which voltage drift caused by factors over time has been suppressed. In Fig. 3, this correction amount is indicated as a voltage correction amount.

[0022] Next, the operation of the reference voltage generation circuit 10 according to the first embodiment will be described. FIG. 4 shows a timing chart illustrating the operation of the reference voltage generation circuit 10 according to the first embodiment. As shown in FIG. 4, in the reference voltage generation circuit 10 according to the first embodiment, the intermittent operation control circuit 25 controls the operating and non-operating periods of the second reference voltage source circuit 22 using the intermittent operation control signal Sint. Also, in the reference voltage generation circuit 10, the intermittent operation control circuit 25 controls whether the voltage drift correction circuit 24 performs a correction amount update process or maintains the correction amount using the intermittent operation control signal Sint. As a result, as shown in FIG. 4, the reference voltage generation circuit 10 constantly outputs the first reference voltage VREF1, and the voltage drift correction circuit 24 outputs the output reference voltage VREF_out based on the first reference voltage VREF1. Also, the reference voltage generation circuit 10 intermittently outputs the second reference voltage VREF2, and the voltage drift correction circuit 24 updates the correction amount applied to the output reference voltage VREF_out in accordance with the timing at which the second reference voltage VREF2 is output.

[0023] As described above, the reference voltage generating circuit 10 according to the first embodiment generates the output reference voltage VREF_out based on the first reference voltage VREF1. The reference voltage generating circuit 10 then intermittently generates the second reference voltage VREF2 to suppress voltage drift over time in the second reference voltage VREF2. The correction amount applied to the output reference voltage VREF_out is then updated based on the second reference voltage VREF2, in which voltage drift over time has been suppressed. This allows the output reference voltage VREF_out output by the reference voltage generating circuit 10 to suppress the influence of voltage drift over time.

[0024] Voltage drift over time occurs over a period of several years, and voltage changes in the reference voltage affect the operational accuracy of the semiconductor device 1. For example, if the semiconductor device 1 is an analog-to-digital conversion circuit, changes in the output reference voltage VREF_out affect the conversion accuracy. However, by using the reference voltage generation circuit 10, the operational accuracy of the semiconductor device 1 can be maintained over a long period of time. In a semiconductor device 1 that is used continuously over a long period of time, the effect of suppressing voltage drift in the output reference voltage VREF_out is significant.

[0025] Embodiment 2 In the second embodiment, a specific example of the voltage drift correction circuit 24 will be described. In the description of the second embodiment, the same components as those described in the first embodiment will be denoted by the same reference numerals as in the first embodiment, and the description thereof will be omitted.

[0026] 5 shows a block diagram of a semiconductor device according to the second embodiment. In the example shown in Fig. 5, an example including a voltage adjustment circuit 31 and a comparator 32 is shown as an example of the voltage drift correction circuit 24. The voltage adjustment circuit 31 generates the output reference voltage VREF_out based on the first reference voltage VREF1, and adjusts the amount of voltage correction applied to the output reference voltage VREF_out so that the voltage value of the output reference voltage VREF_out matches the second reference voltage VREF2.

[0027] More specifically, in the voltage drift correction circuit 24, the comparator 32 compares the voltage value of the second reference voltage VREF2 with the voltage value of the output reference voltage VREF_out, and when the output reference voltage VREF_out becomes higher than the second reference voltage VREF2, the voltage adjustment circuit 31 adjusts the amount of voltage correction to be applied to the output reference voltage VREF_out.

[0028] 6 is a block diagram of the voltage drift correction circuit 24 according to the second embodiment. FIG. 6 illustrates an example of a voltage adjustment circuit 31. In the example shown in FIG. 6, the voltage adjustment circuit 31 includes a control logic circuit 41, a register 42, an operational amplifier 43, a variable resistor R3, and a resistor R4. In the voltage adjustment circuit 31 shown in FIG. 6, a non-inverting amplifier whose gain is determined by (1+R2 / R3) is configured with the variable resistor R3, resistor R2, and operational amplifier 43, and the output reference voltage VREF_out is calculated by (1+R2 / R3)*VREF1. Therefore, the voltage Vcomp to be compared with VREF_out in the comparison circuit of the comparator 32 uses the output of an adjustment amplifier 33 having an gain matching that of the non-inverting amplifier using the operational amplifier 43.

[0029] As described above, the voltage adjustment circuit 31 amplifies the first reference voltage VREF1 using a non-inverting amplifier configured with the variable resistor R3, resistor R2, and operational amplifier 43 to output the output reference voltage VREF_out. At this time, the voltage adjustment circuit 31 increases or decreases the voltage correction amount applied to the output reference voltage VREF_out by changing the resistance value of the variable resistor R3. The variable resistor R3 has resistors R31 to R3n (n is an integer indicating the number of adjustable resistors). The variable resistor R3 also has multiple transistors connected in parallel to each of the resistors R31 to R3n. The variable resistor R3 has the same resistance value as the resistor R2 in its initial state. The variable resistor R3 can be set to a resistance value approximately 1 / 2 to 2 times that of the resistor R2 by adjusting the number of transistors to be turned on in accordance with the correction setting value held in the register 42.

[0030] The adjustment amplifier 33 includes an operational amplifier 51 and resistors R4 and R5. The adjustment amplifier 33 configures a non-inverting amplifier in which the resistors R4 and R5 are set to have the same resistance value, for example, and outputs a comparison reference voltage Vcomp from the second reference voltage VREF2. The comparator 32 compares the magnitude of the comparison reference voltage Vcomp and the output reference voltage VREF_out, and outputs the result as a comparison result signal Comp_o.

[0031] When the comparison result signal Comp_o reaches a first voltage level (for example, a high level) indicating that the output reference voltage VREF_out is higher than the comparison reference voltage Vcomp, the control logic circuit 41 updates the correction set value held in the register 42 based on a preset rule. In this way, the control logic circuit 41 updates the correction set value held in the register 42, thereby updating the resistance value of the variable resistor R3, and thereby changing the voltage value of the output reference voltage VREF_out.

[0032] The register 42 is, for example, a memory, and although a volatile memory such as a dynamic random access memory (DRAM) can be used, a nonvolatile memory such as a flash memory is preferable. By using a nonvolatile memory as the register 42, the voltage correction amount applied up to that point is not lost even when the semiconductor device 1 is powered off and then restarted, and it becomes possible to output the output reference voltage VREF_out with reduced influence of voltage drift even after restart.

[0033] Here, the predetermined rules set in the control logic circuit 41 will be described. In the following description, two operation rules will be described, but other rules can also be applied. In the following, as a first operation example, an example will be described in which a linear search is applied, which changes the amount of correction voltage in preset voltage steps, and as a second operation example, an example will be described in which a binary search is applied, which gradually reduces the amount of correction voltage to be changed. In the following description, for simplicity, the output reference voltage VREF_out and the second reference voltage VREF2 are illustrated as if they have not been amplified by a non-inverting amplifier.

[0034] FIG. 7 is a timing chart illustrating a second operation example of the reference voltage generating circuit 10 according to the second embodiment during the correction processing period. In the example shown in FIG. 7, the period from timings T10 to T16 is the correction processing period during which the intermittent operation control signal Sint is at a high level. When the correction processing period begins, output of the second reference voltage VREF2 begins. At this time, the output reference voltage VREF_out is higher than the second reference voltage VREF2. Therefore, in the first operation example, the comparison result signal Comp_o is referenced after the rising edge of the clock signal input to the control logic circuit 41. If the comparison result signal Comp_o is at a high level, the output reference voltage VREF_out is decreased by a predetermined step size. In the example shown in FIG. 7, the resistance value of the variable resistor R3 is updated at each clock edge from timings T11 to T13 so that the output reference voltage VREF_out decreases.

[0035] FIG. 8 is a timing chart illustrating a second operation example of the reference voltage generating circuit 10 according to the second embodiment during the correction processing period. In FIG. 8, the period from timing T20 to T26 corresponds to the correction processing period during which the intermittent operation control signal Sint is at a high level. When the correction processing period begins, output of the second reference voltage VREF2 begins. At this time, the output reference voltage VREF_out is higher than the second reference voltage VREF2. Therefore, in the second operation example, the comparison result signal Comp_o is referenced at each rising edge of the clock signal input to the control logic circuit 41. If the comparison result signal Comp_o is at a high level, the output reference voltage VREF_out is decreased by a predetermined step size. In the second operation example, if the voltage values ​​of the output reference voltage VREF_out and the second reference voltage VREF2 are reversed, the adjustment step of the output reference voltage VREF_out is reduced, thereby increasing the output reference voltage VREF_out. Then, when the voltage values ​​of the output reference voltage VREF_out and the second reference voltage VREF2 are reversed again, the voltage adjustment range is further reduced to lower the output reference voltage VREF_out. In this way, in the second operation example, the output reference voltage VREF_out is brought closer to the voltage value of the second reference voltage VREF2 while the voltage adjustment range is reduced each time the voltage values ​​of the output reference voltage VREF_out and the second reference voltage VREF2 are reversed.

[0036] As explained above, in the second embodiment, the voltage correction amount determined in the correction amount update process can be used in subsequent operations by storing the correction set value as a digital value in the register 42. Furthermore, by employing a nonvolatile memory as the register 42, even if a state occurs in which the power supply to the semiconductor device 1 is stopped due to a restart or the like, it becomes possible to output the output reference voltage VREF_out with reduced effects of voltage drift in subsequent operations.

[0037] The present invention is not limited to the above-described embodiment, and can be modified as appropriate within the scope of the invention. [Explanation of symbols]

[0038] 1. Semiconductor device 10 Reference voltage generation circuit 11 Analog Circuits 21 First reference voltage source circuit 22 Second reference voltage source circuit 23 Reference voltage source circuit 24 Voltage drift correction circuit 25 Intermittent operation control circuit 31 Voltage Regulator Circuit 32 Comparator 33 Adjustable Amplifier 41 Control logic circuit 42 registers 43 Operational Amplifier 51 Operational Amplifier MP PMOS transistor MN NMOS transistor R1, R2, R4, R5 resistance R3 variable resistor Sint Intermittent operation control signal VREF1 First reference voltage VREF2 Second reference voltage VREF_out output reference voltage Vcomp Comparison reference voltage Comp_o Comparison result signal Scnt Resistance control signal

Claims

1. a first reference voltage source circuit that is constantly operating and outputs a first reference voltage; a second reference voltage source circuit that operates intermittently based on an intermittent operation control signal and outputs a second reference voltage; an intermittent operation control circuit that outputs the intermittent operation control signal; a voltage drift correction circuit that outputs an output reference voltage that is based on the first reference voltage; The voltage drift correction circuit is a reference voltage generating circuit that corrects the difference between the first reference voltage and the output reference voltage so that the output reference voltage approaches the second reference voltage.

2. 2. The reference voltage generation circuit according to claim 1, wherein the voltage drift correction circuit performs a correction amount update process to update a voltage correction amount to be applied to the output reference voltage while the second reference voltage source circuit is operating, based on the intermittent operation control signal, and after the correction amount update process, holds the correction voltage applied to the output reference voltage.

3. 3. The reference voltage generating circuit according to claim 2, wherein the voltage drift correction circuit updates the voltage correction amount every time the correction amount update process is executed.

4. 2. The reference voltage generating circuit according to claim 1, wherein the first reference voltage source circuit and the second reference voltage source circuit output bandgap voltages generated by the same circuit configuration as the first reference voltage and the second reference voltage.

5. 2. The reference voltage generation circuit according to claim 1, wherein the intermittent operation control circuit generates the intermittent operation control signal so that the length of the operation period of the second reference voltage source circuit is 1 / 10 or less of the length of the operation period of the first reference voltage source circuit.

6. 2. The reference voltage generating circuit according to claim 1, wherein the voltage drift correction circuit stores the voltage correction amount applied to the output reference voltage in a nonvolatile memory.

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