Semiconductor device
The semiconductor device integrates a self-power management circuit to manage power supply sequences and ramp times, addressing the complexity of SoC power supply specifications and simplifying external control circuits, ensuring reliable operation.
Patent Information
- Application Number
- JP2024066679
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-04-17
- Publication Date
- 2025-10-29
AI Technical Summary
Recent SoCs require complex power supply specifications including multiple power lanes with different voltages, specific power-on and power-off sequences, and ramp times, which are currently managed by external power supply circuits, posing a risk of malfunction or damage if not correctly controlled.
A semiconductor device with an integrated self-power management circuit that generates control signals for multiple power supply lanes, managing power-up and power-down sequences and ramp times internally, simplifying the need for external control circuits.
The semiconductor device effectively controls multiple external power supply circuits, ensuring compliance with SoC specifications, reducing the complexity of external power supply circuits, and minimizing the risk of malfunction or damage.
Smart Images
Figure 2025163434000001_ABST
Abstract
Description
[Technical Field]
[0001] FIELD An embodiment of the present disclosure relates to a semiconductor device. [Background technology]
[0002] In recent years, the power supply voltage of SoC (System on Chip) has become lower and the current has become larger due to the miniaturization of processes and the improvement of performance. In addition, the internal configuration of SoC has become more complex, which has led to the demand for a variety of power supply functional specifications (see, for example, Patent Document 1). [Prior art documents] [Non-patent literature]
[0003] [Non-Patent Document 1] Renesas Electronics RAA271000 (General-Purpose Power Management IC for the Renesas R-Car SoC series) datasheet: https: / / www.renesas.com / jp / ja / document / dst / raa271000-datasheet?r=1497496 Summary of the Invention [Problem to be solved by the invention]
[0004] Recent computing SoCs for AI processing, etc., have been using lower voltage and higher current power supplies due to process miniaturization and higher performance. In addition, as the internal configuration of SoCs becomes more complex, the following functional specifications for power supplies are now required: (1) to (4). (1) There are multiple types of power lanes (power lanes with different voltages, and different power lanes with the same voltage). (2) When powering on an SoC, there is a specification for the order (sequence) in which multiple power lanes are started up. (3) When powering off an SoC, there is a regulation for the order (sequence) in which multiple power lanes must be shut down. (4) Some power lanes specify the rise time (ramp time).
[0005] These power supply specifications were all achieved by external power supply circuits, as shown in Figure 5. Therefore, it was necessary to control the external circuits to match the power supply functional specifications for each SoC, as shown in Figure 6. In the example of Figure 5, the power supply lanes for the SoC are VDD, VCORE, and VCC, and if the respective voltages are V1, V2, ..., Vn, the SoC requires the following specifications. Power-on sequence: Power on in the order of V2 → Vn → V1, with the time interval specified by tON2n and tONn1 Power supply shutdown sequence: Shuts down in the order of V1 → Vn → V2, with time intervals specified by tOF1n and tOFn2 The rise time (ramp time) of V1 is specified by tR1 The rise time (ramp time) of V2 is specified by tR2 If the above regulations are not observed, the SoC may malfunction or even be destroyed. For this reason, the power management circuit must generate the enable signals (EN1, EN2, ..., ENn) for each power circuit and the reference voltage signals (VREF1, VREF2) for controlling the rise time (ramp time) in accordance with the SoC specifications, as shown in Figure 6.
[0006] The present disclosure aims to provide a semiconductor device that can simplify an external power supply circuit. [Means for solving the problem]
[0007] The semiconductor device disclosed herein is a semiconductor device having a plurality of power supply lanes that each receive power from a plurality of external power supply circuits, and is equipped with a self-power management circuit that outputs a plurality of control signals that respectively control the plurality of power supply circuits. [Effects of the Invention]
[0008] The semiconductor device of the present disclosure can control a plurality of external power supply circuits, thereby simplifying the external power supply circuits. [Brief explanation of the drawings]
[0009] [Figure 1] 1 is a diagram illustrating a configuration of an embodiment of a semiconductor device; [Figure 2] 2 is a waveform diagram showing an example of functional specifications of a power supply lane of the semiconductor device shown in FIG. 1. [Figure 3] FIG. 2 is a diagram illustrating a configuration example of a self-power management circuit. [Figure 4] 4A and 4B are waveform diagrams of an enable signal and a reference voltage signal. [Figure 5] 1 is an example of a prior art SoC power management circuit. [Figure 6] 2 is an example of a control waveform of a conventional SoC power management circuit. DETAILED DESCRIPTION OF THE INVENTION
[0010] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.
[0011] The semiconductor device of this embodiment is an SoC1 configured with devices of various functions. Referring to FIG. 1, the SoC1 includes a CPU 11, a GPU 12, a cache 13, and other peripheral devices 14 as devices of various functions. The SoC1 includes multiple power supply lanes VDD, VCORE, and VCC, and operates by receiving power supply voltages (V1, V2, Vn) for each power supply lane from an external power supply block. Note that the power supply lanes of the SoC are not limited to VDD, VCORE, and VCC shown here. There are generally many other power supply lanes.
[0012] The SoC 1 includes an auxiliary power supply circuit 2 configured with an LDO (Low Drop Out) regulator, and an autonomous power management circuit 3. The auxiliary power supply circuit 2 is a circuit that generates power for the autonomous power management circuit 3 to operate from the main input voltage VIN.
[0013] The self-power management circuit 3 receives power from the auxiliary power circuit 2 and outputs an enable signal ENx and a reference voltage signal VREFx to an external power block. The enable signal ENx is a control signal that controls the power-up sequence (power-up order and time interval) and power-down sequence (power-down order and time interval) of multiple power lanes. The reference voltage signal VREFx is a ramp control control signal that controls the rise time (ramp time). The self-power management circuit 3 also generates a reset signal RESETn to the inside of the SoC1.
[0014] The power supply block includes power supply ICs 201, 202, and 203 that generate power supply voltages (V1, V2, and Vn) for each of the multiple power supply lanes included in the SoC1. n Each of them is equipped with power supply ICs 201, 202, and 20 n The enable signal ENx is generated by the power supply ICs 201, 202, and 203 of the power supply lane, which have a defined sequence (start-up, shutdown). n The reference voltage signal VREFx is output to the power supply ICs 201 and 202 of the power supply lane, which have a specified rise time (ramp time).
[0015] Figure 2 shows an example of the functional specifications for the power supply voltages V1, V2, and Vn of the power supply lanes VDD, VCORE, and VCC of SoC1, and specifies the start-up sequence, the shut-down sequence, and the ramp time.
[0016] The start-up sequence is in the order of power supply voltage V2, power supply voltage Vn, and power supply voltage V1, and the time tON2n from the completion of the start-up of power supply voltage V2 to the start-up of power supply voltage Vn, and the time tONn1 from the start-up of power supply voltage Vn to the start-up of power supply voltage V1 are specified.
[0017] The fall sequence is power supply voltage V1, power supply voltage Vn, power supply voltage V2 in that order, and a time tOF1n from the start of fall of power supply voltage V1 to the start of fall of power supply voltage Vn, and a time tOFn2 from the start of fall of power supply voltage Vn to the start of fall of power supply voltage V2 are specified.
[0018] The ramp time is defined as a time tR1 from when the power supply voltage V1 starts to rise until it reaches a predetermined level, and a time tR2 from when the power supply voltage V2 starts to rise until it reaches a predetermined level.
[0019] The self-power management circuit 3 controls all power supply ICs 201, 202, and 203 that receive power. n The power management circuit 3 controls the power-up sequence and the power-down sequence by outputting enable signals EN1, EN2, and ENn to the power supply ICs 201, 202, and 203, respectively. n For those with specified ramp times, the ramp times are controlled by outputting reference voltage signals VREF1 and VREF2. In other words, the SoC1 itself, which receives power from the outside for multiple power lanes, incorporates an internal power management circuit 3 and outputs signals that control the sequence and rise time (ramp time) of the power supply ICs that supply power to each power lane.
[0020] 3, the power supply self-management circuit 3 includes an internal oscillator 31 for internal logic operation, a VIN voltage detection circuit 32, and delay circuits 331 and 332. The VIN voltage detection circuit 32 is composed of a voltage comparator and the like, and monitors the input voltage VIN to perform start-up detection and shutdown detection.
[0021] The self-power management circuit 3 includes a flip-flop 34 EN1 , 34 EN2 , 34 ENn , 34 RESET Flip-flop 34 EN1 , 34 EN2 , 34 ENn are provided at the output stages of the enable signals EN1, EN2, and ENn, respectively, and assert the enable signals EN1, EN2, and ENn by setting them, and negate them by resetting them. RESETis provided at the output stage of the reset signal RESETn, and sets the reset signal RESETn to high level by setting (negative logic negate) and to low level by resetting (negative logic assert).
[0022] The self-power management circuit 3 includes a delay counter 35 ON2n , 35 ONn1 , 35 OF1n , 35 OFn2 , 35 R1 , 35 R2 Delay counter 35 ON2n , 35 ONn1 The delay counter 35 counts the times tON2n and tONn1 specified in the startup sequence. OF1n , 35 OFn2 The delay counter 35 counts the times tOF1n and tOFn2 defined in the falling sequence. R1 , 35 R2 counts the ramp times tR1 and tR2.
[0023] The self-power management circuit 3 is connected to the D / A converter 36 REF1 , 36 REF2 and Data Selector 37 REF1 , 37 REF2 and D / A converter 36. REF1 , 36 REF2 delay counter 35 R1 , 35 R2 The data selector 37 converts the count values (digital inputs) of the above into analog voltages and outputs them as reference voltage signals VREF1 and VREF2. REF1 , 37 REF2 D / A converter 36 REF1 , 36 REF2 The digital input to the delay counter 35 R1 , 35 R2 It is a circuit that switches between a positive and a negative value.
[0024] The operation of the power supply self-management circuit 3 will be described with reference to FIG. At time t0, when the VIN voltage detection circuit 32 detects that the applied VIN voltage has reached a preset startup voltage, at time t1, the delay circuit 331 outputs a startup detection signal. EN2 , and asserts the enable signal EN2, and the delay counter 35 R2 Delay counter 35 starts counting. R2 is a counter that counts the ramp time tR2 of the reference voltage signal VREF2. R2 The count value of the D / A converter is REF2 The reference voltage signal VREF2 converted into an analog signal by is set to reach a predetermined voltage at time t2 after the ramp time tR2 has elapsed.
[0025] Delay Counter 35 R2 When the delay counter overflows at time t2, ON2n Delay counter 35 starts counting. ON2n is a counter that counts the time tON2n specified in the start-up sequence. ON2n When the overflow occurs at time t3, flip-flop 34 ENn , and asserts the enable signal ENn, and the delay counter 35 ONn1 Delay counter 35 starts counting. ONn1 is a counter that counts the time tONn1 specified in the start-up sequence. ONn1 When the delay counter overflows at time t4, the delay counter R1 Delay counter 35 starts counting. R1 is a counter that counts the ramp time tR1. R1 The count value of the D / A converter is REF1 The reference voltage signal VREF1 converted into an analog signal by is set to reach a predetermined voltage at time t5 after the ramp time tR2 has elapsed.
[0026] Delay Counter 35R1 When the overflow occurs at time t5, the delay circuit 332 delays the output of the flip-flop 34 at time t6. RESET is set, and the reset signal RESETn becomes high level (negative logic negate).
[0027] This allows multiple external power supply ICs 201, 202, and 20 n The enable signals EN1, EN2, and ENn are asserted in a specified order and at specified time intervals. The reference voltage signals VREF1 and VREF2 are fed to the delay counter 35 R1 , 35 R2 , D / A converter 36 REF1 , 36 REF2 is generated.
[0028] Next, at time t10, when the VIN voltage detection circuit 32 detects that the applied VIN voltage has fallen below a preset cutoff voltage, a cutoff detection signal is output from the delay circuit 331 at time t11. EN1 resets the enable signal EN1, negates the enable signal EN1, and REF1 The data is input to the data selector 37. REF1 D / A converter 36 REF1 This causes the reference voltage signal VREF1 to the power supply IC201 to drop to zero potential at the timing when the enable signal EN1 connected to the same power supply IC201 is negated.
[0029] The interruption detection signal is output from the flip-flop 34 RESETn The reset signal RESETn is set to a low level (negative logic assertion), and the delay counter 35 OF1n Delay counter 35 starts counting. OF1n is a counter that counts the time tOF1n specified in the falling edge sequence. OF1nWhen the overflow occurs at time t12, flip-flop 34 ENn resets the enable signal ENn, negates the enable signal ENn, and the delay counter 35 OFn2 Start counting.
[0030] Delay Counter 35 OFn2 is a counter that counts the time tOFn2 specified in the falling edge sequence. OFn2 When the overflow occurs at time t13, flip-flop 34 EN2 resets the enable signal EN2, negates the enable signal EN3, and REF2 The data is input to the data selector 37. REF2 D / A converter 36 REF2 This causes the reference voltage signal VREF2 to the power supply IC202 to drop to zero potential at the timing when the enable signal EN2 connected to the same power supply IC202 is negated.
[0031] This allows multiple external power supply ICs 201, 202, and 20 n The enable signals EN1, EN2, and ENn are negated in a specified order at specified time intervals. The reference voltage signals VREF1 and VREF2 fall to zero potential at the timing when the enable signals EN1 and EN2 connected to the same power supply ICs 201 and 202 are negated.
[0032] Since the self-power management circuit 3 is built into the SoC1, it can be controlled by external power supply ICs 201, 202, and 203 depending on the operating state of the SoC1. n By outputting a status notification signal to the power supply ICs 201, 202, and 203, the power supply characteristics can be changed. Although not shown in the figure, the power supply management circuit 3 outputs a status notification signal while the processing load of the SoC 1 is light and power consumption is reduced. n By lowering the switching frequency or changing the transfer function of the feedback control, the power supply ICs 201, 202, and 20 nThe power consumption of the device itself can be reduced.
[0033] As described above, in this embodiment, a plurality of external power supply ICs 201, 202, and 203 are connected to the power supply ICs 201, 202, and 203. n The SoC1 (semiconductor device) has a plurality of power supply lanes VDD, VCORE, and VCC that receive power supply voltages V1, V2, and Vn from a power supply circuit. n The power supply control circuit 3 outputs a plurality of control signals for controlling the power supply, the power supply and the inverter, respectively. With this configuration, SoC1 (self-power management circuit 3), which receives power supply voltages V1, V2, and Vn to multiple power supply lanes VDD, VCORE, and VCC, can control multiple external power supply circuits, thereby simplifying the external power supply circuits.
[0034] Furthermore, according to this embodiment, the plurality of control signals are transmitted to the plurality of power supply ICs 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, n The enable signals EN1, EN2, and ENn control the order and time intervals of rising and falling of the power supply voltages V1, V2, and Vn from the power supply terminals V1, V2, and Vn. With this configuration, SoC1 (self-power management circuit 3) can control the sequence of power supply voltages V1, V2, and Vn, so that the external power supply circuit can be simplified without the need to prepare a sequence control circuit for each different product.
[0035] Furthermore, according to this embodiment, the control signals are reference voltage signals VREF1 and VREF2 that control the ramp time when the power supply is turned on, and the reference voltage signals VREF1 and VREF2 fall to zero potential at the timing of negation of the enable signals EN1 and EN2 input to the same power supply ICs 201 and 202. With this configuration, SoC1 (self-power management circuit 3) can control the ramp times of the power supply voltages V1, V2, and Vn, so the external power supply circuit can be simplified without the need to prepare a circuit for ramp time control for each different product.
[0036] The reference voltage signals VREF1 and VREF2 are not limited to controlling the rise (ramp) time of the power supply voltage. For SoC1 that requires slope control when the power supply voltage falls, the reference voltage signals VREF1 and VREF2 can be gradually lowered to meet the desired specifications rather than being abruptly reduced to zero potential.
[0037] It is clear that the present invention is not limited to the above-described embodiments, and that each embodiment can be appropriately modified within the scope of the technical concept of the present invention. Furthermore, the number, position, shape, etc. of the above-described components are not limited to the above-described embodiments, and the number, position, shape, etc. can be set to be suitable for implementing the present invention. Note that the same components are denoted by the same reference numerals in each drawing. [Explanation of symbols]
[0038] 1 SoC 2 Auxiliary power circuit 3 Self-power management circuit 201, 202, 20 n power supply IC 31 Internal oscillator 32 VIN voltage detection circuit 331, 332 delay circuits 34 EN1 , 34 EN2 , 34 ENn , 34 RESET flip flop 35 ON2n , 35 ONn1 , 35 OF1n , 35 OFn2 , 35 R1 , 35 R2 Delay Counter 36 REF1 , 36 REF2 D / A converter 37 REF1 , 37 REF2 Data Selector EN1, EN2, ENn enable signals VREF1, VREF2 Reference voltage signals
Claims
1. A semiconductor device including a plurality of power supply lanes each receiving power from a plurality of external power supply circuits, A self-power management circuit outputs a plurality of control signals for controlling the plurality of power supply circuits, respectively. A semiconductor device characterized by:
2. 2. The semiconductor device according to claim 1, wherein the plurality of control signals are a plurality of enable signals that control the order and time intervals of power-on and power-off of the plurality of power supply circuits.
3. 2. The semiconductor device according to claim 1, wherein the plurality of control signals are a plurality of reference voltage signals for controlling a slope when power is turned on or off.