Semiconductor device, electronic equipment, vehicle

Abstract

To control the discharge current flowing during active discharge.SOLUTION: Semiconductor devices (1, 1H, 1L) comprise drive circuits (M1, M2) for turning on or off switch elements (2H, 2L) of a drive target during normal operation (ACD_EN=L), and active discharge circuits (M3, M4) for soft-turning on or soft-turning off the switch elements (2H, 2L) more gently than the drive circuits (M1, M2) during active discharge (ACD_EN=H).SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present disclosure relates to a signal transmission device, an electronic device, and a vehicle. [Background technology]

[0002] Conventionally, signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system from the secondary circuit system have been used in various applications (such as power supply devices or motor drive devices).

[0003] An example of the prior art related to the above is Patent Document 1 by the applicant of the present application. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 070944

[0005] [overview] However, in the conventional signal transmission device, there is room for consideration regarding active discharge, which discharges the capacitor via the half-bridge output stage to be driven.

[0006] For example, a semiconductor device according to the present disclosure includes a drive circuit configured to turn on or off a switch element to be driven during normal driving, and an active discharge circuit configured to soft-turn on or soft-turn off the switch element more slowly than the drive circuit during active discharge. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3]FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram showing the overall configuration of the electronic device. [Figure 11] FIG. 11 is a diagram showing a first embodiment (comparative example) of an electronic device. [Figure 12] FIG. 12 is a diagram showing active discharge in the first embodiment. [Figure 13] FIG. 13 is a diagram showing a second embodiment of the electronic device. [Figure 14] FIG. 14 is a diagram showing active discharge in the second embodiment. [Figure 15] FIG. 15 is a diagram showing a third embodiment of the electronic device. [Figure 16] FIG. 16 is a diagram showing a fourth embodiment of the electronic device. [Figure 17] FIG. 17 is a diagram showing input / output logic of a semiconductor device. [Figure 18] FIG. 18 is a diagram showing active discharge according to the fourth embodiment. [Figure 19] FIG. 19 is a diagram illustrating an example of a configuration of a semiconductor device. [Figure 20] FIG. 20 is a diagram illustrating an example of soft turn-on control. [Figure 21]FIG. 21 is a diagram illustrating an example of soft turn-off control. [Figure 22] FIG. 22 is a diagram showing the exterior of the vehicle.

[0008] [Detailed explanation] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0014] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0020] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0024] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0032] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0038] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0044] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0074] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0081] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0085] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connecting wire 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wire 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wire 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wire 81 is formed spaced apart from the low-potential connecting wire 72 in a plan view and does not face the low-potential connecting wire 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wire 72 and the high-potential connecting wire 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0088] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. The plurality of pad plug electrodes 82 each have a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0089] Referring to FIG. 7, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from that of the high potential coil 23 and the low potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil in the transformers 21A to 21D and suppresses the electric field concentration on the high potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to that of the high potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to that of the high potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include circuitry in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuitry may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0106] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0112] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0113] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0114] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0120] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiments of the present disclosure can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0132] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0133] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0135] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0151] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0153] <Electronic equipment (overall configuration)> 10 is a diagram showing the overall configuration of an electronic device A. Electronic device A includes an upper gate driver IC1H(u / v / w), a lower gate driver IC1L(u / v / w), upper power transistors 2H(u / v / w), lower power transistors 2L(u / v / w), an ECU (electronic control unit) 3, a motor 4, and a capacitor C.

[0154] The upper gate drivers IC1H(u / v / w) drive the upper power transistors 2H(u / v / w) by generating upper gate drive signals in response to upper gate control signals input from the ECU 3 while insulating the ECU 3 from the upper power transistors 2H(u / v / w).

[0155] The lower gate drivers IC1L(u / v / w) drive the lower power transistors 2L(u / v / w) by generating lower gate drive signals in response to lower gate control signals input from the ECU 3 while insulating the ECU 3 from the lower power transistors 2L(u / v / w).

[0156] The signal transmission device 200 described above can be suitably used as the upper gate driver IC1H(u / v / w) and the lower gate driver IC1L(u / v / w).

[0157] The upper power transistors 2H (u / v / w) are connected between the application terminal of the first power supply voltage PVDD and each phase input terminal of the motor 4 as upper switch elements that form a three-phase (U phase / V phase / W phase) half-bridge output stage.

[0158] The lower power transistors 2L (u / v / w) are connected between each phase input terminal of the motor 4 and the application terminal of the second power supply voltage PVEE as lower switch elements that form a three-phase (U phase / V phase / W phase) half-bridge output stage.

[0159] In this figure, IGBTs (insulated gate bipolar transistors) are used as the upper power transistors 2H(u / v / w) and the lower power transistors 2L(u / v / w). However, the upper power transistors 2H(u / v / w) and the lower power transistors 2L(u / v / w) may be replaced with Si devices, SiC devices, or GaN devices.

[0160] The ECU 3 controls the rotational driving of the motor 4 by driving the upper power transistors 2H (u / v / w) and the lower power transistors 2L (u / v / w) via the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), respectively.

[0161] The motor 4 is a three-phase motor that is rotationally driven in response to three-phase drive voltages U / V / W input from three-phase (U-phase / V-phase / W-phase) half-bridge output stages.

[0162] The capacitor C is connected in parallel to the half-bridge output stage between the application terminal of the first power supply voltage PVDD and the application terminal of the second power supply voltage PVEE.

[0163] In this way, the signal transmission device 200 (insulated gate driver IC) can be applied to, for example, an inverter circuit for driving a motor.

[0164] <Considerations regarding the discharge of capacitor C> When it is necessary to discharge the capacitor C, a high-voltage switch for short-circuiting between the application terminal of the first power supply voltage PVDD and the application terminal of the second power supply voltage PVEE and a current-limiting resistor for limiting the current flowing through the high-voltage switch are generally provided (neither is shown in FIG. 10). However, both the high-voltage switch and the current-limiting resistor are expensive.

[0165] In view of the above considerations, an embodiment is proposed below that allows the capacitor C to be discharged without requiring a high-voltage switch and a current-limiting resistor.

[0166] <Electronic Device (First Embodiment)> 11 is a diagram showing a first embodiment (a comparative example to be compared with the second to fifth embodiments described later) of an electronic device A. The electronic device A of this embodiment is based on the above-mentioned FIG. 10 and includes the same semiconductor device 1 as an upper gate driver IC1H and a lower gate driver IC1L.

[0167] The upper power transistor 2H and the lower power transistor 2L correspond to a first switch element and a second switch element connected in series between an application terminal of the first power supply voltage PVDD and an application terminal of the second power supply voltage PVEE to form a half-bridge output stage. The upper gate driver IC1H corresponds to a first drive device that drives the upper power transistor 2H. The lower gate driver IC1L corresponds to a second drive device that drives the lower power transistor 2L.

[0168] The upper gate driver IC1H, the lower gate driver IC1L, the upper power transistor 2H, and the lower power transistor 2L may each be any of the U-phase, V-phase, and W-phase. That is, the output voltage POUT appearing at the connection node between the source of the upper power transistor 2H and the drain of the lower power transistor 2L may be any of the three-phase drive voltages U / V / W.

[0169] The upper gate driver IC1H and the lower gate driver IC1L each include a transistor M1 (e.g., a P-channel MOSFET [metal oxide semiconductor field effect transistor]), a transistor M2 (e.g., an N-channel MOSFET), a transistor M3 (e.g., an N-channel MOSFET), and external terminals T1 to T3 and T4 to T7. Resistors R11 to R13 are externally connected to the upper gate driver IC1H. Resistors R21 to R23 are externally connected to the lower gate driver IC1L.

[0170] Transistor M1 connects / disconnects the connection between the terminal to which the positive power supply voltage VCC2 is applied and external terminal T1. A resistor R11 is connected externally between the external terminal T1 of the high-side gate driver IC1H and the gate of the high-side power transistor 2H. A resistor R21 is connected externally between the external terminal T1 of the low-side gate driver IC1L and the gate of the low-side power transistor 2L. The external terminal T1 can be understood as an output terminal for turn-on during normal driving.

[0171] The transistor M2 connects / disconnects the connection between the application terminal of the negative power supply voltage VEE2 and the external terminal T2. A resistor R12 is connected externally between the external terminal T2 of the high-side gate driver IC1H and the gate of the high-side power transistor 2H. The resistor R12 may have the same resistance value as the resistor R11 or a different resistance value. A resistor R22 is connected externally between the external terminal T2 of the low-side gate driver IC1L and the gate of the low-side power transistor 2L. The resistor R22 may have the same resistance value as the resistor R21 or a different resistance value. The external terminal T2 can be understood as an output terminal for turn-off during normal driving.

[0172] The transistor M3 connects / disconnects the connection between the application terminal of the negative power supply voltage VEE2 and the external terminal T3. A resistor R13 is connected externally between the external terminal T3 of the high-side gate driver IC1H and the gate of the high-side power transistor 2H. The resistor R13 has a higher resistance value than the resistor R12. A resistor R23 is connected externally between the external terminal T3 of the low-side gate driver IC1L and the gate of the low-side power transistor 2L. The resistor R23 has a higher resistance value than the resistor R22. The external terminal T3 can be understood as an output terminal for soft turn-off.

[0173] An upper gate drive signal GH is applied to the gate of the upper power transistor 2H, and a lower gate drive signal GL is applied to the gate of the lower power transistor 2L.

[0174] The external terminal T5 of the high-side gate driver IC1H is connected to an application terminal of the high-side input pulse signal INH. The external terminal T5 of the low-side gate driver IC1L is connected to an application terminal of the low-side input pulse signal INL. The external terminal T5 can be understood as an input terminal.

[0175] The external terminal T6 of the high-side gate driver IC1H is connected to an application terminal of the active discharge control signal ACD_EN. The external terminal T6 of the low-side gate driver IC1L is in an open state or a pull-down state. The external terminal T6 can be understood as an active discharge control terminal.

[0176] The external terminal T7 of the high-side gate driver IC1H is connected to the application terminal of the output voltage PVOUT. The external terminal T7 of the low-side gate driver IC1L is connected to the application terminal of the second power supply voltage PVEE. The external terminal T7 can be understood as a reference voltage terminal (ground terminal).

[0177] The ECU 3 generates the high-side input pulse signal INH, the low-side input pulse signal INL, and the active discharge control signal ACDC_EN. In other words, the ECU 3 corresponds to a control device that controls the high-side gate driver IC1H and the low-side gate driver IC1L.

[0178] <Turn-on / Turn-off / Soft turn-off> When the high-side gate driver IC1H turns on the high-side power transistor 2H, it turns on the transistor M1 and turns off the transistors M2 and M3. At this time, a current flows from the application terminal of the positive power supply voltage VCC2 to the gate of the high-side power transistor 2H via the transistor M1 and the resistor R11. Therefore, the high-side gate drive signal GH, and in turn, the applied voltage ON of the external terminal T1, rises from low to high. As a result, the high-side power transistor 2H is turned on. The slew rate of the high-side gate drive signal GH when it is turned on can be adjusted by the resistance value of the resistor R11.

[0179] On the other hand, when the high-side gate driver IC1H turns off the high-side power transistor 2H, it turns on the transistor M2 and turns off the transistors M1 and M3. At this time, a current flows from the gate of the high-side power transistor 2H to the terminal to which the negative power supply voltage VEE2 is applied via the resistor R12 and the transistor M2. Therefore, the high-side gate drive signal GH, and in turn, the applied voltage OFF of the external terminal T2, falls from high to low. As a result, the high-side power transistor 2H is turned off. The slew rate of the high-side gate drive signal GH when it is turned off can be adjusted by the resistance value of the resistor R12.

[0180] Furthermore, when the high-side gate driver IC1H soft-turns off the high-side power transistor 2H, it turns on transistor M3 and turns off transistors M1 and M2. At this time, a current flows from the gate of the high-side power transistor 2H to the terminal to which the negative power supply voltage VEE2 is applied via resistor R13 and transistor M3. Therefore, the high-side gate drive signal GH, and in turn, the applied voltage STOFF of the external terminal T3, falls from high to low. As a result, the high-side power transistor 2H is soft-turned off. The slew rate of the high-side gate drive signal GH during soft turn-off can be adjusted by the resistance value of resistor R13. Note that the slew rate during soft turn-off is lower than the slew rate during normal turn-off.

[0181] The same applies to the low-side gate driver IC1L. That is, the slew rate at turn-on, turn-off, and soft turn-off of the low-side gate drive signal GL can be adjusted by the resistance values ​​of the resistors R21 to R23, respectively.

[0182] Furthermore, in electronic device A, the upper gate driver IC1H and the lower gate driver IC1L are controlled so as to discharge the capacitor C via the one-phase upper power transistor 2H and the one-phase lower power transistor 2L, respectively, without requiring a high-voltage switch and a current-limiting resistor. This type of discharge control is called active discharge.

[0183] <Active Discharge (First Embodiment)> 12 is a diagram showing active discharge performed in the electronic device A of the first embodiment. In this diagram, from top to bottom, the active discharge control signal ACD_EN, the upper input pulse signal INH, the lower input pulse signal INL, the upper gate drive signal GH, the lower gate drive signal GL, and the discharge current Icap of the capacitor C are depicted.

[0184] The discharge current Icap is defined as a positive direction (direction during charging) from the application terminal of the first power supply voltage PVDD via capacitor C to the application terminal of the second power supply voltage PVEE, and a negative direction (direction during discharging) from the application terminal of the second power supply voltage PVEE via capacitor C to the application terminal of the first power supply voltage PVDD.

[0185] The dashed dotted lines in the figure indicate the on-threshold voltages VthH and VthL of the upper power transistor 2H and the lower power transistor 2L, respectively.

[0186] At time t1, the high-side input pulse signal INH rises from low to high. At this time, the high-side gate drive signal GH rises from low to high at a slew rate that corresponds to the resistance value of resistor R11. As a result, the high-side power transistor 2H is turned on without delay.

[0187] At time t2, the high-side input pulse signal INH falls from high to low. At this time, the active discharge control signal ACD_EN is at high. Therefore, the high-side gate drive signal GH falls gradually from high to low at a slew rate that corresponds to the resistance value of the resistor R13. As a result, the high-side power transistor 2H is soft-turned off gradually over a predetermined transition time.

[0188] On the other hand, at time t3, when the high-side power transistor 2H is soft-turned off, the low-side input pulse signal INL rises from low to high. At this time, the low-side gate drive signal GL rises from low to high at a slew rate that corresponds to the resistance value of the resistor R21. As a result, the low-side power transistor 2L is turned on without delay.

[0189] At time t4, when the high-side power transistor 2H is soft-turned off, the low-side input pulse signal INL falls from high to low. At this time, the low-side gate drive signal GL falls from high to low at a slew rate that corresponds to the resistance value of the resistor R22. As a result, the low-side power transistor 2L is turned off without delay.

[0190] In this way, by turning on the lower power transistor 2L at the timing when the upper power transistor 2H is soft turned off, the discharge current Icap of the capacitor C flows in the half-bridge output stage, and active discharge is performed for the capacitor C. Note that, as shown in this figure, the turn-on / turn-off of the lower power transistor 2L may be repeated even after time t4 until the discharge current Icap stops flowing to the capacitor C.

[0191] In the above-described active discharge, a fluctuation component (dV / dt) occurs in the drain-source voltage Vds(2H) of the upper power transistor 2H as the lower power transistor 2L is turned on / off.

[0192] At this time, a mirror current Im (=Cres×dV / dt) corresponding to the above-mentioned fluctuation component (dV / dt) and the feedback capacitance Cres associated with the upper power transistor 2H flows through the gate of the upper power transistor 2H. Therefore, a fluctuation component (Im×R13) also occurs in the upper gate drive signal GH as the lower power transistor 2L is turned on / off. Although not shown separately, the same applies when the upper power transistor 2H is turned on at the same time that the lower power transistor 2L is soft-turned off.

[0193] As described above, in the above-described active discharge, it is difficult to appropriately control the discharge current Icap of the capacitor C. As a result, an excessively large discharge current Icap may flow through the upper power transistor 2H and the lower power transistor 2L. Therefore, it is necessary to increase the short-circuit withstand voltage of each of the upper power transistor 2H and the lower power transistor 2L.

[0194] In the following, in view of the above considerations, a second embodiment capable of controlling the discharge current Icap of the capacitor C will be proposed.

[0195] <Electronic Device (Second Embodiment)> 13 is a diagram showing a second embodiment of electronic device A. The electronic device A of this embodiment is based on the first embodiment (FIG. 11) described above, but adds a transistor M4 (e.g., a P-channel MOSFET) and an external terminal T4 to the semiconductor device 1. Furthermore, the external terminals T6 of the upper gate driver IC1H and the lower gate driver IC1L are both connected to the application terminal of the active discharge control signal ACD_EN.

[0196] Transistor M4 connects / disconnects the connection between the application terminal of the positive power supply voltage VCC2 and external terminal T4. Resistor R14 is connected externally between external terminal T4 of the high-side gate driver IC1H and the gate of the high-side power transistor 2H. Resistor R14 has a higher resistance value than resistor R11. Resistor R24 ​​is connected externally between external terminal T4 of the low-side gate driver IC1L and the gate of the low-side power transistor 2L. Resistor R24 ​​has a higher resistance value than resistor R21. External terminal T4 can be understood as an output terminal for soft turn-on during active discharge.

[0197] When the high-side gate driver IC1H soft-turns on the high-side power transistor 2H during active discharge, it turns on transistor M4 and turns off transistors M1 to M3. At this time, a current flows from the application terminal of the positive power supply voltage VCC2 to the gate of the high-side power transistor 2H via transistor M4 and resistor R14. Therefore, the high-side gate drive signal GH, and in turn, the applied voltage STON of the external terminal T4, rises from low to high. As a result, the high-side power transistor 2H is soft-turned on. The slew rate of the high-side gate drive signal GH during soft turn-on can be adjusted by the resistance value of resistor R14. Note that the slew rate during soft turn-on is lower than the slew rate during normal turn-on.

[0198] The same applies to the low-side gate driver IC1L. That is, the slew rate during soft turn-on of the low-side gate drive signal GL can be adjusted by the resistance value of resistor R24.

[0199] The transistors M1 and M2 can be understood as components of a drive circuit that turns on or off the upper power transistor 2H and the lower power transistor 2L, respectively, during normal driving (ACD_EN=L). The transistors M3 and M4 can be understood as components of an active discharge circuit that softly turns on or off the upper power transistor 2H and the lower power transistor 2L, respectively, more slowly than the transistors M1 and M2, during active discharge (ACD_EN=H).

[0200] During active discharge, the ECU 3 controls the upper gate driver IC1H and the lower gate driver IC1L so that one of the upper power transistor 2H and the lower power transistor 2L is soft turned on at the timing when the other of the upper power transistor 2H and the lower power transistor 2L is soft turned off.

[0201] <Active Discharge (Second Embodiment)> Fig. 14 is a diagram showing active discharge performed in the electronic device A of the second embodiment. As with Fig. 12, this diagram depicts, from top to bottom, the active discharge control signal ACD_EN, the upper input pulse signal INH, the lower input pulse signal INL, the upper gate drive signal GH, the lower gate drive signal GL, and the discharge current Icap of the capacitor C.

[0202] 12, at time t3, the low-side input pulse signal INL rises from low to high at the same time that the high-side power transistor 2H is soft-turned off. At this time, the low-side gate drive signal GL rises from low to high at a slew rate that corresponds to the resistance value of the resistor R24, as shown by the dashed line in the figure. As a result, the low-side power transistor 2L is gently soft-turned on.

[0203] As described above, in the electronic device A of this embodiment, the lower power transistor 2L is soft turned on at the same time that the upper power transistor 2H is soft turned off. With this configuration, the fluctuation component (dV / dt) occurring in the drain-source voltage Vds of the lower power transistor 2L is kept small. Therefore, it is possible to control the discharge current Icap during active discharge according to the pulse width of the lower input pulse signal INL and the slew rate of the lower gate drive signal GL (i.e., the resistance value of the resistor R24).

[0204] Although not shown in the figures, the ECU 3 may control the upper gate driver IC1H and the lower gate driver IC1L so that, during active discharge of the capacitor C, the upper power transistor 2H is soft turned on at the same time that the lower power transistor 2L is soft turned off.

[0205] Furthermore, as a modified example, the ECU 3 may control the upper gate driver IC1H and the lower gate driver IC1L, respectively, so that, during active discharge of the capacitor C, at the timing when one of the upper power transistor 2H and the lower power transistor 2H is soft turned on, the other of the upper power transistor 2H and the lower power transistor 2L is also soft turned on.

[0206] <Electronic Device (Third Embodiment)> 15 is a diagram showing a third embodiment of the electronic device A. The electronic device A of this embodiment is based on the second embodiment (FIG. 13) described above, but the external terminals T1 to T4 of the semiconductor device 1 are consolidated into external terminals Ta and Tb.

[0207] Referring to this figure, the previously mentioned external terminals T1 and T2 are replaced with an external terminal Ta. The external terminal Ta can be understood as an output terminal for turn-on / turn-off. Furthermore, the previously mentioned external terminals T3 and T4 are replaced with an external terminal Tb. The external terminal Tb can be understood as an output terminal for soft turn-on / turn-off.

[0208] The transistor M1 establishes conduction / cutoff between the application terminal of the positive power supply voltage VCC2 and the external terminal Ta. The transistor M2 establishes conduction / cutoff between the application terminal of the negative power supply voltage VEE2 and the external terminal Ta. The transistor M3 establishes conduction / cutoff between the application terminal of the negative power supply voltage VEE2 and the external terminal Tb. The transistor M14 establishes conduction / cutoff between the application terminal of the positive power supply voltage VCC2 and the external terminal Tb.

[0209] Furthermore, in accordance with this modification of the output format, diodes D11 to D14 are newly attached externally to the upper gate driver IC1H. Referring to this diagram, the anode of diode D11 and the cathode of diode D12 are connected to the external terminal Ta of the upper gate driver IC1H. The cathode of diode D11 is connected to a first terminal of resistor R11. The anode of diode D12 is connected to a first terminal of resistor R12. The second terminals of resistors R11 and R12 are connected to the gate of the upper power transistor 2H.

[0210] The cathode of the diode D13 and the anode of the diode D14 are connected to the external terminal Tb of the high-side gate driver IC1H. The anode of the diode D13 is connected to a first end of the resistor R13. The cathode of the diode D14 is connected to a first end of the resistor R14. The second ends of the resistors R13 and R14 are connected to the gate of the high-side power transistor 2H.

[0211] Similarly to the above, diodes D21 to D24 are newly externally attached to the low-side gate driver IC1L. Referring to this diagram, the anode of the diode D21 and the cathode of the diode D22 are connected to the external terminal Ta of the low-side gate driver IC1L. The cathode of the diode D21 is connected to a first end of a resistor R21. The anode of the diode D22 is connected to a first end of a resistor R22. The second ends of the resistors R21 and R22 are connected to the gate of the low-side power transistor 2L.

[0212] The cathode of the diode D23 and the anode of the diode D24 are connected to the external terminal Tb of the low-side gate driver IC1L. The anode of the diode D23 is connected to a first end of the resistor R23. The cathode of the diode D24 is connected to a first end of the resistor R24. The second ends of the resistors R23 and R24 are connected to the gate of the low-side power transistor 2L.

[0213] When the high-side power transistor 2H is turned on, a current flows from the external terminal Ta of the high-side gate driver IC1H via the diode D11 and resistor R11 to the gate of the high-side power transistor 2H. When the high-side power transistor 2H is turned off, a current flows from the gate of the high-side power transistor 2H via the resistor R12 and diode D12 to the external terminal Ta of the high-side gate driver IC1H.

[0214] On the other hand, during soft turn-off of the upper power transistor 2H, a current flows from the gate of the upper power transistor 2H via the resistor R13 and the diode D13 to the external terminal Tb of the upper gate driver IC1H. Also, during soft turn-on of the upper power transistor 2H, a current flows from the external terminal Tb of the upper gate driver IC1H to the gate of the upper power transistor 2H via the diode D14 and the resistor R14.

[0215] When the low-side power transistor 2L is turned on, a current flows from the external terminal Ta of the low-side gate driver IC1L via the diode D21 and resistor R21 to the gate of the low-side power transistor 2L. When the low-side power transistor 2L is turned off, a current flows from the gate of the low-side power transistor 2L via the resistor R22 and diode D22 to the external terminal Ta of the low-side gate driver IC1L.

[0216] On the other hand, during soft turn-off of the low-side power transistor 2L, a current flows from the gate of the low-side power transistor 2L via the resistor R23 and the diode D23 to the external terminal Tb of the low-side gate driver IC1L. Also, during soft turn-on of the low-side power transistor 2L, a current flows from the external terminal Tb of the low-side gate driver IC1L to the gate of the low-side power transistor 2L via the diode D24 and the resistor R24.

[0217] As described above, the electronic device A of this embodiment has a reduced number of external terminals of the semiconductor device 1 compared to the second embodiment (FIG. 13). Therefore, the semiconductor device 1 can be made smaller and less expensive.

[0218] <Electronic Device (Fourth Embodiment)> 16 is a diagram showing a fourth embodiment of the electronic device A. The electronic device A of this embodiment is based on the second embodiment (FIG. 13) described above, but the external terminal T5 of the semiconductor device 1 is changed to external terminals T5A and T5B.

[0219] The external terminal T5A of the upper gate driver IC1H and the external terminal T5B of the lower gate driver IC1L are connected to an application terminal of a positive input pulse signal INP. The external terminal T5B of the upper gate driver IC1H and the external terminal T5A of the lower gate driver IC1L are connected to an application terminal of a negative input pulse signal INN. The external terminal T5A can be understood as an input terminal of the first input pulse signal INA. The external terminal T5B can be understood as an input terminal of the second input pulse signal INB.

[0220] In this way, the upper gate driver IC1H and the lower gate driver IC1L receive the first input pulse signal INA and the second input pulse signal INB, respectively. The upper gate driver IC1H drives the upper power transistor 2H in accordance with the combination of the logic level of the first input pulse signal INA (=positive input pulse signal INP) and the logic level of the second input pulse signal INB (=negative input pulse signal INN). On the other hand, the lower gate driver IC1L drives the lower power transistor 2L in accordance with the combination of the logic level of the first input pulse signal INA (=negative input pulse signal INN) and the logic level of the second input pulse signal INB (=positive input pulse signal INP).

[0221] FIG. 17 is a diagram showing the input / output logic of the semiconductor device 1. As shown in FIG.

[0222] As shown in the first row, when the active discharge control signal ACD_EN is at a low level and the second input pulse signal INB is at a high level, the external terminal T2 (OFF) is set to a low level and the external terminals T1 (ON), T3 (STOFF), and T4 (STON) are set to a high impedance state, regardless of the logic level of the first input pulse signal INA.

[0223] As shown in the second row, even when the active discharge control signal ACD_EN, the first input pulse signal INA, and the second input pulse signal INB are at a low level, the external terminal T2 (OFF) is set to a low level, and the external terminals T1 (ON), T3 (STOFF), and T4 (STON) are set to a high impedance state.

[0224] As shown in the third row, when the active discharge control signal ACD_EN and the second input pulse signal INB are at a low level and the first input pulse signal INA is at a high level, the external terminal T1 (ON) is set to a high level and the external terminals T2 (OFF), T3 (STOFF) and T4 (STON) are set to a high impedance state.

[0225] As shown in the fourth row, when the active discharge control signal ACD_EN and the second input pulse signal INB are at a high level, the external terminal T3 (STOFF) is set to a low level, and the external terminals T1 (ON), T2 (OFF), and T4 (STON) are set to a high impedance state, regardless of the logic level of the first input pulse signal INA.

[0226] As shown in the fifth row, even when the active discharge control signal ACD_EN is at a high level and the first input pulse signal INA and the second input pulse signal INB are at a low level, the external terminal T3 (STOFF) is set to a low level and the external terminals T1 (ON), T2 (OFF), and T4 (STON) are set to a high impedance state.

[0227] As shown in the sixth row, when the active discharge control signal ACD_EN and the first input pulse signal INA are at a high level and the second input pulse signal INB is at a low level, the external terminal T4 (STON) is set to a high level, and the external terminals T1 (ON), T2 (OFF), and T3 (STOFF) are set to a high impedance state.

[0228] <Active Discharge (Fourth Embodiment)> 18 is a diagram showing active discharge performed in the electronic device A of the fourth embodiment. This diagram depicts, from top to bottom, the active discharge control signal ACD_EN, the positive input pulse signal INP, the negative input pulse signal INN, the upper gate drive signal GH, the lower gate drive signal GL, and the discharge current Icap of the capacitor C.

[0229] First, the turn-on / turn-off control during normal driving will be described, focusing on the low level period (before time tx) of the active discharge control signal ACD_EN.

[0230] At time t11, the logic levels of the positive input pulse signal INP and the negative input pulse signal INN switch from the first input state (INP=L, INN=L) to the second input state (INP=H, INN=L). At this time, the high-side gate driver IC1H sets the external terminal T1 to a high level and the external terminals T2 to T4 to a high-impedance state. Therefore, the high-side gate drive signal GH rises to a high level at a slew rate corresponding to the resistance value of the resistor R11. As a result, the high-side power transistor 2H is turned on. Meanwhile, the low-side gate driver IC1L maintains the external terminal T2 at a low level and the external terminals T1, T3, and T4 in a high-impedance state. Therefore, the low-side gate drive signal GL is maintained at a low level. As a result, the low-side power transistor 2L is maintained in an off state.

[0231] At time t12, the logic levels of the positive input pulse signal INP and the negative input pulse signal INN switch from the second input state (INP=H, INN=L) to the third input state (INP=H, INN=H). At this time, the high-side gate driver IC1H sets the external terminal T2 to a low level and the external terminals T1, T3, and T4 to a high-impedance state. Therefore, the high-side gate drive signal GH falls to a low level at a slew rate corresponding to the resistance value of the resistor R12. As a result, the high-side power transistor 2H is turned off. Meanwhile, the low-side gate driver IC1L maintains the external terminal T2 at a low level and the external terminals T1, T3, and T4 in a high-impedance state. Therefore, the low-side gate drive signal GL is maintained at a low level. As a result, the low-side power transistor 2L is maintained in an off state.

[0232] At time t13, the logic levels of the positive input pulse signal INP and the negative input pulse signal INN switch from the third input state (INP=H, INN=H) to the fourth input state (INP=L, INN=H). At this time, the high-side gate driver IC1H maintains the external terminal T2 at a low level and the external terminals T1, T3, and T4 in a high-impedance state. Therefore, the high-side gate drive signal GH is maintained at a low level. As a result, the high-side power transistor 2H is maintained in an off state. Meanwhile, the low-side gate driver IC1L sets the external terminal T1 to a high level and the external terminals T2 to T4 in a high-impedance state. Therefore, the low-side gate drive signal GL rises to a high level at a slew rate corresponding to the resistance value of the resistor R21. As a result, the low-side power transistor 2H is turned on.

[0233] At time t14, the logic levels of the positive input pulse signal INP and the negative input pulse signal INN switch from the fourth input state (INP=L, INN=H) to the first input state (INP=L, INN=L). At this time, the high-side gate driver IC1H maintains the external terminal T2 at a low level and the external terminals T1, T3, and T4 in a high-impedance state. Therefore, the high-side gate drive signal GH is maintained at a low level. As a result, the high-side power transistor 2H is maintained in an off state. Meanwhile, the low-side gate driver IC1L maintains the external terminal T2 at a low level and the external terminals T1, T3, and T4 in a high-impedance state. Therefore, the low-side gate drive signal GL falls to a low level at a slew rate corresponding to the resistance value of the resistor R22. As a result, the low-side power transistor 2L is turned off.

[0234] After time t15, the same turn-on / turn-off control as above is repeated. In particular, in the turn-on / turn-off control of this embodiment, periods during which both the upper power transistor 2H and the lower power transistor 2L are simultaneously turned off, so-called dead times (times t12 to t13 and t14 to t15), are provided.

[0235] Next, focusing on the high level period (after time tx) of the active discharge control signal ACD_EN, the soft turn-on / soft turn-off control during active discharge will be described.

[0236] At time t21, the logic levels of the positive input pulse signal INP and the negative input pulse signal INN switch from the first input state (INP=L, INN=L) to the second input state (INP=H, INN=L). At this time, the high-side gate driver IC1H sets the external terminal T4 to a high level and the external terminals T1 to T3 to a high-impedance state. Therefore, the high-side gate drive signal GH begins to rise gradually at a slew rate corresponding to the resistance value of the resistor R14 (see the dashed line of GH). As a result, the high-side power transistor 2H is soft-turned on. Meanwhile, the low-side gate driver IC1L maintains the external terminal T3 at a low level and the external terminals T1, T2, and T4 in a high-impedance state. Therefore, the low-side gate drive signal GL is maintained at a low level. As a result, the low-side power transistor 2L is maintained in an off state.

[0237] At time t22, the logic levels of the positive input pulse signal INP and the negative input pulse signal INN switch from the second input state (INP=H, INN=L) to the third input state (INP=H, INN=H). At this time, the high-side gate driver IC1H sets the external terminal T3 to a low level and the external terminals T1, T2, and T4 to a high-impedance state. Therefore, the high-side gate drive signal GH begins to gradually decrease at a slew rate corresponding to the resistance value of resistor R13 (see the dashed line of GH). As a result, the high-side power transistor 2H is soft-turned off. Meanwhile, the low-side gate driver IC1L maintains the external terminal T2 at a low level and the external terminals T1, T3, and T4 in a high-impedance state. Therefore, the low-side gate drive signal GL is maintained at a low level. As a result, the low-side power transistor 2L is maintained in an off state.

[0238] At time t23, the logic levels of the positive input pulse signal INP and the negative input pulse signal INN switch from the third input state (INP=H, INN=H) to the fourth input state (INP=L, INN=H). At this time, the high-side gate driver IC1H maintains the external terminal T3 at a low level and the external terminals T1, T2, and T4 in a high-impedance state. Therefore, the high-side gate drive signal GH continues to gradually decrease at a slew rate corresponding to the resistance value of the resistor R13 (see the dashed line of GH). As a result, the high-side power transistor 2H continues to be soft-turned off. Meanwhile, the low-side gate driver IC1L sets the external terminal T4 to a high level and places the external terminals T1 to T3 in a high-impedance state. Therefore, the low-side gate drive signal GL begins to gradually increase at a slew rate corresponding to the resistance value of the resistor R24 ​​(see the dashed line of GL). As a result, the low-side power transistor 2H is soft-turned on.

[0239] At this time, a discharge current Icap of the capacitor C flows through the upper power transistor 2H and the lower power transistor 2L. The discharge current Icap can be controlled according to the pulse width of the negative input pulse signal INN and the slew rates of the upper gate drive signal GH and the lower gate drive signal GL (i.e., the resistance values ​​of the resistors R14 and R24). The discharge current Icap flows from when the lower gate drive signal GL exceeds the on-threshold voltage VthL of the lower power transistor 2L until the upper gate drive signal GH falls below the on-threshold voltage VthH of the upper power transistor 2H.

[0240] At time t24, the logic levels of the positive input pulse signal INP and the negative input pulse signal INN switch from the fourth input state (INP=L, INN=H) to the first input state (INP=L, INN=L). At this time, the high-side gate driver IC1H maintains the external terminal T3 at a low level and the external terminals T1, T2, and T4 in a high-impedance state. Therefore, the high-side gate drive signal GH continues to gradually decrease at a slew rate corresponding to the resistance value of the resistor R13 and reaches a low level. As a result, the soft turn-off of the high-side power transistor 2H is completed. Meanwhile, the low-side gate driver IC1L sets the external terminal T3 to a low level and the external terminals T1, T2, and T4 in a high-impedance state. Therefore, the low-side gate drive signal GL begins to gradually decrease at a slew rate corresponding to the resistance value of the resistor R23 (see the dashed line of GL). As a result, the low-side power transistor 2L is soft-turned off.

[0241] At time t25, the logic levels of the positive input pulse signal INP and the negative input pulse signal INN switch from the first input state (INP=L, INN=L) to the second input state (INP=H, INN=L). At this time, the high-side gate driver IC1H sets the external terminal T4 to a high level and the external terminals T1 to T3 to a high-impedance state. Therefore, the high-side gate drive signal GH begins to rise slowly at a slew rate corresponding to the resistance value of the resistor R14 (see the dashed line of GH). As a result, the high-side power transistor 2H is soft-turned on. Meanwhile, the low-side gate driver IC1L maintains the external terminal T3 at a low level and the external terminals T1, T2, and T4 in a high-impedance state. Therefore, the low-side gate drive signal GL continues to fall slowly at a slew rate corresponding to the resistance value of the resistor R23 (see the dashed line of GL). As a result, the low-side power transistor 2L continues to be soft-turned off.

[0242] At this time, a discharge current Icap of the capacitor C flows through the upper power transistor 2H and the lower power transistor 2L. The discharge current Icap can be controlled according to the pulse width of the positive input pulse signal INP and the slew rates of the upper gate drive signal GH and the lower gate drive signal GL (i.e., the resistance values ​​of the resistors R14 and R24). The discharge current Icap flows from when the upper gate drive signal GH exceeds the on-threshold voltage VthH of the upper power transistor 2H until the lower gate drive signal GL falls below the on-threshold voltage VthL of the lower power transistor 2L.

[0243] After time t26, the same soft turn-on / soft turn-off control as above is repeated. In particular, in the soft turn-on / soft turn-off control of this embodiment, periods during which both the upper power transistor 2H and the lower power transistor 2L are simultaneously turned off, so-called dead times (times t22 to t23 and t24 to t25), are provided.

[0244] In this way, the electronic device A of this embodiment can achieve appropriate active discharge control while providing a dead time in which both the upper power transistor 2H and the lower power transistor 2L are in the OFF state.

[0245] <Semiconductor device> 19 is a diagram showing a configuration example of the semiconductor device 1. The semiconductor device 1 of this configuration example includes a first chip 410, a second chip 420, and a third chip 430. The first chip 410, the second chip 420, and the third chip 430 may be sealed in a single package.

[0246] Note that, like the signal transmission device 200 (FIG. 1) described above, the semiconductor device 1 may be a semiconductor integrated circuit device (a so-called insulated gate driver IC) that generates an output pulse signal OUT in the second chip 420 in response to an input pulse signal IN input to the first chip 410 while insulating between the input and output, and drives a switch element (not shown).

[0247] In this case, the first chip 410 corresponds to the aforementioned controller chip 210. The second chip 420 corresponds to the aforementioned driver chip 220. The third chip 430 corresponds to the aforementioned transformer chip 230.

[0248] The first chip 410 has an edge detection circuit 411, an oscillation circuit 412, a D flip-flop 413, a pulse generation circuit 414, and transmission circuits 415 and 416 integrated therein.

[0249] The second chip 420 integrates receiving circuits 421 and 422, RS flip-flops 423 and 424, timers 425 to 427, AND gates 428 to 42D, and an inverter 42E. Although not shown in the figure, the second chip 420 also integrates the aforementioned transistors M1 to M4.

[0250] Transformers 431 and 432 (corresponding to a first insulating element and a second insulating element, respectively) are integrated on the third chip 430. The transformer 431 includes a primary coil 431p and a secondary coil 431s. The transformer 432 includes a primary coil 432p and a secondary coil 432s.

[0251] The edge detection circuit 411 detects the rising edge and the falling edge of the input pulse signal IN, respectively, and outputs the edge detection signal Sa. The edge detection circuit 411 may include an input filter for removing noise components superimposed on the input pulse signal IN. For example, the edge detection circuit 411 may generate one low-level pulse in the edge detection signal Sa after a predetermined mask time (e.g., 50 ns) has elapsed since detecting the rising edge and the falling edge of the input pulse signal IN, respectively. The input pulse signal IN may be, for example, the first input pulse signal INA (FIG. 16) described above.

[0252] The oscillator circuit 412 receives the edge detection signal Sa and generates a drive clock signal Sb for the pulse generator circuit 414 .

[0253] The D flip-flop 413 latches the active discharge control signal ACD_EN input to the data input terminal (D) using the edge detection signal Sa input to the clock input terminal (>) as a trigger, and outputs a latch output signal Sc from the output terminal (Q). That is, the logic level of the active discharge control signal ACD_EN is reflected in pulse generation after edge detection of the input pulse signal IN. Note that the D flip-flop 413 resets the logic level of the latch output signal Sc to an initial value (for example, low level) when the fault release signal Sx input to the reset terminal (R) reaches the logic level at the time of fault release.

[0254] The pulse generation circuit 414 receives the drive clock signal Sb and the latch output signal Sc and generates the transmission pulse signals Sd1 and Sd2, respectively. For example, when the latch output signal Sc is at a low level, the pulse generation circuit 414 generates the transmission pulse signal Sd1 or Sd2 with a drive period TX (e.g., 100 ns). On the other hand, when the latch output signal Sc is at a high level, the pulse generation circuit 414 generates a pulse signal with a drive period TY (e.g., 25 ns) for a duration TZ (e.g., 0.5 μs).

[0255] The second chip 420 determines whether the transformer 431 or 432 is in normal driving mode (ACD_EN=L) or active discharge mode (ACD=H) depending on whether the transformer 431 or 432 is pulse-driven with a driving cycle TX or pulse-driven with a driving cycle TY. This point will be described in detail later.

[0256] The transmission circuit 415 receives the transmission pulse signal Sd1 and pulse-drives the primary coil 431p of the transformer 431.

[0257] The transmission circuit 416 receives the transmission pulse signal Sd1 and pulse-drives the primary coil 432p of the transformer 432.

[0258] The receiving circuit 421 receives the receiving pulse signal S1 from the secondary coil 431s of the transformer 431 and outputs the receiving pulse signal S31.

[0259] The receiving circuit 422 receives the receiving pulse signal S2 from the secondary coil 432s of the transformer 432 and outputs the receiving pulse signal S32.

[0260] The RS flip-flop 423 switches the logic levels of the latch output signal S6 output from the output terminal (Q) and the inverted latch output signal S6B output from the inverting output terminal (QB) in response to the timer output signal S4 input to its set terminal (S) and the logical product signal S35 input to its reset terminal (R). For example, the RS flip-flop 423 sets the latch output signal S6 to a high level and the inverted latch output signal S6B to a low level in response to the timer output signal S4. On the other hand, the RS flip-flop 423 resets the latch output signal S6 to a low level and the inverted latch output signal S6B to a high level in response to the logical product signal S35.

[0261] The RS flip-flop 424 switches the logic level of the latch output signal S7 output from the output terminal (Q) in response to the received pulse signal S31 input to the set terminal (S) and the received pulse signal S32 input to the reset terminal (R). For example, the RS flip-flop 424 sets the latch output signal S7 to a high level in response to the received pulse signal S31. On the other hand, the RS flip-flop 424 resets the latch output signal S7 to a low level in response to the received pulse signal S31.

[0262] The timer 425 receives the AND signal S33 as an input and outputs a timer output signal S3. For example, the timer output signal S3 goes high when a pulse is generated in the AND signal S33. The timer output signal S3 goes low when no pulse is generated in the AND signal S33 over a predetermined timer time Tx. The timer time Tx is shorter than the aforementioned drive period TX (e.g., 100 ns) and longer than the drive period TY (e.g., 25 ns). The timer time Tx may be, for example, 40 ns.

[0263] The timer 426 receives the logical product signal S34 and outputs a timer output signal S4. For example, the timer output signal S4 goes high when the logical product signal S34 is maintained at a high level for a predetermined timer time Ty. The timer output signal S4 also goes low without delay when the logical product signal S34 falls to a low level. The timer time Ty may be, for example, 200 ns. The logical product signal S34 can be understood as a reset signal for the timer 426.

[0264] The timer 427 receives the inverted latch output signal S6B and outputs a timer output signal S5. For example, the timer output signal S5 is maintained at a high level for a predetermined timer time Tz after the inverted latch output signal S6B falls to a low level. The timer time Tz may be, for example, 0.8 μs.

[0265] The AND gate 428 receives the received pulse signals S31 and S32 and outputs a logical product signal S33. The logical product signal S33 is at low level when at least one of the received pulse signals S31 and S32 is at low level. The logical product signal S33 is at high level when both the received pulse signals S31 and S32 are at high level.

[0266] The AND gate 429 receives the timer output signal S3 and the UVLO (under voltage lock out) signal Sy as inputs and outputs a logical product signal S34. The logical product signal S34 goes low when at least one of the timer output signal S3 and the UVLO signal Sy is low. The logical product signal S34 goes high when both the timer output signal S3 and the UVLO signal Sy are high. The UVLO signal Sy goes low when UVLO is detected and goes high when UVLO is released.

[0267] The AND gate 42A receives the logical product signal S33 and the timer output signal S5 as inputs and outputs a logical product signal S35. The logical product signal S35 goes low when at least one of the logical product signal S33 and the timer output signal S5 is low. The logical product signal S35 goes high when both the logical product signal S33 and the timer output signal S5 are high.

[0268] The AND gate 42B receives the inverted latch output signal S6B and the latch output signal S7 as inputs and outputs a logical product signal S36. The logical product signal S36 is at a low level when at least one of the inverted latch output signal S6B and the latch output signal S7 is at a low level. The logical product signal S36 is at a high level when both the inverted latch output signal S6B and the latch output signal S7 are at a high level.

[0269] For example, when the AND signal S36 is at a high level, the aforementioned transistor M1 is turned on. On the other hand, when the AND signal S36 is at a low level, the aforementioned transistor M2 is turned on. That is, the AND signal S36 functions as a control signal for the drive circuit that turns on or off the switch element to be driven (the upper-side power transistor 2H or the lower-side power transistor 2L). Therefore, the circuit elements involved in generating the AND signal S36, i.e., the RS flip-flop 424 and the AND gate 42B, together with the aforementioned transistors M1 and M2, can be understood as components of the drive circuit.

[0270] The AND gate 42C receives the latch output signals S6 and S7 as inputs and outputs a logical product signal S37. The logical product signal S37 goes low when at least one of the latch output signals S6 and S7 is low. The logical product signal S37 goes high when both of the latch output signals S6 and S7 are high.

[0271] The AND gate 42D receives the latch output signal S6 and the inverted latch output signal S7B as inputs and outputs a logical product signal S38. The logical product signal S38 goes low when at least one of the latch output signal S6 and the inverted latch output signal S7B is low. The logical product signal S38 goes high when both the latch output signal S6 and the inverted latch output signal S7B are high.

[0272] For example, when the AND signal S37 is at a high level, the aforementioned transistor M3 is turned on. On the other hand, when the AND signal S37 is at a low level, the aforementioned transistor M3 is turned off. Also, when the AND signal S38 is at a high level, the aforementioned transistor M4 is turned on. On the other hand, when the AND signal S38 is at a low level, the aforementioned transistor M4 is turned off.

[0273] That is, the logical product signals S37 and S38 function as control signals for the active discharge circuit that softly turn off or softly turn on the switch element to be driven (the upper power transistor 2H or the lower power transistor 2L). Therefore, the circuit elements involved in generating the logical product signals S37 and S38, respectively, namely, the RS flip-flops 423 and 424, the timers 425 to 427, the AND gates 428 to 42A, 42C and 42D, and the inverter 42E, together with the above-mentioned transistors M3 and M4, can be understood as components of the active discharge circuit.

[0274] The inverter 42E inverts the logic level of the latch output signal S7 to generate the inverted latch output signal S7B. Therefore, the inverted latch output signal S7B is at a low level when the latch output signal S7 is at a high level. On the other hand, the inverted latch output signal S7B is at a high level when the latch output signal S7 is at a low level.

[0275] The transformer 431 provides insulation between the transmitting circuit 415 and the receiving circuit 421, and transmits the transmitting pulse signal Sd1 as the receiving pulse signal S1.

[0276] The transformer 432 provides insulation between the transmitting circuit 416 and the receiving circuit 422, and transmits the transmitting pulse signal Sd2 as the receiving pulse signal S2.

[0277] In the semiconductor device 1 of this configuration example, it is possible to perform not only turn-on control and turn-off control during normal driving but also soft turn-on control and soft turn-off control during active discharge using the transformers 431 and 432. However, if an increase in the number of transformers integrated into the third chip 430 is permitted, dedicated transformers may be used for the soft turn-on control and the soft turn-off control, respectively.

[0278] 20 is a diagram showing an example of soft turn-on control in the semiconductor device 1. This diagram shows, from top to bottom, the active discharge control signal ACD_EN, the input pulse signal IN, the received pulse signals S1 and S2, the timer output signals S3 to S5, the latch output signals S6 and S7, and the gate drive signal GATE. For example, the input pulse signal IN can be understood as the first input pulse signal INA mentioned above. Furthermore, the gate drive signal GATE can be understood as the upper gate drive signal GH or the lower gate drive signal GL mentioned above.

[0279] First, the turn-on / turn-off control during normal driving will be described, focusing on the low level period of the active discharge control signal ACD_EN.

[0280] When the input pulse signal IN is at a high level during a low level period of the active discharge control signal ACD_EN, the received pulse signal S1 is driven at a drive period TX (for example, 100 ns). In this way, the first chip 410 notifies the second chip 420 via the transformer 431 that the input pulse signal IN is at a high level. The high level of the input pulse signal IN can be understood as a logic level for turning on the switch element (upper-side power transistor 2H or lower-side power transistor 2L) to be driven.

[0281] On the other hand, when the input pulse signal IN is at a low level, the received pulse signal S2 is driven at the drive period TX. In this way, the first chip 410 notifies the second chip 420 that the input pulse signal IN is at a low level via the transformer 432. The low level of the input pulse signal IN can be understood as a logic level for turning off the switch element to be driven (the upper-side power transistor 2H or the lower-side power transistor 2L).

[0282] The timer output signal S3 rises to a high level each time a pulse is generated in one of the received pulse signals S1 and S2. However, if the timer time Tx elapses without a pulse being generated in one of the received pulse signals S1 and S2, the timer output signal S3 falls to a low level again. Thus, during normal operation, the timer output signal S3 periodically goes low. Therefore, the timer output signal S4 is maintained at a low level. As a result, the timer output signal S5 and the latch output signal S6 also remain low.

[0283] When the latch output signal S6 is at a low level, the latch output signal S7 is outputted as a logical product signal S36 (not shown), while the logical product signals S37 and S38 (not shown) are fixed to a low level.

[0284] In the above state, for example, if the input pulse signal IN is high and the received pulse signal S1 is pulse-driven, the latch output signal S7 and, in turn, the logical product signal S36 (not shown) are set to high, thereby turning on the transistor M1 and raising the gate drive signal GATE to high.

[0285] On the other hand, if the input pulse signal IN is at a low level and the received pulse signal S2 is pulse-driven, the latch output signal S7 and, in turn, the logical AND signal S36 (not shown) are reset to a low level, so that the transistor M2 is turned on and the gate drive signal GATE falls to a low level.

[0286] In this way, during the low level period of the active discharge control signal ACD_EN, the transistors M1 and M2 perform turn-on / turn-off control of the upper power transistor 2H or the lower power transistor 2L.

[0287] Next, focusing on the high level period of the active discharge control signal ACD_EN, the soft turn-on control during active discharge will be explained.

[0288] When the input pulse signal IN rises from low to high during the high level period of the active discharge control signal ACD_EN, the received pulse signal S2 is driven for a duration TZ (for example, 0.5 μs) at a drive period TY (for example, 25 ns).

[0289] The timer output signal S3 rises to a high level in response to the pulse driving of the received pulse signal S2. The received pulse signal S2 is pulse-driven at a driving period TY that is shorter than the timer time Tx (e.g., 40 ns). Therefore, the timer output signal S3 is maintained at a high level without being periodically reset to a low level.

[0290] The timer output signal S4 goes high when the timer output signal S3, and therefore the logical AND signal S34 (not shown), are maintained at a high level for a timer time Ty (e.g., 200 ns). As a result, the latch output signal S6 is set to a high level. The timer output signal S5 is maintained at a high level for a timer time Tz (e.g., 0.8 μs) after the latch output signal S6 rises to a high level. During the high-level period of the timer output signal S5, the reset operation of the RS flip-flop 423 by the received pulse signals S1 and S2, and therefore the logical AND signal S33 (not shown), is masked.

[0291] When the latch output signal S6 is at a high level, the logical product signal S36 (not shown) is fixed to a low level, while the latch output signal S7 and the inverted latch output signal S7B (not shown) are outputted as logical product signals S37 and S38 (not shown), respectively.

[0292] Referring to this figure, when the input pulse signal IN transitions to a high level and the received pulse signal S2 is pulse-driven, the latch output signal S7 is at a low level, so that the logical product signal S38 (not shown) goes to a high level. Therefore, the transistor M4 is turned on, and the gate drive signal GATE rises to a high level relatively slowly. That is, the transistor M4 performs soft turn-on control of the upper power transistor 2H or the lower power transistor 2L.

[0293] Fig. 21 is a diagram showing an example of soft turn-off control in the semiconductor device 1. As with Fig. 20, this diagram depicts, from top to bottom, the active discharge control signal ACD_EN, the input pulse signal IN, the received pulse signals S1 and S2, the timer output signals S3 to S5, the latch output signals S6 and S7, and the gate drive signal GATE.

[0294] The low level period of the active discharge control signal ACD_EN is the same as that shown in Fig. 20. Therefore, below, the soft turn-off control during active discharge will be described, focusing on the high level period of the active discharge control signal ACD_EN.

[0295] When the input pulse signal IN falls from high to low during the high level period of the active discharge control signal ACD_EN, the received pulse signal S1 is driven for a duration TZ (for example, 0.5 μs) at a drive period TY (for example, 25 ns).

[0296] The timer output signal S3 rises to a high level in response to the pulse driving of the received pulse signal S1. The received pulse signal S1 is pulse-driven at a driving period TY that is shorter than the timer time Tx (for example, 40 ns). Therefore, the timer output signal S3 is maintained at a high level without being periodically reset to a low level. This is the same as in FIG. 20.

[0297] The timer output signal S4 goes high when the timer output signal S3, and in turn, the logical AND signal S34 (not shown), are maintained at a high level for a timer time Ty (e.g., 200 ns). As a result, the latch output signal S6 is set to a high level. The timer output signal S5 is maintained at a high level for a timer time Tz (e.g., 0.8 μs) after the latch output signal S6 rises to a high level. During the high-level period of the timer output signal S5, the reset operation of the RS flip-flop 423 by the received pulse signals S1 and S2, and in turn, the logical AND signal S33 (not shown), is masked. This point is also the same as in FIG. 20.

[0298] When the latch output signal S6 is at a high level, the logical product signal S36 (not shown) is fixed to a low level, while the latch output signal S7 and the inverted latch output signal S7B (not shown) are outputted as logical product signals S37 and S38 (not shown), respectively.

[0299] Referring to this figure, when the received pulse signal S1 is pulse-driven in response to the transition of the input pulse signal IN to a low level, the latch output signal S7 is at a high level, and therefore the logical product signal S37 (not shown) goes to a high level. Therefore, the transistor M3 is turned on, and the gate drive signal GATE falls to a low level relatively slowly. That is, the transistor M3 performs soft turn-off control of the upper power transistor 2H or the lower power transistor 2L.

[0300] <Application to vehicles> 22 is a diagram showing the exterior of a vehicle. Vehicle B of this configuration example is equipped with various electronic devices that operate with power supplied from a battery.

[0301] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0302] The signal transmission device 200 and the semiconductor devices 1, 1H, and 1L described above can be incorporated into any of the electronic devices mounted on the vehicle B.

[0303] <Additional Notes> According to the present disclosure, it is possible to appropriately control the discharge current that flows during active discharge.

[0304] [Appendix 1] A semiconductor device (1, 1H, 1L) comprising: drive circuits (M1, M2) configured to turn on or off switch elements (2H, 2L) to be driven during normal driving (ACD_EN=L); and active discharge circuits (M3, M4) configured to soft-turn on or soft-turn off the switch elements (2H, 2L) more slowly than the drive circuits (M1, M2) during active discharge (ACD_EN=H).

[0305] [Appendix 2] The semiconductor device (1, 1H, 1L) described in Appendix 1, wherein the drive circuit (M1, M2) includes a first transistor (M1) configured to establish / shut off conduction between an application terminal of a first voltage (VCC2) and a first external terminal (T1), and a second transistor (M2) configured to establish / shut off conduction between an application terminal of a second voltage (VEE2) and a second external terminal (T2), and the active discharge circuit (M3, M4) includes a third transistor (M3) configured to establish / shut off conduction between the application terminal of the second voltage (VEE2) and a third external terminal (T3), and a fourth transistor (M4) configured to establish / shut off conduction between the application terminal of the first voltage (VCC2) and a fourth external terminal (T4).

[0306] [Appendix 3] A semiconductor device (1, 1H, 1L) described in Appendix 2, wherein the first external terminal (T1) and the second external terminal (T2) are the same external terminal (Ta), and the third external terminal (T3) and the fourth external terminal (T4) are the same external terminal (Tb).

[0307] [Appendix 4] A semiconductor device (1, 1H, 1L) according to any one of appendices 1 to 3, which receives an input of a first input pulse signal (INP) and a second input pulse signal (INN) and drives the switch element (2H, 2L) according to a combination of the logic levels of the first input pulse signal (INP) and the second input pulse signal (INN).

[0308] [Appendix 5] a first chip (410) configured to receive an input pulse signal (IN); a second chip (420) on which the driving circuits (M1, M2) and the active discharge circuits (M3, M4) are integrated; a third chip (430) on which a first insulating element (431) and a second insulating element (432) are integrated; Equipped with The semiconductor device (1, 1H, 1L) according to any one of Appendices 1 to 4, wherein the first chip (410) notifies the second chip (420) via the first insulating element (431) that the input pulse signal (IN) is at a logic level for turning on the switch elements (2H, 2L), and notifies the second chip (420) via the second insulating element (432) that the input pulse signal (IN) is at a logic level for turning off the switch elements (2H, 2L).

[0309] [Appendix 6] The semiconductor device (1, 1H, 1L) described in Appendix 5, wherein the first chip (410) drives the first isolation element (431) or the second isolation element (432) with a first drive cycle (TX) during the normal drive (ACD_EN=L) and drives the first isolation element (431) or the second isolation element (432) with a second drive cycle (TY) during the active discharge (ACD_EN=H), and the second chip (420) determines whether it is the normal drive (ACD_EN=L) or the active discharge (ACD=H) depending on the drive cycle (TX, TY) of the first isolation element (431) or the second isolation element (432).

[0310] [Appendix 7] a first switch element (2H) and a second switch element (2L) connected in series between an application terminal of a first power supply voltage (PVDD) and an application terminal of a second power supply voltage (PVEE) to form a half-bridge output stage; a capacitor (C) connected in parallel with the half-bridge output stage between an application terminal of the first power supply voltage (PVDD) and an application terminal of the second power supply voltage (PVEE); a first driving device (1H) configured to drive the first switch element (2H); a second drive device (1L) configured to drive the second switch element (2L); a control device (3) configured to control the first drive device (1H) and the second drive device (1L); Equipped with The electronic device (A), wherein the first driving device (1H) and the second driving device (1L) are the semiconductor devices (1, 1H, 1L) described in any one of appendices 1 to 6.

[0311] [Appendix 8] The electronic device (A) described in Appendix 7, wherein the control device (3) controls the first drive device (1H) and the second drive device (1L), respectively, so that at a timing when one of the first switch element (2H) and the second switch element (2L) is soft turned off, the other of the first switch element (2H) and the second switch element (2L) is soft turned on.

[0312] [Appendix 9] The electronic device (A) described in Appendix 7, wherein the control device (3) controls the first drive device (1H) and the second drive device (1L), respectively, so that the other of the first switch element (2H) and the second switch element (2L) is also soft turned on at the timing when one of the first switch element (2H) and the second switch element (2L) is soft turned on.

[0313] [Appendix 10] A vehicle (B) equipped with an electronic device (A) according to any one of Supplementary Notes 7 to 9.

[0314] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0315] 1. Semiconductor device 1H(u / v / w) High-side gate driver IC 1L(u / v / w) Lower gate driver IC 2H(u / v / w) Upper power transistor 2L(u / v / w) Lower power transistor 3 ECU 4 motors 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring 410 First Chip 411 Edge detection circuit 412 Oscillator Circuit 413 D Flip-Flop 414 Pulse Generator Circuit 415, 416 Transmitting circuit 420 Second Chip 421, 422 receiving circuit 423, 424 RS flip-flops 425, 426, 427 Timers 428, 429, 42A, 42B, 42C, 42D AND gates 42E Inverter 430 3rd Chip 431, 432 Transformer (Isolation element) 431p, 432p Primary coil 431s, 432s Secondary coil a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads A Electronic equipment B vehicle C capacitor D11~D14, D21~D24 Diodes L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil M1, M4 transistors (PMOSFET) M2, M3 transistors (NMOSFET) R11~R14, R21~R24 resistance T1~T7, T5A, T5B, Ta, Tb external terminals T21, T22, T23, T24, T25, T26 external terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias

Claims

1. A semiconductor device comprising: a drive circuit configured to turn on or off a switch element to be driven during normal driving; and an active discharge circuit configured to softly turn on or softly turn off the switch element more slowly than the drive circuit during active discharge.

2. 2. The semiconductor device according to claim 1, wherein the drive circuit includes a first transistor configured to establish / shut off conduction between a first voltage application terminal and a first external terminal, and a second transistor configured to establish / shut off conduction between a second voltage application terminal and a second external terminal, and the active discharge circuit includes a third transistor configured to establish / shut off conduction between the second voltage application terminal and a third external terminal, and a fourth transistor configured to establish / shut off conduction between the first voltage application terminal and a fourth external terminal.

3. 3. The semiconductor device according to claim 2, wherein said first external terminal and said second external terminal are the same external terminal, and said third external terminal and said fourth external terminal are the same external terminal.

4. 2. The semiconductor device according to claim 1, wherein the semiconductor device receives a first input pulse signal and a second input pulse signal, and drives the switch element in accordance with a combination of logic levels of the first input pulse signal and the second input pulse signal.

5. a first chip configured to receive an input pulse signal; a second chip on which the driving circuit and the active discharge circuit are integrated; a third chip on which the first isolation element and the second isolation element are integrated; Equipped with 2. The semiconductor device according to claim 1, wherein the first chip notifies the second chip, via the first isolation element, that the input pulse signal is at a logic level for turning on the switch element, and notifies the second chip, via the second isolation element, that the input pulse signal is at a logic level for turning off the switch element.

6. 6. The semiconductor device according to claim 5, wherein the first chip drives the first isolation element or the second isolation element with a first drive cycle during the normal drive and drives the first isolation element or the second isolation element with a second drive cycle during the active discharge, and the second chip determines whether it is the normal drive or the active discharge depending on the drive cycle of the first isolation element or the second isolation element.

7. a first switch element and a second switch element connected in series between an application terminal of a first power supply voltage and an application terminal of a second power supply voltage to form a half-bridge output stage; a capacitor connected in parallel with the half-bridge output stage between an application terminal of the first power supply voltage and an application terminal of the second power supply voltage; a first driver configured to drive the first switch element; a second driver configured to drive the second switch element; a controller configured to control the first drive unit and the second drive unit; Equipped with 7. An electronic device, wherein the first driving device and the second driving device are each a semiconductor device according to claim 1.

8. 8. The electronic device according to claim 7, wherein the control device controls the first drive device and the second drive device, respectively, so that the other of the first switch element and the second switch element is soft turned on at a timing when one of the first switch element and the second switch element is soft turned off.

9. 8. The electronic device according to claim 7, wherein the control device controls the first drive device and the second drive device, respectively, so that the other of the first switch element and the second switch element is also soft-turned on at a timing when one of the first switch element and the second switch element is soft-turned on.

10. A vehicle comprising the electronic device according to claim 7.

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