Method for manufacturing semiconductor device and method for managing product history of the same

Abstract

To provide a technique capable of suppressing an increase in cost while accurately achieving traceability of a semiconductor device.SOLUTION: In a plurality of chip regions (CHPa), a multilayer wiring layer having a metal film (MF) in an uppermost wiring layer is formed. In each of the plurality of chip regions (CHPa), a surface morphology image (1AI) of a specific area (1A) of the metal film (MF) is acquired. A wafer identification number (ID), position information of the plurality of chip regions (CHPa), position information of the specific area (1A) within each chip region (CHPa), and the surface morphology image (1AI) for each chip region (CHPa) are associated with one another and stored in a storage device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a method for managing the product history of a semiconductor device. [Background technology]

[0002] When a defect is discovered after the manufacturing of a semiconductor device, it is necessary to identify the cause of the defect early and provide feedback to the manufacturing process of the semiconductor device. To achieve this, traceability of semiconductor devices determined to be defective is effective. In other words, it is effective to clarify which wafer, which lot number and which wafer identification number the semiconductor device determined to be defective was manufactured on, and at what position within the wafer it was manufactured.

[0003] For example, in Patent Document 1, images of dicing marks on the side of the wafer and images of contact marks on the surface of the pad electrodes formed during probe testing are stored in a storage device at the four corners of the semiconductor chip. Similar images are also acquired for semiconductor chips that have been determined to be defective, and by comparing these images with the images stored in the storage device, the wafer identification number and position within the wafer on which the semiconductor chip determined to be defective was manufactured can be identified. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-165389 Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, in the semiconductor front-end process, an identification code is attached to the wafer. However, the semiconductor chips separated from the wafer do not have an identification code. While attaching an identification code to every semiconductor chip would enable traceability, such an approach would increase costs.

[0006] Semiconductor chips separated from a wafer are packaged through post-processing to manufacture semiconductor devices. During this process, external connection members such as bonding wires or bump electrodes are formed on the surfaces of pad electrodes. The semiconductor chips are also covered with a sealing resin. To ensure traceability of semiconductor devices determined to be defective, it is necessary to accurately obtain information that can identify the semiconductor chips even after the sealing resin is opened and the external connection members are removed.

[0007] In other words, there is a need for a technology that can suppress cost increases and perform semiconductor device traceability with high accuracy. There is also a need for a technology that can identify the cause of semiconductor device defects early and provide feedback to the semiconductor device manufacturing method early. These technologies will enable the supply of highly reliable semiconductor devices after feedback, improve yield, and prevent defective products from being released into the market.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A brief summary of a representative embodiment of the present invention will be given below.

[0010] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) assigning a wafer identification number to a wafer made of semiconductor material; (b) dividing the wafer into a plurality of chip regions arranged in a matrix and generating a wafer map; (c) forming a semiconductor element in each of the plurality of chip regions; (d) forming a multilayer wiring layer in each of the plurality of chip regions, the multilayer wiring layer being located above the semiconductor element and having a metal film in its uppermost wiring layer; (e) acquiring a first surface morphology image of a specific area of ​​the metal film in each of the plurality of chip regions; and (f) linking the wafer identification number, positional information of the plurality of chip regions, positional information of the specific area within the chip region, and the first surface morphology image for each of the plurality of chip regions, and storing them in a storage device.

[0011] A method for managing product history of a semiconductor device according to one embodiment includes: (a) assigning a wafer identification number to a wafer made of semiconductor material; (b) dividing the wafer into a plurality of chip regions arranged in a matrix and generating a wafer map; (c) forming a semiconductor element in each of the plurality of chip regions; (d) forming a metal film in an uppermost wiring layer of a multilayer wiring layer located above the semiconductor element in each of the plurality of chip regions; (e) acquiring a first surface morphology image of a specific area of ​​the metal film in each of the plurality of chip regions; and (f) linking the wafer identification number, position information of the plurality of chip regions, position information of the specific area within the chip region, and the first surface morphology image for each of the plurality of chip regions, and recording the first surface morphology image. (g) obtaining a plurality of semiconductor chips by singulating the plurality of chip regions of the wafer; (h) forming a plurality of first semiconductor devices by encapsulating the plurality of semiconductor chips with encapsulation resin; (i) obtaining a second semiconductor device that has been determined to be defective; (j) opening the encapsulation resin of the second semiconductor device and obtaining a second surface morphology image of a portion of the metal film provided on the second semiconductor device that corresponds to the specific area; and (k) identifying the wafer identification number of the wafer on which the second semiconductor device is manufactured and the position of the chip region on which the second semiconductor device is manufactured by comparing the second surface morphology image with the first surface morphology images for each of the plurality of chip regions stored in the storage device. [Effects of the Invention]

[0012] According to one embodiment, it is possible to suppress an increase in costs and to perform traceability of semiconductor devices with high accuracy. Furthermore, it is possible to identify the cause of a defect in a semiconductor device early and provide feedback to a manufacturing method of the semiconductor device early. [Brief explanation of the drawings]

[0013] [Figure 1]3 is a flowchart showing a method for manufacturing a semiconductor device and a method for managing product history of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a plan view showing a wafer map in the first embodiment. [Figure 3] FIG. 2 is a plan view showing a chip region in the first embodiment. [Figure 4] FIG. 2 is a schematic diagram showing how data is stored in a storage device according to the first embodiment. [Figure 5] FIG. 2 is a schematic diagram showing how data is stored in a storage device according to the first embodiment. [Figure 6] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 7] 7A to 7C are cross-sectional views showing a manufacturing process following FIG. 6. [Figure 8] 8 is a cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a schematic diagram showing the manufacturing process following FIG. 10 and the subsequent product history management process for the semiconductor device. [Figure 12] FIG. 12 is a plan view showing the product history management process following FIG. [Figure 13] FIG. 13 is a plan view showing the product history management process following FIG. [Figure 14] FIG. 10 is a schematic diagram showing a method for matching surface morphology images in the second embodiment. [Figure 15] FIG. 11 is a plan view showing a shape pattern of a metal film in the third embodiment. [Figure 16] FIG. 11 is a plan view showing a chip region in a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0015] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0016] (Embodiment 1) <Method for manufacturing semiconductor device and method for managing product history of semiconductor device> A method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the first embodiment will be described below with reference to Fig. 1. The method for managing the product history of the semiconductor device 100 includes steps S1 to S18 shown in Fig. 1. The method for manufacturing the semiconductor device 100 is part of the method for managing the product history of the semiconductor device 100, and includes steps S1 to S13.

[0017] In addition, in the description of steps S1 to S18, FIGS. 2 to 13 will be used as necessary.

[0018] In step S1, first, a wafer WF is prepared, and a wafer identification number ID is assigned to a portion of the wafer WF as shown in FIG. 4. Next, as shown in FIG. 2, the wafer WF is partitioned into a plurality of chip areas CHPa arranged in a matrix, and a wafer map WFM is generated. Each of the plurality of chip areas CHPa is partitioned by a dicing line DL. The plurality of chip areas CHPa are singulated along the dicing lines DL to obtain a plurality of semiconductor chips CHP.

[0019] 3 is a plan view showing the details of the chip area CHPa (semiconductor chip CHP). The chip area CHPa has multiple wiring layers, and the uppermost wiring layer of the multiple wiring layers has multiple metal films MF. The multiple metal films MF include multiple wirings M9 and multiple dummy patterns DP.

[0020] Although not shown here, the plurality of wirings M9 and the plurality of dummy patterns DP are covered with a protective film PF. Openings are provided in parts of the protective film PF. Portions of the plurality of wirings M9 exposed through the openings become pad electrodes PAD. The portions surrounded by dashed lines in FIG. 3 are pad electrodes PAD. By connecting external connection members such as bonding wires or bump electrodes onto the pad electrodes PAD, the semiconductor chip CHP can be electrically connected to another semiconductor chip, a wiring board, or the like.

[0021] The wirings M9 are electrically connected to a semiconductor element 1Q, which will be described later. The dummy patterns DP are not electrically connected to the semiconductor element 1Q and are electrically floating. Furthermore, no external connection members are connected to the dummy patterns DP.

[0022] In step S2, semiconductor elements 1Q are formed in each of the plurality of chip regions CHPa. Each manufacturing process for forming the semiconductor elements 1Q will be described below with reference to FIGS. 6 to 8. Here, an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as an example of the semiconductor element 1Q. Note that the n-type MOSFET is one example of the semiconductor element 1Q, and a plurality of other semiconductor elements, such as p-type MOSFETs, capacitance elements, and resistance elements, are formed on the wafer WF, but their description will be omitted here.

[0023] 6, first, a wafer WF made of a p-type single crystal silicon substrate is prepared. The wafer WF may be a laminate of the single crystal silicon substrate and a silicon layer formed on the single crystal silicon substrate by epitaxial growth.

[0024] Next, an insulating film such as a silicon nitride film is formed on the wafer WF by a film formation process using, for example, a CVD (Chemical Vapor Deposition) method. Next, a hard mask is formed by patterning the insulating film. Next, trenches are formed in the wafer WF using the hard mask as a mask. Next, an insulating film such as a silicon oxide film is formed on the wafer WF by a film formation process using, for example, a CVD method so as to fill the insides of the trenches. Next, the insulating film located outside the trenches is removed by a polishing process using a CMP (Chemical Mechanical Polishing) method. Next, the hard mask is removed by a wet etching process. As a result of the above, multiple element isolation portions STI that define active regions are formed in the wafer WF.

[0025] 7, first, a well region DNW, which is an n-type impurity region, is formed in the wafer WF by photolithography and ion implantation. Next, a well region PW, which is a p-type impurity region, is formed in the well region DNW by photolithography and ion implantation.

[0026] Next, a gate insulating film GI made of a silicon oxide film is formed on the wafer WF by thermal oxidation. Next, an n-type polycrystalline silicon film, for example, is formed on the gate insulating film GI by a film formation process using, for example, a CVD method. Next, the polycrystalline silicon film is patterned to form a gate electrode GE.

[0027] As shown in FIG. 8, first, in the well region PW exposed from the gate electrode GE, an extension region NEX, which is an n-type impurity region, is formed by photolithography and ion implantation.

[0028] Next, a silicon oxide film and a silicon nitride film are sequentially formed by a film formation process using, for example, a CVD method so as to cover the gate electrode GE. Next, the silicon oxide film and the silicon nitride film are processed by an anisotropic etching process. As a result, sidewall spacers SW are formed on the side surfaces of the gate electrode GE.

[0029] Next, in the well region PW exposed by the sidewall spacer SW, a high-concentration diffusion region NR, which is an n-type impurity region, is formed by photolithography and ion implantation. The high-concentration diffusion region NR has an impurity concentration higher than that of the extension region NEX.

[0030] As a result of the above, an n-type MOSFET is formed as the semiconductor element 1Q. The n-type MOSFET has a gate insulating film GI, a gate electrode GE, sidewall spacers SW, extension regions NEX, and heavily doped diffusion regions NR. The extension regions NEX and heavily doped diffusion regions NR form the source region or drain region of the n-type MOSFET. The portion of the well region PW that is sandwiched between the two extension regions NEX and located below the gate electrode GE forms the channel region of the n-type MOSFET.

[0031] In step S3, a multi-layer wiring layer is formed in each of the chip areas CHPa, the multi-layer wiring layer being located above the semiconductor element 1Q. Each manufacturing step for forming the multi-layer wiring layer will be described below with reference to FIGS.

[0032] The multi-layer wiring layer is composed of, for example, a first wiring layer WL1 to a ninth wiring layer WL9. Here, the ninth wiring layer WL9 is the uppermost wiring layer of the multi-layer wiring layer, but the number of wiring layers is just an example and can be changed as appropriate.

[0033] 9, a plurality of wirings M1 to M8 are formed in the first wiring layer WL1 to the eighth wiring layer WL8, respectively. The plurality of wirings M1 to M8 can be formed using an existing damascene method or dual damascene method. The plurality of wirings M1 to M8 are each composed of, for example, a barrier metal film including a tantalum film and a tantalum nitride film, and a copper film formed on the barrier metal film and having a thickness greater than that of the barrier metal film.

[0034] As shown in FIG. 10 , first, an interlayer insulating film IL9 is formed on the eighth wiring layer WL8 by a film formation process using, for example, a CVD method. The interlayer insulating film IL9 is made of, for example, a silicon oxide film. Next, contact holes are selectively formed in the interlayer insulating film IL9 by photolithography and anisotropic etching. Next, a titanium nitride film and a tungsten film are sequentially formed on the interlayer insulating film IL9 by a film formation process using a sputtering method or a CVD method so as to fill the inside of the contact hole. Next, the titanium nitride film and the tungsten film located outside the contact hole are removed by a polishing process using a CMP method, thereby forming a via V9 inside the contact hole.

[0035] Next, an aluminum-based film is formed on the interlayer insulating film IL9 by a film formation process using a sputtering method or a CVD method. Specifically, the aluminum-based film is a laminated film including a barrier metal film made of, for example, a titanium tungsten film and an aluminum alloy film, which is formed on the barrier metal film and has, for example, copper or silicon added thereto.

[0036] Next, the aluminum-based film is patterned using photolithography and anisotropic etching. This forms multiple metal films MF in the ninth wiring layer. As shown in Figure 2, the multiple metal films MF include multiple wirings M9 and multiple dummy patterns DP.

[0037] Next, a protective film PF is formed on the interlayer insulating film IL9 by a film formation process using, for example, a CVD method so as to cover the multiple wirings M9 and the multiple dummy patterns DP. The protective film PF is, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride film, or a laminate film formed by appropriately stacking these. Next, a portion of the protective film PF located on the wirings M9 is patterned using photolithography and anisotropic etching to expose the region of the wirings M9 that will become the pad electrode PAD. The protective film PF may further include a polyimide film.

[0038] On the surface of the pad electrode PAD, an external connection member BW such as a bonding wire or a bump electrode is formed in step S7 described later.

[0039] As a result of the above, a multi-layer wiring layer having the metal film MF in the uppermost wiring layer (ninth wiring layer WL9) is formed.

[0040] Moreover, the processing history included in the manufacturing process of the semiconductor element 1Q in step S2 and the manufacturing process of the multi-layer wiring layer in step S3 is stored in the storage device MD.

[0041] In step S4, a surface morphology image 1AI of a specific area 1A of the metal film MF is acquired in each of the plurality of chip regions CHPa.

[0042] As shown in FIG. 3, a portion of the metal film MF present in the chip area CHPa is provided as a specific area 1A. The position of the specific area 1A is the same for each of the multiple chip areas CHPa. In the example of FIG. 3, for example, a portion of the dummy pattern DP is used as the specific area 1A. A portion of the wiring M9 that is not used as a pad electrode PAD may also be used as the specific area 1A. The planar size of the specific area 1A is, for example, 50 μm×50 μm or more and 200 μm×200 μm or less.

[0043] As shown in FIG. 11, a surface morphology image 1AI of a specific area 1A is acquired for each of a plurality of chip regions CHPa, and the surface morphology images 1AI are stored in the memory device MD.

[0044] In step S4, it is desirable to acquire a surface morphology image 1AI through the protective film PF while the specific area 1A is covered with the protective film PF. The surface morphology image 1AI is later used for comparison with a surface morphology image 2AI of the semiconductor device 200 determined to be defective. For example, if the specific area 1A is set within a pad electrode PAD, there is a risk that an external connection member BW will be provided in the specific area 1A. In this case, it will be impossible to acquire a surface morphology image 2AI of the semiconductor device 200.

[0045] Furthermore, if the specific area 1A is not covered with the protective film PF when the surface morphology image 2AI is acquired, there is a risk that the surface condition of the specific area 1A of the semiconductor device 200 will change, which makes it difficult to acquire an accurate surface morphology image 2AI.

[0046] 4, the wafer identification number ID, the position information of the plurality of chip regions CHPa, the position information of the specific area 1A within the chip region CHPa, and the surface morphology image 1AI for each of the plurality of chip regions CHPa are linked and stored in the memory device MD. The surface morphology image 1AI linked with each piece of information in this way can be effectively used for traceability of the semiconductor device 200 determined to be defective.

[0047] In step S6, the plurality of chip areas CHPa of the wafer WF are diced along the dicing lines DL to obtain a plurality of semiconductor chips CHP.

[0048] In step S7, a plurality of semiconductor devices 100 are formed by sealing the plurality of semiconductor chips CHP with sealing resin SR.

[0049] For example, first, the semiconductor chip CHP is mounted on a lead frame, and the pad electrodes PAD are electrically connected to the lead terminals using external connection members BW. Next, the semiconductor chip CHP and each lead terminal are encapsulated with a sealing resin SR such as epoxy resin. Each lead terminal is then separated from the lead frame to form a semiconductor device 100 as shown in FIG.

[0050] As described above, a plurality of semiconductor devices 100 can be obtained from the wafer WF.

[0051] In embodiment 1, in the process of manufacturing the semiconductor device 100 from the wafer WF, in-line inspection, electrical characteristic testing, and screening testing are performed, and the acquired inspection data or test data is used to identify defects in the semiconductor device 200 described below.

[0052] In step S8, an in-line inspection is appropriately performed during steps S3 and S4. The in-line inspection includes, for example, one or more of a foreign substance inspection, a defect inspection, a dimension inspection, an overlay inspection, and a visual inspection.

[0053] In step S9, before step S6 is performed, an electrical characteristic test is performed on the semiconductor elements 1Q for each of the plurality of chip areas CHPa.

[0054] In step S10, before step S9 is performed, a screening test is performed to screen the reliability of each of the plurality of semiconductor devices 100. The screening test is, for example, a burn-in test.

[0055] As described above, the processing history included in the manufacturing process of the semiconductor element 1Q in step S2 and the manufacturing process of the multi-layer wiring layer in step S3 is stored in the storage device MD.

[0056] In step S11, as shown in FIG. 5, the processing history, the inspection data from the in-line inspection, the test data from the electrical characteristic test, the test data from the sorting test, and the surface morphology image 1AI for each of the multiple chip areas CHPa are linked and stored in the memory device MD.

[0057] For example, suppose a foreign particle is detected in a chip area CHPa during in-line foreign particle inspection. At this point, the process history can be referenced to review the manufacturing conditions of the manufacturing process in which the foreign particle occurred. However, not all foreign particles directly lead to defects, and some foreign particles will not lead to defects even if left unattended. Therefore, if the foreign particle does not affect the electrical characteristics of the semiconductor element 1Q or the reliability of the semiconductor device 100, it may be determined that the foreign particle can be left unattended.

[0058] However, there is a possibility that the semiconductor device 100 may become defective for some reason during use, and a failure analysis may reveal that the neglected foreign matter was the cause of the defect. In this way, in order to quickly perform traceability on the semiconductor device 100 having a potential defect factor and identify the cause of the defect, the processing history, each inspection data, and each test data are linked to the surface morphology image 1AI.

[0059] In step S12, as shown in Fig. 11, a semiconductor device 200 determined to be defective is acquired. The semiconductor device 200 determined to be defective is, for example, a semiconductor device that has been shipped to a customer and then returned because the customer pointed out a defect. In order to perform traceability on such a semiconductor device 200, the sealing resin SR of the semiconductor device 200 is opened. Furthermore, the external connection member BW of the semiconductor device 200 is removed as necessary.

[0060] In step S13, a surface morphology image 2AI is acquired for a portion of the metal film MF provided on the semiconductor device 200 that corresponds to the specific area 1A. At this time, if the portion corresponding to the specific area 1A is covered with a protective film PF, the surface morphology image 2AI may be acquired with the protective film PF remaining, or the surface morphology image 2AI may be acquired after the protective film PF is removed. Because the specific area 1A is protected by the protective film PF, the surface of the specific area 1A remains in good condition even after the sealing resin SR is removed. Therefore, a highly accurate surface morphology image 2AI can be acquired.

[0061] In step S14, as shown in FIG. 12, the surface morphology image 2AI is compared with the surface morphology images 1AI for each of the multiple chip areas CHPa stored in the memory device MD, thereby identifying the wafer identification number ID of the wafer WF on which the semiconductor device 200 is manufactured and the position of the chip area CHPa1 on which the semiconductor device 200 is manufactured.

[0062] If the surface morphology image 2AI does not match any of the surface morphology images 1AI for the plurality of chip areas CHPa stored in the memory device MD, the semiconductor device 200 can be identified as a counterfeit product.

[0063] In step S15, the position of the chip area CHPa1 in which the semiconductor device 200 is manufactured is identified, thereby making it possible to identify the processing history corresponding to the semiconductor device 200, and to identify one or more of the inspection data from the in-line inspection, the test data from the electrical characteristic test, and the test data from the sorting test corresponding to the semiconductor device 200.

[0064] For example, if the chip area CHPa1 in which the semiconductor device 200 was manufactured was the chip area CHPa in which a foreign substance that would not cause any problems if left alone was detected during a foreign substance inspection, it can be inferred that the foreign substance may have been the cause of the defect.

[0065] In step S16, a failure analysis is performed on the semiconductor device 200. The failure analysis includes one or more of an optical emission analysis, an OBIRCH analysis, a DLS analysis, an IDDQ analysis, a heat generation analysis, a nanoprober analysis, and an EBAC analysis.

[0066] In step S17, the cause of defects in the semiconductor device 200 can be identified from the relationship between the analysis data of the failure analysis and one or more of the inspection data of the in-line inspection corresponding to the semiconductor device 200, the test data of the electrical characteristic test, and the test data of the screening test.

[0067] If the inspection data from the in-line inspection, the test data from the electrical characteristic test, and the test data from the screening test corresponding to the semiconductor device 200 are identified in step S15, the appropriate analysis can be prioritized among the failure analyses performed in step S16. For example, in the case of a semiconductor device 200 that has a history of detecting a foreign particle in a foreign particle inspection and a history of not detecting an abnormality in a dimensional inspection, it can be predicted that there is a high possibility that the defect was caused by the detected foreign particle. Therefore, a failure analysis appropriate for detecting the predicted defect can be prioritized.

[0068] In step S18, the result of step S17 is fed back to the manufacturing method of the semiconductor device 100. For example, the result of step S17 is fed back to steps S2 and S3, and each manufacturing condition is reviewed. For example, if a foreign particle detected during a foreign particle inspection performed as an in-line inspection is identified as the cause of the defect, a countermeasure can be taken, such as reviewing the manufacturing process immediately before the foreign particle was generated, by referring to the processing history. Alternatively, a countermeasure can be taken, such as not commercializing the chip area CHPa1.

[0069] 13, in step S15, there may be another chip area CHPa having similar data to the inspection data of the in-line inspection, the test data of the electrical characteristic test, and the test data of the screening test corresponding to the semiconductor device 200 (chip area CHPa1). In this case, it can be estimated that the semiconductor device 100 manufactured from the corresponding chip area CHPa is likely to have the same defects as the semiconductor device 200. Therefore, the corresponding chip area CHPa may be collated on the wafer map WFM, and the same feedback as in step S18 may be performed for the corresponding chip area CHPa.

[0070] As described above, according to the first embodiment, traceability can be achieved without the need to attach an identification mark to every semiconductor chip CHP or to perform special processing within the wafer WF, thereby suppressing increases in costs associated with traceability.

[0071] Furthermore, an accurate surface morphology image 2AI can be acquired even after the sealing resin SR is opened and the external connection member BW is removed. That is, information that leads to the identification of the semiconductor chip CHP can be acquired with high accuracy. Furthermore, the cause of the defect in the semiconductor device 200 can be identified early, and feedback can be provided to the manufacturing method of the semiconductor device 100 early. As a result, after feedback, highly reliable semiconductor devices 100 can be supplied, the yield can be improved, and the release of defective products into the market can be suppressed.

[0072] (Embodiment 2) 14, a method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the second embodiment will be described below. Note that in the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0073] In the second embodiment, as shown in FIG. 14, a surface morphology image 1AI and a surface morphology image 2AI are collated using a plurality of feature amounts extracted from each image.

[0074] In step S4, the surface morphology image 1AI is acquired and multiple feature amounts are extracted from the surface morphology image 1AI. For example, an intersection of multiple line segments or the center of an area surrounded by line segments is defined as a feature point in the surface morphology image 1AI, and feature amounts at the feature point are extracted.

[0075] In step S5, the plurality of feature amounts are stored in the storage device MD as information related to the surface morphology image 1AI.

[0076] In step S13, a surface morphology image 2AI is acquired, and a plurality of feature amounts of the surface morphology image 2AI are extracted.

[0077] In step S14, the surface morphology image 2AI is matched with the surface morphology image 1AI for each of the multiple chip areas CHPa stored in the memory device MD by comparing multiple feature amounts of the surface morphology image 2AI with multiple feature amounts of the surface morphology image 1AI.

[0078] In the second embodiment, a plurality of feature amounts are compared with each other, so even if the coordinates of the surface morphology image 1AI and the surface morphology image 2AI do not completely match, it is possible to determine whether the images are within the specific area 1A.

[0079] For example, there may be cases where the coordinates at which the surface morphology image 2AI was captured are slightly different from the coordinates at which the surface morphology image 1AI was captured, or where the surface morphology image 2AI was captured in a rotated state relative to the surface morphology image 1AI. Even in such cases, if multiple feature amounts match, these images can be determined to be images within the specific area 1A. Therefore, by using multiple feature amounts from each other, the accuracy of matching between the surface morphology image 1AI and the surface morphology image 2AI can be improved.

[0080] (Embodiment 3) 15, a method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the third embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0081] In the third embodiment, as shown in Fig. 15, a geometric pattern 20 is provided on a metal film MF located within a specific area 1A, around the specific area 1A, or both. In Fig. 15, the region of the metal film MF surrounded by a dashed line is shown as the specific area 1A. Fig. 15 also illustrates a case where a rectangular dummy pattern DP is used as the metal film MF including the specific area 1A.

[0082] By providing the geometric pattern 20, it becomes easier to find the specific area 1A when acquiring the surface morphology image 1AI or the surface morphology image 2AI. This makes it easier to align the exact coordinates of the specific area 1A, improving the accuracy of matching the surface morphology image 1AI with the surface morphology image 2AI. The shape data of the geometric pattern 20 is stored in the memory device MD as information related to the position information of the specific area 1A within the chip area CHPa.

[0083] As examples of the geometric pattern 20, "Pattern 1" to "Pattern 4" shown in FIG. 15 are shown. In "Pattern 1," a plurality of irregularities are provided as the geometric pattern 20 on at least one of the four sides of the metal film MF in a planar view. In "Pattern 2," three two-dimensional code patterns are provided on the metal film MF as the geometric pattern 20. In the case of "Pattern 2," the area surrounded by the three geometric pattern patterns 20 can be recognized as the specific area 1A. In "Pattern 3" and "Pattern 4," slits are provided on the metal film MF as the geometric pattern 20.

[0084] The geometric design pattern 20 is not limited to the shapes of "Pattern 1" to "Pattern 4", and may be any other pattern as long as it has a shape that makes it easy to find the specific area 1A.

[0085] The technology disclosed in the third embodiment can be applied in combination with the technology disclosed in the second embodiment.

[0086] (Fourth embodiment) 16, a method for manufacturing the semiconductor device 100 and a method for managing the product history of the semiconductor device 100 according to the fourth embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0087] In the fourth embodiment, a plurality of specific areas 1A are provided in the chip area CHPa as shown in Fig. 16. In step S4, a surface morphology image 1AI is acquired for each of the plurality of specific areas 1A in the plurality of chip areas CHPa.

[0088] In step S13, a plurality of surface morphology images 2AI of locations corresponding to a plurality of specific areas 1A are obtained.

[0089] In step S14, the plurality of surface morphology images 2AI are collated with the plurality of surface morphology images 1AI for each of the plurality of chip areas CHPa stored in the memory device MD.

[0090] When a surface morphology image 1AI of only one specific area 1A is acquired for one chip region CHPa, and the portion of the semiconductor device 200 determined to be defective that corresponds to the specific area 1A is damaged or deformed, it becomes difficult to acquire a surface morphology image 2AI. For example, stress from the sealing resin SR or the protective film PF may damage or deform a portion of the metal film MF.

[0091] If multiple surface morphology images 1AI of multiple specific areas 1A are acquired for one chip region CHPa, even if it is difficult to acquire a surface morphology image 2AI at a certain location, it is possible to acquire a surface morphology image 2AI at another location. Therefore, according to the fourth embodiment, it becomes easy to eliminate the risk that the surface morphology image 1AI and the surface morphology image 2AI cannot be matched.

[0092] The technique disclosed in the fourth embodiment can be applied in combination with the techniques disclosed in the second and third embodiments.

[0093] Although the present invention has been specifically described above based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0094] 100 Semiconductor device 200 Semiconductor device judged to be defective 20 Geometric Patterns 1A Specific Area 1AI, 2AI surface morphology images 1Q semiconductor element BW external connection materials CHP semiconductor chip CHPa chip area CHPa1 identified chip region DL dicing line DP Dummy Pattern DNW well region GE gate electrode GI gate insulating film ID Wafer identification number IL9 interlayer insulating film M1 to M9 wiring MD storage device MF metal film NEX Extension Area NR high concentration diffusion region PAD Pad electrode PF protective film PW well region SR sealing resin STI element isolation section SW Sidewall Spacer V9 Via WF wafer WFM Wafer Map WL1 to WL9 wiring layers

Claims

1. (a) assigning a wafer identification number to a wafer of semiconductor material; (b) partitioning the wafer into a plurality of chip regions arranged in a matrix to generate a wafer map; (c) forming semiconductor elements in each of the plurality of chip regions; (d) forming a multilayer wiring layer in each of the plurality of chip regions, the multilayer wiring layer being located above the semiconductor element and having a metal film in its uppermost wiring layer; (e) acquiring a first surface morphology image of a specific area of ​​the metal film in each of the plurality of chip regions; (f) storing the wafer identification number, the position information of the plurality of chip regions, the position information of the specific area within the chip region, and the first surface morphology image for each of the plurality of chip regions in a storage device in association with each other; A method for manufacturing a semiconductor device, comprising:

2. 2. The method for manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the metal film is a film containing aluminum as a main component.

3. 2. The method for manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein an external connection member is not connected to the metal film.

4. 2. The method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the specific area has a planar size of 50 μm×50 μm or more and 200 μm×200 μm or less.

5. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (d), a protective film is formed on a part of the metal film so as to cover the specific area; In the step (e), the first surface morphology image is acquired through the protective film.

6. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (e), a plurality of first feature amounts are extracted from the first surface morphology image; In the step (f), the plurality of first feature amounts are stored in the storage device as information related to the first surface morphology image.

7. 2. The method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein a geometric pattern is provided on the metal film located within the specific area, around the specific area, or both.

8. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (e), a plurality of the first surface morphology images of a plurality of the specific areas are acquired in each of the plurality of chip regions.

9. 2. The method for manufacturing a semiconductor device according to claim 1, (g) storing in the storage device a process history included in the manufacturing process of the semiconductor element in the process (c) and the manufacturing process of the multilayer wiring layer in the process (d); (h) performing in-line inspection during the steps (c) and (d); (i) storing the processing history, the inspection data of the in-line inspection, and the first surface morphology image for each of the plurality of chip regions in the storage device in association with each other; The method for manufacturing a semiconductor device further comprises:

10. 10. The method for manufacturing a semiconductor device according to claim 9, The method for manufacturing a semiconductor device, wherein the in-line inspection includes any one or more of a foreign substance inspection, a defect inspection, a dimension inspection, an overlay inspection, and a visual inspection.

11. 2. The method for manufacturing a semiconductor device according to claim 1, (j) performing an electrical characteristic test on the semiconductor elements in each of the plurality of chip regions; (k) linking the test data of the electrical characteristic test with the first surface morphology image for each of the plurality of chip regions and storing them in the storage device; The method for manufacturing a semiconductor device further comprises:

12. 2. The method for manufacturing a semiconductor device according to claim 1, (l) obtaining a plurality of semiconductor chips by singulating the plurality of chip regions of the wafer; (m) forming a plurality of first semiconductor devices by sealing the plurality of semiconductor chips with a sealing resin; (n) performing a screening test to screen the reliability of each of the plurality of first semiconductor devices; (o) linking test data of the screening test with the first surface morphology image for each of the plurality of chip regions and storing the linked test data in the storage device; The method for manufacturing a semiconductor device further comprises:

13. (a) assigning a wafer identification number to a wafer of semiconductor material; (b) partitioning the wafer into a plurality of chip regions arranged in a matrix to generate a wafer map; (c) forming semiconductor elements in each of the plurality of chip regions; (d) forming a metal film in an uppermost wiring layer of a multilayer wiring layer located above the semiconductor element in each of the plurality of chip regions; (e) acquiring a first surface morphology image of a specific area of ​​the metal film in each of the plurality of chip regions; (f) storing the wafer identification number, the position information of the plurality of chip regions, the position information of the specific area within the chip region, and the first surface morphology image for each of the plurality of chip regions in a storage device in association with each other; (g) obtaining a plurality of semiconductor chips by singulating the plurality of chip regions of the wafer; (h) forming a plurality of first semiconductor devices by sealing the plurality of semiconductor chips with sealing resin; (i) acquiring a second semiconductor device determined to be defective; (j) removing the sealing resin from the second semiconductor device and acquiring a second surface morphology image of a portion of the metal film provided on the second semiconductor device that corresponds to the specific area; (k) identifying the wafer identification number of the wafer on which the second semiconductor device is manufactured and the position of the chip area on which the second semiconductor device is manufactured by collating the second surface morphology image with the first surface morphology image for each of the plurality of chip areas stored in the storage device; A semiconductor device product history management method comprising:

14. 14. The method for managing product history of a semiconductor device according to claim 13, (l) storing in the storage device a processing history included in the manufacturing process of the semiconductor element in the step (c) and the manufacturing process of the multilayer wiring layer in the step (d); (m) linking the processing history with the first surface morphology image for each of the plurality of chip regions and storing the linked processing history in the storage device; Further provided with A semiconductor device product history management method, in which the processing history corresponding to the second semiconductor device can be identified by identifying the position of the chip region in which the second semiconductor device is manufactured in the step (k).

15. 15. The semiconductor device product history management method according to claim 14, (n) performing in-line inspection during the (c) step and the (d) step; (o) performing an electrical characteristic test on the semiconductor element; (p) after the step (h), performing a screening test to screen the reliability of each of the plurality of first semiconductor devices; (q) linking the inspection data of the in-line inspection, the test data of the electrical characteristic test, the test data of the screening test, and the first surface morphology image for each of the plurality of chip regions, and storing them in the storage device; Further provided with A product history management method for semiconductor devices, which can identify one or more of the inspection data of the in-line inspection, the test data of the electrical characteristic test, and the test data of the sorting test corresponding to the second semiconductor device by identifying the position of the chip area in which the second semiconductor device was manufactured in the (k) step.

16. 16. The semiconductor device product history management method according to claim 15, (r) performing a failure analysis on the second semiconductor device; Further provided with A product history management method for semiconductor devices, which can identify the cause of defects in the second semiconductor device from the relationship between the analysis data of the failure analysis and one or more of the inspection data of the in-line inspection corresponding to the second semiconductor device, the test data of the electrical characteristic test, and the test data of the screening test.

17. 17. The semiconductor device product history management method according to claim 16, The failure analysis includes at least one of an optical emission analysis, an OBIRCH analysis, a DLS analysis, an IDDQ analysis, a heat generation analysis, a nanoprober analysis, and an EBAC analysis.

18. 18. The semiconductor device product history management method according to claim 17, The identified cause of the defect of the second semiconductor device is fed back to the steps (c) and (d).

19. 14. The method for managing product history of a semiconductor device according to claim 13, A product history management method for semiconductor devices, wherein the second semiconductor device can be identified as a counterfeit product if the second surface morphology image does not match any of the first surface morphology images for each of the plurality of chip regions stored in the storage device.

20. 2. The semiconductor device product history management method according to claim 1, In the step (e), a plurality of first feature amounts are extracted from the first surface morphology image; In the step (g), the plurality of first feature amounts are stored in the storage device as information related to the first surface morphology image; In the step (j), a plurality of second feature amounts of the second surface morphology image are extracted; In the step (k), the second surface morphology image is matched with the first surface morphology image for each of the plurality of chip regions stored in the memory device by comparing the plurality of second features with the plurality of first features stored in the memory device.

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