Semiconductor device

Abstract

To provide a semiconductor device capable of being downsized.SOLUTION: A semiconductor device 1 comprises: power transistors H_PN, L_PN supplying current to a load 2; a current detection circuit detecting current flowing through the power transistors H_PN, L_PN; a device control circuit controlling current flowing through the power transistors H_PN, L_PN on the basis of first detection current H_DI1, L_DI1 based on the current detected by the current detection circuit and an input signal Inp; an over range comparator circuit outputting over range signals H_OV, L_OV when voltage of the power transistors H_PN, L_PN exceeds a prescribed voltage; and an abnormal signal generation circuit 6 outputting an abnormal signal EER indicative of the excess current state of the power transistors on the basis of second detection current H_DI2, L_DI2 based on current detected by the current detection circuit and the over range signals H_OV, L_OV.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device equipped with a detection technique for detecting a current in a power device that drives a load such as a coil. [Background technology]

[0002] Techniques for detecting the current flowing through a power device are disclosed in, for example, Patent Documents 1 to 3.

[0003] Patent Document 1 describes a technology in which a sense transistor (7) detects a current proportional to the current of a high-side transistor (Figure 1: symbol 2), which is a power device, and an operational amplifier (13) performs feedback control so that the voltage at node (11) (the source voltage of the sense transistor 7) is the same as the voltage at node (5) (the source voltage of the high-side transistor 2), thereby aligning the gate-source voltage and the drain-source voltage of the high-side transistor (2) and the sense transistor (7), thereby detecting the current with high precision.

[0004] Like Patent Document 1, Patent Document 2 discloses a technology in which a current proportional to the current of a high-side transistor (Tr1 in Figure 12) is detected by a sense transistor (NM1), and an operational amplifier (A1) is controlled so that the drain voltage of the sense transistor is the same as the drain voltage of the high-side transistor, thereby aligning the gate-source voltage and drain-source voltage of the sense transistor and high-side transistor and detecting the current with high precision.

[0005] Patent Document 3 discloses a technology that reduces the difference in the degree of degradation between the high-side transistor and the sense transistor by connecting a switch (SW3) between the high-side transistor (MN1 in Figure 4) and the sense transistor (Tr11) and controlling the switch (SW3) so that the source-drain voltages are the same when the high-side transistor and the sense transistor are in the off state. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 6,377,034 [Patent Document 2] U.S. Patent No. 10,256,725 [Patent Document 3] U.S. Patent No. 1,138,5266 Summary of the Invention [Problem to be solved by the invention]

[0007] The present inventors have studied a semiconductor device that detects a current proportional to the current of a power device and controls the power device based on the detected current, using the techniques shown in Patent Documents 1 to 3. As will be explained later with reference to the drawings, the inventors' study has revealed a problem in that the area occupied by a detection circuit that detects the current of a power device becomes large. [Means for solving the problem]

[0008] A brief summary of a representative embodiment of the present invention will be given below.

[0009] That is, a semiconductor device according to one embodiment includes a power device that supplies current to a load, a current detection circuit that detects the current flowing through the power device, a device control circuit that controls the current flowing through the power device based on a first detection current based on the current detected by the current detection circuit and an input signal, an overrange comparison circuit that outputs an overrange signal when the voltage of the power device exceeds a predetermined voltage, and an abnormality signal generation circuit that outputs an abnormality signal indicating an overcurrent state of the power device based on a second detection current based on the current detected by the current detection circuit and the overrange signal.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Effects of the Invention]

[0011] According to one embodiment, it is possible to provide a semiconductor device that can be miniaturized by suppressing an increase in the area occupied by the detection circuit. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing a configuration of a high-side detection circuit according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram showing a configuration of the overrange comparison circuit according to the first embodiment. [Figure 4] 4(A) and 4(B) are circuit diagrams showing the configuration of the generating circuit unit according to the first embodiment. [Figure 5] FIG. 5 is a circuit diagram showing a configuration of a low-side detection circuit according to the first embodiment. [Figure 6] FIG. 6 is a circuit diagram showing a configuration of the overrange comparison circuit according to the first embodiment. [Figure 7] 7(A) and 7(B) are circuit diagrams showing examples of the generating circuit unit according to the first embodiment. [Figure 8] FIG. 8 is a waveform diagram illustrating the operation of the high-side detection circuit according to the first embodiment. [Figure 9] FIG. 9 is a waveform diagram illustrating the operation of the low-side detection circuit according to the first embodiment. [Figure 10] FIG. 10 is a circuit diagram showing a state during self-diagnosis of the high-side detection circuit according to the first embodiment. [Figure 11] 11(A) and 11(B) are waveform diagrams for explaining the self-diagnosis function of the high-side detection circuit according to the first embodiment. [Figure 12]FIG. 12 is a circuit diagram illustrating a state during self-diagnosis of the low-side detection circuit according to the first embodiment. [Figure 13] FIG. 13 is a circuit diagram illustrating a state during self-diagnosis of the low-side detection circuit according to the first embodiment. [Figure 14] 14(A) to 14(D) are waveform diagrams for explaining the self-diagnosis function of the low-side detection circuit according to the first embodiment. [Figure 15] FIG. 15 is a circuit diagram showing a configuration of a high-side detection circuit according to the second embodiment. [Figure 16] FIG. 16 is a circuit diagram showing a configuration of an overrange comparison circuit according to the second embodiment. [Figure 17] FIG. 17 is a circuit diagram illustrating a configuration of a low-side detection circuit according to the second embodiment. [Figure 18] FIG. 18 is a circuit diagram showing a configuration of the overrange comparison circuit according to the second embodiment. [Figure 19] FIG. 19 is a block diagram showing a configuration of a first comparative example that detects a current flowing through a high-side N-type transistor. [Figure 20] FIG. 20 is a block diagram showing the configuration of Comparative Example 2 developed by the present inventors. [Figure 21] FIG. 21 is a waveform diagram for explaining the operation of the second comparative example. [Figure 22] FIG. 22 is a block diagram showing a configuration of a comparative example 3 that detects a current flowing through a low-side N-type transistor. [Figure 23] FIG. 23 is a block diagram showing the configuration of Comparative Example 4 developed by the present inventors. [Figure 24] FIG. 24 is a waveform diagram for explaining the operation of the fourth comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, various embodiments of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and any appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included within the scope of the present invention.

[0014] Furthermore, in this specification and each drawing, elements similar to those previously described with respect to the previous drawings are given the same reference numerals, and detailed descriptions thereof may be omitted as appropriate.

[0015] <Study by the present inventors> The present inventors have devised a method for detecting a current proportional to the current flowing through a power device, controlling the current of the power device to a desired value using the detected current, and detecting whether an abnormal overcurrent is flowing through the power device. In this case, the power device is composed of a high-side power device that supplies current to a load and a low-side power device that draws current from the load. Therefore, the present inventors have investigated a configuration for detecting current in both the high-side and low-side power devices. Furthermore, the present inventors have investigated a power device using a field-effect transistor (hereinafter simply referred to as a transistor). Although not particularly limited, this specification describes an example in which an N-channel transistor (hereinafter also referred to as an N-type transistor) is used as the power device, but the present invention is not limited thereto. For example, a P-channel transistor (hereinafter also referred to as a P-type transistor) may also be used as the power device. Note that a transistor has a source terminal, a drain terminal, and a gate terminal. However, in the following description, the source terminal and the drain terminal may be collectively referred to as a pair of terminals.

[0016] <<Comparative example of high side>> <<<Comparative Example 1>>> Fig. 19 is a block diagram showing the configuration of Comparative Example 1, which detects a current proportional to the current flowing through a high-side transistor. In Fig. 19, CB denotes a power supply terminal, to which a power supply voltage CBV is supplied from, for example, a battery. CH denotes an output terminal, to which a load is connected. In Fig. 19, a coil LL is connected as a load to the output terminal CH. Because it is on the high side, a current IL is supplied from the output terminal CH to the coil LL (hereinafter, the arrow indicates the direction of the current).

[0017] 19, H_PN denotes an N-type transistor (hereinafter also referred to as a power transistor) that constitutes a power device, and H_SN1 and H_SN2 denote N-type transistors (hereinafter also referred to as sense transistors) that sense a current proportional to the current flowing through the power transistor H_PN. The drain terminals of the power transistor H_PN and the sense transistor H_SN1 are connected to a power supply terminal CB, and the source terminals of the power transistor H_PN and the sense transistor H_SN2 are connected to an output terminal CH. The gate terminals of the power transistor H_PN and the sense transistors H_SN1 and H_SN2 are connected in common, and the output of the driver H_DRV is supplied to them.

[0018] The sizes of the sense transistors H_SN1 and H_SN2 are smaller than the size of the power transistor H_PN. For example, if the sizes of the sense transistors H_SN1 and H_SN2 are 1, the size of the power transistor H_PN is 4000. By connecting the gate terminals of the sense transistors H_SN1 and H_SN2 and the gate terminal of the power transistor H_PN together and driving them together with the driver H_DRV, a current proportional to the current IL flowing through the power transistor H_PN flows through the sense transistors H_SN1 and H_SN2. In this case, the ratio of the current flowing through the sense transistors H_SN1 and H_SN2 to the current IL flowing through the power transistor H_PN is proportional to the size of the transistors. That is, according to the size example described above, the current flowing through the sense transistors H_SN1 and H_SN2 is approximately 1 / 4000 of the current IL flowing through the power transistor H_PN.

[0019] The current flowing through the sense transistor H_SN1 is supplied to a current detection circuit H_IDC. This current detection circuit H_IDC is configured based on the configuration shown in Patent Document 1. The current detection circuit H_IDC is connected to a power supply terminal CB and a voltage regulator H_ARG. The voltage regulator H_ARG is connected to the power supply terminal CB and a ground voltage CGV, and generates a voltage CBV-VDDA by subtracting a predetermined voltage VDDA from the power supply voltage CBV supplied to the power supply terminal CB. As a result, the current detection circuit H_IDC operates using the power supply voltage CBV and the voltage CBV-VDDA at the power supply terminal CB as its power supply voltage.

[0020] Although not shown in FIG. 19, a signal corresponding to the difference between the current detected by the current detection circuit H_IDC and the target current is supplied to the driver H_DRV, and the driver H_DRV drives the power transistor H_PN and the sense transistors H_SN1 and H_SN2 to reduce the difference. The driver H_DRV is connected to the output terminal CH and the voltage regulator H_DRG. The voltage regulator H_DRG is connected to the voltage CPV and the output terminal CH, and generates a voltage CHV+VDDD by adding a predetermined voltage VDDD to the voltage CHV at the output terminal CH. The voltage CPV is a voltage generated by, for example, a charge pump circuit (not shown), and has a value higher than the power supply voltage CBV. As a result, the driver H_DRV operates using the voltage CHV+VDDD and the voltage CHV at the output terminal CH as its power supply voltage.

[0021] The current flowing through the sense transistor H_SN2 is supplied to an overcurrent detection circuit H_OID. The overcurrent detection circuit H_OID is configured based on the configuration shown in Patent Document 2. The overcurrent detection circuit H_OID operates using the power supply voltage CBV and the voltage CPV at the power supply terminal CB as power supplies. Based on the current flowing through the sense transistor H_SN2, the overcurrent detection circuit H_OID detects whether the current IL flowing through the power transistor H_PN exceeds a predetermined value. For example, if the output terminal CH is connected to the ground voltage CGV (a ground fault state) as shown by the dashed line, the current IL flowing through the power transistor H_PN becomes an overcurrent and is detected by the overcurrent detection circuit H_OID. Although not particularly limited, when an overcurrent is detected by the overcurrent detection circuit H_OID, for example, the driver H_DRV drives the power transistor H_PN and the sense transistors H_SN1 and H_SN2 to an off state.

[0022] 19, the current IL flowing through the power transistor H_PN can be controlled to a desired value based on the current detected by the current detection circuit H_IDC. Also, the overcurrent detection circuit H_OID can detect whether an abnormal overcurrent is flowing through the power device.

[0023] However, in the configuration of Comparative Example 1, the current flowing through the power transistor H_PN is detected by individual sense transistors (H_SN1 and H_SN2) and detection circuits (current detection circuit H_IDC and overcurrent detection circuit H_OID), which poses a problem of a large occupied area. Therefore, the inventors developed Comparative Example 2, which will be described next.

[0024] <<<Comparative Example 2>>> FIG. 20 is a block diagram showing the configuration of Comparative Example 2 developed by the present inventors to solve the problem of the occupied area. The main difference from Comparative Example 1 shown in FIG. 19 is that in FIG. 20, the sense transistor H_SN2 and the overcurrent detection circuit H_OID are eliminated, and the current flowing through the sense transistor H_SN1 is supplied to the current detection circuit / overcurrent detection circuit H_IOD rather than the current detection circuit H_IDC. The current detection circuit / overcurrent detection circuit H_IOD detects a current used to control the current IL flowing through the power transistor H_PN to a desired value based on the current flowing through the sense transistor H_SN1, and also detects overcurrents generated by ground faults, etc. This solves the problem of a large occupied area.

[0025] However, when the inventors further studied Comparative Example 2, they found that, as will be explained below with reference to FIG. 21, when an overcurrent flows through the power transistor H_PN due to a ground fault or the like, the sense transistor H_SN1 turns off, and a current proportional to the overcurrent flowing through the power transistor H_PN is not supplied to the current detection circuit and overcurrent detection circuit H_IOD, making it impossible to detect a ground fault or the like.

[0026] Fig. 21 is a waveform diagram for explaining the operation of Comparative Example 2. Fig. 21 shows the state from which the output terminal CH changes from a normal state to a ground-fault state (the output terminal CH is short-circuited to the ground voltage CGV). In Fig. 21, the horizontal axis represents the current IL flowing through the power transistor H_PN, and the vertical axis represents the voltage of each part (node) of Comparative Example 2. The value of the current IL flowing through the power transistor H_PN increases from a value rg0 (normal state) to a value rg4 (ground-fault state).

[0027] 21, SN1_G denotes the gate voltage supplied from the driver H_DRV to the gate terminal of the sense transistor H_SN1. When the power transistor H_PN is in the on state, the voltage CHV of the output terminal CH becomes equal to the power supply voltage CBV of the power supply terminal CB, and therefore the gate voltage SN1_G changes from the voltage CHV (=CBV)+VDDD, as shown in FIG.

[0028] 21, the dashed line CHV indicates the voltage of the output terminal CH, SN1_S indicates the source voltage of the source terminal of the sense transistor H_SN1, and SN1_GS indicates the gate-source voltage of the sense transistor H_SN1.

[0029] The current detection circuit and overcurrent detection circuit H_IOD is configured based on the configuration shown in Patent Document 1. That is, the current detection circuit and overcurrent detection circuit H_IOD includes an operational amplifier (not shown) (corresponding to reference numeral 13 in FIG. 1 of Patent Document 1), and the operational amplifier performs feedback control so that the source voltages of the sense transistor H_SN1 and the power transistor H_PN are equal.

[0030] 21, in a region RG1 where the value of the current IL flowing through the power transistor H_PN is between values ​​rg0 and rg2, the source voltage SN1_S of the sense transistor H_SN1 is equal to the source voltage of the power transistor H_PN, i.e., the voltage CHV of the output terminal CH, due to feedback control by the operational amplifier in the current detection circuit and overcurrent detection circuit H_IOD. At value rg2, when the source voltage SN1_S of the sense transistor H_SN1 falls below the lower limit operating voltage of the current detection circuit and overcurrent detection circuit H_IOD, i.e., the voltage CBV-VDDA supplied by the voltage regulator H_ARG, the feedback control by the operational amplifier in the current detection circuit and overcurrent detection circuit H_IOD breaks down, and the source voltage SN1_S of the sense transistor H_SN1 becomes stuck at the voltage CBV-VDDA in region RG2.

[0031] As the state approaches a ground fault, the current IL increases further, causing the voltage CHV at the output terminal CH to drop further. The voltage generated by the voltage regulator H_DRG also drops from voltage CHV+VDDD to voltage VDDD, and the gate voltage SN1_G supplied to the sense transistor H_SN1 from the driver H_DRV also drops, as shown in Figure 21. As a result, the gate-source voltage SN1_GS of the sense transistor H_SN1 also drops at value rg2, as shown in Figure 21, and becomes smaller than the threshold voltage Vth of the sense transistor H_SN1 at value rg3, causing the sense transistor H_SN1 to turn off.

[0032] The current detection circuit and overcurrent detection circuit H_IOD generates and outputs an overcurrent signal, as shown in FIG. 21, though not limited thereto. Here, a value corresponding to (proportional to) the value rg1 is set as the overcurrent threshold. The current detection circuit and overcurrent detection circuit H_IOD keeps the overcurrent signal low until the current supplied from the sense transistor H_SN1 reaches the overcurrent threshold. When the supplied current exceeds the overcurrent threshold, the overcurrent signal goes high. However, at the value rg3, the sense transistor H_SN1 is turned off, and in the region RGof shown in FIG. 21, the sense transistor H_SN1 remains off. In this region RGof, no current is supplied from the sense transistor H_SN1 to the current detection circuit and overcurrent detection circuit H_IOD, making it impossible to detect an overcurrent. Note that in FIG. 21, the region RGn indicates a region where no overcurrent flows and the circuit is operating normally.

[0033] <<Low-side comparison example>> <<<Comparative Example 3>>> Fig. 22 is a block diagram showing the configuration of Comparative Example 3, which detects the current flowing through a low-side N-type transistor. In Fig. 22, CL denotes an output terminal to which a load (coil LL) is connected. Since Fig. 22 shows the low side, a current IL is drawn from the coil LL to the output terminal CL.

[0034] In Figure 22, L_PN denotes a power transistor constituting a low-side power device, and L_SN1 and L_SN2 denote sense transistors that sense a current proportional to the current flowing through the power transistor L_PN. The source terminals of the power transistor L_PN and the sense transistors L_SN1 and L_SN2 are connected to a ground terminal CG to which a ground voltage CGV is supplied, and the drain terminal of the power transistor L_PN is connected to the output terminal CL. The drain terminal of the sense transistor L_SN1 is also connected to the output terminal CL via a bidirectional diode circuit CDC consisting of two diodes connected in parallel in both directions. Furthermore, the gate terminals of the power transistor L_PN and the sense transistors L_SN1 and L_SN2 are commonly connected, and the output of the driver L_DRV is supplied to them.

[0035] The bidirectional diode circuit CDC reduces the voltage difference between the voltage at the drain terminal of the sense transistor L_SN1 and the voltage at the drain terminal of the power transistor L_PN. This bidirectional diode circuit CDC achieves a function similar to that of the switch (SW3) shown in Patent Document 3. That is, the bidirectional diode circuit CDC operates to make the source-drain voltage of the sense transistor L_SN1 and the source-drain voltage of the power transistor L_PN approximately equal, thereby reducing the difference in the degree of deterioration between the sense transistor L_SN1 and the power transistor L_PN. Furthermore, using the bidirectional diode circuit instead of the switch (SW3) eliminates the need for a control signal to control the on / off of the switch (SW3).

[0036] The size of the sense transistors is made smaller than the size of the power transistors, as in Comparative Example 1. For example, when the size of the sense transistors L_SN1 and L_SN2 is 1, the size of the power transistor L_PN is 4000. As a result, by driving the sense transistors L_SN1 and L_SN2 and the power transistor L_PN in common with the driver L_DRV, a current proportional to the current IL flowing through the power transistor L_PN (a current approximately 1 / 4000th of the current) flows through the sense transistors L_SN1 and L_SN2.

[0037] The current flowing through the sense transistor L_SN1 is supplied to a current detection circuit L_IDC. The current detection circuit L_IDC is configured based on the configuration shown in Patent Document 1. The current detection circuit H_IDC is connected to a ground terminal CG and a voltage regulator L_ARG. The voltage regulator L_ARG is connected to a power supply terminal CB and the ground terminal CG, and generates a predetermined voltage VDDA from a power supply voltage CBV supplied to the power supply terminal CB. As a result, the current detection circuit L_IDC operates using the ground voltage CGV and the voltage VDDA as power supply voltages.

[0038] Although not shown in FIG. 22, the driver L_DRV, like the driver H_DRV shown in Comparative Example 1, receives a signal corresponding to the difference between the current detected by the current detection circuit L_IDC and the target current, and the driver L_DRV drives the power transistor L_PN and the sense transistors L_SN1 and L_SN2 to reduce the difference. The driver L_DRV is connected to a ground terminal CG and a voltage regulator L_DRG. The voltage regulator L_DRG is connected to a power supply terminal CB and a ground terminal CG and generates a predetermined voltage VDDD. As a result, the driver L_DRV operates using the voltage VDDD and the ground voltage CGV as its power supply voltage.

[0039] The current flowing through the sense transistor L_SN2 is supplied to an overcurrent detection circuit L_OID. The overcurrent detection circuit L_OID is configured based on the configuration shown in Patent Document 2. The overcurrent detection circuit L_OID operates using the power supply voltage CBV at the power supply terminal CB and the ground voltage CGV as power supply voltages. Like the overcurrent detection circuit H_OID shown in Comparative Example 1, this overcurrent detection circuit L_OID also detects whether the current IL flowing through the power transistor L_PN exceeds a predetermined value based on the current flowing through the sense transistor L_SN2. For example, if the output terminal CL is connected to the power supply voltage CBV (short-to-power state) as shown by the dashed line, the current IL flowing through the power transistor L_PN becomes an overcurrent and is detected by the overcurrent detection circuit L_OID. Although not particularly limited, when an overcurrent is detected by the overcurrent detection circuit L_OID, for example, the driver L_DRV drives the power transistor L_PN and the sense transistors L_SN1 and L_SN2 to an off state.

[0040] According to Comparative Example 3 shown in FIG. 22, the current IL flowing through the power transistor L_PN can be controlled to a desired value based on the current detected by the current detection circuit L_IDC. Also, based on the current detected by the overcurrent detection circuit L_OID, it can be detected whether or not an abnormal overcurrent is flowing through the power device. However, Comparative Example 3 also has the problem of a large occupied area because the current flowing through the power transistor L_PN is detected by individual sense transistors (L_SN1 and L_SN2) and detection circuits (current detection circuit L_IDC and overcurrent detection circuit L_OID). Therefore, the present inventors developed Comparative Example 4, which will be described next.

[0041] <<<Comparative Example 4>>> FIG. 23 is a block diagram showing the configuration of Comparative Example 4 developed by the present inventors to solve the problem of the occupied area. The main difference from Comparative Example 3 shown in FIG. 22 is that in FIG. 23, the sense transistor L_SN2 and the overcurrent detection circuit L_OID are omitted, and the current detected by the sense transistor L_SN1 is supplied to the current detection circuit and overcurrent detection circuit L_IOD rather than the current detection circuit L_IDC. The current detection circuit and overcurrent detection circuit L_IOD controls the current IL flowing through the power transistor L_PN to a desired value using the current detected by the sense transistor L_SN1, and also detects overcurrents caused by a power short or the like. This makes it possible to solve the problem of a large occupied area.

[0042] The inventors further studied Comparative Example 4 and found that, as will be described next with reference to FIG. 24 , in Comparative Example 4, when an overcurrent flows through the power transistor L_PN due to a short to power or the like, a voltage is applied to the current detection circuit / overcurrent detection circuit L_IOD via the bidirectional diode circuit CDC, making it impossible to detect a state of a short to power or the like.

[0043] Fig. 24 is a waveform diagram for explaining the operation of Comparative Example 4. Fig. 24 shows the state in which the output terminal CL goes from a normal state to a power short state (the output terminal CL is shorted to the power supply voltage CBV). In Fig. 24, the horizontal axis represents the current IL flowing through the power transistor L_PN, and the vertical axis represents the voltage of each part (node) in Comparative Example 4. The value of the current IL flowing through the power transistor L_PN increases from a value rg0 (normal state) to a value rg4 (power short state).

[0044] In Figure 24, IOD_V indicates the power supply voltage of the current detection circuit and overcurrent detection circuit L_IOD. Because the current detection circuit and overcurrent detection circuit L_IOD operates on voltage VDDA from voltage regulator L_ARG, the range in which it can operate IOD_VR is the range from ground voltage CGV to voltage VDDA, as indicated by the power supply voltage IOD_V. Also in Figure 24, IOD_I indicates the input voltage of the current detection circuit and overcurrent detection circuit L_IOD, and the dashed line CLV indicates the voltage at the output terminal CL.

[0045] The current detection circuit and overcurrent detection circuit L_IOD, like the current detection circuit and overcurrent detection circuit H_IOD described in Comparative Example 2, is configured based on the configuration shown in Patent Document 1. That is, the current detection circuit and overcurrent detection circuit L_IOD includes an operational amplifier (not shown) (corresponding to reference numeral 13 in FIG. 1 of Patent Document 1), and the operational amplifier performs feedback control so that the drain voltages of the sense transistor L_SN1 and the power transistor L_PN are equal. In the current detection circuit and overcurrent detection circuit H_IOD of Comparative Example 2, feedback control is performed so that the source voltages are equal, but in the current detection circuit and overcurrent detection circuit L_IOD, feedback control is performed so that the drain voltages are equal.

[0046] 24, when the value of the current IL flowing through the power transistor L_PN increases from a value rg0, exceeds a value rg1 corresponding to an overcurrent threshold (a predetermined value) for determining an overcurrent, and exists in a region RG1 up to a value rg2, feedback control by the operational amplifier in the current detection circuit and overcurrent detection circuit L_IOD causes the drain voltage of the sense transistor L_SN1 to become equal to the drain voltage of the power transistor L_PN, i.e., the voltage CLV of the output terminal CL. As shown in FIG. 24, in the region RG1, the input voltage IOD_I of the current detection circuit and overcurrent detection circuit L_IOD rises in the same manner as the voltage CLV of the output terminal CL.

[0047] When the current IL exceeds the value rg2 and the voltage CLV at the output terminal CL rises and exceeds the power supply voltage IOD_V of the current detection circuit and overcurrent detection circuit L_IOD, the feedback control within the current detection circuit and overcurrent detection circuit L_IOD fails, and the input voltage IOD_I becomes stuck at the power supply voltage IOD_V. If the voltage CLV at the output terminal CL rises further and becomes higher than the threshold voltage Vf of the diodes that make up the bidirectional diode circuit CDC relative to the input voltage IOD_I, the input voltage IOD_I will rise again. In FIG. 24, the range from value rg2 to value rg3 is shown as region RG2, and the range from value rg3 to value rg4 is shown as region RG3.

[0048] The current detection circuit and overcurrent detection circuit L_IOD generates and outputs an overcurrent signal, as shown in FIG. 24, though not limited thereto. Here, a value corresponding to rg1 is set as the overcurrent threshold. The current detection circuit and overcurrent detection circuit L_IOD outputs the overcurrent signal at a low level, indicating normal operation, until the current supplied from the sense transistor L_SN1 reaches the overcurrent threshold (a value proportional to rg1). When the supplied current exceeds the overcurrent threshold, the current detection circuit and overcurrent detection circuit L_IOD outputs the overcurrent signal at a high level, indicating abnormal operation. However, in region RG3, the input voltage IOD_I exceeds the power supply voltage IOD_V of the current detection circuit and overcurrent detection circuit L_IOD, causing the current detection circuit and overcurrent detection circuit L_IOD to malfunction and become unable to detect the current from the sense transistor L_SN1. Therefore, the overcurrent signal becomes a low level, indicating normal operation, in region RGov, corresponding to region RG3. Note that in FIG. 24, region RGn indicates a region of normal operation where no overcurrent flows.

[0049] As described above, according to Comparative Examples 2 and 4, it is possible to prevent the occupied area from increasing, but it is difficult to detect overcurrents caused by ground faults and / or power faults, etc. The embodiments described below provide semiconductor devices that are capable of detecting overcurrents, are capable of reducing the occupied area, and can be made smaller.

[0050] (Embodiment 1) <Configuration of semiconductor device> FIG. 1 is a block diagram showing the configuration of a semiconductor device according to a first embodiment. In FIG. 1, 1 denotes the semiconductor device. Semiconductor device 1 is formed with a plurality of circuit blocks and external terminals (hereinafter also simply referred to as terminals), but FIG. 1 depicts only the circuit blocks and external terminals necessary for explanation. In FIG. 1, CB, CH, CL, and CG denote external terminals provided on semiconductor device 1, with CB denoting a power supply terminal (first voltage terminal), CG denoting a ground terminal (second voltage terminal), and CH and CL denoting output terminals (load terminal, first load terminal, second load terminal). A power supply voltage CBV (first voltage) is supplied to the power supply terminal CB from, for example, a battery, and a ground voltage CGV (second voltage) is supplied to the ground terminal CG.

[0051] A load 2 is connected between output terminals CH and CL. Although not limited to this, the load 2 is configured by a contactor such as an electromagnetic switch or a relay. In FIG. 1, both ends of a coil LL that configures the load 2 are connected to output terminals CH and CL. Here, the output terminal CH is a high-side output terminal, and the output terminal CL is a low-side output terminal. Therefore, a current IL is supplied from the output terminal CH to the coil LL, and a current IL is drawn from the coil LL to the output terminal CL. The load 2 generates an output signal OUT based on the magnetic field generated by the current IL flowing through the coil LL.

[0052] The semiconductor device 1 includes a high-side power transistor H_PN (first power transistor), a low-side power transistor L_PN (second power transistor), a drive circuit 4, a high-side detection circuit H_DO, a low-side detection circuit L_DO, a charge pump circuit 3, a high-side analog-to-digital conversion circuit (hereinafter also referred to as an ADC circuit) H_ADC, a low-side ADC circuit L_ADC, an abnormality signal generation circuit 6, a detection current processing circuit 7, a drive control circuit 8, an arithmetic circuit 9, and a control circuit 10.

[0053] The drain terminal of the power transistor H_PN is connected to the power supply terminal CB, the source terminal is connected to the output terminal CH, and the gate terminal is connected to the drive circuit 4. The charge pump circuit 3 is connected to the power supply terminal CB and generates a voltage CPV that is higher than the power supply voltage CBV and supplies it to the drive circuit 4. The source terminal of the power transistor L_PN is connected to the ground terminal CG, the drain terminal is connected to the output terminal CL, and the gate terminal is connected to the drive circuit 4.

[0054] The drive circuit 4 includes a high-side driver (first driver) H_DRV, a low-side driver (second driver) L_DRV, a high-side voltage regulator (first regulator) H_DRG, a low-side voltage regulator (second regulator) L_DRG, and a drive signal generation circuit 5.

[0055] The voltage regulator H_DRG is connected to the charge pump circuit 3 and the output terminal CH, and generates a voltage CHV+VDDD by adding a predetermined voltage VDDD to the voltage CHV based on the voltage CPV generated by the charge pump circuit 3 and the voltage CHV at the output terminal CH. The driver H_DRV is connected to the voltage regulator H_DRG and the output terminal CH, and operates using the voltage CHV+VDDD and the voltage CHV as power supply voltages. That is, the driver H_DRV receives a high-side drive signal H_DRS from the drive signal generation circuit 5, and supplies a drive signal H_DRD that becomes the voltage CHV+VDDD or the voltage CHV according to the logical value of the drive signal H_DRS to the gate terminal of the power transistor H_PN.

[0056] The voltage regulator L_DRG is connected to the power supply terminal CB and the ground terminal CG, and generates a predetermined voltage VDDD based on the power supply voltage CBV and the ground voltage CGV. The driver L_DRV is connected to the voltage regulator L_DRG and the ground terminal CG, and operates using the voltage VDDD and the ground voltage CGV as power supply voltages. That is, the driver L_DRV receives a low-side drive signal L_DRS from the drive signal generation circuit 5, and supplies a drive signal L_DRD, which becomes the voltage VDDD or the ground voltage CGV according to the logical value of the drive signal L_DRS, to the gate terminal of the power transistor L_PN.

[0057] The drive signal generation circuit 5 is supplied with a high-side control signal H_CNT and a low-side control signal L_CNT from the drive control circuit 8, and is supplied with an abnormality signal EER from the abnormality signal generation circuit 6. The drive signal generation circuit 5 generates the drive signals H_DRS and L_DRS based on the high-side control signal H_CNT, the low-side control signal L_CNT, and the abnormality signal EER.

[0058] Although not particularly limited, when the abnormality signal EER does not indicate an overcurrent state, the drive signal generation circuit 5 generates the drive signals H_DRS and L_DRS according to the high-side control signal H_CNT and the low-side control signal L_CNT. On the other hand, when the abnormality signal EER indicates an overcurrent state, the drive signal generation circuit 5 generates the drive signals H_DRS and L_DRS that turn off the power transistors H_PN and L_PN, regardless of the high-side control signal H_CNT and the low-side control signal L_CNT.

[0059] The high-side detection circuit H_DO and the low-side detection circuit L_DO will be described briefly here, as they will be explained in detail later using the drawings. The detection circuit H_DO is connected to the drain terminal, source terminal, and gate terminal of the power transistor H_PN, and detects a current proportional to the current IL flowing through the power transistor H_PN, as well as the voltage (source-drain voltage) of the power transistor H_PN, and generates two detection currents related to the high side (a first detection current H_DI1 on the high side and a second detection current H_DI2 on the high side) and an overrange signal H_OV related to the high side.

[0060] Similarly, the detection circuit L_DO is connected to the drain terminal, source terminal, and gate terminal of the power transistor L_PN, detects a current proportional to the current IL flowing through the power transistor L_PN, detects the voltage (source-drain voltage) of the power transistor L_PN, and generates two detection currents related to the low side (a first detection current L_DI1 on the low side and a second detection current L_DI2 on the low side) and an overrange signal L_OV related to the low side.

[0061] The first detected current H_DI1 generated by the detection circuit H_DO is supplied to the high-side ADC circuit H_ADC, and the first detected current converted into a digital signal by the ADC circuit H_ADC is supplied to the detected current processing circuit 7. Similarly, the first detected current L_DI1 generated by the detection circuit L_DO is supplied to the low-side ADC circuit L_ADC, and the first detected current converted into a digital signal by the ADC circuit L_ADC is supplied to the detected current processing circuit 7.

[0062] The detected current processing circuit 7 generates a detected current HL_DI1, which is a digital signal proportional to the current IL flowing through the power transistors H_PN and L_PN, based on the first detected currents of the two digital signals supplied thereto. For example, the detected current processing circuit 7 adds the two first detected currents (digital signals) supplied thereto and generates the average value as the detected current HL_DI1.

[0063] The detection current HL_DI1 generated by the detection current processing circuit 7 is supplied to the arithmetic circuit 9. The arithmetic circuit 9 is supplied with an input signal Inp, which is a digital signal indicating the target value of the current IL flowing through the power transistors H_PN and L_PN, i.e., the current flowing through the coil LL. This input signal Inp may be supplied from the outside via an external terminal (not shown) provided on the semiconductor device 1, or may be generated by a circuit block (not shown) inside the semiconductor device 1. The arithmetic circuit 9 calculates the difference between the input signal Inp and the detection current HL_DI1, and supplies the calculated difference to the drive control circuit 8.

[0064] The drive control circuit 8 generates high-side control signal H_CNT and low-side control signal L_CNT with values ​​that reduce the supplied difference and supplies them to the drive circuit 4. The high-side control signal H_CNT and low-side control signal L_CNT are, for example, PWM control signals, and the drive control circuit 8 generates PWM control signals that reduce the supplied difference. Through this feedback, the current IL supplied to the coil LL is controlled to be the target value specified by the input signal Inp.

[0065] The second detection currents H_DI2, L_DI2 and overrange signals H_OV, L_OV generated by the detection circuits H_DO, L_DO are supplied to the abnormality signal generation circuit 6. The abnormality signal generation circuit 6 will also be described in detail later using drawings, so will be briefly described here. The abnormality signal generation circuit 6 uses the second detection current and the overrange signal to determine whether an overcurrent is flowing through the power transistors H_PN, L_PN, and notifies the drive circuit 4 of the determination result by means of an abnormality signal EER. As described above, when the abnormality signal EER indicates an overcurrent state, the drive circuit 4 operates to turn off the power transistors H_PN and L_PN, thereby protecting the power transistors H_PN, L_PN from destruction. From the perspective of protection, the drive circuit 4 can also be considered to be equipped with protection logic that operates based on the abnormality signal.

[0066] The control circuit 10 generates control signals CNTs and the like that control each circuit block in the semiconductor device 1. As will be explained later with reference to the drawings, the detection circuits H_DO and L_DO are provided with a plurality of switches configured by transistors. These switches are switch-controlled by the control signals CNTs and the like generated by the control circuit 10.

[0067] 1 shows an example in which a load coil LL is connected between the output terminals CH and CL, but the present invention is not limited to this. For example, the output terminals CH and CL may be a single common output terminal. In this case, the coil LL is connected, for example, between the common output terminal and a ground terminal CG, and the source terminal of the power transistor H_PN and the drain terminal of the power transistor L_PN are connected to the common output terminal.

[0068] In FIG. 1, the detection current processing circuit 7, the drive control circuit 8, the arithmetic circuit 9, and the drive circuit 4 can be considered to constitute a device control circuit that controls the power transistors H_PN and L_PN based on the input signal Inp and the first detection currents H_DI1 and L_DI1.

[0069] <High-side detection circuit H_DO> Fig. 2 is a circuit diagram showing the configuration of the detection circuit H_DO according to embodiment 1. For convenience of explanation, Fig. 2 also shows the high-side power transistor H_PN, the high-side generation circuit unit 6_H in the abnormality signal generation circuit 6, and the like shown in Fig. 1.

[0070] The detection circuit H_DO includes a high-side over-range comparison circuit H_OVC and a high-side current detection circuit H_ID.

[0071] <<Current detection circuit H_ID>> 2, the portion of the detection circuit H_DO indicated by the dashed line excluding the overrange comparison circuit H_OVC corresponds to the current detection circuit H_ID. That is, the current detection circuit H_ID includes a sense transistor H_SN1 (first sense transistor), a high-side operational amplifier H_OP1, a high-side voltage regulator H_ARG, P-type transistors PM1 to PM6, a high-side diagnostic current source H_TEI, high-side switches SWH1 to SWH9, a voltage source VB1 of a predetermined value, and a resistor R2.

[0072] The switches SWH1 to SWH9 are switch-controlled by the control circuit 10 shown in Fig. 1. When the detection circuit H_DO detects a current proportional to the current IL, the control circuit 10 controls the switches SWH1 to SWH9 to be in the state shown in Fig. 2.

[0073] The drain terminal of the sense transistor H_SN1 is connected to the power supply terminal CB, the source terminal is connected to the node H_ND1, and the gate terminal is connected to the gate terminal of the power transistor H_PN. The size of the sense transistor H_SN1 is smaller than that of the power transistor H_PN. Although not particularly limited, when the size of the sense transistor H_SN1 is 1, the size of the power transistor H_PN is 4000. The gate terminal of the sense transistor H_SN1 and the gate terminal of the power transistor H_PN are common, and a drive signal H_DRD from the driver H_DRV is supplied in common. As a result, the current H_IS flowing between the source and drain of the sense transistor H_SN1 is proportional to the current IL flowing between the source and drain of the power transistor H_PN, and the current H_IS is approximately 1 / 4000 of the current IL.

[0074] The inverting input terminal (-) of the operational amplifier H_OP1 is connected to a node H_ND1 via a switch SWH6, and the non-inverting input terminal (+) is connected to a node H_ND2, which connects the source terminal of the power transistor H_PN and the output terminal CH, via a switch SWH7. The power supply terminal of the operational amplifier H_OP1 is connected to a power supply terminal CB and a voltage regulator H_ARG. The voltage regulator H_ARG is connected to the power supply terminal CB and a ground voltage CGV, and generates a voltage CBV-VDDA by subtracting a predetermined voltage VDDA from the power supply voltage CBV based on the power supply voltage CBV and the ground voltage CGV. As a result, the operational amplifier H_OP1 operates using the power supply voltage CBV and the voltage CBV-VDDA as its power supply voltages.

[0075] The source terminals of P-type transistors PM1, PM3, and PM5 are connected to node H_ND3, and the source terminals of P-type transistors PM2, PM4, and PM6 are connected to the drain terminals of the corresponding P-type transistors PM1, PM3, and PM5. That is, P-type transistors PM1 and PM2 are cascade-connected, P-type transistors PM3 and PM4 are cascade-connected, and further P-type transistors PM5 and PM6 are cascade-connected.

[0076] The gate terminals of P-type transistors PM1, PM3, and PM5 are connected to the output terminal of operational amplifier H_OP1 via switch SWH9, and the gate terminals of P-type transistors PM2, PM4, and PM6 are connected to the gate terminals of P-type transistors PM1, PM3, and PM5 via voltage source VB1. Because the positive side of voltage source VB1 is connected to the gate terminals of P-type transistors PM1, PM3, and PM5, the output of operational amplifier H_OP1, shifted negative by the voltage of voltage source VB1, is supplied to the gate terminals of P-type transistors PM1, PM3, and PM5.

[0077] The source terminal of the P-type transistor PM2 is connected to the ground voltage CGV via a resistor R1 provided outside the detection circuit H_DO, and the source terminal of the P-type transistor PM4 is connected to the high-side generation circuit unit 6_H in the abnormality signal generation circuit 6 (FIG. 1) provided outside the detection circuit H_DO. Furthermore, the source terminal of the P-type transistor PM6 is connected to the ground voltage CGV via a resistor R2.

[0078] The P-type transistors PM1, PM2 and resistor R1 form a series circuit DTR1 connected between node H_ND3 and ground voltage CGV, the P-type transistors PM3, PM4 form a series circuit DTR2 connected between node H_ND3 and generation circuit unit 6_H, and the P-type transistors PM5, PM6 and resistor R2 form a series circuit DTR3 connected between node H_ND3 and ground voltage CGV.

[0079] The node H_ND3 is connected to the node H_ND1 via the switch SWH5. The series circuits DTR1-DTR3 connected to the node H_ND3 operate to shunt a current H_IS supplied from the sense transistor H_SN1 to the node H_ND3, i.e., a current (approximately 1 / 4000) proportional to the current IL flowing through the power transistor H_PN. Although not particularly limited, the P-type transistors PM1-PM6 and resistors R1, R2, etc. are set so that when the shunt current H_IS1 (=first detection current H_DI1: FIG. 1) flowing through the series circuit DTR1 and the shunt current H_DI2 (=second detection current) flowing through the series circuit DTR2 are each 1, the shunt current H_IS3 flowing through the series circuit DTR3 is 3, i.e., the current ratio is 1:1:3 (DTR1:DTR2:DTR3).

[0080] The operational amplifier H_OP1 generates an output voltage so that the voltage at its inverting input terminal (-) (the voltage at node H_ND1) becomes equal to the voltage at its non-inverting input terminal (+) (the voltage at node H_ND2) (so that the differential voltage decreases), and supplies this output voltage from its output terminal to the gate terminals of P-type transistors PM1, PM3, and PM5. At this time, the output voltage of the operational amplifier H_OP1, shifted toward the negative side by the voltage of the voltage source VB1, is also supplied to the gate terminals of P-type transistors PM2, PM4, and PM6. As a result, the voltage at node H_ND3 changes in accordance with the output voltage of the operational amplifier H_OP1, and further, the voltage at node H_ND1 changes. In other words, the source voltage of the sense transistor H_SN1 (the voltage at node H_ND1) is controlled to become equal to the source voltage of the power transistor H_PN (the voltage at node H_ND2) through feedback control by the operational amplifier H_OP1.

[0081] Because the drain terminal of the sense transistor H_SN1 and the drain terminal of the power transistor H_PN are both connected to the power supply terminal CB, the source voltage of the sense transistor H_SN1 and the source voltage of the power transistor H_PN can be made equal through feedback control by the operational amplifier H_OP1, thereby aligning the source-drain voltage of the sense transistor H_SN1 and the source-drain voltage of the power transistor H_PN. This enables the sense transistor H_SN1 to accurately detect a current proportional to the current IL.

[0082] The shunt current H_IS1 (=first detection current H_DI1) flowing through the series circuit DTR1 is converted into a corresponding voltage by the resistor R1 and supplied to the ADC circuit H_ADC, while the shunt current flowing through the series circuit DTR2 is supplied to the generation circuit unit 6_H as a second detection current H_DI2.

[0083] The high-side diagnostic current source H_TEI and the switches SWH1 to SWH9 will be described later in the self-diagnosis function, and will not be described here.

[0084] In FIG. 2, it can be considered that the operational amplifier H_OP1, the P-type transistors PM1 to PM6, the resistor R2, and the voltage source VB1 constitute a first control circuit.

[0085] <<Overrange comparison circuit H_OVC>> The input of the overrange comparison circuit H_OVC is connected to the node H_ND4 and the power supply terminal CB. Since the node H_ND4 is connected to the node H_ND2 via the switch SWH7, the input of the overrange comparison circuit H_OVC is connected to the drain terminal and source terminal of the power transistor H_PN. This overrange comparison circuit H_OVC compares the voltage (source-drain voltage) of the power transistor H_PN with a predetermined voltage, and if the voltage of the power transistor H_PN exceeds the predetermined voltage, it generates an overrange signal H_OV and supplies it to the generation circuit unit 6_H.

[0086] <<Generation circuit section 6_H in abnormality signal generation circuit 6>> The generating circuit section 6_H includes an over-range current source 6_HOI and an over-current comparing circuit 6_HIC.

[0087] An overrange signal H_OV is supplied to the overrange current source 6_HOI, and when the overrange signal H_OV indicates that the voltage of the power transistor H_PN exceeds a predetermined voltage, the overrange current source 6_HOI outputs an overrange current H_OVI. A second detection current H_DI2 is added to this overrange current H_OVI, and the result is supplied to the overcurrent comparison circuit 6_HIC. The overcurrent comparison circuit 6_HIC determines whether the sum of the supplied overrange current H_OVI and the second detection current H_DI2 exceeds a predetermined value, and outputs a high-side abnormality signal H_EER indicating whether or not the sum has exceeded the predetermined value to the drive signal generation circuit 5.

[0088] Next, an example of the over-range comparison circuit H_OVC and the generation circuit unit 6_H will be described with reference to the drawings.

[0089] <<<Example of Overrange Comparator Circuit H_OVC and Generation Circuit Unit 6_H>>> 3 is a circuit diagram showing the configuration of the overrange comparison circuit H_OVC according to embodiment 1. The overrange comparison circuit H_OVC includes P-type transistors PM7 to PM10, N-type transistors NM1 and NM2, and a constant current source H_IOS1.

[0090] The drain terminal and gate terminal of each of the P-type transistors PM7 and PM8 are connected together, and a diode is formed between the source terminal and drain terminal. The source terminal of the P-type transistor PM7 is connected to the power supply terminal CB, the source terminal of the P-type transistor PM8 is connected to the drain terminal of the P-type transistor PM7, and the source terminal of the P-type transistor PM8 is connected to a node H_ND4 as an input of the overrange comparator circuit H_OVC. As a result, the two diodes formed by the P-type transistors PM7 and PM8 are connected in series between the power supply terminal CB and the node H_ND4. The two diodes connected in series form a reference voltage circuit H_VTC that determines the threshold voltage of the overrange comparator circuit H_OVC. In this case, the threshold voltage determined by the reference voltage circuit H_VTC is the sum of the threshold voltages of the P-type transistors PM7 and PM8 that form the diode.

[0091] The source-drain paths of P-type transistors PM9 and PM10 and N-type transistor NM1 are connected in series between power supply terminal CB and voltage CBV-VDDA generated by voltage regulator H_ARG, as shown in Figure 3. The gate terminals of P-type transistors PM9 and PM10 are connected to the drain terminals of P-type transistors PM7 and PM8, and the gate terminal of N-type transistor NM1 is connected to the drain terminal of N-type transistor NM1 and the gate terminal of N-type transistor NM2, whose source terminal is connected to voltage CBV-VDDA.

[0092] The constant current source H_IOS1 is connected between the power supply terminal CB and the drain terminal of the N-type transistor NM2, and an overrange signal H_OV is output from the connection node between the constant current source H_IOS1 and the N-type transistor NM2.

[0093] When the voltage at node H_ND4 drops below the threshold voltage determined by the reference voltage circuit H_VTC relative to the power supply voltage CBV at the power supply terminal CB, a detection current I_OV1 flows through the reference voltage circuit H_VTC, and a detection current I_OV2 proportional to the detection current I_OV1 flows through the P-type transistors PM9 and PM10, which form a mirror with the P-type transistors PM7 and PM8. Furthermore, a detection current I_OV3 proportional to the detection current I_OV2 flows through the N-type transistor NM2, which forms a mirror with the N-type transistor NM1. When the value of the detection current I_OV3 becomes larger than the value of the reference current Iref1 output from the constant current source H_IOS1, the overrange signal H_OV changes from high to low.

[0094] That is, when the voltage between the power supply terminal CB and the node H_ND4, i.e., the voltage of the power transistor H_PN, exceeds a predetermined voltage, the overrange comparison circuit H_OVC changes the overrange signal H_OV to low level. In the configuration of the overrange comparison circuit H_OVC shown in Figure 3, this predetermined voltage is determined mainly by the threshold voltage of the reference voltage circuit H_VTC and the reference current Iref1 of the constant current source H_IOS1.

[0095] Fig. 4 is a circuit diagram showing the configuration of the generation circuit unit 6_H according to embodiment 1. Here, Fig. 4(A) shows the configuration of the over-range current source 6_HOI, and Fig. 4(B) shows the configuration of the overcurrent comparison circuit 6_HIC.

[0096] 4A, the overrange current source 6_HOI includes a P-type transistor PM11. The source terminal of this P-type transistor PM11 is connected to the power supply terminal CB, the gate terminal is connected to the input HOI_I of the overrange current source 6_HOI, and the drain terminal is connected to the output HOI_O of the overrange current source 6_HOI. An overrange signal H_OV is supplied to the input HOI_I, and an overrange current H_OVI according to the overrange signal H_OV is output from the output HOI_O. That is, when the overrange signal H_OV goes low, the P-type transistor PM11 is turned on, and the P-type transistor PM11 outputs the overrange current H_OVI.

[0097] As shown in FIG. 4(B), the overcurrent comparison circuit 6_HIC includes a P-type transistor PM12, an N-type transistor NM3, an inverter circuit IV1, and constant current sources H_IOS2 to H_IOS4.

[0098] The constant current source H_IOS2 is connected between the input HIC_I of the overcurrent comparison circuit 6_HIC and the ground voltage CGV, and the sum of the second detection current H_DI2 and the overrange current H_OVI (H_DI2+H_OVI) is supplied to this input HIC_I.

[0099] The input HIC_I is connected to the gate terminal of an N-type transistor NM3, whose source terminal is connected to a ground voltage CGV and whose drain terminal is connected to the input of the inverter circuit IV1. The gate terminal of a P-type transistor PM12 is connected to a predetermined voltage VDDA via a constant current source H_IOS4 and is also connected to the input of the inverter circuit IV1.

[0100] The source terminal of the P-type transistor PM12 is connected to the voltage VDDA via the constant current source H_IOS3, and the drain terminal is connected to the input HIC_I. The current Iref3 flowing through the P-type transistor PM12 is a current for generating hysteresis. The current Iref3 for generating hysteresis is added to the current (H_DI2+H_OVI) supplied to the input HIC_I. The difference between the current (H_DI2+H_OVI+Iref3) resulting from the addition and the reference current Iref2 generated by the constant current source H_IOS2 is calculated, and the N-type transistor NM3 is turned on or off according to the difference. Functionally, the current (H_DI2+H_OVI+Iref3) resulting from the addition is compared with the reference current Iref2, and the N-type transistor NM3 is turned on or off depending on the comparison result. The value of the current Iref3 for generating hysteresis changes depending on whether the N-type transistor NM3 is on or off, so the overcurrent comparator circuit 6_HIC has a hysteresis characteristic and can reduce malfunctions due to noise, for example.

[0101] If the current resulting from the addition (H_DI2+H_OVI+Iref3) exceeds the reference current Iref2, which is the desired current value, the N-type transistor NM3 turns on, and a high-level abnormality signal H_EER is output from the output HIC_O of the inverter circuit IV1.

[0102] <Low-side detection circuit L_DO> Fig. 5 is a circuit diagram showing the configuration of the detection circuit L_DO according to embodiment 1. For convenience of explanation, Fig. 5 also shows the low-side power transistor L_PN, the low-side generation circuit unit 6_L in the abnormality signal generation circuit 6, and the like shown in Fig. 1.

[0103] The detection circuit L_DO includes a low-side over-range comparison circuit L_OVC and a low-side current detection circuit L_ID.

[0104] <<Current detection circuit L_ID>> 5 (enclosed by a dashed line), the portion excluding the overrange comparison circuit L_OVC corresponds to the current detection circuit L_ID. That is, the current detection circuit L_ID includes a sense transistor L_SN1 (second sense transistor), a low-side operational amplifier L_OP1, a low-side voltage regulator L_ARG, P-type transistors PM14 to PM19, a low-side diagnostic current source L_TEI, low-side switches SWL1 to SWH12, a voltage source VB2 of a predetermined value, and a bidirectional diode circuit CDC.

[0105] The switches SWL1 to SWL12 are switch-controlled by the control circuit 10 shown in Fig. 1. When the detection circuit L_DO detects a current proportional to the current IL, the control circuit 10 controls the switches SWL1 to SWL12 to be in the state shown in Fig. 5.

[0106] The source terminal of the sense transistor L_SN1 is connected to the ground voltage CGV, the drain terminal is connected to the node L_ND1, and the gate terminal is connected to the gate terminal of the power transistor L_PN. The size of the sense transistor L_SN1 is smaller than that of the power transistor L_PN. On the low side, there is no particular restriction, but when the size of the sense transistor H_SN1 is 1, the size of the power transistor L_PN is 4000. The gate terminal of the sense transistor L_SN1 and the gate terminal of the power transistor L_PN are connected in common, and a drive signal L_DRD from the driver L_DRV is supplied in common. As a result, the current L_IS flowing between the source and drain of the sense transistor L_SN1 is proportional to the current IL flowing between the source and drain of the power transistor L_PN, and the current L_IS is approximately 1 / 4000 of the current IL.

[0107] A bidirectional diode circuit (bidirectional circuit) CDC is connected between the node L_ND1 and the drain terminal of the power transistor L_PN. This reduces the voltage difference between the voltage at the drain terminal of the sense transistor L_SN1 and the voltage at the drain terminal of the power transistor L_PN. This bidirectional diode circuit CDC achieves a function similar to that of the switch (SW3) shown in Patent Document 3. That is, the bidirectional diode circuit CDC operates to make the source-drain voltage of the sense transistor L_SN1 and the source-drain voltage of the power transistor L_PN approximately equal, thereby reducing the difference in the degree of deterioration between the sense transistor L_SN1 and the power transistor L_PN. Furthermore, using the bidirectional diode circuit CDC instead of the switch (SW3) eliminates the need for a control signal to control the on / off of the switch (SW3).

[0108] The non-inverting input terminal (+) of the operational amplifier L_OP1 is connected to a node L_ND1 via a switch SWL2, and the inverting input terminal (-) is connected to a node L_ND2, which connects the drain terminal of the power transistor L_PN and the output terminal CL, via a switch SWL3. The power supply terminal of the operational amplifier L_OP1 is connected to a ground voltage CGV and a voltage regulator L_ARG. The voltage regulator L_ARG is connected to a power supply terminal CB and the ground voltage CGV, and generates a predetermined voltage VDDA lower than the power supply voltage CBV (see Figure 1) based on the power supply voltage CBV and the ground voltage CGV. This allows the operational amplifier L_OP1 to operate using the voltage VDDA and the ground voltage CGV as its power supply voltages.

[0109] The source terminals of P-type transistors PM14, PM16, and PM18 are connected to voltage VDDA, and the drain terminals are connected to the source terminals of corresponding P-type transistors PM15, PM17, and PM19. The gate terminal of P-type transistor PM14 is connected to the output terminal of operational amplifier L_OP1 via switch SWL7 and further to the gate terminal of P-type transistor PM16 via switch SWL9, and P-type transistor PM18 is connected to the gate terminal of P-type transistor PM16 via switch SWL11. The gate terminals of P-type transistors PM15, PM17, and PM19 are connected to the negative side of a voltage source VB2 of a predetermined voltage, the positive side of which is connected to voltage VDDA.

[0110] P-type transistors PM14 and PM15 are cascade-connected, P-type transistors PM16 and PM17 are also cascade-connected, and further, P-type transistors PM18 and PM19 are also cascade-connected.

[0111] The drain terminal of the P-type transistor PM15 is connected to a node L_ND1 via a switch SWL1, the drain terminal of the P-type transistor PM17 is connected to a generation circuit unit 6_L in the abnormality signal generation circuit 6, and the drain terminal of the P-type transistor PM19 is connected to a node L_ND3. The node L_ND3 is connected to a ground voltage CGV via a resistor R3 and is further connected to the input of the ADC circuit L-ADC.

[0112] The cascaded P-type transistors PM14, PM15, PM16, PM17, and PM18, PM19 form a current mirror. That is, a current proportional to the current flowing through the cascaded P-type transistors PM14, PM15 flows through the cascaded P-type transistors PM16, PM17 and the cascaded P-type transistors PM18, PM1. Although not particularly limited, in the first embodiment, the sizes of the P-type transistors PM14 to PM19, the value of resistor R3, and the like are set so that when the current flowing through the cascaded P-type transistors PM18, PM19 and the cascaded P-type transistors PM16, PM17 is 1, the current flowing through the cascaded P-type transistors PM14, PM15 is 5.

[0113] Because the drain terminal of P-type transistor PM15 is connected to node L_ND1 and sense transistor L_SN1 via switch SWL1, the current flowing through the cascaded P-type transistors PM14 and PM15 becomes current L_IS, which is proportional to current IL flowing through power transistor L_PN. Cascaded P-type transistors PM16 and PM17 supply a current proportional to current L_IS as second detection current L_DI2 to the generation circuit unit 6_L. Cascaded P-type transistors PM18 and PM19 also supply a current proportional to current L_IS as first detection current L_DI1 to node L_ND3. The first detection current L_DI1 is converted to a voltage by resistor R3 and then converted to a digital signal by ADC circuit L-ADC.

[0114] The operational amplifier L_OP1 generates an output voltage so that the voltage at the non-inverting input terminal (+) (the voltage at node L_ND1) becomes equal to the voltage at the inverting input terminal (-) (the voltage at node L_ND2) (so that the differential voltage decreases), and supplies this output voltage from the output terminal to the gate terminals of P-type transistors PM14, PM16, and PM18 via switch SWL7. This causes the voltage at node L_ND1 to change in accordance with the output voltage of the operational amplifier L_OP1. In other words, feedback control by the operational amplifier L_OP1 controls the drain voltage of the sense transistor L_SN1 to become equal to the drain voltage of the power transistor L_PN.

[0115] Because the source terminal of the sense transistor L_SN1 and the source terminal of the power transistor L_PN are both connected to the ground voltage CGV, the drain voltage of the sense transistor L_SN1 and the drain voltage of the power transistor L_PN can be made equal through feedback control by the operational amplifier L_OP1, thereby aligning the source-drain voltage of the sense transistor L_SN1 and the source-drain voltage of the power transistor L_PN. As a result, a current proportional to the current IL can be detected with high accuracy by the sense transistor L_SN1.

[0116] The low-side diagnostic current source L_TEI and the switches SWL1 to SWL13 will be described later in the self-diagnosis function, and will not be described here.

[0117] In FIG. 5, it can be considered that the operational amplifier L_OP1, the P-type transistors PM14 to PM19, and the voltage source VB2 constitute a second control circuit.

[0118] <<Overrange comparison circuit L_OVC>> The input of the overrange comparator circuit L_OVC is connected to node L_ND4 and ground voltage CGV. Node L_ND4 is connected to node L_ND2 via switch SWL3, so the input of the overrange comparator circuit L_OVC is connected to the drain and source terminals of the power transistor L_PN. This overrange comparator circuit L_OVC compares the voltage (source-drain voltage) of the power transistor L_PN with a predetermined voltage, and if the voltage of the power transistor L_PN exceeds the predetermined voltage, it generates an overrange signal L_OV and supplies it to the generation circuit unit 6_L in the abnormality signal generation circuit 6.

[0119] <<Generation circuit section 6_L in abnormality signal generation circuit 6>> The generating circuit unit 6_L includes an over-range current source 6_LOI and an over-current comparing circuit 6_LIC.

[0120] An overrange signal L_OV is supplied to the overrange current source 6_LOI. When the overrange signal L_OV indicates that the voltage of the power transistor L_PN exceeds a predetermined voltage, the overrange current source 6_LOI outputs an overrange current L_OVI. A second detection current L_DI2 is added to this overrange current L_OVI and supplied to the overcurrent comparison circuit 6_LIC. The overcurrent comparison circuit 6_LIC determines whether the sum of the supplied overrange current L_OVI and the second detection current L_DI2 exceeds a predetermined value, and outputs a low-side abnormality signal L_EER indicating whether or not the sum exceeds the predetermined value to the drive signal generation circuit 5 (FIG. 1). Note that the abnormality signal EER shown in FIG. 1 is a signal obtained by combining the abnormality signal H_EER shown in FIG. 2 and the abnormality signal L_EER shown in FIG. 5.

[0121] Next, an example of the over-range comparison circuit L_OVC will be described with reference to the drawings.

[0122] <<<Example of overrange comparison circuit L_OVC>>> 6 is a circuit diagram showing the configuration of the overrange comparison circuit L_OVC according to embodiment 1. The overrange comparison circuit L_OVC includes N-type transistors NM4 to NM7 and a constant current source L_IOS1.

[0123] The drain terminal and gate terminal of each of the N-type transistors NM4 and NM5 are connected together, forming a diode between their source and drain terminals. The source terminal of the N-type transistor NM5 is connected to the ground voltage CGV, the drain terminal of the N-type transistor PM5 is connected to the source terminal of the N-type transistor NM4, and the drain terminal of the N-type transistor NM4 is connected to a node L_ND4 as an input of the overrange comparator circuit L_OVC. As a result, the two diodes formed by the N-type transistors NM4 and NM5 are connected in series between the ground voltage CGV and the node L_ND4. The two series-connected diodes form a reference voltage circuit L_VTC that determines the threshold voltage of the overrange comparator circuit L_OVC. In this case, the threshold voltage determined by the reference voltage circuit L_VTC is the sum of the threshold voltages of the N-type transistors NM4 and NM5 that form the diode.

[0124] As shown in Figure 6, the source-drain paths of N-type transistors NM7 and NM6 and the constant current source L_IOS1 are connected in series between the ground voltage CGV and the voltage VDDA generated by the voltage regulator L_ARG (Figure 5). The gate terminals of N-type transistors NM6 and NM7 are connected to the drain terminals of N-type transistors NM4 and NM5 so as to form a mirror with N-type transistors NM4 and NM5. An overrange signal L_OV is output from the connection node between the constant current source L_IOS1 and N-type transistor NM6.

[0125] For example, if a short circuit to the power supply connects the output terminal CL to the power supply voltage CBV, the voltages at the nodes L_ND2 and L_ND4 rise, and the voltage at the node L_ND4 rises above the threshold voltage determined by the reference voltage circuit L_VTC relative to the ground voltage CGV, a detection current I_OV4 flows through the reference voltage circuit L_VTC, and a detection current I_OV5 proportional to the detection current I_OV4 flows through the N-type transistors NM6 and NM7 that form the mirror. If the value of the detection current I_OV5 becomes larger than the value of the reference current Iref4 output from the constant current source L_IOS1, the overrange signal L_OV changes from high to low.

[0126] That is, when the voltage between the ground terminal CG and the node L_ND4, i.e., the voltage of the power transistor L_PN, exceeds a predetermined voltage, the overrange comparator circuit L_OVC changes the overrange signal L_OV to low level. In the configuration of the overrange comparator circuit L_OVC shown in Figure 6, this predetermined voltage is determined mainly by the threshold voltage of the reference voltage circuit L_VTC and the reference current Iref4 of the constant current source L_IOS1.

[0127] <<<An example of the generation circuit unit 6_L>>> As shown in Fig. 5, the generation circuit unit 6_L includes an over-range current source 6_LOI and an overcurrent comparison circuit 6_LIC. Fig. 7 is a circuit diagram showing an example of the generation circuit unit 6_L according to the first embodiment. Here, Fig. 7(A) shows the configuration of the over-range current source 6_LOI, and Fig. 7(B) shows the configuration of the overcurrent comparison circuit 6_LIC.

[0128] Figure 7(A) is similar to Figure 4(A), except that the source terminal of P-type transistor PM20, which corresponds to P-type transistor PM11 in Figure 4(A), is connected to voltage VDDA generated by voltage regulator L_ARG (Figure 5) instead of power supply terminal CB.

[0129] When an overrange signal L_OV is supplied to the input LOI_I of the overrange current source 6_LOI, an overrange current L_OVI according to the overrange signal L_OV is output from the output LOI_O.

[0130] Figure 7(B) is similar to Figure 4(B). The only difference is that the symbols have been changed. That is, the configuration and operation of the overcurrent comparison circuit 6_LIC shown in Figure 7(B) are the same as those of the overcurrent comparison circuit 6_HIC shown in Figure 4(B), but only the symbols indicating the transistors, constant current sources, inverter circuits, etc. have been changed. Therefore, a detailed description of the overcurrent comparison circuit 6_LIC will be omitted.

[0131] The sum of the second detection current L_DI2 and the over-range current L_OVI (L_DI2+L_OVI) is supplied to the input LIC_I of the overcurrent comparison circuit 6_LIC. The N-type transistor NM8 turns on / off depending on whether the sum of this current (L_DI2+L_OVI) and the current Iref6 for generating hysteresis (L_DI2+L_OVI+Iref6) exceeds the reference current Iref5. If an overcurrent flows through the power transistor L_PN, the sum of the current (L_DI2+L_OVI+Iref6) exceeds the reference current Iref5, the N-type transistor NM8 turns on, and a high-level abnormality signal L_EER is output from the output LIC_O.

[0132] <Operation of the detection circuits H_DO and L_DO> Next, the operation of the high-side detection circuit H_DO shown in FIG. 2 and the low-side detection circuit L_DO shown in FIG. 5 will be described with reference to the drawings.

[0133] <<Operation of the detection circuit H_DO>> FIG. 8 is a waveform diagram showing the operation of the high-side detection circuit according to the first embodiment. FIG. 8 is similar to FIG. 21. The main difference is that an overrange signal H_OV and an abnormality signal H_EER are added in FIG. 8. Also, while FIG. 21 shows detection by the current detection circuit and overcurrent detection circuit H_IOD (FIG. 20), FIG. 8 shows detection by the detection circuit H_DO of FIG. 2. Therefore, for example, the feedback control performed in region RG1 of FIG. 8 is realized by the operational amplifier H_OP1 shown in FIG. 2.

[0134] In FIG. 8, the overcurrent threshold corresponds to the threshold of the overcurrent comparison circuit 6_HIC. Taking the overcurrent comparison circuit 6_HIC shown in FIG. 4(B) as an example, the overcurrent threshold is determined mainly by the reference currents Iref2 and Iref3. The overcurrent signal shown in FIG. 8 corresponds to the second detection current H_DI2. In the first embodiment, the second detection current H_DI2 is an analog value. Therefore, in FIG. 8, the time when the second detection current H_DI2 exceeds the overcurrent threshold is shown as the timing when the level of the overcurrent signal changes to high level.

[0135] In Figure 8, the overrange threshold (the value corresponding to the value rg1_1) corresponds to the threshold of the overrange comparison circuit H_OVC. Taking the overrange comparison circuit H_OVC shown in Figure 3 as an example, the threshold of the overrange comparison circuit H_OVC is determined mainly by the values ​​of the reference voltage circuit H_VTC and the reference current Iref1. In Figure 8, the state in which the overrange signal H_OV exceeds the overrange threshold is depicted as the high level of the overrange signal H_OV.

[0136] 8, region RG1 is a region where the source voltage of the sense transistor H_SN1 is equal to the source voltage of the power transistor H_PN due to feedback control by the operational amplifier H_OP1 (FIG. 2). In region RG1, where the second detection current H_DI2 has not reached the overcurrent threshold, the overcurrent signal is at a low level, no overcurrent is flowing, and this region is RGn during normal operation.

[0137] When the current IL flowing through the power transistor H_PN is between values ​​rg0 and rg1_1, the voltage CHV at the output terminal CH does not drop significantly, and the voltage at node H_ND2 (=H_ND4), which is the source terminal of the power transistor H_PN, does not exceed the overrange threshold. Therefore, in the region between values ​​rg0 and rg1_1, the overrange signal H_OV is low. In region RGn, where both the overcurrent signal and the overrange signal H_OV are low, the abnormality signal H_EER is low, indicating that no overcurrent has occurred due to a ground fault or the like. In region RGn, the current IL output from the power transistor H_PN is detected by the current detection circuit H_ID (Figure 2) and controlled to a value consistent with the input signal Inp (Figure 1).

[0138] When the current IL flowing through the power transistor H_PN reaches a value rg1, the second detection current H_DI2 reaches the overcurrent threshold. As a result, as shown in FIG. 8, the overcurrent signal changes to a high level, and the abnormality signal H_EER also changes to a high level. When the abnormality signal H_EER changes to a high level, it is determined that an abnormal current is occurring due to a ground fault that connects the output terminal CH to the ground voltage CGV, and the drive circuit 4 shown in FIG. 1 turns off the power transistor H_PN. This makes it possible to prevent the power transistor H_PN from being destroyed.

[0139] Subsequently, when the current IL flowing through the power transistor H_PN reaches a value rg1_1, the voltage at node H_ND4 reaches the overrange threshold, and the overrange signal H_OV changes from low to high. Meanwhile, when the current IL reaches a value rg2, the feedback control by the operational amplifier H_OP1 fails, causing the gate-source voltage of the sense transistor H_SN1 to decrease. When the current IL reaches a value rg3, the gate-source voltage falls below the threshold voltage Vth of the sense transistor H_SN1, turning off the sense transistor H_SN1. As a result, the overcurrent signal changes from high to low again. At this time, the voltage at node H_ND4 continues to exceed the overrange threshold, so the overrange signal H_OV remains high. As a result, the fault signal H_EER remains high even when the current IL exceeds a value rg3, indicating that an overcurrent due to a ground fault or other cause continues to occur. Furthermore, as the abnormality signal H_EER continues to be at a high level, the drive circuit 4 shown in FIG. 1 keeps the power transistor H_PN in an OFF state.

[0140] <<Detection circuit L_DO operation>> FIG. 9 is a waveform diagram illustrating the operation of the low-side detection circuit according to the first embodiment. FIG. 9 is similar to FIG. 24. The main difference is that FIG. 9 adds an overrange signal L_OV and an abnormality signal L_EER. While FIG. 24 illustrates detection by the current detection circuit and overcurrent detection circuit L_IOD (FIG. 23), FIG. 9 illustrates detection by the detection circuit L_DO of FIG. 5. Therefore, for example, the feedback control performed in region RG1 of FIG. 9 is realized by the operational amplifier L_OP1 shown in FIG. 5. In FIG. 9, IOD_I represents the input voltage (node ​​L_ND2) of the current detection circuit L_ID, and IOD_V represents the power supply voltage of the current detection circuit L_ID. The current detection circuit L_ID operates on voltage VDDA from the voltage regulator L_ARG. Therefore, its operable range is from ground voltage CGV to voltage VDDA, as indicated by the power supply voltage IOD_V.

[0141] In FIG. 9, the overcurrent threshold corresponds to the threshold of the overcurrent comparison circuit 6_LIC. Taking the overcurrent comparison circuit 6_LIC shown in FIG. 7(B) as an example, the overcurrent threshold is determined mainly by the reference current Iref5 and the current Iref6. The overcurrent signal shown in FIG. 9 corresponds to the second detection current L_DI2. In the first embodiment, the second detection current L_DI2 is also an analog value. Therefore, in FIG. 9, the moment when the second detection current L_DI2 exceeds the overcurrent threshold is shown as the timing when the level of the overcurrent signal changes to high.

[0142] In Figure 9, the overrange threshold corresponds to the threshold of the overrange comparison circuit L_OVC. Using the overrange comparison circuit L_OVC shown in Figure 6 as an example, the threshold of the overrange comparison circuit L_OVC is determined mainly by the values ​​of the reference voltage circuit L_VTC and the reference current Iref4. In Figure 9, the state in which the overrange signal L_OV exceeds the overrange threshold is depicted as the high level of the overrange signal L_OV.

[0143] In FIG. 9, region RG1 is a region where the drain voltage of the sense transistor L_SN1 is controlled to be equal to the drain voltage of the power transistor L_PN by feedback control using the operational amplifier L_OP1 (FIG. 5). In this region RG1, when the current IL flowing through the power transistor L_PN increases from value rg0 to value rg1, the second detection current L_DI2 also increases. When the current IL reaches value rg1, the second detection current L_DI2 reaches the overcurrent threshold, and the overcurrent signal changes from low to high. This change in the overcurrent signal also changes the abnormality signal L_EER from low to high. When the abnormality signal L_EER changes to high, an abnormality is detected, and the drive circuit 4 turns off the power transistor L_PN.

[0144] If the current IL continues to increase and exceeds the value rg3, the voltage CLV of the output terminal CL will exceed the threshold voltage Vf of the diode in the bidirectional diode circuit CDC relative to the power supply voltage IOD_V, causing the current detection circuit L_ID to fail and the overcurrent signal to change to low level again.

[0145] On the other hand, when the current IL flowing through the power transistor L_PN reaches a value rg1_1, the voltage at node L_ND4 reaches the overrange threshold, and the overrange signal L_OV changes from low to high. When the current IL reaches a value rg3, the overcurrent signal changes back to low, as described above. However, before that, the overrange signal L_OV goes high, and the overrange current L_OVI is supplied to the overcurrent comparator circuit 6_LIC. As a result, the abnormality signal L_EER remains high even when the current IL exceeds the value rg3, indicating that an overcurrent due to a power short or the like continues to occur. Furthermore, because the abnormality signal L_EER remains high, the drive circuit 4 shown in FIG. 1 keeps the power transistor L_PN in an off state.

[0146] <Self-diagnosis function> A description will be given of the self-diagnosis function according to the first embodiment. Here, a function for diagnosing a circuit block added in the first embodiment will be described for the second and fourth comparative examples.

[0147] <<High-side detection circuit>> Fig. 10 is a circuit diagram showing the state during self-diagnosis of the high-side detection circuit according to embodiment 1. Fig. 10 differs from Fig. 2 in that the states of switches SWH1 to SWH3 and SWH5 to SWH8 are different from those in Fig. 2, and that the over-range current TEI_OVI during diagnosis is shown.

[0148] Although not particularly limited, the switches SWH1 to SWH9 are configured by N-channel field effect transistors and are switch-controlled by a control signal CNTs output from the control circuit 10 shown in Fig. 1. The switches SWH1 to SWH9 are used to prevent the semiconductor device from being destroyed when the power transistor H_PN is switched, and to forcibly supply an overcurrent to a predetermined location during self-diagnosis.

[0149] The circuit blocks to be diagnosed will be described by taking as an example the current path section that generates the second detection current H_DI2 etc., the overrange comparison circuit H_OVC, the overrange current source 6_HOI, and the overcurrent comparison circuit 6_HIC.

[0150] The current path section to be diagnosed is composed of P-type transistors PM1 to PM6, and this current path section is used to detect current during normal operation. Therefore, diagnosis is performed during normal operation. For the circuit block to be diagnosed excluding the current path section, an overcurrent is forcibly supplied to the overrange comparison circuit H_OVC during self-diagnosis, and diagnosis is performed based on the output at this time (abnormal signal H_EER).

[0151] FIG. 11 is a waveform diagram illustrating the self-diagnosis function of the high-side detection circuit according to the first embodiment. Here, FIG. 11(A) shows a waveform determined to be normal in the self-diagnosis, and FIG. 11(B) shows a waveform determined to be abnormal in the self-diagnosis. During the self-diagnosis, the control circuit 10 (FIG. 1) outputs, as the control signal CNTs, self-diagnosis control signals sw_h1 to sw_h9 (which correspond one-to-one to the switches SWH1 to SWH9) that turn on the switches SWH1 to SWH3 and SWH8 and turn off the other switches SWH4 to SWH7 and SWH9. Only the self-diagnosis control signals sw_h1 to sw_h3 and sw_h8 that turn on the switches SWH1 to SWH3 and SWH8 are shown in FIG. 11.

[0152] The switches SWH1 to SWH3 and SWH8 are turned on, and the other switches SWH4 to SWH7 and SWH9 are turned off, resulting in the state shown in FIG. 10. Because the switches SWH4 to SWH7 and SWH9 are turned off, the operational amplifier H_OP1 no longer performs feedback control. Therefore, self-diagnosis is performed when the semiconductor device 1 is started up, etc. For example, when a power supply voltage CBV is applied to the semiconductor device 1, the control circuit 10 outputs a self-diagnosis control signal as shown in FIG. 11.

[0153] The self-diagnosis control signal sw_h8 turns on the switch SWH8, connecting the current source H_TEI to the overrange comparison circuit H_OVC via the switch SWH8. This causes the voltage at the node H_ND4 to drop. If the overrange comparison circuit H_OVC, the overrange current source 6_HOI, the overcurrent comparison circuit 6_HIC, and the current path section (P-type transistors PM1 to PM6) are normal, the abnormality signal H_EER goes high as shown in FIG. 11(A). On the other hand, if at least one of the overrange comparison circuit H_OVC, the overrange current source 6_HOI, the overcurrent comparison circuit 6_HIC, and the current path section is abnormal, the abnormality signal H_EER goes low as shown in FIG. 11(B).

[0154] An abnormality signal at the time of self-diagnosis is supplied to, for example, the control circuit 10, and when the semiconductor device 1 is started up, the control circuit 10 notifies the outside of the semiconductor device 1 as the result of the self-diagnosis.

[0155] <<Low-side detection circuit>> Figures 12 and 13 are circuit diagrams showing the state during self-diagnosis of the low-side detection circuit according to embodiment 1. Figures 12 and 13 differ from Figure 5 in that the states of switches SWL1 to SWL13 in Figures 12 and 13 are different from those in Figure 5, and that the over-range current TEI_OVI and second detection current TEI_DI2 during diagnosis are shown in Figures 12 and 13.

[0156] Although not particularly limited, the switches SWL1 to SWL13 are configured by N-channel field effect transistors and are switch-controlled by a control signal CNTs output from the control circuit 10 shown in Fig. 1. The switches SWL1 to SWL13 are used to prevent the semiconductor device from being destroyed when the power transistor L_PN is switched, and to forcibly pass a current during self-diagnosis.

[0157] The circuit blocks to be diagnosed will be described by taking as an example the current mirror that generates the second detection current L_DI2, the overrange comparison circuit L_OVC, the overrange current source 6_LOI, and the overcurrent comparison circuit 6_LIC.

[0158] Fig. 14 is a waveform diagram for explaining the self-diagnosis function of the low-side detection circuit according to the first embodiment. Fig. 14(A) shows a waveform determined to be normal in the self-diagnosis, and Figs. 14(B) to 14(D) show waveforms determined to be abnormal in the self-diagnosis. That is, Fig. 14(B) shows a waveform when the overrange comparison circuit is abnormal, Fig. 14(C) shows a waveform when the current mirror is abnormal, and Fig. 14(D) shows a waveform when the overcurrent comparison circuit is abnormal.

[0159] The self-diagnosis of the low-side detection circuit is performed in two stages (Phase 1 (PHASE1) and Phase 2 (PHASE2)).

[0160] In phase 1, the control circuit 10 outputs, as control signals CNTs, self-diagnosis control signals (sw_l4, sw_l6, sw_l8, sw_l12, sw_l13) that turn on switches SWL4, SWL6, SWL8, SWL12, and SWL13, and self-diagnosis control signals that turn off other switches. The state of the detection circuit in phase 1 is shown in FIG. 12. Meanwhile, in phase 2, the control circuit 10 outputs, as control signals CNTs, self-diagnosis control signals (sw_l4, sw_l5, sw_l6, sw_l7, sw_l10, sw_l12) that turn on switches SWL4, SWL5, SWL6, SWL7, SWL10, and SWL12, and self-diagnosis control signals that turn off other switches. The state of the detection circuit in phase 2 is shown in FIG. 13.

[0161] In phase 1, as shown in FIG. 12, the switch SWL13 is turned on, and the current source L_TEI is connected to the overrange comparison circuit L_OVC via the switch SWL13. This forces a current to be supplied to the overrange comparison circuit L_OVC. If the overrange comparison circuit L_OVC and the overrange current source 6_LOI are normal, the overrange current TEI_OVI (FIG. 12) is output. If the overcurrent comparison circuit 6_LIC is also normal, the abnormality signal L_EER goes high at timing TT1 in response to the self-diagnosis control signal of phase 1, as shown in FIG. 14(A). Meanwhile, in phase 2, as shown in FIG. 13, the switch SWL10 is turned on. As a result, the P-type transistor PM16 that constitutes the current mirror turns on, and if this current mirror is normal, the second detection current TEI_DI2 (Figure 13) flows, and if the overcurrent comparison circuit 6_LIC is also normal, the abnormality signal L_EER becomes high level at timing TT2 in response to the self-diagnosis control signal of phase 2, as shown in Figure 14(A).

[0162] In contrast, if there is an abnormality in the overrange comparison circuit L_OVC, for example, the abnormality signal L_EER goes low at timing TT1 as shown in Fig. 14(B). If there is an abnormality in the current mirror, the abnormality signal L_EER goes low at timing TT2 as shown in Fig. 14(C). If there is an abnormality in the overcurrent comparison circuit 6_LIC, the abnormality signal L_EER goes low at both timing TT1 and timing TT2.

[0163] As with the high-side detection circuit, an abnormality signal generated during self-diagnosis is supplied to, for example, the control circuit 10, and when the semiconductor device 1 is started up, the control circuit 10 notifies the result of the self-diagnosis to an external device of the semiconductor device 1. Note that the self-diagnosis for the low-side detection circuit may start from either phase 1 or phase 2. Furthermore, when self-diagnosis is performed on both the high-side and low-side detection circuits, the self-diagnosis may start from either detection circuit.

[0164] In the first embodiment, an overcurrent flowing through a power transistor is detected using not only the second detection current (H_DI2, L_DI2) but also the overrange signal (H_OV, L_OV) based on the voltage of the power transistor (H_PN, L_PN). This makes it possible to detect an overcurrent caused by a short circuit (ground fault, short to supply) of the output terminal, which cannot be detected using only the second detection current. While it is possible to detect an overcurrent by detecting only the voltage of the power transistor, this requires converting the voltage to a current, which may limit the conversion accuracy and degrade the accuracy of the threshold value used to detect the overcurrent. In contrast, in the first embodiment, the second detection current, which does not require conversion to a current, is also used to detect the overcurrent, thereby preventing the accuracy of the threshold value used to detect the overcurrent from degrading. For example, in FIGS. 8 and 9, there are two threshold values ​​used to detect an overcurrent: an overcurrent threshold and an overrange threshold, and the overcurrent threshold can be set more accurately to the desired threshold value.

[0165] For example, the transistor symbols shown in Figures 1 to 7 are drawn to match the size and structure (gate oxide film) of the actual transistors. For example, in Figures 2 and 5, the symbols for the power transistors H_PN and L_PN are larger than the symbols for the sense transistors H_SN1 and L_SN1. This indicates that the size of the power transistors is larger than the size of the sense transistors.

[0166] Furthermore, in the transistor symbols, the thickness of the vertical lines representing the gates is drawn to match the thickness of the transistor's gate oxide film. For example, in Figures 2 to 4, the vertical lines representing the gates of P-type transistors PM1, PM3, PM5, PM7 to PM12 and N-type transistors NM1 to NM3 are thinner than the vertical lines representing the gates of P-type transistors PM2, PM4, PM6 and N-type transistors H_SN1 and H_PN. This indicates that the gate oxide films of P-type transistors PM1, PM3, PM5, PM7 to PM12 and N-type transistors NM1 to NM3 are thinner and have lower breakdown voltages than those of P-type transistors PM2, PM4, PM6 and sense transistor H_SN1 and power transistor H_PN. The same is true for Figures 5 to 7.

[0167] As shown in Figures 3-4 and 6-7, the overrange comparison circuits H_OVC, L_OVC, overrange current sources 6_HOI, 6_LOI, and overcurrent comparison circuits 6_HIC, 6_LIC are configured as simple circuits made up of low-voltage transistors, which makes it possible to suppress an increase in the occupied area and achieve miniaturization.In addition, only one high-voltage sense transistor is required on each of the high and low sides, which further suppresses an increase in the occupied area and enables miniaturization.

[0168] Furthermore, in Comparative Example 1, as shown in Fig. 19, it was necessary to supply voltage CPV from the charge pump circuit to overcurrent detection circuit H_OID as well, but in Embodiment 1, as shown in Fig. 1 and Fig. 2, it is not necessary to supply voltage CPV to high-side detection circuit H_DO. This makes it possible to reduce the area occupied by charge pump circuit 3 (Fig. 1) that generates voltage CPV.

[0169] According to the self-diagnosis function of embodiment 1, it is possible to self-diagnose the overrange comparison circuits H_OVC, L_OVC, the overrange current sources 6_HOI, 6_LOI, and the overcurrent comparison circuits 6_HIC, 6_LIC, for example, when the semiconductor device is started up, making it possible to provide a highly safe semiconductor device.

[0170] (Embodiment 2) In the first embodiment, an example was shown in which an overcurrent is detected by adding the second detection current (for example, H_DI2 in FIG. 2) and the over-range current (H_OVI in FIG. 2), both of which are analog values, but in the second embodiment, an example will be described in which an overcurrent is detected by the logical sum of the second detection current, which is a digital value, and the overcurrent signal, which is a digital value. Note that the addition performed in the first embodiment can also be considered to be realized by an addition circuit configured with a wired OR.

[0171] <High-side detection circuit> Fig. 15 is a circuit diagram showing the configuration of a high-side detection circuit according to embodiment 2. Fig. 15 is similar to Fig. 2. The main differences are that in Fig. 15, the overrange comparison circuit is changed to a digital overrange comparison circuit H_OVC2, and the high-side generation circuit unit 6_H is composed of an overcurrent comparison circuit 6_HIC and a digital OR circuit (logic circuit) 6_HOR.

[0172] The overcurrent comparison circuit 6_HIC is similar to that described in embodiment 1, and has the configuration described in Fig. 4(B), for example. The difference is that while in Fig. 4(B) the sum of the second detection current H_DI2 and the over-range current H_OVI is supplied to the input HIC_I of the overcurrent comparison circuit 6_HIC, in Fig. 15 only the second detection current H_DI2 is supplied to the input HIC_I of the overcurrent comparison circuit 6_HIC, and the output HIC_O of the overcurrent comparison circuit 6_HIC is connected to one input of a two-input OR circuit 6_HOR.

[0173] The other input of the two-input OR circuit 6_HOR is supplied with the overrange signal H_OV2 from the overrange comparator circuit H_OVC2, which causes the OR circuit 6_HOR to output a high-level abnormality signal H_EER when at least one of the overcurrent signal from the overcurrent comparator circuit 6_HIC and the overrange signal H_OV2 is high (logical value 1).

[0174] Next, an example of the over-range comparison circuit H_OVC2 will be described with reference to the drawings.

[0175] <<Example of the configuration of the overrange comparison circuit H_OVC2>> FIG. 16 is a circuit diagram showing the configuration of an overrange comparison circuit according to a second embodiment. FIG. 16 is similar to FIG. 3. The difference is that FIG. 16 adds a Schmitt trigger inverter circuit IV2 with hysteresis and a level shifter LVF to the overrange comparison circuit of FIG. 3. That is, in FIG. 16, the input of the inverter circuit IV2 is connected to the node connecting the constant current source H_IOS1 and the N-type transistor NM2. The output of the inverter circuit IV2 is level-shifted by the level shifter LVF and supplied as the overrange signal H_OV2 to the other input of the OR circuit 6_HOR in the generation circuit unit 6_H. The level shift circuit LVF is supplied with the power supply voltage CBV, the voltage CBV-VDDA, the voltage VDDA, and the ground voltage CGV. As a result, the level shift circuit LVF converts the output of the inverter circuit IV2, which varies between the power supply voltage CBV and the voltage CBV, into a digital overrange signal H_OV2, which varies between the voltage VDDA and the ground voltage CGV.

[0176] As a result, according to the second embodiment, it is possible to generate the abnormality signal H_EER by taking the logical sum of the digital signals.

[0177] <Low-side detection circuit> Fig. 17 is a circuit diagram showing the configuration of a low-side detection circuit according to embodiment 2. Fig. 17 is similar to Fig. 5. The main differences are that in Fig. 17, the overrange comparison circuit is changed to a digital overrange comparison circuit L_OVC2, and the low-side generation circuit unit 6_L is composed of an overcurrent comparison circuit 6_LIC and a digital OR circuit (logic circuit) 6_LOR.

[0178] The overcurrent comparison circuit 6_LIC is similar to that described in embodiment 1, and has the configuration described in Fig. 7(B), for example. The difference is that in Fig. 7(B), the sum of the second detection current L_DI2 and the overrange current L_OVI is supplied to the input LIC_I of the overcurrent comparison circuit 6_LIC, but in Fig. 17, only the second detection current L_DI2 is supplied to the input LIC_I of the overcurrent comparison circuit 6_LIC, and the output LIC_O of the overcurrent comparison circuit 6_LIC is connected to one input of a two-input OR circuit 6_LOR.

[0179] The other input of the two-input OR circuit 6_LOR is supplied with the overrange signal L_OV2 from the overrange comparator circuit L_OVC2, which causes the OR circuit 6_LOR to output a high-level abnormality signal L_EER when at least one of the overcurrent signal from the overcurrent comparator circuit 6_LIC and the overrange signal L_OV2 is high (logical value 1).

[0180] Next, an example of the over-range comparison circuit L_OVC2 will be described with reference to the drawings.

[0181] <<Example of the configuration of the overrange comparison circuit L_OVC2>> FIG. 18 is a circuit diagram showing the configuration of an overrange comparison circuit according to a second embodiment. FIG. 18 is similar to FIG. 6. The difference is that in FIG. 18, a Schmitt trigger inverter circuit IV3 with hysteresis is added to the overrange comparison circuit shown in FIG. 6. That is, in FIG. 18, the input of the inverter circuit IV3 is connected to the node connecting the constant current source L_IOS1 and the N-type transistor NM6, and the overrange signal L_OV2 is output from the inverter circuit IV3. When an overcurrent occurs and the voltage at the node L_ND4 rises, the current I_OV5 increases and exceeds the reference current Iref4. As a result, the overrange signal L_OV2 changes to a high level.

[0182] As a result, according to the second embodiment, it is possible to generate the abnormality signal L_EER by taking the logical sum of the digital signals.

[0183] In the second embodiment, a self-diagnosis function may also be provided, as described in the self-diagnosis function of the first embodiment.

[0184] In the first embodiment, the second detection current and the over-range current are added together in an analog manner to generate the abnormality signal. In contrast, in the second embodiment, the abnormality signal is generated by the logical sum of digital signals. This is more advantageous than the first embodiment in terms of occupied area, current consumption, and speed. The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0185] 1. Semiconductor device 2. Load 3 Charge pump circuit 4. Drive circuit 5. Drive signal generation circuit 6 Abnormal signal generation circuit 7. Detection current processing circuit 8 Drive control circuit 9 Arithmetic circuit 10 Control circuit EER, H_EER, L_EER abnormal signal H_DI1, L_DI1 First detection current H_DI2, L_DI2 Second detection current H_DO, L_DO detection circuit H_OV, H_OV2, L_OV, L_OV2 Overrange signals H_PN, L_PN power transistors H_SN1, L_SN1 sense transistors

Claims

1. a power device that supplies current to a load; a current detection circuit that detects a current flowing through the power device; a device control circuit that controls a current flowing through the power device based on an input signal and a first detected current that is based on the current detected by the current detection circuit; an overrange comparison circuit that outputs an overrange signal when the voltage of the power device exceeds a predetermined voltage; an abnormality signal generating circuit that outputs an abnormality signal indicating an overcurrent state of the power device based on a second detected current based on the current detected by the current detecting circuit and the overrange signal; Equipped with Semiconductor device.

2. 2. The semiconductor device according to claim 1, the power device includes a power transistor having a pair of terminals including a terminal connected to the load and a gate terminal connected to the device control circuit; the current detection circuit includes a sense transistor having a pair of terminals and a gate terminal connected to a gate terminal of the power transistor, and the current detection circuit generates the first detection current and the second detection current based on a current flowing between the pair of terminals of the sense transistor; the overrange comparison circuit compares the voltage between a pair of terminals of the power transistor with the predetermined voltage, and outputs the overrange signal when the voltage between the terminals exceeds the predetermined voltage. Semiconductor device.

3. 3. The semiconductor device according to claim 2, the power transistor comprises a first power transistor having one terminal connected to a first voltage terminal to which a first voltage is supplied, another terminal connected to a load terminal to which the load is connected, and a gate terminal connected to the device control circuit; the sense transistor comprises a first sense transistor having one terminal connected to the first voltage terminal and a gate terminal connected to a gate terminal of the first power transistor; the current detection circuit includes a first control circuit that operates so that a voltage at the other terminal of the first sense transistor matches a voltage at the other terminal of the first power transistor, and the first control circuit generates the second detection current corresponding to the first power transistor. Semiconductor device.

4. 3. The semiconductor device according to claim 2, the power transistor includes a second power transistor having one terminal connected to a second voltage terminal to which a second voltage is supplied, one terminal connected to a load terminal to which the load is connected, and a gate terminal connected to the device control circuit; the sense transistor includes a second sense transistor having the other terminal connected to the second voltage terminal and a gate terminal connected to a gate terminal of the second power transistor; The current detection circuit a bidirectional circuit connected between one terminal of the second power transistor and one terminal of the second sense transistor, and operating to match a terminal voltage between a pair of terminals of the second sense transistor and a terminal voltage between a pair of terminals of the second power transistor; a second control circuit that operates so that the voltage at one terminal of the second sense transistor matches the voltage at one terminal of the second power transistor; the second control circuit generates the second detection current corresponding to the second power transistor; Semiconductor device.

5. 3. The semiconductor device according to claim 2, The abnormality signal generating circuit an overrange current source that outputs an overrange current according to the overrange signal; an adder circuit that adds the second detection current and the over-range current; an overcurrent comparison circuit that compares the output of the adder circuit with a predetermined current and outputs the abnormality signal; Equipped with Semiconductor device.

6. 3. The semiconductor device according to claim 2, The abnormality signal generating circuit an overcurrent comparison circuit that outputs an overcurrent signal when the second detected current exceeds a predetermined current; a logic circuit that calculates a logical sum between the overcurrent signal and the overrange signal and outputs the result as the abnormality signal; Equipped with Semiconductor device.

7. 3. The semiconductor device according to claim 2, The semiconductor device further comprises: a switch that is turned on during diagnosis in accordance with a diagnostic signal; a current source connected to the overrange comparison circuit via the switch and supplying a current; Equipped with Semiconductor device.

8. 4. The semiconductor device according to claim 3, the power transistor includes a second power transistor having one terminal connected to a second voltage terminal to which a second voltage different from the first voltage is supplied, one terminal connected to a load terminal to which the load is connected, and a gate terminal connected to the device control circuit; the sense transistor includes a second sense transistor having the other terminal connected to the second voltage terminal and a gate terminal connected to a gate terminal of the second power transistor; The current detection circuit a bidirectional circuit connected between one terminal of the second power transistor and one terminal of the second sense transistor, and operating to match a terminal voltage between a pair of terminals of the second sense transistor and a terminal voltage between a pair of terminals of the second power transistor; a second control circuit that operates so that the voltage at one terminal of the second sense transistor matches the voltage at one terminal of the second power transistor; Equipped with the second control circuit generates the second detection current corresponding to the second power transistor; Semiconductor device.

9. 9. The semiconductor device according to claim 8, the load terminals include a first load terminal to which the first power transistor and the first sense transistor are connected, and a second load terminal to which the second power transistor and the second sense transistor are connected; the load comprises a coil connected between the first load terminal and the second load terminal; Semiconductor device.

10. 10. The semiconductor device according to claim 9, the first power transistor, the second power transistor, the first sense transistor, and the second sense transistor are configured by N-channel transistors, The device control circuit a first regulator that operates based on a voltage at the first load terminal and a voltage higher than the first voltage; a first driver connected to gate terminals of the first power transistor and the first sense transistor and operated by an output voltage of the first regulator; a second regulator that operates based on the second voltage and the first voltage; a second driver connected to gate terminals of the second power transistor and the second sense transistor and operated by an output voltage of the second regulator; Equipped with Semiconductor device.

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